Remote Firmware Down Load. Xilinx V4LX25 Altera Stratix Control Altera Stratix Control Xilinx V4FX20 EPROM XCF08 EPROM XCF08 EPROM EPC16 EPROM EPC16 EPROM

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Text of Remote Firmware Down Load. Xilinx V4LX25 Altera Stratix Control Altera Stratix Control Xilinx V4FX20...

  • Remote Firmware Down Load

  • Xilinx V4LX25Xilinx V4LX25Altera StratixControlXilinx V4FX20EPROMXCF08EPROMEPC16EPROMXCF08EPROMXCF08Altera Atmel uControllerEPROMEPC16CTPSDTIFADC250ROCSRAMVXS IsquareCVMEVMEEthernetFirmware FilesFirmware Download Diagram for Front-End Readout ModulesVXS IsquareC

  • FADC-250 Configuration Scheme Loading Configurarion During Code DevelopmentConnect (Altera or Xilinx) JTAG cableSet Dip Switch to select JTAG ChainRun Altera Quartus or Xilinx Impact program to config Devices.Loading Configurarion After InstallationControl FPGA receives config. data via VME-64 bus and temporary stores to SRAM. Config. data for one or more FPGA can be received at once. Control FPGA programs config. data into EPROM.Control FPGA read back config data from EPROM to SRAM.VME host (ROC) read and compare data. If OK, issue config command.Control FPGA issues config command to EPROM to load new config. data to FPGA..

    Altera Stratix (control)Altera CPLDXilinxLX25XilinxFX20XilinxLX25XilinxXCF08EPROMXilinxXCF08EPROMXilinxXCF08EPROMAltera EPC16EPROMPCSRAMVME USBJTAGFPGA Boot

  • FADC : Config data size: LX25 = .97744 Mbytes FX20 = .90528 Mbytes Stratix = 1.205 Mbyte VME transfer time (VME 30MByte/Sec): LX25 = .032 sec FX20 = .032 sec Stratix = .042 sec VME transfer for 1 FADC (all FPGA) to Control: .14 sec JTAG transfer time (JTAG clock of 3MHz) LX25 = 3 sec FX20 = 3 sec Stratix = 4 sec Time to erase FLASH: LX25, FX20 = 9 sec Stratix = 20.5 sec Time to program FLASH LX25 = 31.3 sec FX20 = 25.0 sec Straitx = 76.5 sec Total ~= 238 sec. ~= 4 minutes.

    FADC-250 Configuration Time

  • CTP Configuration Scheme Remote ConfigVXS IsquareCLoading Configurarion During Code DevelopmentConnect Xilinx JTAG cableRun Xilinx Impact program to config Devices.Loading Configurarion After InstallationLX110 config. data via VXS IsquareC and temporary stores to RAM inside FPGA. Config. Data has to be segmented due to limited RAM. LX110 programs config. data into EPROM.LX110 read back config data from EPROM to SRAM.VME host (ROC) read and compare data. If OK, send next segment.VME host (ROC) issues config command when all segments are stored in ROM.LX110 issues config command to EPROM to load new config data to FPGA..

  • CTP Configuration Time CTP : Config data size: LX50 = 1.57 Mbytes LX110 = 3.64 Mbytes VME transfers to TI (VME 30MByte/Sec): LX50 = .053 sec LX110 = .122 sec TI transfers to CTP (IsquareC 34.43Kbytes/Sec write; 40.08 Kbytes/Sec read (1) ): LX50 = 56 sec (wr); 40 sec (rd) LX110 = 106 sec (wr); 91 sec (rd) JTAG transfer time (JTAG clock of 3MHz) LX50 = 5.2 sec LX110 = 12 sec Time to erase FLASH: LX50 = 16 sec LX110 = 36 sec Time to program FLASH LX50 = 50 sec LX110 = 117 sec Total ~= 720 sec. ~= 12 minutes. (1) Documentation of I2C Protocol Project, Sebouh Paul

  • VHDL Block Diagram to Remotely Configure FADC-250 Remote Configurarion SequenceVME host (ROC) write configuration data for one or more FPGA to SRAM (memory map TBD). VME host write CMD Registers to initiate EPROM stored.VHDL Code takes over control of SRAM. Read config. data from SRAM, send OP-Code to EPROM, and stores config data to EPROM. After store, read back EPROM data to SRAM.VHDL code relinquishes control of SRAM and signals VME host.VME host verifies EPROM stored data. If OK, write CMD Register to initiate FPGA config.VHDL Code issues config command to EPROM to load new config data to FPGA.

    VME BUS

  • VHDL Block Diagram to Remotely Configure CTP IsquareC IFACECMD REGSEPROM OP-CODE TABLEEPROM OP_CODE SEQUENCER

    JTAG IFACE

    VHDL Code to Remotely Configure FPGA

    VHDL Operating Code

    SelectLX110 FPGA

    JTAGRAMIsquareCBusXilinxXCF16EPROMXilinxXCF16EPROMXilinxXCF32EPROMRemote Configurarion SequenceVME host (ROC) write configuration data in segments (Host to TI and then TI to LX110).VME host write CMD Registers to initiate EPROM stored.VHDL Code takes over control of SRAM. Read config. data from SRAM, send OP-Code to EPROM, and stores config data to EPROM. After store, read back EPROM data to SRAMVHDL code relinquishes control of SRAM and signals VME host.VME host verifies EPROM stored data. If OK, repeat for all segmens.When all segments are done, twrite CMD Register to initiate FPGA config.VHDL Code issues config command to EPROM to load new config data to FPGA.

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