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Dirk J. Wouters RWTH Aachen, Institut für Werkstoffe der Elektrotechnik, Aachen, Germany Resistive Memories (RRAM) - principles & technology 30 April 2015 Workshop on Memristive systems for Space applications 30 April 2015 ESTEC, Noordwijk, NL

Resistive Memories (RRAM) - principles & technology J. Wouters RWTH Aachen, Institut für Werkstoffe der Elektrotechnik, Aachen, Germany Resistive Memories (RRAM) - principles & technology

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Page 1: Resistive Memories (RRAM) - principles & technology J. Wouters RWTH Aachen, Institut für Werkstoffe der Elektrotechnik, Aachen, Germany Resistive Memories (RRAM) - principles & technology

Dirk J. Wouters

RWTH Aachen, Institut für Werkstoffe der Elektrotechnik, Aachen, Germany

Resistive Memories (RRAM) - principles & technology

30 April 2015

Workshop on Memristive systems for Space applications

30 April 2015

ESTEC, Noordwijk, NL

Page 2: Resistive Memories (RRAM) - principles & technology J. Wouters RWTH Aachen, Institut für Werkstoffe der Elektrotechnik, Aachen, Germany Resistive Memories (RRAM) - principles & technology

Folie 2 Dirk Wouters ESA WS April 2015

Outline

1. Definition and classification

2. Filamentary switching

• Oxygen vacancy based (VCM)

• Metal cation based (ECM)

3. Interfacial switching devices

4. RRAM array organization

5. Status and outlook

Page 3: Resistive Memories (RRAM) - principles & technology J. Wouters RWTH Aachen, Institut für Werkstoffe der Elektrotechnik, Aachen, Germany Resistive Memories (RRAM) - principles & technology

Folie 3 Dirk Wouters ESA WS April 2015

Resistive Switching Memories

– Memory element is R (MIM-type 2-terminal)

• r can be altered by applying V/I on R

• readout R at low voltage

– Bipolar or Unipolar Switching depending on mechanism

Kawai et al., 2nd RRAM workshop Oct 2012

V

I Low R

High R

Page 4: Resistive Memories (RRAM) - principles & technology J. Wouters RWTH Aachen, Institut für Werkstoffe der Elektrotechnik, Aachen, Germany Resistive Memories (RRAM) - principles & technology

Folie 4 Dirk Wouters ESA WS April 2015

Taxonometry of Resistive Switching

Memories : based on Mechanism

Page 5: Resistive Memories (RRAM) - principles & technology J. Wouters RWTH Aachen, Institut für Werkstoffe der Elektrotechnik, Aachen, Germany Resistive Memories (RRAM) - principles & technology

Folie 5 Dirk Wouters ESA WS April 2015

Resistance Modulation Geometry

Page 6: Resistive Memories (RRAM) - principles & technology J. Wouters RWTH Aachen, Institut für Werkstoffe der Elektrotechnik, Aachen, Germany Resistive Memories (RRAM) - principles & technology

Folie 6 Dirk Wouters ESA WS April 2015

1D Filamentary switching

Page 7: Resistive Memories (RRAM) - principles & technology J. Wouters RWTH Aachen, Institut für Werkstoffe der Elektrotechnik, Aachen, Germany Resistive Memories (RRAM) - principles & technology

Folie 7 Dirk Wouters ESA WS April 2015

Indications for filamentary switching

Page 8: Resistive Memories (RRAM) - principles & technology J. Wouters RWTH Aachen, Institut für Werkstoffe der Elektrotechnik, Aachen, Germany Resistive Memories (RRAM) - principles & technology

Folie 8 Dirk Wouters ESA WS April 2015

Electrical fingerprint from device characteristics

• Area (in)dependence of LRS/HRS and switching voltages

F.Nardi et al, IEEE Trans. El.Dev. 59(9). 2661 (2012)

Indications for filamentary switching

Page 9: Resistive Memories (RRAM) - principles & technology J. Wouters RWTH Aachen, Institut für Werkstoffe der Elektrotechnik, Aachen, Germany Resistive Memories (RRAM) - principles & technology

Folie 9 Dirk Wouters ESA WS April 2015

Different steps in a filamentary switching process

▸ Forming

▸ RESET

▸ SET

Akihito Sawa, materialstoday, Vol11(6), 2008

1.E-09

1.E-07

1.E-05

1.E-03

0 0.5 1 1.5

forming

set

reset

Voltage

Cu

rren

t

real switching curves

L.Goux (imec), NiO/Ni RRAM cell

C.Cagli, IEDM 2008

Page 10: Resistive Memories (RRAM) - principles & technology J. Wouters RWTH Aachen, Institut für Werkstoffe der Elektrotechnik, Aachen, Germany Resistive Memories (RRAM) - principles & technology

Folie 10 Dirk Wouters ESA WS April 2015

Forming: creating a conduction

path by “breakdown”

NiO by MOCVD imec

0

1

2

3

4

5

6

7

8

0.0 5.0 10.0 15.0 20.0 25.0 30.0

Thickness (nm)

V f

orm

ing

(V

)

Similar to (soft) breakdown in dielectrics (defect &

percolation path generation)

Forming

voltage scales

with thickness

Page 11: Resistive Memories (RRAM) - principles & technology J. Wouters RWTH Aachen, Institut für Werkstoffe der Elektrotechnik, Aachen, Germany Resistive Memories (RRAM) - principles & technology

Folie 11 Dirk Wouters ESA WS April 2015

Y.Satoet al, Trans.El.Dev. 2008 D.Ielmini et al, Trans.El.Dev. 58(12), p.4309, 2011

Maximum current during Forming(/SET)

controls filament “Strength”

Page 12: Resistive Memories (RRAM) - principles & technology J. Wouters RWTH Aachen, Institut für Werkstoffe der Elektrotechnik, Aachen, Germany Resistive Memories (RRAM) - principles & technology

Folie 12 Dirk Wouters ESA WS April 2015

“Scaling of filamentary switching”

▸ 2D and 3D switching:

- Current levels scale with area of the cell ~ F2

▸ 1D switching:

- Current levels independent of cell area

- Current level determined by filament “diameter”

Determined by operation conditions (Forming/SET CC)

We can have small current even in large device

- Limitations ?

Cell area ~ filament size..

Smallest filament size ?

• ~ nm ??

F.Nardi et al, Trans.El.Dev. 59(9), p.2461,2012

Page 13: Resistive Memories (RRAM) - principles & technology J. Wouters RWTH Aachen, Institut für Werkstoffe der Elektrotechnik, Aachen, Germany Resistive Memories (RRAM) - principles & technology

Folie 13 Dirk Wouters ESA WS April 2015

Switching during SET/RESET:

SET = Forming

0

0.2

0.4

0.6

0.8

1

RE

Se

t vo

lta

ge

, V

S [

V]

1m 100nm 10nm 10nmCell size

5nm HfOx10nm HfOx

10nm-size cells0

0.2

0.4

0.6

0.8

1

RE

Re

se

t vo

lta

ge

, V R

[V

]

1m 100nm 10nm 10nmCell size

5nm HfOx10nm HfOx

10nm-size cells

B.Govoreanu, IEDM2011

Absence of oxide thickness effect on

VSET/RESET indicative of LOCAL

filament switching

Page 14: Resistive Memories (RRAM) - principles & technology J. Wouters RWTH Aachen, Institut für Werkstoffe der Elektrotechnik, Aachen, Germany Resistive Memories (RRAM) - principles & technology

Folie 14 Dirk Wouters ESA WS April 2015

Bipolar Switching OxRRAM :

“Oxygen Vacancy Migration”

1D Filamentary

Oxygen vacancy migration

TE

BE

MIT

BIPOLAR

Material : TMO’s , e.g. HfO,TiO,TaO..

H.Y.Lee et al, “Low Power

and High Speed Bipolar

Switching with A Thin

Reactive Ti Buffer Layer in

Robust HfO2 Based

RRAM”, IEDM, Tech. Dig.,

pp. 297, 2008

Page 15: Resistive Memories (RRAM) - principles & technology J. Wouters RWTH Aachen, Institut für Werkstoffe der Elektrotechnik, Aachen, Germany Resistive Memories (RRAM) - principles & technology

Folie 15 Dirk Wouters ESA WS April 2015

▸ Filament switching involves oxygen transport

▸ Filament observations indicate local lower O concent

- Magnelli phase of Ti4O7 or Ti5O9 , essentially TiO2-x

Oxygen vacancy defects

Szot et al., Nature materials (2006)

Bubbles < O2 released to the gas phase or adsorbed by the grainboundaries

of the Pt electrode

D. H. Kwon et al., Nature Nano technology(2010)

Role of oxygen / oxygen vacancy

defects in OxRRAM memories

Page 16: Resistive Memories (RRAM) - principles & technology J. Wouters RWTH Aachen, Institut für Werkstoffe der Elektrotechnik, Aachen, Germany Resistive Memories (RRAM) - principles & technology

Folie 16 Dirk Wouters ESA WS April 2015

Oxygen vacancy filament conduction

▸ Oxygen vacancies influence conduction

- Electron hopping from one vacancy to another

- Act as local “doping” thermally activated conduction

aka VCM : valency change mechanism

- Create conductive defect band in Metal Oxide (e.g. at GB)

Metallic conduction

S.Larentis et al,

Trans. El.Dev. 59(9), 2012, p.

2468

G.Bersuker et al.,

J. Appl. Phys. 110, 124518 (2011)

N.Xu et al,

VLSI Technology, 2008

Page 17: Resistive Memories (RRAM) - principles & technology J. Wouters RWTH Aachen, Institut für Werkstoffe der Elektrotechnik, Aachen, Germany Resistive Memories (RRAM) - principles & technology

Folie 17 Dirk Wouters ESA WS April 2015

“Oxygen vacancy drift” based

RRAM

▸ Reset/Set :

- Transport = drift of oxygen vacancies

- Filament constriction shrinks/expands with

drift of oxygen vacancies up/down

▸ Closed system:

- NO Generation/Recombination of VO

Page 18: Resistive Memories (RRAM) - principles & technology J. Wouters RWTH Aachen, Institut für Werkstoffe der Elektrotechnik, Aachen, Germany Resistive Memories (RRAM) - principles & technology

18 VCM-type switching: Switching mechanism

Switching based on oxygen

vacancy migration and local

redox reactions

Material systems

• SrZrO3, SrTiO3

• TiO2, Ta2O5, HfO2, ZrOx

Characteristics

• Nonlinear ON/OFF state

• Highly nonlinear switching kinetics

• Electroforming required

Page 19: Resistive Memories (RRAM) - principles & technology J. Wouters RWTH Aachen, Institut für Werkstoffe der Elektrotechnik, Aachen, Germany Resistive Memories (RRAM) - principles & technology

Folie 19 Dirk Wouters ESA WS April 2015

M-cap HfO2

“Oxygen vacancy drift” based

RRAM

After

processing

oxygen vacancy reservoir excess oxygen

▸ Controlled introduction of oxygen

vacancy by process

- Oxygen scavenging metal cap layer on top

of stoechiometric HfO2 (ALD)

Ti, Hf, Ta,....

Local formation of HfO2-d

- Deposition of substoichiometric HfOx

(PVD)

▸ Need for asymmetric profile of

oxygen vacancies

- Otherwise competing switching layers [1]

Stack M-

Cap HfO2

TE

BE

F.Nardi et al, “Complementary switching in metal oxides: toward diode-less Xbad RRAMs”, IEDM 2011

Page 20: Resistive Memories (RRAM) - principles & technology J. Wouters RWTH Aachen, Institut für Werkstoffe der Elektrotechnik, Aachen, Germany Resistive Memories (RRAM) - principles & technology

Folie 20 Dirk Wouters ESA WS April 2015

HfO2 RRAM demonstrator

NTHU/ITRI ISSCC 2011 1T1R

Page 21: Resistive Memories (RRAM) - principles & technology J. Wouters RWTH Aachen, Institut für Werkstoffe der Elektrotechnik, Aachen, Germany Resistive Memories (RRAM) - principles & technology

Folie 21 Dirk Wouters ESA WS April 2015

Conductive Bridge RRAM :

“Programmable Metallization Cell”

1D Filamentary

Material :

Ag or Cu based

Electro- chemical

Cation Source (Ag+, Cu+ or...)

Cu+

Ag+

BE

ME

TA

LIC

FIL

AM

EN

T

BIPOLAR

Ag/Cu electrode

Inert electrode

Page 22: Resistive Memories (RRAM) - principles & technology J. Wouters RWTH Aachen, Institut für Werkstoffe der Elektrotechnik, Aachen, Germany Resistive Memories (RRAM) - principles & technology

Folie 22 Dirk Wouters ESA WS April 2015

Electrochemical filament formation

▸ Oxidation at anode: forming of metal ions (Ag Ag+ + e-)

▸ Drift of metal ions through insulating switching layer

▸ Reduction at cathode: plating out of metal ions (Ag+ + e- Ag)

- Growing filament forms “virtual cathode”

U. Russo et al., IEEE TRANSACTIONS ON ELECTRON DEVICES, 56(5), p. 1040, 2009

Rainer Waser et al., Adv.

Mater. 2009, 21, 2632–2663

Page 23: Resistive Memories (RRAM) - principles & technology J. Wouters RWTH Aachen, Institut für Werkstoffe der Elektrotechnik, Aachen, Germany Resistive Memories (RRAM) - principles & technology

23 ECM-type switching: Switching mechanism

Material systems

• AgI, GeSe, GeSx, Cu:TCNQ

• SrTiO3, SiO2, WOx

• TiO2, Ta2O5, HfO2

Electrodes

• Ag or Cu active electrode

• One inert electrode

I-V Characteristics

• Linear I-V in ON state

• Nonlinear OFF state

Switching based on Ag/Cu filamentary

growth and dissolution

Page 24: Resistive Memories (RRAM) - principles & technology J. Wouters RWTH Aachen, Institut für Werkstoffe der Elektrotechnik, Aachen, Germany Resistive Memories (RRAM) - principles & technology

Folie 24 Dirk Wouters ESA WS April 2015

Bipolar Switching

1.E-12

1.E-08

1.E-04

-3 -1.5 0 1.5 3

after 103 cycles

Vbit-line (V)

Curr

ent

(A)

Asymmetric switching

VRESET < VSET

Deep RESET

~ complete filament annihilation?

L.Goux et al., VLSI Technology 2012

Page 25: Resistive Memories (RRAM) - principles & technology J. Wouters RWTH Aachen, Institut für Werkstoffe der Elektrotechnik, Aachen, Germany Resistive Memories (RRAM) - principles & technology

Folie 25 Dirk Wouters ESA WS April 2015

Materials and Structures

Ag electrode

Inert electrode

GexSe

matrix

Ag2Se

nanoparticles

1st generation : Ag-doped chalcogenide

All-in-one, non-homogeneous material

[1] M.Kozicki,

IEEE Trans. On

Nanotechnology

4(3), 331 (2005)

Cu(X) electrode

Inert electrode

Metal-oxide

matrix

2nd generation: Metal-Oxide

Cu source separated from switching layer

K.Aratani et al., IEDM 2007

Page 26: Resistive Memories (RRAM) - principles & technology J. Wouters RWTH Aachen, Institut für Werkstoffe der Elektrotechnik, Aachen, Germany Resistive Memories (RRAM) - principles & technology

Folie 26 Dirk Wouters ESA WS April 2015

SONY ISSCC 2011 CBRAM 1T1R

Page 27: Resistive Memories (RRAM) - principles & technology J. Wouters RWTH Aachen, Institut für Werkstoffe der Elektrotechnik, Aachen, Germany Resistive Memories (RRAM) - principles & technology

Folie 27 Dirk Wouters ESA WS April 2015

The Time-Voltage Dilemma

Fast programming

▸ At ~1V, need programming in ~10nsec

Good retention

▸ At ~0.1V, need stable read for ~ 10 years

Need operation mechanism with extreme non-linear behavior:

>15 orders of magnitude in time over 1 decade in voltage

R.Waser (RWTH/Julich)

How can we make a 2-terminal NVM ?

Page 28: Resistive Memories (RRAM) - principles & technology J. Wouters RWTH Aachen, Institut für Werkstoffe der Elektrotechnik, Aachen, Germany Resistive Memories (RRAM) - principles & technology

Folie 28 Dirk Wouters ESA WS April 2015

▸ Oxygen vacancy defect based cells (also

called VMC cells)

- Drift of oxygen vacancies requires strong

thermal activation

Limit of min current (> 1uA, typically few

10 of uA’s)

Limits RESET depth

Further comparison of 2 types of bipolar switching RRAM : different kinetics

▸ Metal cation based cells (ECM

cells)

- Drift of metal cations possible

without thermal activation

Lower current operation possible

Strong RESET

compromised retention

Menzel et al., Adv. Funct. Mat 2011

SET kinetics can be

modeled be E-

activation only

S. Menzel et al., Phys. Chem. Chem. Phys., 15, 18 (2013)

Switching kinetics are limited by

• I: Nucleation

• II: Electron transfer reactions

• III: Electron transfer reactions

and ion hopping transport

Page 29: Resistive Memories (RRAM) - principles & technology J. Wouters RWTH Aachen, Institut für Werkstoffe der Elektrotechnik, Aachen, Germany Resistive Memories (RRAM) - principles & technology

Folie 29 Dirk Wouters ESA WS April 2015

RRAM Cell and Array configurations ▸ RRAM element = RRAM cell ?

- Raw Cross Point array = highest density configuration

- Cell size = 4F2

Akihito Sawa,

MaterialsTodayJUNE 2008 |

VOLUME 11 | NUMBER 6 p. 28

Page 30: Resistive Memories (RRAM) - principles & technology J. Wouters RWTH Aachen, Institut für Werkstoffe der Elektrotechnik, Aachen, Germany Resistive Memories (RRAM) - principles & technology

Folie 30 Dirk Wouters ESA WS April 2015

RAW XP LIMITATIONS

▸ Read errors due to sneak current paths

▸ Program disturbs on half-select cells (1/2 or 1/3 V

scheme)

▸ Power dissipation due to current through half-

selected cells

E.Linn en al, NATURE MATERIALS VOL 9 p. 403 MAY 2010 J.Liang et al., IEEE TRANSACTIONS ON ELECTRON

DEVICES, VOL. 57, NO. 10, p.2532 OCTOBER 2010

Page 31: Resistive Memories (RRAM) - principles & technology J. Wouters RWTH Aachen, Institut für Werkstoffe der Elektrotechnik, Aachen, Germany Resistive Memories (RRAM) - principles & technology

Folie 31 Dirk Wouters ESA WS April 2015

1T1R cell

0 1 2 3 40

200

400Reset

Set

I(A

)V_topelectrode_NiOcell (V)

Forming

F.Nardi et al, IMW 2010

F,Chen ITRI

Transistor is ideal selector

▸ Both isolation switch and current limiter (during SET)

▸ 3-terminal device : large cell

▸ Best suited for embedded RRAM

Page 32: Resistive Memories (RRAM) - principles & technology J. Wouters RWTH Aachen, Institut für Werkstoffe der Elektrotechnik, Aachen, Germany Resistive Memories (RRAM) - principles & technology

Folie 32 Dirk Wouters ESA WS April 2015

1D1R -1S1R cell

▸ Diode selector

- Good selector : strong asymmetry (rectification) combined

with strong (exponential) non-linearity

- 2 terminal selector on top of RRAM

Small cell size possible

- Only for unipolar switching RRAM

- Voltage drop over diode

- Large aspect ratio

▸ For bipolar RRAM

- New 2 terminal selectors :

“Symmetric” diode type and Volatile Switching types

P.Wong (Stanford)

Page 33: Resistive Memories (RRAM) - principles & technology J. Wouters RWTH Aachen, Institut für Werkstoffe der Elektrotechnik, Aachen, Germany Resistive Memories (RRAM) - principles & technology

Folie 33 Dirk Wouters ESA WS April 2015

2- Terminal SELECTOR concepts

unipolar bipolar

Diode types

-p(i)n diode

-Schottky diode

Symmetric diode type

-Zener

-Punch Through Diode

Volatile switching

type

-MOTT

-OTS

-MIEC

VO2

Chalcogenide novel

materials

Diode types

MOx pn/Schottky diode

Using

semiconducting

material

Y.Sasago et al, VLSI Tech.Symp. 2009

M-J. Lee, Advanced Functional Materials,

2008, 18, p.1

M-J. Lee, Advanced Materials, 2007, 19, p.3919

D.Kau et al, IEDM 2009

Ion Conductor

K.Gopalankhrisnan et al. VLSI 2010

Symmetric diode

type

- Schottky Diode

-Tunnel

Diode

MOx

J-J. Huang, EDL 11(10) 2011

J-J. Huang, IEDM 2011

Page 34: Resistive Memories (RRAM) - principles & technology J. Wouters RWTH Aachen, Institut für Werkstoffe der Elektrotechnik, Aachen, Germany Resistive Memories (RRAM) - principles & technology

Folie 34 Dirk Wouters ESA WS April 2015

3D Stackable RRAM

3D RRAM ARRAY OPTIONS

M. Lee, et al., IEDM Tech. Dig. 2007

“pseudo 3D” = 2D stacking

3D Matrix, Semiconductor International , 7 Jan. 2005 1S1R

Page 35: Resistive Memories (RRAM) - principles & technology J. Wouters RWTH Aachen, Institut für Werkstoffe der Elektrotechnik, Aachen, Germany Resistive Memories (RRAM) - principles & technology

Folie 35 Dirk Wouters ESA WS April 2015

3D Stackable RRAM 3D VRRAM

3D RRAM ARRAY OPTIONS

H.Yoon, et al., VLSI Tech. 2009

“true” 3D

No place for

selector !

SRC

Page 36: Resistive Memories (RRAM) - principles & technology J. Wouters RWTH Aachen, Institut für Werkstoffe der Elektrotechnik, Aachen, Germany Resistive Memories (RRAM) - principles & technology

Folie 36 Dirk Wouters ESA WS April 2015

Self Rectifying Cell

▸ Cell with strong nonlinearity (in ON state)

▸ Some proposals, but still limited nonlinearity

Hynix VLSI Tech. 2012 M.Jo et al, VLSI Tech. 2010

Pt/

Al/PC

MO

/Pt

Page 37: Resistive Memories (RRAM) - principles & technology J. Wouters RWTH Aachen, Institut für Werkstoffe der Elektrotechnik, Aachen, Germany Resistive Memories (RRAM) - principles & technology

Folie 37 Dirk Wouters ESA WS April 2015

Steady improvement of RRAM

operation speed & current

Slide courtesy G.Jurczak, imec

Page 38: Resistive Memories (RRAM) - principles & technology J. Wouters RWTH Aachen, Institut für Werkstoffe der Elektrotechnik, Aachen, Germany Resistive Memories (RRAM) - principles & technology

Folie 38 Dirk Wouters ESA WS April 2015

> 1012 cyclability in TaOx

Y-B.Kim et al, VLSI Technology 2011

Page 39: Resistive Memories (RRAM) - principles & technology J. Wouters RWTH Aachen, Institut für Werkstoffe der Elektrotechnik, Aachen, Germany Resistive Memories (RRAM) - principles & technology

Folie 39 Dirk Wouters ESA WS April 2015

<10nm scalability of HfO2 RRAM cells

B.Govoreanu et al IEDM 2011

G.Kar et al VLSI 2012

Page 40: Resistive Memories (RRAM) - principles & technology J. Wouters RWTH Aachen, Institut für Werkstoffe der Elektrotechnik, Aachen, Germany Resistive Memories (RRAM) - principles & technology

Folie 40 Dirk Wouters ESA WS April 2015

Array Demonstrations of 1T-1R RRAM

Pt/TaOx/Pt

8kb bipolar array

Panasonic, IEDM 2008

Ru/TiOx/TaOx/Ru

1kb unipolar array

NEC, VLSI 2010

TaN/CuSixOy/Cu

1Mb bipolar array

SMIC, VLSI 2010

Page 41: Resistive Memories (RRAM) - principles & technology J. Wouters RWTH Aachen, Institut für Werkstoffe der Elektrotechnik, Aachen, Germany Resistive Memories (RRAM) - principles & technology

Folie 41 Dirk Wouters ESA WS April 2015

Array Demonstrations of 1S-1R RRAM

Page 42: Resistive Memories (RRAM) - principles & technology J. Wouters RWTH Aachen, Institut für Werkstoffe der Elektrotechnik, Aachen, Germany Resistive Memories (RRAM) - principles & technology

Folie 42 Dirk Wouters ESA WS April 2015

Elpida ELPIDA

64Mb, 50nm process,

Collaboration with AIST and SHARP

Page 43: Resistive Memories (RRAM) - principles & technology J. Wouters RWTH Aachen, Institut für Werkstoffe der Elektrotechnik, Aachen, Germany Resistive Memories (RRAM) - principles & technology

Folie 43 Dirk Wouters ESA WS April 2015

Toshiba_Sandisk will announce a 32Gb

1D1R RRAM in 24nm @ ISSCC2013

EETimes Asia 21 Nov. 2012

RRAM is fastly emerging !

Page 44: Resistive Memories (RRAM) - principles & technology J. Wouters RWTH Aachen, Institut für Werkstoffe der Elektrotechnik, Aachen, Germany Resistive Memories (RRAM) - principles & technology

Folie 44 Dirk Wouters ESA WS April 2015

Status - outlook

Main issue :

C2C variability, especially for HR/thin filaments

(lack of control of defect positions on atomic scale)

LRS/HRS distribution overlap

Application :

- embedded NVM (simple process, no HV)

- NAND Flash replacement (2D -3D): scalability

- Storage Class Memories : performance