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RISCRISC
By
Don Nichols
ContentsContents
IntroductionHistoryProblems with CISCRISC PhilosophyEarly RISCModern RISC
IntroductionIntroduction
What is RISC?
Not a game of world domination
RISC stands for Reduced Instruction Set Computer
IntroductionIntroduction
RISC is opposite of CISC which stands for Complex Instruction Set Computer
IntroductionIntroduction
Some Examples of RISCSome Examples of RISC MIPS: Found in SGI computers and Nintendo 64 IBM’s POWER series used in all of their minis
and mainframes Sun’s SPARC and UltraSPARC machines Hewlett-Packard’s PA-RISC HP/PA DEC Alpha Palm, Inc. PDAs (originally used CISC)
History: Pre-RISCHistory: Pre-RISCBefore compiler technology existed, programming was done in either machine code or Assembly language. Computer architects, to make some of the programming easier, created very complex instructions which were direct representations of high level functions of high level programming languages. The current attitude was that since hardware design was simpler than compiler design, it was the hardware that was made complex.
History: Pre-RISCHistory: Pre-RISC
Small memory sizes were also a big factor in the design of complex instructions. With memory being so small, instructions were designed to carry out multiple tasks, such as data movement and data calculation. Not only were instructions designed to do multiple tasks, but also, different versions were written for different variations of the tasks i.e. one version that added two numbers would store the result in memory and another version would store the result in a register.
History: Pre-RISCHistory: Pre-RISC
“The general goal at the time was to provide every possible addressing mode for every instruction, a principle known as "orthogonality." This led to some complexity on the CPU, but in theory each possible command could be tuned individually, making the design faster than if the programmer used simpler commands.”
This concept of overloading each instruction came to be known as CISC.
Problems with CISCProblems with CISC
In the late 1970’s, research showed that many of the orthogonal addressing modes were being ignored by most programs
This was due to the increased use of compilers and the decrease in use of assembly language
Problems with CISCProblems with CISC
Another problem was that chip designers didn’t have time to tune every instruction
Only the most used instructions were tunedResulted in the other instructions running
slower than a series of smaller instructions performing the same task
Problems with CISCProblems with CISC
CPU’s were rapidly becoming faster than the memory they dealt with
This lead to a need for more registers (and later, cache as well)
The board space needed to accommodate these additions could be gained by reducing the complexity of the CPU
RISC PhilosophyRISC Philosophy
Reduce the size of the instruction set (hence the name)
Implement code as a series of simple instructions instead of one complex instruction
RISC PhilosophyRISC Philosophy
This leaves more room in the instruction itself to carry data with it
This reduced the need to use registers or memory, which meant the memory interface could be simpler allowing it to be tuned
RISC PhilosophyRISC PhilosophyExampleExample
Andrew Tanenbaum showed that 98% of all constants in a program could be stored in 13 bits
By having a smaller instruction, these constants could be stored right there in the instruction
RISC PhilosophyRISC PhilosophyExampleExample
By storing numbers right inside the instruction it increases the speed of execution by reducing the number of accesses to registers and memory
RISC PhilosophyRISC PhilosophyDrawbacksDrawbacks
A series of instructions is needed for even simple tasks
The total number of instructions that are read from memory is larger and thusly takes longer
Early RISCEarly RISC
First computer that would be known as RISC was the CDC 6600 supercomputer, designed by Seymour Cray in 1964
Designed as a number crunching CPU
Early RISCEarly RISC
Only had 74 op-codes as opposed to the 400 op-codes on the 8086
Had a “load/store” architecture with only two addressing modes
Had 11 pipelined functional units for arithmetic and logic, plus 5 load units and 2 store units
Early RISCEarly RISC
RISC evolved from two projects
1. UC Berkley’s RISC project
2. Stanford’s MIPS project
Early RISCEarly RISCBerkley’s RISC projectBerkley’s RISC project
Started in 1980Directed by David PattersonIdea was to gain performance with
pipelining and the use of register windows
Early RISCEarly RISCWhat is a register window?What is a register window?
Normal CPU has small number of registers that can be used at any time
A CPU with windows has many registers but a program can only access a few of them at a time
Allows fast procedure calls by letting the call and return move the window to the set of registers used by that procedure
Early RISCEarly RISCRISC - IRISC - I
The RISC project brought the RISC – I processor in 1982
Had only 44,420 transistors (compared to the average 100,000 in current CISC designs
Had only 32 instructionsOut performed all other single-chip designs
Early RISCEarly RISCRISC - IIRISC - II
The RISC – II came in 1983Had 39 instructions40,760 transistorsOver 3 x as fast as RISC – I
Early RISCEarly RISCStanford’s MIPS projectStanford’s MIPS project
Microprocessor w/o Interlocked Pipeline Stages
Started by John Hennessy in 1981Main focus was the pipeline, running it as
“full” as possibleFar faster than other pipeline designs
Early RISCEarly RISCStanford’s MIPS projectStanford’s MIPS project
All instructions in this design must complete in one cycle
This requirement unfortunately disqualified instructions such as multiply and divide which took more than one cycle to execute
Accounted for with a special pair of HI/LO registers that had hardware interlocks
Modern RISCModern RISC
Almost all modern RISC processors are copies of the RISC – II design
Sun’s success with RISC chips in their SPARC machines showed that the benefits of RISC were real
Modern RISCModern RISC
John Hennessy left Stanford and started MIPS Computer Systems
Their MIPS chips are one of the most common among embedded processors used in high end applications
The entire mainframe world is now completely RISC based
Modern RISCModern RISCThings to noteThings to note
Some say RISC is now a meaningless term, why?
Current RISC architectures have grown and some instructions are not all that reduced (most of which are related to graphics)
Also, CISC designers have adopted some of the RISC philosophies in order to streamline their CPUs
Modern RISCModern RISCThings to noteThings to note
Because of this convergence in design, some feel that the distinction of RISC vs. CISC no longer has meaning
RISC is more accurately described today as “load-store”
CISC is more accurately described as “register-memory”
ReferencesReferences
http://en.wikipedia.org/wiki/RISC http://www.webopedia.com/TERM/R/RISC.html http://www.hyperdictionary.com/dictionary/Micro
processor+without+Interlocked+Pipeline+Stages