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Model Engineering College Drift-Tolerant Multilevel Phase-Change Memory

Department of Electronics Engineering 1

Chapter 1

INTRODUCTION

Phase-change memory (PCM) is a new solid-state memory technology that

exploits the thermally-induced resistivity change of chalcogenide compounds for

nonvolatile data storage. PCM possesses certain features, such as high cycling

endurance, low read/write latency and excellent scalability, that make it an interesting

candidate not only for extending and eventually replacing the incumbent Flash

memory, but also for enabling disruptive changes in future computing systems. The

latter stems from the potential ability of PCM to act as both storage (non-volatile,

cheap, high capacity) as well as memory (fast, durable),because of its universal

characteristics .It is widely believed that multilevel-cell (MLC) storage is essential for

enhancing the cost-per-bit competitiveness of PCM technology and thus its potential

for market acceptance.

In order for PCM to become a viable technology for high-volume

manufacturing, a number of critical issues need to be addressed. First and foremost,

the reliability of the technology has to be brought to levels similar to those of existing

technologies. Experimental results and simulations suggest that thermal disturbance

and resistance drift are the most important potential reliability concerns in PCM.

Thermal disturbance refers to the problem of inadvertently altering the state of a cell

by programming another cell in its vicinity; it is relevant for PCM because the latter

relies on thermally induced state change, which may cause thermal interference

between adjacent cells at small device dimensions .Resistance drift, on the other hand,is a phenomenon according to which the resistivity of the amorphous phase of

chalcogenide materials increases in time. Drift has been attributed to structural

relaxation and stress release in the amorphous matrix ,and is particularly detrimental

in multilevel cell storage, because random fluctuations of the programmed resistance

of closely-spaced levels may cause them to overlap and thus lead to decoding errors.

By means of a prototype chip platform we demonstrate four levels-per-cell

storage at large scale. We then illustrate the effect of drift, which causes rapid

deterioration of performance in conventional, reference-cell based detection schemes.


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Finally, we present a new drift-tolerantmodulation coding scheme for MLC PCM and

demonstrate reliable storage of data for over 30 days at room temperature, with raw

bit error rates in the order of 10-5

.


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Chapter 2

PCM HISTORY AND BACKGROUND

In the 1960s Stanford R. Ovshinsky of Energy Conversion Devices first

explored the properties of chalcogenide glasses as a potential memory technology. In

1969, Charles Sie published a dissertation, at Iowa State University that both

described and demonstrated the feasibility of a phase change memory device by

integrating chalcogenide film with a diode array. A cinematographic study in 1970

established that the phase change memory mechanism in chalcogenide glass involves

electric-field-induced crystalline filament growth, In the September 1970 issue of

Electronics, Gordon Moore - co-founder of Intel -published an article on the

technology. However, material quality and power consumption issues prevented

commercialization of the technology. More recently, interest and research have

resumed as flash and DRAM memory technologies are expected to encounter scaling

difficulties as chip lithography shrinks. A cross-section of two PRAM memory cells.

One cell is in low resistance crystalline state, the other in high resistance amorphousstate.

The crystalline and amorphous states of chalcogenide glass have dramatically

different electrical resistivity, and this forms the basis by which data are stored. The

amorphous, high resistance state is used to represent a binary 0, and the crystalline,

low resistance state represents a 1. Chalcogenide is the same material used in re-

writable optical media (such as CD-RW and DVD-RW). In those instances, the

material's optical properties are manipulated, rather than its electrical resistivity, as

chalcogenide's refractive index also changes with the state of the material.

Although PRAM has not yet reached the commercialization stage for

consumer electronic devices, nearly all prototype devices make use of a chalcogenide

alloy of germanium, antimony and tellurium (GeSbTe) called GST. The stoichiometry

or Ge:Sb:Te element ratio is 2:2:5. When GST is heated to a high temperature (over

600C), its chalcogenide crystallinity is lost. Once cooled, it is frozen into an


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amorphous glass-like state and its electrical resistance is high. By heating the

chalcogenide to a temperature above its crystallization point, but below the melting

point, it will transform into a crystalline state with a much lower resistance. The time

to complete this phase transition is temperature-dependent. Cooler portions of the

chalcogenide take longer to crystallize, and overheated portions may be remelted.

Commonly, a crystallization time scale on the order of 100 ns is used. This is longer

than conventional volatile memory devices like modern DRAM, which have a

switching time on the order of two nanoseconds.

In August 2004, Nanochip licensed PRAM technology for use in MEMS

(micro-electric-mechanical-systems) probe storage devices. These devices are notsolid state. Instead, a very small platter coated in chalcogenide is dragged beneath

many (thousands or even millions) of electrical probes which can read and write the

chalcogenide. Hewlett-Packard's micro-mover technology can accurately position the

platter to 3 nm so densities of more than 1 Tbit (125 GB) per square inch will be

possible if the technology can be perfected. The basic idea is to reduce the amount of

wiring needed on-chip; instead of wiring every cell, the cells are placed closer

together and read by current passing through the MEMS probes, acting like wires.

This approach bears much resemblance to IBM's Millipede technology.

In September 2006, Samsung announced a prototype 512 Mb (64 MB) device

using diode switches.[10] The announcement was something of a surprise, and it was

especially notable for its fairly high density. The prototype featured a cell size of only

46.7 nm, smaller than commercial Flash devices available at the time. Although Flash

devices of higher capacity were available (64 Gb, or 8 GB, was just coming to

market), other technologies competing to replace Flash generally offered lower

densities (larger cell sizes). The only production MRAM and FeRAM devices are

only 4 Mb, for example. The high density of Samsung's prototype PRAM device

suggested it could be a viable Flash competitor, and not limited to niche roles as other

devices have been. PRAM appeared to be particularly attractive as a potential

replacement for NOR Flash, where device capacities typically lag behind those of

NAND Flash devices. (State-of-the-art capacities on NAND passed 512 Mb some

time ago.) NOR Flash offers similar densities to Samsung's PRAM prototype and


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already offers bit addressability (unlike NAND where memory is accessed in banks of

many bytes at a time).

Samsung's announcement was followed by one from Intel and

STMicroelectronics, who demonstrated their own PCM devices at the 2006 Intel

Developer Forum in October.[11] They showed a 128 Mb part that recently began

manufacture at STMicroelectronics's research fab in Agrate, Italy. Intel stated that the

devices were strictly proof of concept, but they expect to start sampling within

months, and have widespread commercial production within a few years. Intel

appears to be aiming their PCM products at the same market as Samsung.

PCM is also a promising technology in the military and aerospace industries

where radiation effects make the use of standard non-volatile memories such as Flash

impractical. PCM memory devices have been introduced by BAE Systems, referred to

as C-RAM, claiming excellent radiation tolerance (rad-hard) and latchup immunity.

Additionally, BAE claims a write cycle endurance of 108, which will allow it to be a

contender for replacing PROMs and EEPROMs in space systems.

In February 2008, Intel engineers, in cooperation with STMicroelectronics,

revealed the first multilevel (MLC) PCM array prototype. The prototype stored two

logical bits in each physical cell, effectively 256 Mb of memory stored in a 128 Mb

physical array. This means that instead of the normal two statesfully amorphous

and fully crystallinean additional two distinct intermediate states represent different

degrees of partial crystallization, allowing for twice as many bits to be stored in the

same physical area on the chip.

Also in February 2008, Intel and STMicroelectronics began shipping

prototype samples of their first PCM product released to customers. The 90 nm, 128

Mb (16 MB) product is called Alverstone.

In April 2010, Numonyx announced the Omneo line of 128-Mbit NOR-

compatible phase-change memories and Samsung announced shipment of it 512 Mb


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phase-change RAM (PRAM) in a multi-chip package (MCP) for use in mobile

handsets by Fall 2010.

In June 2011, IBM announced that they had created stable, reliable, multi-bit

phase change memory with high performance and stability.


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Chapter 3

PCM TECHNOLOGY

The PCM storage element is comprised of two electrodes separated by a

resistive heater and a chalcogenide, the phase change material as shown in Figure 3.1.

Ge2Sb2Te5 (GST) is most commonly used, but other chalcogenides over higher

resistivity and improves the device's electrical characteristics. Nitrogen doping

increases resistivity and lowers programming current while GS offers lower latency

phase changes.

Fig 3.1: Storage element with heater and chalcogenide between electrodes.

Phase changes are induced by injecting current into the resistor junction and

heating the chalcogenide. Current and voltage characteristics of the chalcogenide are

identical regardless of its initial phase, which lowers programming complexity and

latency. The amplitude and width of the injected current pulse determine the

programmed state.


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Fig 3.2: Cell structure with storage element and BJT access device.

Phase change memory cells are 1T/1R devices, comprised of the resistive

storage element and an access transistor (Figure 1). Access is typically controlled by

one of three devices: field effect transistor (FET), bipolar junction transistor (BJT), or

diode. In future, FET scaling and large voltage drops across the cell will adversely

a_ect gate oxide reliability for unselected word lines. BJTs are faster and expected to

scale more robustly without this vulnerability. Diodes occupy smaller areas and

potentially enable greater cell densities, but require higher operating voltages.

3.1 Writes

The access transistor injects current into the storage material and thermally

induces phase change, which is detected during reads. Logical data values are

captured by the resistivity of the chalcogenide. A high, short current pulse increases

resistivity by abruptly discontinuing current, quickly quenching heat generation, and

freezing the chalcogenide into an amorphous state (RESET). A moderate, long current

pulse reduces resistivity by ramping down current, gradually cooling the chalcogenide

and inducing crystal growth (SET). Requiring longer current pulses, SET latency


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determines write performance. Requiring higher current pulses, RESET energy

determines write power.

Cells that store multiple resistance levels might be implemented by leveraging

intermediate states, in which the chalcogenide is partially crystalline and partially

amorphous . Smaller current slopes (i.e., slow ramp down) produce lower resistances

and larger slopes (i.e. fast ramp down) produce higher resistances. Varying slopes

induce partial phase transitions and/or change the size, shape of the amorphous

material produced at the contact area, giving rise to resistances between those

observed from fully amorphous or fully crystalline chalcogenide. The difficulty and

high latency cost of di_erentiating between a large number of resistances may

constrain such multi-level cells (MLC) to a small number of bits per cell.

3.2 Wear and Endurance

Writes are the primary wear mechanism in phase change memory. When

injecting current into a volume of phase change material, thermal expansion and

contraction degrades the electrode-storage contact, such that programming currents

are no longer reliably injected into the cell. Since material resistivity is highly

dependent on current injection, current variability causes resistance variability. This

greater variability degrades the read window, the difference between programmed

minimum and maximum resistance.

Write endurance, the number of writes performed before the cell cannot be

programmed reliably, ranges from 1E+04 to 1E+09. Write endurance depends on

process and differs across manufacturers. Relative to Flash, PCM is likely to exhibit

greater write endurance by several orders of magnitude (e.g., 1E+07 to 1E+08). TheITRS roadmap projects improved endurance of 1E+12 writes at 32nm. With wear

reduction and leveling techniques, write limits may not be exposed to the system

during a memory's lifetime.

3.3 Reads

Prior to reading the cell, the bitline is precharged to the read voltage. Thewordline is active low when using a BJT access transistor (Figure 3.2. If a selected


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cell is in a crystalline state, the bitline is discharged with current owing through the

storage element and access transistor. Otherwise, the cell is in an amorphous state,

preventing or limiting bit line current.

3.4 Scalability

As process technologies scale and heating contact areas shrink, programming

current scales linearly. As the contact area decreases with feature size, thermal

resistivity increases and the volume of phase change material that must be melted to

completely block current ow decreases. Speci_cally, as feature size scales down

(1=k), contact area decreases quadratically (1=k2). Reduced contact area causes

resistivity to increase linearly (k), which causes programming current to decrease

linearly (1=k). These e_ects enable, not only smaller storage elements, but also

smaller access devices for current injection. At the system level, scaling translates into

lower memory subsystem energy. This PCM scaling mechanism has been

demonstrated in a 32nm device prototype. As a scalable DRAM alternative, PCM

could provide a clear roadmap for increasing main memory density and capacity.

3.5 PCM Characteristics

To realize the vision of PCM as a scalable memory, however, PCM

disadvantages relative to DRAM must _rst be understood and overcome. Table 1

shows derived technology parameters from nine prototypes published in the past _ve

years by multiple semiconductor manufacturers [13]. Access latencies of up to 150

nanoseconds are several times slower than those of DRAM. At present 90nm

technology nodes, PCM writes require energy intensive current injection. More over,

writes induce thermal expansion and contraction within the storage element,

degrading injection contacts and limiting endurance to hundreds of millions of writes

per cell at current processes. Prototypes implement 9 to 12F2 PCM cells using BJT

access devices, up to 50 percent larger than 6 to 8F2 DRAM cells. These limitations

currently position PCM as a Flash replacement; in this market, PCM properties are

drastic improvements. For a DRAM alternative, however, we must architect PCM forfeasibility in main memory within general-purpose systems.


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3.6 PCM ATTRIBUTES AND CAPABILITIES

Phase Change Memory blends the attributes commonly associated with NOR-

type flash, memory NAND-type flash memory, and RAM or EEPROM. These

attributes are summarized in the chart in table3.1.

Table3.1: PCM Attributes:

Attributes PCM DRAM NAND NOR

Scaling Longest term 32nm 25nm 32nm

Bit Alterable yes yes no no

Non-volatile yes no yes yes

Random read ~=NOR 50ns 25000ns 100ns

Write speed >5MB/s 100MB/s >10MB/s 1MB/s

Endurance 106+ unlimited 104 105

Power ~= Flash high low Low

Data retention Cycling

independent

ms F(cycles) F(cycles)

Bit-alterableLike RAM or EEPROM, PCM is bit alterable. Flash technology requires a

separate erase step in order to change information. Information stored in bit-alterable

memory can be switched from a one to zero or zero to a one without a separate erase

step.


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Non-volatileLike NOR flash and NAND flash, PCM is nonvolatile. RAM, of course,

requires a constant power supply, such as a battery backup system, to retain

information. DRAM technologies also suffer from susceptibility to so-called soft

errors or random bit corruption caused by alpha particles or cosmic radiation1. Early

testing results conducted by Intel on multimegabit PCM arrays for long term data

retention show excellent results.

Read speedLike RAM and NOR-type flash, the technology features fast random access

times. This enables the execution of code directly from the memory, without an

intermediate copy to RAM. The read latency of PCM is comparable to single bit per

cell NOR flash, while the read bandwidth can match DRAM. In contrast, NAND flash

suffers from long random access times on the order of 10s of microseconds that

prevent direct code execution.

Write/erase speed

PCM is capable of achieving write speeds like NAND, but with lower latency

and with no separate erase step required. NOR flash features moderate write speeds

but long erase times. As with RAM, no separate erase step is required with PCM, but

the write speed (bandwidth and latency) does not match the capability of RAM today.

The capability of PCM is expected, however, however, to improve with each process

generation as the PCM cell area decreases.

ScalingScaling is the fifth area where PCM will offer a difference. Both NOR and

NAND rely on memory structures which are difficult to shrink at small lithos. This is

due to gate thickness remaining constant and the need for operation voltage of more


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than 10V while the operation of CMOS logic has been scaled to 1V or even less. This

scaling effect is often referred to as Moores Law, where memory densities double

with each smaller generation. With PCM, as the memory cell shrinks, the volume of

GST material shrinks as well, providing a truly scalable solution.


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Chapter 4

PCM PROTOTYPE

This section describes the phase-change memory prototype environment that

was used in this work. Fig. 1 shows a schematic of the phase-change memory array

and cell. The memory array is organized in word-lines (WLs) and bit lines (BLs), with

NMOS FET as the selection device. The PCM cell consists of the active phase-change

element (PCE), sandwiched between a top and a bottom electrode, which is integrated

on top of the access device. The memory cell is of mushroom type with doped

Ge2Sb2Te5 as the phase-change material. It was integrated in 90-nm CMOS

technology using the key-hole process described in. A TEM picture of the PCM cell is

shown in Fig. 4.1.

Fig 4.1 Schematic showing the memory array organized in word-lines and bit-lines,

and the memory cell with the phase-change element and the FET access device. A

TEM picture of the PCM cell is also presented.

The PCM cells were integrated into a prototype chip serving as a

characterization platform. In addition to the PCM cell array (2 2 Mcells), the


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memory chip, illustrated in Fig. 4.2, contains the addressing, readout, and

programming circuitry. In readout, the selected bit-line is biased to a constant voltage

(typically 200-400 mV) by a voltage regulator. The sensed current, iread, is integrated

by a capacitor, and the resulting voltage is then digitized by an on-chip 8-bit cyclic

analog-to-digital converter (ADC). The readout characteristic is calibrated via the use

of on-chip reference polysilicon resistors. For programming, a voltage generated off-

chip is converted on-chip into a programming current, iprog. This current is then

mirrored into the selected BL for the desired duration of the programming pulse. The

memory chip was fabricated in a 90-nm CMOS process with 4 levels of copper

interconnects and occupies 2.7 x 2.2 mm2.

Fig. 4.2: Prototype memory chip: circuit diagram

The prototype PCM chip is controlled by a FPGA that implements the

necessary logic in order to access the memory array and the on-chip electronics. The

FPGA also implements the read and write algorithms for MLC operation and controls

the off-chip peripherals, including power supplies, reference voltages, and external

digital-to-analog and analog-to-digital converters. Finally, the FPGA implements a

data acquisition module for rapid collection of measurements and diagnostics.


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Fig. 4.3 Prototype memory chip: chip micrograph

Table 4.1 the chip specifications.

CHIP SPECIFICATIONS

size 2.7x2.2 mm2

technology 90nm CMOS

interconnect 4 levels of Cu

PCM Doped GST

SupplyDigital:1.2v

PCM & analog:2.5v

Capacity 2x2 Mcells


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Chapter 5

MULTILEVEL CELL CONCEPT

PCM is a memory technology that stores data by programming and reading the

resistance of the memory elements. Although earlier research on PCM was focused on

single bit operation, recently, the focus of PCM research has been moving towards

MLC operation, mainly to keep up with the increasing demand for low cost memory.

Figure 4 shows the concept of MLC devices that can store 2 bits/cell and 4 bits/cell.

The resistance range of each level decreases exponentially as the number of bits per

cell increases. The maximum number of bits that can be stored in a given MLC device

is a function of precision in reading technology, device data integrity, and precision in

writing. As technology improves, the number of bits in MLC devices is expected to

increase. The ITRS roadmap projects that PCM cells will have 4 bits/cell by 2012.

Fig 5.1: Concept of Multi-Level PCM (Figure not to scale)


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Chapter 5

MULTILEVEL CELL STORAGE

Multilevel PCM is achieved by programming the memory cell into

intermediate resistance levels between RESET and SET. The programming space is

defined by the characteristic programming curve, which quantifies the change of the

cell resistance as a function of the programming current or voltage. Fig. 5.1 shows the

typical programming curve obtained with rectangular programming pulses ofdecreasing amplitude, when programming starts from RESET. Accurate control of the

cell current is necessary in order to achieve multiple resistance levels. In practice, an

iterative programming scheme is used to account for cell and access device variability

issues that manifest themselves in large memory arrays due to material and/or process

variations, and give rise to different programming characteristics among cells. Fig. 5.1

illustrates the concept of iterative multilevel programming. Starting from a level-

dependent best-guess programming pulse, the algorithm uses a sequence of write-

and-verify steps in order to program the memory cell to the target resistance value. At

each step, the algorithm adjusts the programming current based on the error between

the target and the programmed resistance, therefore tracking the programming curve

of each cell.

The example of Fig. 5.1 corresponds to a multilevel programming sequence, in

which the algorithm operates on the partial-RESET regime of the programming curve,

i.e., melting pulses are invoked in order to partially amorphize the material.


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Fig 5.1 Schematic illustrating the basic iterative programming concept using a

sequence of adaptive write-and-verify steps.

5.1 Four levels-per-cell Programming

A 200 kcell sub-unit of the prototype PCM array is programmed at 4 levels-

per-cell. The target resistance levels were defined in the average programming curve

of the array shown in Fig. 5.1 The two corner levels are programmed with single

shot RESET and SET pulses respectively, whereas the two intermediate levels are

programmed using iterative write and verify steps. Each programming pulse is a box-

type rectangular pulse. The RESET pulse is a programming pulse of high current,

while for SET a trapezoidal pulse of long trailing edge is used to allow sufficient

crystallization. Table 5.1 lists the definition of the two intermediate levels, in read

current, along with convergence statistics. The small number of iterations and high

rate of convergence attest to the effectiveness of the iterative write-and-verify

algorithm to achieve multilevel programming.


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Table 5.1: Level allocation for MLC programming

Level Itarget ImarginAvg no of

iterationsConvergence rate

0 Imin n/a n/a n/a

1 8.3 uA 0.6 uA 2.7 98.2%

2 12.8 uA 0.6 uA 5.6 99.5%

3 Imax n/a n/a n/a


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Chapter 6

DRIFT OF PROGRAMMED LEVELS OF MULTI LEVELPCM OVER TIME

In PCM, the low-field resistance of the memory cell increases over time, a

phenomenon known as resistance drift. Drift affects the stability of the electrical

behavior of the device, and thus the reliability of MLC storage. In order to investigate

the evolution of the programmed resistance levels due to drift, the programmed array

was monitored at different time instances. Fig. 4 shows cumulative histograms of the

programmed resistance distributions over time. One observation from these plots is

that drift affects all stored levels starting at very short time scales, i.e., s after

programming. The spread of each resistance distribution is due to read noise, cell

variability and non-uniform drift dynamics across cells.

Fig. 6.1. Time evolution of programmed resistance distributions of 200 kcells due to

drift: (a) as programmed, and (b) 40 us, (c) 1000 s, (d) 46,000 s after programming.


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From the measured data of Fig.6.1 one can estimate the average drift behavior

as a function of the programmed resistance. Using the drift power-law model , i.e.,

R(t)=R(t0) = (t=t0)v, one can calculate the evolution of the programmed resistance

levels over time, and also extract the average drift exponent v for each resistance level

(Fig. 6.2). Here, t0 is set to 40 s after programming.

Fig. 6.2. Evolution of mean programmed resistance values over time and extracted

mean drift exponent according to the resistance drift power-law model.


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Chapter 7

DRIFT-TOLERANT PCM

In this section, a new method to enhance the reliability of PCM devices in the

presence of drift is presented. As illustrated in the previous section, drift causes the

distributions of programmed resistance levels to shift from their initial positions after

programming, and also to move further apart, thus increasing the average resistance

margin between adjacent levels over time. At the same time, the spread of each

distribution does not change appreciably with time. Therefore, in order to reliably

detect the stored levels, appropriate level thresholds would have to be placed between

distributions of adjacent levels, and those thresholds would have to be adjusted over

time according to the shift of levels due to drift. In practice, adjustment of the

thresholds may be achieved by using reference cells, i.e., cells with known stored

data, used to estimate the changing resistance values over time.

Despite the use of adaptive level thresholds, the bit error rate in MLC PCM

deteriorates over time, although the noise margin between adjacent levels tends to

increase. This is because drift is a random process and thus the increase of the

resistance of each cell evolves in a stochastic manner. Moreover, the rate of increase,

i.e., the drift exponent v, is itself a random variable. While it is true that the average

drift exponent increases with the cell resistance, significant variability is typically

observed around the mean values. As a result of this, a small number of cells from

each resistance distribution exhibit a distinctly different drift exponent from the rest.

The resistance vs time trajectories of two such cells programmed in the adjacentlevels 2 and 3 are shown in Fig. 6. It can be seen that, although the cell-levels after

programming are apart, they eventually shift closer together and finally cross each

other at later time instants, due to drift exponents deviating from the mean behavior.

Therefore, in practice, the error-rate in PCM increases over time due to drift. This is a

phenomenon that cannot be mitigated simply by adapting level thresholds. One way

to deal with it is to enforce redundancy in the form of modulation coding.

The main idea of the proposed coding technique lies in the fact that, in the

majority of cases, the relative order of cells programmed in different resistance levels


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does not change due to drift. To this end, information is encoded in the relative order

of cell resistance levels within a small group of cells that forms the codeword. In most

cases drift does not affect this ordering, thus the codeword can be correctly decoded.

A decoding error will occur only when two resistance levels corresponding to two

cells of the same codeword cross each other in the course of time, for example due to

drift behavior deviating from the average one. However, because of the small number

of cells in a codeword, such events are quite rare, giving rise to superior performance,

which comes at the expense of some capacity loss.

Fig. 7.1 Resistance vs. time trajectories of two cells programmed at levels 2 and

3. The levels cross each other over time due to drift coefficients deviating from the

average ones. Dashed and dash-dotted lines depict the average resistance-time

trajectories of all cells programmed at levels 2 and 3, respectively.

To assess the performance of the proposed drift-tolerant coding scheme, data

were encoded and then stored in a sub array of 200 kcells of the PCM prototype chip

described above. The codeword length was 7, and the rate of the particular code used

was 1.57 bits/cell. Other codes can be constructed that have higher rate, at the expense

of encoder/decoder complexity or performance. Two detection methods were


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considered. The first method treats the stored data as uncoded, and applies appropriate

level thresholds to detect the stored levels. The thresholds are adaptive, and are

calculated at each time instant based on the stored levels in a collection of reference

cells. For fairness of comparison, the number of cells that were used as reference cells

corresponds to the same amount of capacity loss, i.e., redundancy, as the proposed

code. The second method decodes the code applied to the cell array by using a

combination of minimum-distance decoding and a sorting operation. The performance

of the two methods is illustrated in Fig. 7.2, where REF-CELL and CODE denote

the first and the second detection method, respectively. Although the two decoding

methods have the same overhead, drift-tolerant coding is superior by more than one

order of magnitude in error-rate. Even more importantly, the performance of driftcoding appears to degrade much more gracefully with time than that of the reference-

cell-based scheme, suggesting that it is significantly more tolerant to drift.

Fig. 7.2. Bit-error-rate of reference-cell and the proposed coding methods on a

PCM array of 200 kcells. Measurements have been performed starting at 40 s after

programming and for extended periods of time.


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It is quite impressive that drift-tolerant coding exhibits a raw error rate around

105 even after 37 days at room temperature, a result that cannot be matched by a

reference cell- based scheme. If the error rates are extrapolated, by assuming a linear

trend of bit-error-rate vs. log-time, then it appears that excellent performance, i.e., raw

error rates well below 104, may be maintained over extended periods of time by using

the proposed drift-tolerant coding method. Simple, low-redundancy error-correction

codes could then be sufficient to bring the overall error rate down to levels around

1015 or less, which are required for practical memory devices. Methods that enhance

reliability, such as the one proposed, are key stepping stones in the path towards

enabling practical memory devices based on PCM. Combined with advances in

materials and process technology, they will ensure that a viable roadmap of superiorPCM devices can be sustained.


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Chapter 7

MARKET APPLICATIONS OF PCM

Target products for PCM technology address both stand alone memory and embedded

memory. Product applications include:

NOR Flash Memory - PCM is a direct replacement for this very popular type

of nonvolatile memory (NVM) used primarily for code storage. PCM also

offers the performance capability of execute In Place (XIP) operation as NOR

flash for improved system level performance, but with improved cycle life,

reduced programming time, lower power, smaller cell size, reduced

manufacturing cost and enhanced scalability.

Unified Memory - PCM, with its unique NVM performance attributes, has

the ability to create a new class of NVM that combines the capability of other

dissimilar memory technologies (volatile and non-volatile) into a single

solution. In particular, PCMs capability of direct bit overwrite (no erase

required) and high speed R/W performance coupled with high cycle life

endurance, allows it to replace a previous dual chip solution of DRAM and

Flash with a single unified memory solution for lower cost, reduced power and

smaller form factor.

DRAM (Dynamic Random Access Memory) - PCM can displace a significant

amount of DRAM in both mobile and PC/server applications. PCM today

already offers a cell size smaller than DRAM and with PCMs inherentenhanced scalability over DRAM; the cost advantage of PCM will increase

with time. As more volatile DRAM is displaced by non-volatile PCM,

significant power savings will be realized, providing extended battery life in

mobile applications and significantly reduced power consumption in PC and

server applications. Initially, PCM will not be targeted as a direct replacement

for all DRAM, but rather to displace a large percentage of DRAM in

applications that dont require the infinite DRAM cycle endurance and can

benefit the most from the dramatically reduced power consumption of PCM.


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NAND Flash Memory is the largest growth area of NVM due primarily to its

very low cost and continued steep declining cost curve. However, as NAND

Flash scales, the random R/W speed performance and cycle endurance

continues to degrade, accentuating the need and size of a buffer memory

where PCM would be an ideal memory solution. Longer term, when/if NAND

Flash cost reduction slows down due to scaling limits (such as reaching a

finite number of electrons), there have been innovative proposals to

incorporate PCM in multi-layer cross point architectures to be competitive,

even in the lowest cost NVM applications.

Embedded Memory in microprocessors, microcontrollers and System-on-a-

Chip (SOC) applications, PCMs competitive advantage in this very importantand growing segment of the semiconductor device market comes from its

scalability, small cell size, and ease of integration into existing process flows

for logic devices. PCMs capability to be embedded in these devices enables

the high level of integration of memory and logic functions that will be

necessary for both high-performance computing and for a wide range of low-

cost embedded microcontroller, microprocessor, and SOC applications in

consumer and automotive electronic devices.

Field Programmable Logic Devices (FPLDs) and Field Programmable

Gate Arrays (FPGAs) are an important segment of the MOS logic market.

These devices are widely used in networking infrastructure, video games,

computer chipsets, etc. The ability to use PCM technology will permit the

manufacture of nonvolatile, high cycle-life reprogrammable devices. This will

provide a key competitive advantage over mask-programmable, one-time

programmable, volatile SRAM reprogrammable, and Flash reprogrammable

solutions.

Radiation-hard applications are a natural fit for PCM due to the atomic

structural nature of memory data storage. Unlike charge-storage based

memory technologies, PCM stores the phase of a material, which is effectively

immune to radiation. Thus, PCM is an ideal candidate for military, space, and

other radiation sensitive applications


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Chapter 7

CONCLUSION

The reliability of multilevel-cell phase-change memory is adversely affected

by resistance drift. Reference cells may be used to cope with the shift of resistance

levels over time, however their effectiveness is limited due to the stochastic nature of

drift. A new drift-tolerant coding method is proposed that is significantly robust to

drift, by encoding information in the relative order of resistance levels in a codeword.

The new method is demonstrated, in a test memory chip, to be vastly superior to

reference-cell based schemes of the same redundancy, thus offering largely enhanced

reliability for MLC PCM over extended periods of time.

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ruff justified