S3C6410XType Circuit Design Guide Rev1[1].00

Confidential Proprietary of Samsung Electronics Co., Ltd Copyright © 2008 Samsung Electronics, Inc. All Rights Reserved

Circuit Design Guide S3C6410X

RISC Microprocessor

July 18, 2008

REV 1.00

S3C6410_CIRCUIT DESIGN GUIDE REV 1.00

Important Notice

The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication. Samsung assumes no responsibility, however, for possible errors or omissions, or for any consequences resulting from the use of the information contained herein.

Samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes.

This publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of Samsung or others.

Samsung makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation any consequential or incidental damages.

"Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by the customer's technical experts.

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S3C6410X RISC Microprocessor Circuit Design Guide, Revision 1.00

Copyright © 2008-2008 Samsung Electronics Co.,Ltd.

All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior written consent of Samsung Electronics Co.,Ltd.

Samsung Electronics Co., Ltd. San #24 Nongseo-Dong, Giheung-Gu Yongin-City Gyeonggi-Do, Korea 446-711

Home Page: http://www.samsungsemi.com/ E-Mail: [email protected]

Printed in the Republic of Korea

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Revision History Revision No Description of Change Refer to Author(s) Date

0.00 - Initial Release for review - W.J.JANG June 2, 2008 1.00 - Public Release - H.M.NOH July 18, 2008

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Table of Contents

1. Overview.................................................................................................................................................... 6 1.1 S3C6410 Pin Description ............................................................................................................... 6 1.2 Pin Power Domain.......................................................................................................................... 14 1.3 Booting Option ................................................................................................................................ 15 1.4 Feature of the IROM Boot mode .................................................................................................... 16 1.5 Recommend Operating Conditions ................................................................................................ 17 1.6 Difference of S3C6410 and S3C6400 ............................................................................................ 18

2. MEMORY MAP ......................................................................................................................................... 20 2.1 Maximum Address range of the Memory Port0.............................................................................. 20 2.2 Maximum Address range of the Memory Port1.............................................................................. 20

3. Syscon....................................................................................................................................................... 21 3.1 Power.............................................................................................................................................. 21 3.1.1 Power On Sequence ................................................................................................................... 21 3.1.2 Power Off Sequence ................................................................................................................... 24 3.1.3 Power Scheme Diagram.............................................................................................................. 25 3.1.4 Circuit Guide for DVS Scheme.................................................................................................... 26 3.2 Clock............................................................................................................................................... 27 3.2.1 PLL .............................................................................................................................................. 27 3.3 Reset .............................................................................................................................................. 29 3.3.1 HardWare Reset.......................................................................................................................... 29

4. MEMORY SUBSYSTEM........................................................................................................................... 30 5. DRAM Controller ....................................................................................................................................... 31

5.1 Memory Port0 ................................................................................................................................. 31 5.2 Memory Port1 ................................................................................................................................. 31 5.3 DRAM Initialize Sequence.............................................................................................................. 33 5.4 PCB LAYOUT GUIDELINES FOR DDR ........................................................................................ 36

6. SROM Controller ....................................................................................................................................... 39 6.1 Address Connection ....................................................................................................................... 39 6.2 SRAM/ROM Interface Examples .................................................................................................... 39

7. OneNAND Controller................................................................................................................................. 41 7.1 Overview......................................................................................................................................... 41 7.2 Signal Description........................................................................................................................... 41 7.3 Circuit Diagram Example................................................................................................................ 41 7.4 Caution .......................................................................................................................................... 42

8. NAND Flash .............................................................................................................................................. 43 8.1 Interface for Multi Chip Select NAND ............................................................................................. 43

9. CF Controller ............................................................................................................................................. 44 9.1 CF Interface .................................................................................................................................... 44 9.2 Cautions.......................................................................................................................................... 45 9.3 ATA 2 Slot operation guide............................................................................................................. 46

10. GPIO........................................................................................................................................................ 48 11. DMA Controller........................................................................................................................................ 54 12. VECTORED INTERRUPT CONTROLLER............................................................................................. 55 13. SECURITY SUB-SYSTEM...................................................................................................................... 56 14. DISPLAY CONTROLLER ....................................................................................................................... 57 15. POST PROCESSOR............................................................................................................................... 61 16. TV SCALER ............................................................................................................................................ 62 17. TV ENCODER......................................................................................................................................... 63 18. GRAPHICS 2D ........................................................................................................................................ 65 19. IMAGE ROTATOR .................................................................................................................................. 66 20. CAMERA INTERFACE............................................................................................................................ 67

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20.1 CAMIF INPUT............................................................................................................................... 67 20.2 Signal Description......................................................................................................................... 67

21. MULTI-FORMAT VIDEO CODEC........................................................................................................... 69 22. JPEG CODEC ......................................................................................................................................... 70 23. MODEM INTERFACE ............................................................................................................................. 71

23.1 Pin Description ............................................................................................................................. 71 23.2 Pin Connection Example .............................................................................................................. 72 23.3 Caution ......................................................................................................................................... 72

24. HOST INTERFACE................................................................................................................................. 73 25. USB Host................................................................................................................................................. 74

25.1 Power Domain .............................................................................................................................. 74 25.2 Circuit Diagram Example.............................................................................................................. 74 25.3 USB Host connection ................................................................................................................... 74 25.4 Caution ......................................................................................................................................... 74

26. USB 2.0 HS OTG .................................................................................................................................... 75 26.1 Power Domain .............................................................................................................................. 75 26.2 Circuit Diagram Example.............................................................................................................. 75 26.3 USB PLL Specification ................................................................................................................. 77 26.4 USB SIGNAL ROUTING .............................................................................................................. 77

27. SD/MMC HOST CONTROLLER ............................................................................................................. 79 28. MIPI HSI INTERFACE CONTROLLER................................................................................................... 82 29. SPI........................................................................................................................................................... 83 30. IIC-BUS INTERFACE.............................................................................................................................. 84

30.1 Pin Description ............................................................................................................................. 84 30.2 Equation of the pull-up resistor value ........................................................................................... 84

31. UART....................................................................................................................................................... 85 32. PWM TIMER ........................................................................................................................................... 86 33. RTC ......................................................................................................................................................... 87 34. WATCHDOG TIMER............................................................................................................................... 88 35. AC97 CONTROLLER.............................................................................................................................. 89

35.1 AC97 Signal Description............................................................................................................... 89 35.2 Audio Ports ................................................................................................................................... 89 35.3 Signal Description......................................................................................................................... 89

36. IIS BUS CONTROLLER.......................................................................................................................... 90 36.1 Signal Description......................................................................................................................... 90 36.2 Audio Port ..................................................................................................................................... 90 36.3 External Clock Source .................................................................................................................. 90 36.4 Connection Example .................................................................................................................... 90

37. PCM BUS CONTROLLER ...................................................................................................................... 92 37.1 Signal Description......................................................................................................................... 92 37.2. Audio Port .................................................................................................................................... 92 37.3 External Clock Source .................................................................................................................. 92 37.4 Connection Example .................................................................................................................... 93

38. IRDA CONTROLLER .............................................................................................................................. 94 39. ADC&TOUCH SCREEN INTERFACE.................................................................................................... 95 40. KEYPAD INTERFACE ............................................................................................................................ 96 41. IIS MULTI AUDIO INTERFACE .............................................................................................................. 97

41.1 Signal Description......................................................................................................................... 97 41.2 Audio Ports ................................................................................................................................... 97 41.3 External Clock Source .................................................................................................................. 98 41.4 Connection Example .................................................................................................................... 98

42. GRAPHIC 3D .......................................................................................................................................... 99

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1. Overview

1.1 S3C6410 Pin Description Check Items Recommendations

Signal Used Unused Check

Shared Memory Port 0 (SROMC/OneNAND/NAND/ATA)

Xm0BEn[1:0] Connect to Byte Enable of External device. Leave as a No Connect

Xm0CSn[5:0] Connect to Chip Select of External device.

* Xm0CSn3 is not used for SROMC at OneNAND/Modem Boot Mode

Leave as a No Connect

GPO[5:4] Using as GPIO Leave as a No Connect

Xm0ADDR[19:0] Connect to Address lines of External device. Leave as a No Connect

Xm0OEn Connect to Output Enable of External device. Leave as a No Connect

Xm0WEn Connect to Write Enable of External device. Leave as a No Connect

Xm0ADRVALID Connect to Address Valid pin of OneNAND Leave as a No Connect

Xm0SMCLK Connect to OneNAND Clock Leave as a No Connect

Xm0DATA[15:0] Connect to Data lines of External device. Leave as a No Connect

Xm0WAITn Connect to Wait signal of External device. 4.7Kohm pull-up resistor required. Leave as a No Connect

Connect to OneNAND Bank0 Ready Xm0RDY0_ALE Connect to NAND Flash or External device

Address Latch Enable Leave as a No Connect

Connect to OneNAND Bank1 Ready Xm0RDY1_CLE Connect to NAND Flash or External device

Command Latch Enable Leave as a No Connect

Connect to OneNAND Bank0 Interrupt Xm0INTsm0_FWEn

Connect to NAND Flash Write Enable Leave as a No Connect

Connect to OneNAND Bank1 Interrupt Xm0INTsm1_FREn

Connect to NAND Flash Read Enable Leave as a No Connect

Connect to OneNAND Reset. Xm0RPn_RnB Connect to NAND Flash Ready/Busy.

4.7Kohm pull-up resistor required. Leave as a No Connect

GPQ[6:2] Use as GPIO Leave as a No Connect

Xm0INTata Connect to Interrupt Request pin of CF Socket

(Indirect Path) Leave as a No Connect

Xm0RESETata Connect to CF Card Reset pin(Indirect Path) Leave as a No Connect

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Xm0INPACKata Connect to Input Ack pin of CF Socket(Indirect Path) Leave as a No Connect

Xm0REGata Connect to REG pin of CF Socket(Indirect Path) Leave as a No Connect

Xm0WEata Connect to Write Enable pin of CF Socket(Indirect Path) Leave as a No Connect

Xm0OEata Connect to Read Enable pin of CF Socket(Indirect Path) Leave as a No Connect

Xm0CData Connect to Card Detect pin of CF Socket Pull-up resistor is required(Indirect Path). Leave as a No Connect

Shared Memory Port 1 (SROMC/DRAM1)

Xm1CKE[1:0] Connect to DRAM Clock Enable Leave as a No Connect

Xm1SCLK, Xm1SCLKn Connect to DRAM Clock Leave as a No Connect

Xm1CSn[1:0] Connect to Chip Select of DRAM. Leave as a No Connect

Xm1ADDR[15:0] Connect to Address and bank select of DRAM. Leave as a No Connect

Xm1RASn Connect to DRAM Row Address Strobe. Leave as a No Connect

Xm1CASn Connect to DRAM Column Address Strobe. Leave as a No Connect

Xm1WEn Connect to DRAM Write Enable Leave as a No Connect

Xm1DATA[31:0] Connect to Data lines of External device. Leave as a No Connect

Xm1DQM[3:0] Connect to DRAM Data Mask. Leave as a No Connect

Xm1DQS[3:0] Connect to DRAM Data Strobe Leave as a No Connect

UART/IrDA/CF

XuRXD[1:0] Connect to UART Rx Data Lines Leave as a No Connect

XuTXD[1:0] Connect to UART Tx Data Lines Leave as a No Connect

XuCTSn[1:0] Connect to UART Clear To Send signal Leave as a No Connect

XuRTSn[1:0] Connect to UART Request To Send signal Leave as a No Connect

Connect to UART Rx Data Line.

Connect to IrDA Rx Data Line.

Connect to External DMA Request Line. XuRXD[2]

Connect to Address[0] of the ATA device.


Connect to UART Tx Data Line.

Connect to IrDA Tx Data Line.

Connect to External DMA Ack Line. XuTXD[2]



XuRXD[3] Connect to UART Rx Data Line. Leave as a No Connect

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Connect to IrDA Rx Data Line.

Connect to External DMA Request Line.

Connect to IIC device Clock.

1Kohm pull-up resistor required


Connect to UART Tx Data Line.

Connect to IrDA Tx Data Line.

Connect to External DMA Ack Line. XuTXD[3]

Connect to IIC device Data 1Kohm pull-up resistor required.


Connect to IrDA transceiver control signal

Connect to Camera Field signal. CF_Data_DIR/ XirSDBW

If necessary, use to control the Data Buffer Direction for ATA device


IIC Bus

Xi2cSCL Connect to IIC device Clock 1Kohm pull-up resistor is required. Leave as a No Connect

Xi2cSDA Connect to IIC device Data 1Kohm pull-up resistor is required Leave as a No Connect

SPI

XspiMISO[0] Connect to SPI device SPIMISO Leave as a No Connect

XspiMOSI[0] Connect to SPI device SPIMOSI Leave as a No Connect

XspiCLK[0] Connect to SPI device Clock Leave as a No Connect

XspiCS[0] Connect to SPI device Chip Select Leave as a No Connect

Connect to SPI device SPIMISO

Connect to MMC2 Card Command. 10Kohm pull-up resistor to VDD_MMC is required

XspiMISO[1]

Connect to IIS 5.1CH CODEC Data Output


XspiMOSI[1] Connect to SPI device SPIMOSI Leave as a No Connect

Connect to SPI device Clock

Connect to MMC2 Card Clock. XspiCLK[1]

Connect to IIS 5.1CH CODEC Data Output


Connect to SPI device Chip Select XspiCS[1]

Connect to IIS 5.1CH CODEC Data Output Leave as a No Connect

PCM/IIS/AC97

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Connect to PCM Serial Shift Clock

Connect to IIS CODEC Serial Clock XpcmDCLK[1:0]

Connect to AC97 Bit Clock


Connect to PCM reference clock(optional)

Connect to IIS CODEC System Clock XpcmEXTCLK[1:0]

Connect to AC97 Codec H/W Reset pin


Connect to PCM Sync indicating start of word.

Connect to IIS CODEC channel Clock XpcmFSYNC[1:0]

Connect to AC97 Codec SYNC pin


Connect to PCM Serial Data Input

Connect to IIS CODEC Data Input XpcmSIN[1:0]

Connect to AC97 CODEC Data Input pin


Connect to PCM Serial Data Output

Connect to IIS CODEC Data Output XpcmSOUT[1:0]

Connect to AC97 CODEC Data Output pin


USB Host

XuhDN Connect to USB Host Data Minus. 15Kohm Pull-down resistor is required.

Connect 15Kohm series resistor to GND.

XuhDP Connect to USB Hot Data plus . 15Kohm Pull-down resistor is required.

Connect 15Kohm series resistor to GND.

USB OTG

XusbDP Connect to USB Data pin DATA(+) Leave as a No Connect

XusbDM Connect to USB Data pin DATA(-) Leave as a No Connect

XusbXTI

Connect to Crystal XI signal if using Crystal. Connect to GND if using Oscillator.

Connect to 1M Ohm resistor between XusbXTI and XusbXTO (case of using Crystal)

Connect to GND.

Connect like left column in order to supply 48MHz clock for other IPs (USB Host, IrDA, HSMMC, SPI)

XusbXTO

Connect to Crystal/Oscillator XO signal

Connect to 1M Ohm resistor between XusbXTI and XusbXTO(case of using Crystal)

Connect to GND

Connect like left column in order to supply 48MHz clock for other IPs (USB Host, IrDA, HSMMC, SPI)

XusbREXT

Connect to External 44.2ohm(+/- 1%) resistor to GND


Connect like left column in order to supply 48MHz clock for other IPs (USB Host, IrDA, HSMMC,

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SPI)

XusbVBUS Connect USB mini-receptacle VBUS Leave as a No Connect

XusbID Connect USB mini-receptacle Identifier

Device Mode : leave as a no connect Leave as a No Connect

XusbDRVVBUS Connect to Drive Vbus for Off-Chip Charge Pump.

Device Mode : leave as a no connect Leave as a No Connect

External Interrupts

Connect to External Device XEINT[7:0]

Connect to Row signals of Keypad Leave as a No Connect

XEINT[15:8] Connect to External Device Leave as a No Connect

Host I/F / MIPI / Key I/F / ATA

Connect to Chip Select that driven by Modem XhiCSn

Connect to ATA Chip Enable0 Strobe Leave as a No Connect

Connect to Chip Select for LCD bypass main XhiCSn_main

Connect to ATA Chip Enable1 Strobe Leave as a No Connect

Connect to Chip Select for LCD bypass sub XhiCSn_sub

Connect to ATA Read strobe for I/O Mode Leave as a No Connect

Connect to Write Enable that driven by ModemXhiWEn

Connect to ATA Write strobe for I/O Mode Leave as a No Connect

Connect to Read Enable that driven by ModemXhiOEn

Connect to ATA Wait signal Leave as a No Connect

Connect to Interrupt Request pin to the ModemXhiINTR

Connect to CF Data DIR Leave as a No Connect

Connect to Address bus of Modem

Connect to Column signals of Keypad XhiADDR[7:0]

Connect to ATA Control Signal


Connect to Address bus of Modem XhiADDR[12:8]

Connect to ATA Control Signal Leave as a No Connect

Connect to Data bus of Modem

Connect to ATA Data[7:0] XhiDATA[7:0]

Connect to MIPI HIS I/F


Connect to Data bus of Modem XhiDATA[15:8]

Connect to Row signals of Keypad


10


Connect to ATA Data[15:8]

XhiDATA[17:16] Connect to Data bus for LCD bypass Leave as a No Connect

PWM

Connect to PWM Timer External Clock Input XpwmECLK

Connect to UART External Clock Input Leave as a No Connect

XpwmTOUT[1:0] Connect to External Device Timer Output Leave as a No Connect

Camera Interface

XciCLK Connect to Camera Master Clock Leave as a No Connect

XciHREF Connect to Camera Horizontal Synchronous Leave as a No Connect

XciPCLK Connect to Camera Pixel Clock Leave as a No Connect

XciVSYNC Connect to Camera Vertical Synchronous Leave as a No Connect

XciRSTn Connect to Camera Software Reset Leave as a No Connect

XciYDATA[7:0] Connect to Camera Pixel Data Lines Leave as a No Connect

TFT LCD Display Interface

XvVD[23:0] Connect to LCD Pixel Data Lines Leave as a No Connect

XvVCLK Connect to Pixel Clock signal Leave as a No Connect

XvVSYNC Connect to Vertical synchronous signal Leave as a No Connect

XvHSYNC Connect to Horizontal synchronous signal Leave as a No Connect

XvVDEN Connect to Data enable signal Leave as a No Connect

DAC

XdacVREF Connect 100nF capacitor to GND. Connect 100nF capacitor to GND.

XdacIREF Connect 6.49Kohm resistor to GND. Connect 6.49Kohm resistor to GND.

XdacCOMP Connect 100nF capacitor to VDDDAC. Connect 100nF capacitor to VDDDAC.

XdacOUT_0 Connect to Video AMP Leave as a No Connect

XdacOUT_1 Connect to Video AMP Leave as a No Connect

ADC

Connect to Analog signal

Xadc_AIN[7:4] Touch Panel Interface


If not use AIN[7], tie AIN [7] to VDDA_ADC or ADCTSC register must be setting to 0xd3.

Xadc_AIN[3:0] Connect to Analog signal Leave as a No Connect

PLL

XpllEFILTER Connect 1.8nF capacitor to GND Connect 1.8nF capacitor to GND

MMC

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XmmcCLK0 Connect to MMC0 Card Clock. Leave as a No Connect

XmmcCMD0 Connect to MMC0 Card Command. 10Kohm pull-up resistor to VDD_MMC is required


XmmcDAT0[3:0] Connect to MMC0 Card Data Lines. 10Kohm pull-up resistor to VDD_MMC is required


XmmcCDN0 Connect to MMC0 or MMC1 Card Detect 10Kohm pull-up resistor is required. Leave as a No Connect

Connect to MMC1 Card Clock. XmmcCLK1

Connect to Column Line of the Keypad Leave as a No Connect

Connect to MMC1 Card Command. 10Kohm pull-up resistor to VDD_MMC is required XmmcCMD1

Connect to Column Line of the Keypad


Connect to MMC1 Card Data Lines. 10Kohm pull-up resistor to VDD_MMC

Connect to Column Line of the Keypad

Connect to I2S 5.1CH codec.

XmmcDATA1[7:0]

Connect to ATA Address[2:0]


Reset

XnRESET Connect to Reset Circuit or Reset Button Connect to Reset Circuit or Reset Button

XnRSTOUT Connect to External Device Reset Leave as a No Connect

Clock

XrtcXTO

Connect a 13~22pF capacitor from each signal to GND.

Connect to 5M Ohm resistor between XrtcTI and XrtcTO

XrtcXTO leave as a No Connect.

XrtcXTI

Connect to crystal oscillator.

Connect to 5M Ohm resistor between XrtcTI and XrtcTO

Pull-up resistor to VDD_RTC.

X27mXTI Connect to crystal oscillator

Connect to 1M Ohm resistor between X27mXTI and X27mXTO

Pull-up resistor to VDD_SYS

X27mXTO Connect to crystal oscillator

Connect to 1M Ohm resistor between X27mXTI and X27mXTO


XXTO Connect a 15~22pF capacitor from each XXTO leave as a No Connect.

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signal to GND.

Connect to 1M Ohm resistor between XXTI and XXTO

XXTI Connect to a crystal oscillator.

Connect to 1M Ohm resistor between XXTI and XXTO

Pull-up resistor to VDD_SYS

XEXTCLK Connect to External Clock Source(Oscillator). Pull-dn resistor to GND

JTAG

XjTRSTn

Connect to JTAG Reset Port for Debugging.

10Kohm pull-up resistor to VDD_SYS.

Connect 470ohm series resistor to nRESET

10Kohm pull-dn resistor to

GND.

XjTMS Connect to JTAG Mode Select Port.


10Kohm pull-up resistor to

VDD_SYS.

XjTCK Connect to JTAG Mode Select Port.

10Kohm pull-dn resistor to GND.

10Kohm pull-dn resistor to

GND.

XjRTCK Connect to JTAG Return Clock Port Leave as a No Connect

XjTDI Connect to JTAG Mode Select Port.


10Kohm pull-up resistor to

VDD_SYS.

XjTDO Connect to JTAG Data Input Port Leave as a No Connect

10Kohm pull-dn resistor to GND for Core debugging.

XjDBGSEL 10Kohm pull-up resistor to VDD_SYS for SJF.

10Kohm pull-dn resistor to GND.

MISC

XOM[4:0] Connect to VDD_SYS or GND Connect to VDD_SYS or GND.

XPWRRGTON Connect to Regulator Enable Pin (VDD_ARM, VDD_INT, VDD_xPLL )

Connect to Regulator Enable Pin (VDD_ARM, VDD_INT, VDD_xPLL )

Connect to VDD_SYS for NAND XSELNAND

Connect to GND for OneNAND Connect to VDD_SYS or GND

XnBATF Connect to Probe Signal for Battery State. Connect to High.(VDD_SYS)

XeffVDD 10Kohm pull-dn resistor to GND 10Kohm pull-dn resistor to GND

WR_TEST Pull-up resistor to VDD_SYS Pull-up resistor to VDD_SYS

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1.2 Pin Power Domain

User should obey the operating voltage range between External device and S3C6410 IP.

Power Voltage VDDRTC 1.8V ~3.0V XrtcXTI, XrtcXTO

VDDMEM0 1.8V~3.3V

Xm0ADDR[19:0], Xm0DATA[15:0], Xm0CSn[5:0], Xm0OEn, Xm0Wen, Xm0ADV, Xm0SMCLK, Xm0WAITn, Xm0RDY0/ALE, Xm0RDY1/CLE, Xm0INTsm0/FWEn, Xm0INTsm1/FREn, Xm0RPn/RnB, Xm0INTATA, Xm0Cdata, Xm0BEn[1:0], GPQ[6:2]

VDDSS 1.8V~3.3V Xm0INTata, Xm0RESETata, Xm0INPACKata, Xm0REGata, Xm0WEata, Xm0OEata, Xm0CData

VDDMEM1 1.8V~2.5V Xm1ADDR[15:0], Xm1DATA[31:0], Xm1CSn[1:0], Xm1CKE[1:0], Xm1SCLK, Xm1SCLKn, Xm1RASn, Xm1CASn, Xm1WEn, Xm1DQM[3:0], Xm1DQS[3:0]

VDDEXT 1.8V~3.3V

XuRXD[3:0], XuTXD[3:0], XuCTSn[1:0], XuRTSn[1:0], XirSDBW, Xi2cSCL, Xi2cSDA, XspiMISO[0], XspiCLK[0], XspiMOSI[0], XspiCS[0], SciCLK, XciHREF, XciPCLK, XciRSTn, XciVSYNC, XciDATA[7:0], XpwmECLK, XpwmTOUT[1:0]

VDDMMC 1.8V~3.3V XspiMISO[1], XspiCLK[1], XspiMOSI[1], XspiCS[1], XmmcCLK[1:0], XmmcCMD[1:0], XmmcDATA0[3:0], XmmcCDN0, XmmcDATA1[7:0]

VDDPCM 1.8V~3.3V XpcmDCLK[1:0], XpcmEXTCLK[1:0], XpcmFSYNC[1:0], XpcmSIN[1:0], XpcmSOUT[1:0]

VDD_LCD 1.8V~3.3V XvVD[23:0], XvHSYNC, XcVSYNC, XvVDEN, XvVCLK

VDDHI 1.8V~3.3V XhiDATA[17:0], XhiADDR[12:0], XhiCSn, XhiCSn_main, XhiCSn_sub, XhiWEn, XhiOEn, XhiRQn

VDDSYS 1.8V~3.3V

XEINT[15:0], XnRESET, WR_TEST, XsRSTOUTn, XjTRSTn, XjTMS, XjTCK, XjRTCK, XjTDI, XjTDO, XjDBGSEL, XOM[4:0], XSELNAND, XPWRRGTON, XnBATF, X27mXTI, X27mXTO, XXTI, XXTO, XEXTCLK

VDDADC 3.3V Xadc_AIN[7:0], VDDDAC 3.3V XdacOUT_0, XdacOUT_1, XdacIREF, XdacVREF, XdacCOMP

VDDUH 3.3V XuhDN, XuhDP

VDDOTG 3.3V XusbDP, XusbDM, XusbXTI, XusbXTO, XusbREXT, XusbVBUS, XusbID, XusbDRVVBUS

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1.3 Booting Option OM[4:0] pin should be tied with VDDSYS or GND, directly. It is aimed for minimize leakage current when entering the sleep mode. But if you have to get an option, you should add a pull-up and pull-down resistor with 100K ohms over.

For example, let’s we assume IROM boot and crystal

OM[4:0] = b’11110

OM[4] OM[3] OM[2] OM[1] OM[0] OM[4] OM[3] OM[2] OM[1] OM[0] Operation Mode

0 OSC 0

1 SROM

EXT

0 OSC 0

1 1

NOR(26bit) EXT

SROM

0 OSC 0

1 OneNAND

EXT

Muxed OneNAND

(XSELNAND pin must be “0”)

0 OSC

0 1

1

1 1

Ext.

Boot

MODEM EXT

MODEM

0 OSC 1 1 1 1

1

Internal Boot Internal ROM

EXT Internal ROM

* IROM Boot loader of the S3C6410X support boot from various memory devices such as MoviNAND, MMC, Muxed OneNAND and NAND. It’s defined by OM[4:0] and GPN[15:13]

15


1.4 Feature of the IROM Boot mode

IROM Boot loader of the S3C6410X supports boot from various memory devices such as MoviNAND, MMC, Muxed OneNAND and NAND. It’s defined by OM[4:0] and GPN[15:13]

Boot Device Page Size Address Cycle GPN15

GPN14

GPN13 OM[4:0]

SDMMC(Channel 0) - - 0 0 0

OneNAND - - 0 0 1

3 0 1 0 512

4 0 1 1

4 1 0 0 2048

5 1 0 1

NAND

4096 5 1 1 0

SDMMC(Channel1) - - 1 1 1

5b’1111x

(XOM[0]:

Select Crystal or Oscillator)

Note) 1. NAND : Using S/W 8bit ECC at boot page

2. SDMMC(Channel1) is supported as 4bit. But It can be changed to 8bit by BL1

3. Don’t use GPN[15:13] as GPIO or EINT in IROM Boot.

4. When NAND uncorrectable ECC error is detected, GPN15 is toggled.

For detail, refer to “IROM Application Note”

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1.5 Recommend Operating Conditions Parameter Symbol Min Typ Max Unit

DC Supply Voltage for Alive Block VDDALIVE 1.15 1.2 1.25

VDDAPLL VDDMPLL VDDEPLL

1.15 1.2 1.25

VDDINT 1.15 1.2 1.25

VDDARM 533MHz 1.05 1.10 1.15

VDDARM 667MHz 1.15 1.20 1.25

DC Supply Voltage for Core Block

VDDARM 800MHz 1.25 1.30 1.35

DC Supply Voltage for Memory Interface0 (NOR/NAND/OneNAND/ CF) VDDMEM0 1.7 1.8 /

2.5/3.3 3.6

DC Supply Voltage for ATA IO muxed in MEM0 port VDDSS 1.7 1.8 /

2.5/3.3 3.6

DC Supply Voltage for Memory Interface1 (DRAM) VDDMEM1 1.75 1.8 / 2.5 2.7

DC Supply Voltage for I/O Block VDDMMC/VDDHI/VDDLCD/VDDPCM/VDD

EXT/VDDSYS 1.7 1.8 / 2.5 /

3.3 3.6

DC Supply Voltage for RTC VDDRTC 1.7 1.8~3.0 3.3

DC Supply Voltage for ADC VDDADC 3.0 3.3 3.6

DC Supply Voltage for DAC VDDDAC 3.0 3.3 3.6

DC Supply Voltage for USB OTG Phy 3.3V

VDDOTG 3.0 3.3 3.6

DC Supply Voltage for USB OTG Internal VDDOTGI 1.15 1.2 1.25

DC Supply Voltage for USB Host VDDUH 3.0 3.3 3.6

V

TA Industrial -40 to 85 oC

Operating Temperature TA Extended 0 to 70 oC

17


1.6 Difference of S3C6410 and S3C6400

1) Typical Voltage of the S3C6410

Symbol S3C6410X S3C6400X

533MHz 1.1V 1.1V

667MHz 1.2V 1.2V (Upto 634MHz)VDDARM

800MHz 1.3V Not Available

VDDINT 133MHz 1.2V 1.0V

VDDALIVE - 1.2V 1.0V

VDDxPLL - 1.2V 1.0V

VDDOTGI - 1.2V 1.1V

VDDRTC - 1.8V ~ 3.0V 2.5V

2) The Feedback resistors should be inserted between XTAL Input and Output pad

S3C6410X S3C6400X

Main Clock (XXTI, XXTO) 1M Ohm No need

27MHz(X27MXTI, X27MXTO) 1M Ohm No need

RTC(XrtcXTI, XrtcXTO) 5M Ohm No need

USBOTG(XotgTI,XotgTO) 1M Ohm No need

3) The value of resistor on DAC and USB OTG is changed

- The value of pull down resistor is changed.

Signal Name S3C6410X S3C6400X

XREXT 44.2 Ohm 3.4K Ohm

XdacIREF 6.49K Ohm 6.24K Ohm

4) SROM Address Bus Width (In case of using the x32 data bus width in memory port1)

- S3C6410X S3C6400X

Address Bus Width 20 bit 16 bit

18


5) DRAM Interface in Memory Port 0

- S3C6410X S3C6400X

DRAM I/F Not support SDR/mSDR/mDDR 16 bit

6) GPIO Muxing

Function S3C6410X S3C6400X

IIC 2-Ch 1-Ch

IIS 5-Ch Support Not support

Camera Interlace Mode Support Not support

For detail, please refer to Pin Description Document.

19


2. MEMORY MAP

2.1 Maximum Address range of the Memory Port0 Data pin [26:16] of memory port 1 can be used as Address pin [26:16] of memory port 0 by configuration from system controller (MEM_SYS_CFG[7])

Address Range of the SROMC Address Width Max. Size

Memory Port 1: 32bit Bus width DRAM 20bit 1MB

Memory Port 1: 16bit Bus width DRAM 27bit 128MB

2.2 Maximum Address range of the Memory Port1 1) 16bit Data Bus Width DRAM : 1Gb / Chip Select

2) 32bit Data Bus Width DRAM : 2Gb / Chip Select

Start

Address

End

Address

Int.

ROM

SROM

Ctrl.

OneNAND

Ctrl. 0

OneNAND

Ctrl. 1

DRAM

Ctrl 1

0x00000000 0x07FFFFFF O1 O1 O1 - -

0x08000000 0x0BFFFFFF O - - - -

0x0C000000 0x0FFFFFFF - - - - -

0x10000000 0x17FFFFFF - O - - -

0x18000000 0x1FFFFFFF - O - - -

0x20000000 0x27FFFFFF - O2 O2 - -

0x28000000 0x2FFFFFFF - O2 O2 -

0x30000000 0x37FFFFFF - O - - -

0x38000000 0x3FFFFFFF - O - - -

0x40000000 0x47FFFFFF - - - - - 0x48000000 0x4FFFFFFF - - - - -

0x50000000 0x5FFFFFFF - - - - O

0x60000000 0x6FFFFFFF - - - - O

1 Refer to Memory sub-system chapter(Refer to User’s manual) for details.

2 This address range can be assigned to both SROM controller and OneNAND controller. The decision is made by System Controller. Refer to Memory sub-system chapter for details. In case of OneNAND boot mode, It is not used for SROM controller.

20


3. Syscon

3.1 Power

3.1.1 Power On Sequence

VDD_IO

VDDALIVE

XPWRRGTON

VDDINT/ARM/PLL

nRESET

tOA

tAI

tOSC

tOR

tAE

VCOoutput

MCU operates by XTIpll or EXTCLK clcok.

ClockDisable

tPLL

FCLK is new frequency.

PLL is configured by S/W

VCO is adapted to new clock frequency.

FCLK

...

...

...

tRST2RUN

XTIpll orEXTCLK It can operate PLL .

XPWRRGTON HIGH is possible in this area

After VDD_IO & VDDALIVE are turned on, XPWRRGTON is always HIGH

Figure 3_1) Power on sequence

Note) OSC’s frequency should be meet the specification which is 10Mhz ~ 20Mhz

21


XTIpll

VCOOutput

ClockDisable

FCLK

Several slow clock cycles (XTIpll or EXTCLK)

Sleep mode is initiated.

tOSC2

EXTCLK

Wake up from sleep mode

Figure 3_2) Sleep Mode Return Oscillation Setting Timing

1/2 VDD_SYS1/2 VDD_SYS

tXTALCYC

NOTE: The clock input from the XTIpll pin.

Figure 3_3) XTI Clock Timing

22


tEXTHIGH

1/2 VDD_SYSVILVIL

VIHVIH1/2 VDD_SYS

tEXTLOW

tEXTCYC

NOTE: The clock input from the EXTCLK pin.

Figure 3_4) XEXTCLK Input Timing

Clock Timing Constants (VDDINT= 1.2V± 0.05V, TA = -40 to 85°C, VDDSYS = 3.3V ± 0.3V, 2.5V ± 0.25V, 1.8V ± 0.15V)

Parameter Symbol Min Typ Max Unit VDDpadIO to VDDalive tOA 0 ms

VDDalive to VDDi/VDDarm tAI 1 us

VDDarm to PWR_EN(PWRRGTON) tAE 1 10 ns

VDDLOGIC/VDDarm to Oscillator stabilization tOSC 10 cycle

Oscillator stabilization to nRESET & nTRST high tOR 1 us

External clock input high level pulse width tEXTHIGH 25 - ns

External clock to HCLK (without PLL) tEX2HC 5 10 ns

HCLK (internal) to CLKOUT tHC2CK 4 10 ns

HCLK (internal) to SCLK tHC2SCLK 2 8 ns

Reset assert time after clock stabilization tRESW 4 - XTIpll or EXTCLK

APLL&MPLL Lock Time tPLL - 300 us

EPLL Lock Time - 300 us Sleep mode return oscillation setting time. (2) tOSC2 24 216 XTIpll or

EXTCLKThe interval before CPU runs after nRESET is released.

tRST2RUN 5 - XTIpll or EXTCLK

23


3.1.2 Power Off Sequence

Figure 3_5) Power off sequence

Symbol Description Min TYP Max Units tloa VDDIO/VDDMEM to VDDALIVE 0 ms tloi VDDIO/VDDMEM to VDDINT/VDDARM 0 ms

24


3.1.3 Power Scheme Diagram

Figure 3_6) Power Scheme Diagram Note 1) VDDxPLL can use same power source with VDDINT

25


3.1.4 Circuit Guide for DVS Scheme VDDARM and VDDINT are depended by operating frequency. Recommended circuit guide is that used Voltage Controlled regulator for VDDARM and VDDINT. The following diagram describes 2 step DVS application circuit. User can control the VDDARM, VDDINT voltage using feedback resister.

Figure 3_7) Example of the Power Scheme Diagram

26


3.2 Clock

3.2.1 PLL

Input Clock (X-tal or ExtCLK)

E X T C L K

X T I p l l

X T O p l l

E X T C L K

X T I p l l

X T O p l l

E x t e r n a l O S C

a ) X - T A L O s c i l l a t i o n ( O M [ 0 ] = 0 ) b ) E x t e r n a l C l o c k S o u r c e ( O M [ 0 ] = 1 )

C E X T

C E X T

V D D _ S Y S

R f e d

Figure 3_8) Input Clock Example

Usual Conditions for A/MPLL & Clock Generator PLL & Clock Generator generally uses the following conditions.

Loop filter capacitance CLFNeed not Loop Filter

Capacitance

External X-tal frequency - 10 – 20 MHz

External capacitance used for X-tal CEXT 15 – 22 pF

Feedback resistor between XXTI with XXTO

Rfed 1M Ohm

The output frequencies of APLL/MPLL can be calculated using the following equations:

FOUT = MDIV X FIN / (PDIV X 2SDIV)

MDIV: 64 ≤ MDIV ≤ 1023

PDIV: 1 ≤ PDIV ≤ 63

SDIV: 0 ≤ SDIV ≤ 5

FVCO =(MDIV X FIN / PDIV): 800MHz ≤ FVCO ≤ 1600MHz

27


FIN : 10MHz ≤ FIN ≤ 20MHz

Don’t set the value P and M to all zeros

FOUT = MDIV X FIN / (PDIV X 2SDIV)

NOTE: Although there is the equation for choosing PLL value, we strongly recommend only the values in the PLL value recommendation table. If you have to use other values, please contact us.

FIN (MHz) Target FOUT (MHz) MDIV PDIV SDIV 12 100 400 3 4 12 200 400 3 3 12 266 266 3 2 12 400 400 3 2 12 533 266 3 1 12 667 333 3 1

Usual Conditions for EPLL & Clock Generator PLL & Clock Generator generally uses the following conditions.

Loop filter capacitance CLF XpllEFILTER: 1.8nF

External X-tal frequency - 10 – 20 MHz

External capacitance used for X-tal CEXT 15 – 22 pF

The output frequencies of EPLL can be calculated using the following equations:

FOUT = (MDIV + KDIV / 216) X FIN / (PDIV X 2SDIV)

where, MDIV, PDIV, SDIV for APLL and MPLL must meet the following conditions :

MDIV: 16 ≤ MDIV ≤ 255

PDIV: 1 ≤ PDIV ≤ 63

KDIV: 0 ≤ KDIV ≤ 65535

SDIV: 0 ≤ SDIV ≤ 4

FVCO (= (MDIV + KDIV / 216) X FIN / PDIV) : 300MHz ≤ FVCO ≤ 600MHz

FOUT : 20MHz ≤ FOUT ≤ 600MHz

FIN : 10MHz ≤ FIN ≤ 20MHz

Don’t set the value P and M to all zeros

NOTE: Although there is the equation for choosing PLL value, we strongly recommend only the values in the PLL value recommendation table. If you have to use other values, please contact us.

28


EPLL Value (P, M, S)

FIN (MHz) FOUT (MHz) MDIV PDIV SDIV KDIV 12 36 48 1 4 0 12 48 32 1 3 0 12 60 40 1 3 0 12 72 48 1 3 0 12 84 28 1 2 0 12 96 32 1 2 0 12 32.768 43 1 4 45264 12 45.158 30 1 3 6903 12 49.152 32 1 3 50332 12 67.738 45 1 2 10398 12 73.728 49 1 3 9961

3.3 Reset

3.3.1 HardWare Reset The hardware reset is invoked when XnRESET pin is asserted and all units in the system (except RTC) are reset to known states. During this period, the following actions occur.

• All internal registers and ARM1176 core go to the pre-defined reset states.

• All pins get their reset state.

• XnRSTOUT pin is asserted when XnRESET is asserted.

Caution: An external power source, regulator, for S3C6410X must be stable prior to the deassertion of XnRESET. Otherwise, it damages to S3C6410X and its operation will not be guaranteed.

29


4. MEMORY SUBSYSTEM 4.1 USAGE OF THE MEMORY PORT0 & MEMORY PORT1

Memory Port0 Memory Port1

Op. Voltage VDD_MEM0(1.7V~3.6V,typ:1.8/2.5V/3.3V) VDD_MEM1(1.75V~2.7V,typ:1.8/2.5V)

Device SRAM, NOR, NAND, OneNAND, CF I/F x16 mDDR, DDR x32 mSDR, SDR, mDDR, DDR

Chip Select

Xm0nCS[1:0] : SRAM, NOR ( NOR Booting : Xm0nCS0) Xm0nCS[3:2] : SRAM, NOR, NAND, OneNAND (OneNAND Booting: Xm0nCS2 and Xm0nCS3 can’t support SROMC at OneNAND/Modem booting mode)

Xm0nCS[5:4] : SRAM, NOR, CF

Xm1nCS0, Xm1nCS1 : DRAM

Others If use x32 DRAM in Memory Port1, Memory Port0 use only Xm0ADDR[19:0]

Can’t be connected with x16 mSDR 16bit Data Bus: Default, ADDR_EXPAND =”1” 32bit Data Bus: ADDR_EXPAND=”0”

30


5. DRAM Controller

5.1 Memory Port0

The Memory Port0 of the S3C6410 can’t support DRAM.

5.2 Memory Port1 DRAM S3C6410X

16bit A0 Xm1ADDR0 Addr. Connection

(DDR/SDRAM) 32bit A0 Xm1ADDR0

BA[1:0] addr for SDR/DDR Xm1ADDR14 and Xm1ADDR15 fixed regardless of memory size

Data Bus Width Xm1DATA[26:16] are muxed with SROMC(Memory Port0) address[26:16] signal.

Bus Loading 15pF@133MHz, 1.8V 25pF@133MHz, 2.5V

1) Xm1DATA[26:16] are operating as address[26:16] of the memory port0, when reset state.

2) To expand data bus, set ‘ADDR_EXPAND’ field to “0”(In SYSCON, MEM_SYS_CFG sfr)

3) Memory Interface Example

31


Caution ) The state of the DRAM Controller can be controlled by DRAM Controller Command Register. The SFR in DRAM Controller can change in Config and Low power state.

32


5.3 DRAM Initialize Sequence

33


Caution)

1. The value of the SFRs should be changed in “Config” state of the DRAM Controller.

2. Should be set to correct value to “Memory Configuration” and “Memory Configuration 2”

Check Point :

1) Active chips, Memory burst ( It must be matched the memory device), AP bit,

Row/Column address

2) Memory type, Memory width, Read delay

3. All of external DRAM should be executed memory device initialize sequence by “DIRECTCMD” Sfr

MOBILE DDR SDRAM INITIALIZATION SEQUENCE

Program mem_cmd in direct_cmd to ‘2’b10’, which makes DRAM Controller issue ‘NOP’ memory command.

Program mem_cmd in direct_cmd to ‘2’b00’, which makes DRAM Controller issue ‘Prechargeall’ memory command.

Program mem_cmd in direct_cmd to ‘2’b11’, which makes DRAM Controller issue ‘Autorefresh’ memory command.


Program mem_cmd to ‘2’b10’ in direct_cmd, which makes DRAM Controller issue ‘MRS’ memory command

o Bank address for EMRS must be set. Program mem_cmd to ‘2’b10’ in direct_cmd, which makes DRAM Controller issue ‘MRS’ memory

command. o Bank address for MRS must be set.

34


DDR1 SDRAM INITIALIZATION SEQUENCE

Program mem_cmd in direct_cmd to ‘2’b10’, which makes DRAM Controller issue ‘NOP’ memory command.


Program mem_cmd to ‘2’b10’ in direct_cmd, which makes DRAM Controller issue ‘MRS’ memory command

o Bank address for EMRS must be set. Enable DLL should be set. Program mem_cmd to ‘2’b10’ in direct_cmd, which makes DRAM Controller issue ‘MRS’ memory

command. o Bank address for MRS must be set. Assert Reset DLL




Program mem_cmd to ‘2’b10’ in direct_cmd, which makes DRAM Controller issue ‘MRS’ memory command.

o Bank address for MRS must be set. Deassert Reset DLL

35


5.4 PCB LAYOUT GUIDELINES FOR DDR

5.4.1 POWER AND GROUND DESIGN GUIDE

General design rule is applied on this case.

I. Ground layer has to be placed adjacent to signal layer for current return path.

II. Ground plane has not to be splitted.

III. Connection of ground pins

a) Connect to ground plane through ground via near ground pin as short as possible.

b) Connect to ground plane through ground via near ground pad of bypass capacitor as short as possible.

c) Join together ground pins adjacent each other for making lower impedance.

IV. Connection of power pin

a) Place bypass capacitor near power pin as short as possible.

b) Connect to power plane through power via near power pad of bypass capacitor as short as possible.

c) Pay attention whether power via makes ground plane splitted or not.

The value of bypass capacitor is determined by considering capacitance of PCB board. And the number of capacitors is as large as possible considering of PCB space.

5.4.2 TRACE ROUTING GUIDE

I. DQ, DQM, DQS signal

Signals in same group have pattern length matched within 1.5mm for equalizing timing skew. If signals in same group have to be routed on different layer, impedance of the layer must be considered.

Data Group Mask Signal Clock

DQ [7:0] DQM0 DQS0

DQ [15:8] DQM1 DQS1

DQ[23:16] DQM2 DQS2

DQ[31:24] DQM3 DQS3

36


II. CSn, CKE, ADDR[13:0], BA[1:0], RASn, CASn, WEn, AP signal

These signals are routed separating with other signal groups.

III. SCLK, SCLKn signal

These clock signals must have differential impedance. The length of clock signal is longer than signals in data signal group and control signal groups.

DQ, DQM, DQS < CSn, CKE, ADDR, BA, RASn, CASn, WEn, AP < SCLK, SCLKn

The difference of pattern length between signal groups is around 10mm.

IV. Others

a) If termination resister is required for EMI or signal integrity, resisters may be applied. The adequate value of resister is not mentioned on this document.

b) If there is another device connected on MEM0, shared signals have to be branched near AP side.

c) General design rules have to be kept according to know-how of PCB design engineer.

X O O O X

37


Xm1CKE0[2]

Xm1DATA7

CB70

100nF

Xm1RASn [2]

Xm1ADDR15[2]

Xm1DATA11

Xm1ADDR9

Xm1ADDR4

Xm1WEn [2]

Xm1CSn0 [2]

Xm1CKE0[2]

Xm1ADDR15[2]

Xm1DQM3[2] Xm1CSn0 [2]

Xm1DATA21

Xm1DQS3[2] Xm1CASn [2]Xm1DQS2[2]

Xm1ADDR8

Xm1ADDR2

CB72

100nF

Xm1ADDR[15:0][2]

Xm1DATA2

Xm1ADDR1

Xm1SCLKn[2]

Xm1DATA29

Xm1RASn [2]

Xm1DATA10

Xm1DATA[31:0] [2]

CB73

100nF

Xm1ADDR14[2]

Xm1DQM2[2]

Xm1DQS1[2]

Xm1ADDR1

Xm1DATA13

Xm1DATA23

!!SAMEROUTELENGTH

Xm1ADDR[15:0][2]

+CTB30

10uF/6.3V/T2012

Xm1ADDR3

CB74

100nF

Xm1DQS0[2]

Xm1DATA3

Xm1DATA5

Xm1ADDR7

Xm1ADDR12

Xm1ADDR11

Xm1DATA18

CB57

100nF

VDD_DMEM

Xm1DATA17

CB61

100nF

Xm1SCLKn[2]

Xm1ADDR9

Xm1DATA12

Xm1DATA25

Xm1ADDR7

Xm1DATA15

Xm1ADDR2

Xm1ADDR10

Xm1ADDR4Xm1ADDR5

Xm1DATA30

Xm1ADDR6

Xm1ADDR11 Xm1DATA27

Xm1DATA14

Xm1DATA19

CB60

100nF

VDD_DMEM

Xm1DATA0

Xm1DATA9

Xm1ADDR8

Xm1ADDR10

Xm1DATA16

Xm1DATA1

Xm1DATA20

Xm1ADDR6

Xm1ADDR0

Xm1DATA28

CB71

100nF

+CTB28

10uF/6.3V/T2012

Xm1SCLK[2]

Xm1DATA8

Xm1DATA31

Xm1ADDR3

U22

K4X51163PE-L(F)E/GC6

J8J9K7K8K2K3J1J2J3H1J7H2H3

H8H9

F8F2E8

A9

E2

G1G2G3

A8

H7G9G8G7

F3

K1

F7

A1F1F9

K9

C9E9A7B1D1 D9

B9A3E1C1

B7B8C7

D7C8

D8E7E3D2D3C2C3

B3B2

A2

A0A1A2A3A4A5A6A7A8A9A10/APA11A12

BA0BA1

LDMUDMLDQS

VDD

UDQS

CKECKnCK

DQ0

nCSnRASnCASnWE

NC

VSS

NC

VSSVSSVDD

VDD

VDDQVDDQVDDQVDDQVDDQ VSSQ

VSSQVSSQVSSQVSSQ

DQ1DQ2DQ3

DQ5DQ4

DQ6DQ7DQ8DQ9

DQ10DQ11DQ12

DQ14DQ13

DQ15

Xm1DATA6

CB58

100nF

Xm1DATA26

Xm1DATA24

CB69

100nF

Xm1ADDR0

Xm1CASn [2]

Xm1ADDR5

Xm1ADDR14[2]

CB62

100nF

!!SAMEROUTELENGTH

U20

K4X51163PE-L(F)E/GC6

J8J9K7K8K2K3J1J2J3H1J7H2H3

H8H9

F8F2E8

A9

E2

G1G2G3

A8

H7G9G8G7

F3

K1

F7

A1F1F9

K9

C9E9A7B1D1 D9

B9A3E1C1

B7B8C7

D7C8

D8E7E3D2D3C2C3

B3B2

A2

A0A1A2A3A4A5A6A7A8A9A10/APA11A12

BA0BA1

LDMUDMLDQS

VDD

UDQS

CKECKnCK

DQ0

nCSnRASnCASnWE

NC

VSS

NC

VSSVSSVDD

VDD

VDDQVDDQVDDQVDDQVDDQ VSSQ

VSSQVSSQVSSQVSSQ

DQ1DQ2DQ3

DQ5DQ4

DQ6DQ7DQ8DQ9

DQ10DQ11DQ12

DQ14DQ13

DQ15

Xm1DATA[31:0] [2]

Xm1DQM1[2]

Xm1ADDR12

Xm1DATA22

CB59

100nF

Xm1WEn [2]

Xm1DATA4

Xm1DQM0[2]

Xm1SCLK[2]

Figure 5_1) Memory port 1 interface example

38


6. SROM Controller

6.1 Address Connection

SRAM/ROM S3C6410X

8bit data bus A0 Xm0ADDR0 Addr. connection

16bit data bus A0 Xm0ADDR1

6.2 SRAM/ROM Interface Examples

Figure 6_1) Memory Interface with 8-bit SRAM

39


Figure 6_2) Memory Interface with 16-bit SRAM Note. 1) The Xm0CSn3 can’t be used for SROM controller in OneNAND/Modem Boot mode.

40


7. OneNAND Controller

7.1 Overview S3C6410X supports external 16-bit bus for both asynchronous and synchronous OneNAND external memory via shared memory port 0.

7.2 Signal Description

I/O Description Signal

Xm0DATA[15:0] IO Xm0DATA[15:0] (Data Bus) outputs address during memory read/write address phase, inputs data during memory read data phase and outputs data during memory write data phase.

Xm0CSn[3:2] O

Xm0CSn[3:2] (Chip Select) are activated when the address of a memory is within the address region of each bank. Xm0CSn[3:2] can be assigned to either SROMC or OneNAND controller by System Controller SFR setting. Active LOW.

Xm0WEn O Xm0WEn (Write Enable) indicates that the current bus cycle is a write cycle.Active LOW.

Xm0OEn O Xm0OEn (Output Enable) indicates that the current bus cycle is a read cycle. Active LOW.

Xm0INTsm0_FWEn Xm0INTsm1_FREn I

Interrupt inputs from OneNAND memory Bank 0, 1. If OneNAND memory is not used, these signals must be tied to zero.

Xm0ADDRVALID O Address valid output. Active LOW.

Xm0RPn_RnB O System reset output for OneNAND memory. Active LOW.

Xm0RDY0_ALE Xm0RDY1_CLE I

Xm0RDY is a synchronous burst wait input that the external device uses to delay a synchronous burst transfer. Xm0RDY indicates data valid in synchronous read modes and is activated while Xm0CSn is low.

Xm0SMCLK O Static memory clock for synchronous static memory devices. Must be less than 67MHz.

7.3 Circuit Diagram Example Xm0CSn2 is used for OneNAND boot device. If you want OneNAND boot, Xm0CSn2 should be used for boot. Optionally you can use Xm0CSn3 for storage.

41


Xm0DATA13

Xm0WEn

VDD_mem

Xm0ADDRVALID

Xm0DATA3

Xm0DATA9

Xm0DATA1

Xm0DATA4

Xm0RDY0_ALE

Xm0DATA15

Xm0DATA10

Xm0DATA[15:0]

Xm0CSn2

Xm0DATA2

Xm0DATA12

Xm0DATA7

Xm0DATA5

Xm0DATA14

C508

100nF

Xm0DATA8

Xm0DATA11

Xm0INTsm0_FWEn

Xm0DATA6

Xm0RPn_RnB

UM1

KFN2G16Q2M-DEB6

D1A3A6B1C3C4B5B2C1D6D5C2C5E3B3D3

E1A1E2B4

F3A2

A4A5

H1G1

B6C6

ADQ0ADQ1ADQ2ADQ3ADQ4ADQ5ADQ6ADQ7ADQ8ADQ9ADQ10ADQ11ADQ12ADQ13ADQ14ADQ15

CLKnWEnCEnOE

nAVDnRP

VSS0VSS1

RDYINT

VCCcoreVCCIO

Xm0SMCLK

Xm0OEn

Xm0DATA0

Figure 7_1) Using only one OneNand Device

Xm0DATA13

Xm0WEn

VDD_mem

Xm0OEn

Xm0ADDRVALID

Xm0WEn

Xm0DATA7

Xm0RDY0_ALEXm0DATA3

Xm0DATA9

Xm0DATA14

Xm0DATA[15:0] UM1

KFN2G16Q2M-DEB6


E1A1E2B4

F3A2

A4A5

H1G1

B6C6


CLKnWEnCEnOE

nAVDnRP

VSS0VSS1

RDYINT

VCCcoreVCCIO

VDD_mem

C508

100nF

Xm0DATA1

Xm0DATA4

Xm0RDY1_CLE

Xm0DATA15

Xm0DATA13

Xm0RPn_RnBXm0DATA4

Xm0DATA10

Xm0DATA[15:0]

Xm0CSn3

Xm0DATA2

Xm0DATA9

Xm0DATA12

Xm0DATA2

Xm0DATA12

Xm0DATA5

Xm0DATA7

Xm0DATA0

Xm0DATA5Xm0DATA6

Xm0DATA14

C508

100nF

Xm0DATA15

Xm0INTsm0_FWEn

Xm0DATA1

Xm0DATA8

Xm0DATA11Xm0SMCLKXm0DATA11

Xm0INTsm1_FREn

Xm0DATA8Xm0CSn2

Xm0DATA3

Xm0DATA6

Xm0RPn_RnB

UM2

KFN2G16Q2M-DEB6


E1A1E2B4

F3A2

A4A5

H1G1

B6C6


CLKnWEnCEnOE

nAVDnRP

VSS0VSS1

RDYINT

VCCcoreVCCIO

Xm0SMCLK

Xm0OEn

Xm0DATA0

Xm0ADDRVALID

Xm0DATA10

Figure 7_2) Using two OneNand Device

7.4 Caution • Each memory bank supports only Muxed OneNAND

• To use OneNAND Flash, ‘XSELNAND’ pin must be connected to zero (Low level). For detail, refer to Overview Chapter.

• OneNand signal power domain belongs to VDD_MEM0

42


8. NAND Flash

8.1 Interface for Multi Chip Select NAND Xm0nCS2/Xm0nCS3 are used for nand device. But large capacity NAND flash have two nCE signal. If some nand flash have 4-CE device, you can use GPIO which have external 10K pull-up resistor because the GPIO default setting is input/pulldown.

Figure 8_1) 1-CE case and 2-CE case connection

Figure 8_2) 4-CE case connection (1) Nand signal power domain belongs to VDD_MEM0. Confirm the voltage level another SRAM interface.

(2) RnB signal have open-drain input, so user should add external 4.7K pull-up resistor.

43


9. CF Controller

9.1 CF Interface There are two operational modes in CF Controller. The one is an indirect mode and the other is a direct mode. These operational modes can be selected by configuring INDEP_CF bit of MEM_SYS_CFG register(0x7E00F120) in System Controller.

The host(CF controller in S3C6410X) can control device through EBI in indirect mode. If the IO voltage of external memory is not 3.3V, a level shifter is required for data bus. The Level shifter needs a direction control bit for data bus. Two pins, XhiIRQn or XirSDBW, can be selected for a direction control bit. (These two pins can be used as a control bit not only in UDMA mode but also in PC-CARD mode and PIO mode.)

CF card or micro-drive can be connected directly to S3C6410X chip without being through memory port 0 in direct mode. There are multiplexed signals which refer to below table, direct mode column for direct mode.

Indirect mode Direct mode (UDMA mode only) I/O Description

XhiCSn Xm0CSn[4]

XhiADR[8] O

Card enable strobe PC card mode : lower byte enable strobe True-IDE mode : chip selection (nCS0)

XhiCSn_main Xm0CSn[5]

XhiADR[9] O

Card enable strobe PC card mode : higher byte enable strobe True-IDE mode : chip selection (nCS1)

Xm0REGata Xm0REGata

XhiADDR[6] O

Register in CF card strobe PC card mode : It is used for accessing register in CF card True-IDE mode : DMA Acknowledge

Xm0OEata Xm0OEata OOutput enable strobe PC card mode : output enable strobe for memory True-IDE mode : GND.

Xm0RESETata Xm0RESETata

XhiADDR[4] O

CF card reset PC card mode : active high True-IDE mode : active low

Xm0WEata Xm0WEata OWrite enable strobe PC card mode : output enable strobe for memory True-IDE mode: VCC.

XhiCSn_sub Xm0OEn

XhiADR[10] O Read strobe for I/O mode

UDMA mode : host strobe XhiWEn

Xm0WEn XhiADR[11]

O Write strobe for I/O mode

Xm0ADDR[0] XhiADDR[0], XuRXD[2], XmmcDATA1[4]

O

Xm0ADDR[1] XhiADDR[1], XuTXD[2], XmmcDATA1[5]

O

Xm0ADDR[2] XhiADDR[2], XmmcDATA1[6], XuRXD[3]

O

CF card address PC card mode : full address use True-IDE mode : only ADDR[2:0] use, The other address line is connected to GND.

44


Xm0ADDR[10:3] O XhiDATA[0] BXhiDATA[1] BXhiDATA[2] BXhiDATA[3] BXhiDATA[4] BXhiDATA[5] BXhiDATA[6] BXhiDATA[7] BXhiDATA[8] (XhiDATA[16]) B

XhiDATA[9] (XhiDATA[17]) B

XhiDATA[10](XhiCSn) BXhiDATA[11] (XhiCSn_main) B

XhiDATA[12] (XhiCSn_sub) B

XhiDATA[13] (XhiWE) BXhiDATA[14] (XhiOEn) B

Xm0DATA[15:0]

XhiDATA[15](XhiIRQn) B

CF data bus

Xm0CData Xm0CData

XhiADDR[7] I Card detect signals

Xm0INTata Xm0INTata

XhiADDR[3] I

Interrupt request from CF card. PC card mode : active low (memory mode : level triggering, I/O mode : edge triggering) True-IDE mode : active high

XhiADR[12] Xm0WAITn

XhiOEnI I Wait signal from CF card

UDMA mode : device strobe

Xm0INPACKata Xm0INPACKata

XhiADDR[5] I

Input acknowledge in I/O mode PC card mode : not used True-IDE mode : DMA request

9.2 Cautions (1) Check voltage domain of CF address and data, because addr/data shared another SRAM interface. If user

use 1.8V NAND flash, you should add a level shifter.

(2) S3C6410X has dedicated CF chip select signals as Xm0CSn4 = nCS_CF0, Xm0CSn5 = nCS_CF1

(3) If using CF device in direct mode, you cannot utilize some functions multiplexed with CF direct path such as Host I/F, Keypads, UART.

45


B_ADDR9

B_REGata

R36 10K

CON2

CompactFlash_1

212223234564748492728293031501214151617181920

7323435421

373839404124434445469

13333626258

1011

D0D1D2D3D4D5D6D7D8D9

D10D11D12D13D14D15

GND2A7A6A5A4A3A2A1A0

nCE1nCE2nIORDnIOWRnWAITGND1IREQVCC2nCSELnVS2/OPENRESETWPnINPACKnREGnSPKRnSTSCHGnOEVCC1nVS1/GNDnWECD1CD2A10A9A8

B_RESETP_DATA7

P_DATA15

P_DATA11

CD1_CF

R1311 0

B_INTata

P_DATA12B_INPACKata

P_DATA1

B_ADDR[26:0]

R40 10K

P_ADDR1

P_DATA14

CE_CF1

B_ADDR10

P_DATA5

VDD_CF

R13

1210

K

B_ADDR[26:0]

P_DATA3

P_ADDR0

P_ADDR[2:0]

CD2_CF

R38 10K

P_DATA0

nIOWR_CF

B_ADDR5

P_DATA13

B_WEata

R41 10K

CE_CF0

VDD_CF

P_DATA8

B_ADDR3

P_DATA4

B_OEata

nIORD_CF

R37 10K

B_ADDR7

P_DATA9

B_ADDR8

P_DATA6

B_ADDR6

IORDY_CF

P_DATA[15:0]

P_ADDR2

P_DATA10

P_DATA2

B_ADDR4

Figure 9_1) CF Connection Example

9.3 ATA 2 Slot operation guide (1) S3C6410X CF Controller can use CF card and HDD together by using 2slot operation (master and slave)

(2) Follow Figure 9_2) using 2 slot schematic

CF pin list matched S3C6410X Signal CF pin list matched S3C6410X Signal A0 XhiADDR[0] or XuRXD[2] or XmmcDAT1[4] D12 XhiDATA[12] A1 XhiADDR[1] or XuTXD[2] or XmmcDAT1[5] D13 XhiDATA[13] A2 XhiADDR[2] or XuRXD[3] or XmmcDAT1[6] D14 XhiDATA[14] D0 XhiDATA[0] D15 XhiDATA[15] D1 XhiDATA[1] CS0 XhiCSn or XhiADDR[8] D2 XhiDATA[2] CS1 XhiCSn_main or XhiADDR[9] D3 XhiDATA[3] IORD XhiCSn_sub or XhiADDR[10] D4 XhiDATA[4] IOWR XhiWEn or XhiADDR[11] D5 XhiDATA[5] IORDY XhiOEn or XhiADDR[12] D6 XhiDATA[6] INTRQ XhiADDR[3] D7 XhiDATA[7] RESET XhiADDR[4] D8 XhiDATA[8] nINPACK XhiADDR[5] D9 XhiDATA[9] REG XhiADDR[6]

D10 XhiDATA[10] CData XhiADDR[7] D11 XhiDATA[11]

46


Figure 9_2) CF ATA 2 Slot Operation Schematic

47


10. GPIO GPIO consists of two parts, alive-part and off-part. In Alive-part power is supplied on sleep mode, but in off-part it is not the same. Therefore, the registers in alive-part can keep their values during sleep mode. And registers in off-part register can keep their values by each GP(*)SLPCON and GP(*)PUDSLP register during sleep mode. Internal pull-up and pull-down register is about 50~100Kohm. Alive part GPIO register groups contain GPK, GPL, GPM and GPN ports.

External Interrupt is consists of 10 groups numbered from 0 to 9. Only external interrupt group 0 is used for wake-up source in Stop and Sleep mode. And, In idle mode, all interrupts can be wake-up sources.

Wakeup source GPIO is GPL[14:8], GPM[4:0] and GPN[15:0] ports.

Every S3C6410X pin reset value is as below.

Pin Name Default Function I/O state @Reset I/O

Type XURXD0/GPA0 GPA0 I (pull-down) hag XUTXD0/GPA1 GPA1 I (pull-down) hag

XUCTSN0/GPA2 GPA2 I (pull-down) hag XURTSN0/GPA3 GPA3 I (pull-down) hag XURXD1/GPA4 GPA4 I (pull-down) hag XUTXD1/GPA5 GPA5 I (pull-down) hag

XUCTSN1/GPA6 GPA6 I (pull-down) hag XURTSN1/GPA7 GPA7 I (pull-down) hag XURXD2/GPB0 GPB0 I (pull-down) hag XUTXD2/GPB1 GPB1 I (pull-down) hag XURXD3/GPB2 GPB2 I (pull-down) hag XUTXD3/GPB3 GPB3 I (pull-down) hag

XIRSDBW/GPB4 CF_data_dir O(L) hag XI2CSCL/GPB5 GPB5 I (pull-down) hag XI2CSDA/GPB6 GPB6 I (pull-down) hag

XSPIMISO0/GPC0 GPC0 I (pull-down) hag XSPICLK0/GPC1 GPC1 I (pull-down) hag

XSPIMOSI0/GPC2 GPC2 I (pull-down) hag XSPICS0/GPC3 GPC3 I (pull-down) hag

XSPIMISO1/GPC4 GPC4 I (pull-down) hag XSPICLK1/GPC5 GPC5 I (pull-down) hag

XSPIMOSI1/GPC6 GPC6 I (pull-down) hag XSPICS1/GPC7 GPC7 I (pull-down) hag

XPCMDCLK0/GPD0 GPD0 I (pull-down) hag XPCMEXTCLK0/GPD1 GPD1 I (pull-down) hag XPCMFSYNC0/GPD2 GPD2 I (pull-down) hag

48


XPCMSIN0/GPD3 GPD3 I (pull-down) hag XPCMSOUT0/GPD4 GPD4 I (pull-down) hag XPCMDCLK1/GPE0 GPE0 I (pull-down) hag

XPCMEXTCLK1/GPE1 GPE1 I (pull-down) hag XPCMFSYNC1/GPE2 GPE2 I (pull-down) hag

XPCMSIN1/GPE3 GPE3 I (pull-down) hag XPCMSOUT1/GPE4 GPE4 I (pull-down) hag

XCICLK/GPF0 GPF0 I (pull-down) hag XCIHREF/GPF1 GPF1 I (pull-down) hag XCIPCLK/GPF2 GPF2 I (pull-down) hag XCIRSTN/GPF3 GPF3 I (pull-down) hag

XCIVSYNC/GPF4 GPF4 I (pull-down) hag XCIYDATA0/GPF5 GPF5 I (pull-down) hag XCIYDATA1/GPF6 GPF6 I (pull-down) hag XCIYDATA2/GPF7 GPF7 I (pull-down) hag XCIYDATA3/GPF8 GPF8 I (pull-down) hag XCIYDATA4/GPF9 GPF9 I (pull-down) hag

XCIYDATA5/GPF10 GPF10 I (pull-down) hag XCIYDATA6/GPF11 GPF11 I (pull-down) hag XCIYDATA7/GPF12 GPF12 I (pull-down) hag XPWMECLK/GPF13 GPF13 I (pull-down) hag

XPWMTOUT0/GPF14 GPF14 I (pull-down) hag XPWMTOUT1/GPF15 GPF15 I (pull-down) hag

XMMCCLK0/GPG0 GPG0 I (pull-down) hag XMMCCMD0/GPG1 GPG1 I (pull-down) hag

XMMCDATA0_0/GPG2 GPG2 I (pull-down) hag XMMCDATA0_1/GPG3 GPG3 I (pull-down) hag XMMCDATA0_2/GPG4 GPG4 I (pull-down) hag XMMCDATA0_3/GPG5 GPG5 I (pull-down) hag

XMMCCDN0/GPG6 GPG6 I (pull-down) hag XMMCCLK1/GPH0 GPH0 I (pull-down) hag XMMCCMD1/GPH1 GPH1 I (pull-down) hag

XMMCDATA1_0/GPH2 GPH2 I (pull-down) hag XMMCDATA1_1/GPH3 GPH3 I (pull-down) hag XMMCDATA1_2/GPH4 GPH4 I (pull-down) hag XMMCDATA1_3/GPH5 GPH5 I (pull-down) hag XMMCDATA1_4/GHP6 GHP6 I (pull-down) hag XMMCDATA1_5/GPH7 GPH7 I (pull-down) hag XMMCDATA1_6/GPH8 GPH8 I (pull-down) hag XMMCDATA1_7/GPH9 GPH9 I (pull-down) hag

XVVD0/GPI0 GPI0 I (pull-down) hag_a

49


XVVD1/GPI1 GPI1 I (pull-down) hag_a XVVD2/GPI2 GPI2 I (pull-down) hag_a XVVD3/GPI3 GPI3 I (pull-down) hag_a XVVD4/GPI4 GPI4 I (pull-down) hag_a XVVD5/GPI5 GPI5 I (pull-down) hag_a XVVD6/GPI6 GPI6 I (pull-down) hag_a XVVD7/GPI7 GPI7 I (pull-down) hag_a XVVD8/GPI8 GPI8 I (pull-down) hag_a XVVD9/GPI9 GPI9 I (pull-down) hag_a

XVVD10/GPI10 GPI10 I (pull-down) hag_a XVVD11/GPI11 GPI11 I (pull-down) hag_a XVVD12/GPI12 GPI12 I (pull-down) hag_a XVVD13/GPI13 GPI13 I (pull-down) hag_a XVVD14/GPI14 GPI14 I (pull-down) hag_a XVVD15/GPI15 GPI15 I (pull-down) hag_a XVVD16/GPJ0 GPJ0 I (pull-down) hag_a XVVD17/GPJ1 GPJ1 I (pull-down) hag_a XVVD18/GPJ2 GPJ2 I (pull-down) hag_a XVVD19/GPJ3 GPJ3 I (pull-down) hag_a XVVD20/GPJ4 GPJ4 I (pull-down) hag_a XVVD21/GPJ5 GPJ5 I (pull-down) hag_a XVVD22/GPJ6 GPJ6 I (pull-down) hag_a XVVD23/GPJ7 GPJ7 I (pull-down) hag_a

XVHSYNC/GPJ8 GPJ8 I (pull-down) hag_a XVVSYNC/GPJ9 GPJ9 I (pull-down) hag_a XVDEN/GPJ10 GPJ10 I (pull-down) hag_a XVVCLK/GPJ11 GPJ11 I (pull-down) hag_a

XHIDATA0/GPK0 XHIDATA0 I(pull-down) hag_a XHIDATA1/GPK1 XHIDATA1 I(pull-down) hag_a XHIDATA2/GPK2 XHIDATA2 I(pull-down) hag_a XHIDATA3/GPK3 XHIDATA3 I(pull-down) hag_a XHIDATA4/GPK4 XHIDATA4 I(pull-down) hag_a XHIDATA5/GPK5 XHIDATA5 I(pull-down) hag_a XHIDATA6/GPK6 XHIDATA6 I(pull-down) hag_a XHIDATA7/GPK7 XHIDATA7 I(pull-down) hag_a XHIDATA8/GPK8 XHIDATA8 I(pull-down) hag_a XHIDATA9/GPK9 XHIDATA9 I(pull-down) hag_a

XHIDATA10/GPK10 XHIDATA10 I(pull-down) hag_a XHIDATA11/GPK11 XHIDATA11 I(pull-down) hag_a XHIDATA12/GPK12 XHIDATA12 I(pull-down) hag_a XHIDATA13/GPK13 XHIDATA13 I(pull-down) hag_a

50


XHIDATA14/GPK14 XHIDATA14 I(pull-down) hag_a XHIDATA15/GPK15 XHIDATA15 I(pull-down) hag_a XHIDATA16/GPL13 XHIDATA16 I(pull-down) hag_a XHIDATA17/GPL14 XHIDATA17 I(pull-down) hag_a

XHIADR0/GPL0 XHIADR0 I(pull-down) hag_a XHIADR1/GPL1 XHIADR1 I(pull-down) hag_a XHIADR2/GPL2 XHIADR2 I(pull-down) hag_a XHIADR3/GPL3 XHIADR3 I(pull-down) hag_a XHIADR4/GPL4 XHIADR4 I(pull-down) hag_a XHIADR5/GPL5 XHIADR5 I(pull-down) hag_a XHIADR6/GPL6 XHIADR6 I(pull-down) hag_a XHIADR7/GPL7 XHIADR7 I(pull-down) hag_a XHIADR8/GPL8 XHIADR8 I(pull-down) hag_a XHIADR9/GPL9 XHIADR9 I(pull-down) hag_a

XHIADR10/GPL10 XHIADR10 I(pull-down) hag_a XHIADR11/GPL11 XHIADR11 I(pull-down) hag_a XHIADR12/GPL12 XHIADR12 I(pull-down) hag_a

XHICSN/GPM0 XHICSN I(pull-up) hag_a XHICSN_MAIN/GPM1 XHICSN_MAIN I(pull-up) hag_a XHICSN_SUB/GPM2 XHICSN_SUB I(pull-up) hag_a

XHIWEN/GPM3 XHIWEN I(pull-up) hag_a XHIOEN/GPM4 XHIOEN I(pull-up) hag_a XHIIRQN/GPM5 XHIIRQN O(H) hag_a XEINT0/GPN0 GPN0 I (pull-down) hag_a XEINT1/GPN1 GPN1 I (pull-down) hag_a XEINT2/GPN2 GPN2 I (pull-down) hag_a XEINT3/GPN3 GPN3 I (pull-down) hag_a XEINT4/GPN4 GPN4 I (pull-down) hag_a XEINT5/GPN5 GPN5 I (pull-down) hag_a XEINT6/GPN6 GPN6 I (pull-down) hag_a XEINT7/GPN7 GPN7 I (pull-down) hag_a XEINT8/GPN8 GPN8 I (pull-down) hag_a XEINT9/GPN9 GPN9 I (pull-down) hag_a

XEINT10/GPN10 GPN10 I (pull-down) hag_a XEINT11/GPN11 GPN11 I (pull-down) hag_a XEINT12/GPN12 GPN12 I (pull-down) hag_a XEINT13/GPN13 GPN13 I (pull-down) hag_a XEINT14/GPN14 GPN14 I (pull-down) hag_a XEINT15/GPN15 GPN15 I (pull-down) hag_a XM0CSN2/GPO0 XM0CSN2 O(H) hbg XM0CSN3/GPO1 XM0CSN3 O(H) hbg

51


XM0CSN4/GPO2 XM0CSN4 O(H) hbg XM0CSN5/GPO3 XM0CSN5 O(H) hbg

GPO4 Reserved O(H) hbg GPO5 Reserved O(H) hbg

XM0ADDR6/GPO6 XM0ADDR6 O(L) hbg XM0ADDR7/GPO7 XM0ADDR7 O(L) hbg XM0ADDR8/GPO8 XM0ADDR8 O(L) hbg XM0ADDR9/GPO9 XM0ADDR9 O(L) hbg

XM0ADDR10/GPO10 XM0ADDR10 O(L) hbg XM0ADDR11/GPO11 XM0ADDR11 O(L) hbg XM0ADDR12/GPO12 XM0ADDR12 O(L) hbg XM0ADDR13/GPO13 XM0ADDR13 O(L) hbg XM0ADDR14/GPO14 XM0ADDR14 O(L) hbg XM0ADDR15/GPO15 XM0ADDR15 O(L) hbg XM0ADRVALID/GPP0 XM0ADRVALID O(L) hbg

XM0SMCLK/GPP1 XM0SMCLK O(H) hbg XM0WAITN/GPP2 XM0WAITN I hbg

XM0RDY0_ALE/GPP3 XM0RDY0_ALE I/O(L) hbg XM0RDY1_CLE/GPP4 XM0RDY1_CLE I/O(L) hbg

XM0INTSM0_FWEN/GPP5 XM0INTSM0_FWEN I/O(H) hbg XM0INTSM1_FREN/GPP6 XM0INTSM1_FREN I/O(H) hbg

XM0RPN_RNB/GPP7 XM0RPN_RNB O(L)/I hbg XM0INTATA/GPP8 XM0INTATA I hbg

XM0RESETATA/GPP9 XM0RESETATA O(H) hbg XM0INPACKATA/GPP10 XM0INPACKATA I hb_c

XM0REGATA/GPP11 XM0REGATA O(H) hbg XM0WEATA/GPP12 XM0WEATA O(H) hbg XM0OEATA/GPP13 XM0OEATA O(H) hbg XM0CDATA/GPP14 XM0CDATA I hbg

XM0ADDR[18]/GPQ0 Xm0ADDR[18] O(L) hbg XM0ADDR[19]/GPQ1 Xm0ADDR[19] O(L) hbg

GPQ2 Reserved O(L) hbg GPQ3 Reserved O(H) hbg GPQ4 Reserved O(H) hbg GPQ5 Reserved I hbg GPQ6 Reserved I hbg

Xm0ADDR[17]/GPQ7 Xm0ADDR[17] O(L) hbg Xm0ADDR[16]/GPQ8 Xm0ADDR[16] O(L) hbg

52


THE TABLE BELOW SHOWS I/O TYPES AND DESCRIPTIONS.

Input (I)/Output (O) Type Descriptions

hag(pvhbsudtartg) 1.8V~3.3V Wide Range Bi-directional Buffer with Schmitt Trigger Input, Controllable Pull-up/down Resistor and A type Output driver

hag_a (pvhbsudtag_alv) 1.8V~3.3V Wide Range Bi-directional Alive Buffer with Schmitt Trigger Input, Controllable Pull-up/down Resistor and A type Output driver

hbg(pvhbsudtbrtg) 1.8V~3.3V Wide Range Bi-directional Buffer with Schmitt Trigger Input, Controllable Pull-up/down Resistor and B type Output driver

mbg(pvmbsudtbrtg) 1.8V~2.5V Wide Range Bi-directional Buffer with Schmitt Trigger Input, Controllable Pull-up/down Resistor and B type Output driver

Pin configuration guide in Sleep mode

Pin Condition Configuration

which are configured as Input Internal Pull-up/dn Enable or Output Low GPIO Pin which are configured as

Ouput Internal Pull-up/dn Disable or Output Low

Input Pin, which doesn't have internal Pull-up/dn control.

If External Device doesn't always drive Pin's level. External Pull-up Enable with Pull-up Resistor

If External Device's Power is Off Output Low Output pin, which are

connected to External device If External Device's Power is

On High or Low (It depends on External device's status)

If Memory's Power is Off Output Low and External Buffer does exist If Buffer can hold bus level, Pull-up Disable.

Data Bus

Memory's Power is On and no External Buffer Output Low

NOTE: 1. Don’t leave Floating Condition. 2. ADC should be set as Standby mode if ADC operation doesn't run. 3. XP & YP pins should not be connected to any external GND source in sleep mode. In other words, XP & YP should be floating in sleep mode.

4. USB OTG pads should be Suspend mode or Turn off the VDDOTG&VDDOTGI 5. USB Host’s DN,DP should be Pull-down as follows.

- USB Host’s DN,DP pull-down with 15K Ohm resistors. (even if USB Host is not used.) * This table is just for informational use only. User should consider his own Board condition and application.

53


11. DMA Controller DMA Controller has 2 signals out which are external DMA Request(ExdREQ) and External DMA Acknowledge(ExdACK). These signals are multiplexed with UART RXD[3:2] and UART TXD[3:2].

Therefore it is requisite to set GPIO 's GPB ports as a external DMA function.

Refer to the description of GPB0 , GPB1, GPB2 and GPB3 on GPBCON register.

The DMA request occurred when “DMA Request” signal is falling edge ( H -> L).

54


12. VECTORED INTERRUPT CONTROLLER

This Chapter is for internal Logic.

55


13. SECURITY SUB-SYSTEM


56


14. DISPLAY CONTROLLER

14.1 FEATURE OF THE DISPLAY CONTROLLER

Video Output Interface

Parallel RGB I/F : upto 24BPP Serial RGB I/F : upto 24BPP I80 I/F ITU-R BT.601 I/F (YUV 422 8bit) 5 Windows & Color Key & 16-level alpha blending

Window0 Support 1/2/4/8 BPP Palletized Color. Support 16/18/24BPP non-palletized color Support local bus.

Window1 Support 1/2/4/8 BPP Palletized Color. Support 16/18/24BPP non-palletized color Support local bus.

Window2 Support 1/2/4 BPP Palletized Color. Support 16/18/24BPP non-palletized color Support local bus.

Window3 Support 1/2/4 BPP Palletized Color. Support 16/18/24BPP non-palletized color

Layer

Window4 Support 1/2 BPP Palletized Color. Support 16/18/24BPP non-palletized color

Maximum Maximum 16M virtual screen size Size Recommended Upto WVGA(800x480)

: 24BPP Window 2ea + Window 1ea(for cursor)

57


14.2 VD SIGNAL CONNECTION

Below table shows that how to connect VD signal connection each bpp mode.

Parallel RGB Serial RGB 601

24BPP (888)

18BPP (666)

16BPP (565) 24BPP (888) 18BPP (666)

VD[23] R[7] R[5] R[4] D[7] D[5] VD[22] R[6] R[4] R[3] D[6] D[4] VD[21] R[5] R[3] R[2] D[5] D[3] VD[20] R[4] R[2] R[1] D[4] D[2] VD[19] R[3] R[1] R[0] D[3] D[1] VD[18] R[2] R[0] - D[2] D[0] VD[17] R[1] - - D[1] - VD[16] R[0] - - D[0] - VD[15] G[7] G[5] G[5] - - VD[14] G[6] G[4] G[4] - - VD[13] G[5] G[3] G[3] - - VD[12] G[4] G[2] G[2] - - VD[11] G[3] G[1] G[1] - - VD[10] G[2] G[0] G[0] - - VD[9] G[1] - - - - VD[8] G[0] - - - - VD[7] B[7] B[5] B[4] - - VEN_DATA[7] VD[6] B[6] B[4] B[3] - - VEN_DATA[6] VD[5] B[5] B[3] B[2] - - VEN_DATA[5] VD[4] B[4] B[2] B[1] - - VEN_DATA[4] VD[3] B[3] B[1] B[0] - - VEN_DATA[3] VD[2] B[2] B[0] - - - VEN_DATA[2] VD[1] B[1] - - - VEN_DATA[1] VD[0] B[0] - - - - VEN_DATA[0]

58


I80 CPU I/F (Parallel)

16BPP(565) 18BPP(666) 18BPP(666) 24BPP (888)

18BPP(666) 16BPP(565)

Lx_DATA16

000 001 010 011 100 101

1st 2nd 1st 2nd 1st 2nd 1st 2ndVD[23] - - - - - - - - - - VD[22] - - - - - - - - - - VD[21] - - - - - - - - - - VD[20] - - - - - - - - - - VD[19] - - - - - - - - - - VD[18] - - - - - - - - - - VD[17] - - - - - - - R[5] - - VD[16] - - - - - - - R[4] - - VD[15] R[4] R[5] - - - R[7] B[7] R[3] - - VD[14] R[3] R[4] - - - R[6] B[6] R[2] - - VD[13] R[2] R[3] - - - R[5] B[5] R[1] - - VD[12] R[1] R[2] - - - R[4] B[4] R[0] - - VD[11] R[0] R[1] - - - R[3] B[3] G[5] - - VD[10] G[5] R[0] - - - R[2] B[2] G[4] - - VD[9] G[4] G[5] - - - R[1] B[1] G[3] - - VD[8] G[3] G[4] - R[5] G[2] R[0] B[0] G[2] - - VD[7] G[2] G[3] - R[4] G[1] G[7] - G[1] R[4] G[2]VD[6] G[1] G[2] - R[3] G[0] G[6] - G[0] R[3] G[1]VD[5] G[0] G[1] - R[2] B[5] G[5] - B[5] R[2] G[0]VD[4] B[4] G[0] - R[1] B[4] G[4] - B[4] R[1] B[4]VD[3] B[3] B[5] - R[0] B[3] G[3] - B[3] R[0] B[3]VD[2] B[2] B[4] - G[5] B[2] G[2] - B[2] G[5] B[2]VD[1] B[1] B[3] B[1] G[4] B[1] G[1] - B[1] G[4] B[1]VD[0] B[0] B[2] B[0] G[3] B[0] G[0] - B[0] G[3] B[0]

When S3C6410X display controller output interface is parallel RGB(RGB16bpp), you want to connect parallel RGB(RGB18bpp) to LDI. Check example as below.

59


Figure 14_1) LCD connection example

60


15. POST PROCESSOR


61


16. TV SCALER


62


17. TV ENCODER

VDDDAC V 3.3V (± 0.3V)

XdacCOMP Connect 0.1uF ceramic capacitor to VDDDAC

XdacIREF Connect 0.1uF ceramic capacitor to GND

XdacVREF Connect 6.49KΩ to GND

XdacOUT[1:0] Connect 150Ω to GND

External X-tal frequency - 27MHz, 10ppm

External capacitance used for X-tal CEXT

25pF@CL=12.5 Note. This value depends on the

board design.

Feedback resistor between X27mXTI with X27mXTO 1M Ohms

U50

COMPOSITE

12

VIDEOGND

C178

100nF

+

C18233uF/10V

R327

150

R324

75

R331

150

C176

100nF U49

NJM2561

6

5

4

1

2

3

V+

GND

VIN

POWER

VOUT

VSAG

YC

Yn Cn

CN1

CONN_SVIDEO_12P

34

12

R3224.7K

VDD3.3V

XdacOUT_0

XdacOUT_1

R330

75

R329

0

R323

0

+

C18433uF/10V

+

C17733uF/10V

VDD3.3V

U51

NJM2561

6

5

4

1

2

3

V+

GND

VIN

POWER

VOUT

VSAG

+ C175

10uF/6.3V

C181

100nF

R3284.7K

R325 0+

C17933uF/10V

C183

100nF

+ C180

10uF/6.3V

R326

0

Figure 17_1) TV Encoder connection example

63


C2

100nF

VDD_DAC

CB5

100nF

XdacVREF

TP9DACVREF

XdacCOMP

XdacIREF

R26

6.49K/R1005

Figure 17_2) DAC Reference pin connection

64


18. GRAPHICS 2D


65


19. IMAGE ROTATOR


66


20. CAMERA INTERFACE

20.1 CAMIF INPUT CAMIF can support the next video standards,

(1) ITU-R BT 601 YCbCr 8-bit mode

(2) ITU-R BT 656 YCbCr 8-bit mode

* Maximum. 4096 x 4096 pixels Camera input support

Preview & Codec max. Horizontal size

Preview Codec Prescaled input Max Hsize 720 pixels 2048 pixels Scaler bypass 4096 pixels 4096 pixels

4096 pixels (Bypass YCbCr) 720 pixels (Except Bypass)

4096 pixels (Bypass YCbCr) 2048 pixels (Except Bypass)

TargetHsize (no rotation)

720 pixels (RGB) TargetHsize (with rotation)

360 pixels (YCbCr)


Name I/O Active Description

XciPCLK I - Pixel Clock, driven by the Camera processor

XciVSYNC I H/L Frame Sync, driven by the Camera processor

XciHREF I H/L Horizontal Sync, driven by the Camera processor

XciDATA[7:0] I - Pixel Data driven by the Camera processor

XciCLK O - Master Clock to the Camera processors

XciRSTn O H/L Software Reset or Power Down for the Camera processor

XcamFIELD I H/L 601 FIELD signal for External Camera Interface

User check interface signal mapping properly.

Note) S3C6410X have some restriction about video timing. User should be check following items

1. HREF should be valid after VSYNC pulse at capture start.

67


- PROGRESSIVE INPUT

In progressive mode, all the input data is stored in four buffers (pingpong memory which is designated by SFR) sequentially by the unit of frame.

- INTERACED INPUT

In interlace mode, the input data is stored in four buffers(pingpong memory which is designated by SFR). In this mode, even field frame data and odd field frame data is stored in turn. Therefore even field frame data is stored in 1st and 3rd pingpong memory while odd field frame data is stored 2nd and 4th pingpong memory. In case of image capture, start frame is always even field frame. In 601 interlaced input mode GPIO B[4] port is used field signal. GPIO B[4] port is used IrDA SDBW , CAM FIELD, input, output, CF Data DIR and EINT1[12].

B_XciPCLK

B_XciYDATA[7:0]

Xi2cSDA

B_XirSDBW

B_XciYDATA4

B_XciYDATA0B_XciYDATA[7:0]

B_XciRSTn

B_XciYDATA6

Camera Interface

R204

10K

VDD_CAM

B_XciYDATA2

VDD_CAM

B_XciYDATA5

B_XciCLK

B_XciYDATA1

B_XciVSYNC

B_XciYDATA3

J7

2.54mm header f emale

12345678910111213141516171819202122232425262728293031323334353637383940

B_XciYDATA7

B_XciHREFXi2cSCL

Figure 20_1) Camera Interface

68


21. MULTI-FORMAT VIDEO CODEC


69


22. JPEG CODEC


70


23. MODEM INTERFACE

This specification defines the interface between the Base-band Modem and the Application Processor for the data-exchange of these two devices. For the data-exchange, the AP (Application Processor, S3C6410X) has a DPSRAM(Dual Port SRAM, 8KB) buffer (on-chip) and the Modem chip can access that DPSRAM buffer using a typical asynchronous-SRAM interface.

23.1 Pin Description

Signal I/O Description XhiCSn I Chip select, driven by the Modem chip XhiWEn I Write enable, driven by the Modem chip XhiOEn I Read enable, driven by the Modem chip XhiINTR O Interrupt request to the Modem chip

XhiADDR[12:0] I Address bus, driven by the Modem chip XhiDATA[17:0] IO Data bus, driven by the Modem chip XEINT[27:16] I External interrupts

71


23.2 Pin Connection Example

Figure 23_1) Modem I/F Pin connection example

23.3 Caution (1) Voltage level is same between MODEM(memory bus and EXINT) and AP(MODEM I/F). Confirm the

datasheet what you want to use.

(2) There is only one interrupt request pin from AP to MODEM(XhiINTR). Any other extra interrupt request pin needs not between AP and modem because interrupt requests from modem to AP are delivered through Xhi_A[12:0] and Xhi_D[16:0] by writing some value to INT2AP register of DPSRAM in AP.

(3) If you use AP booing function, you must connect the CS(Chip Select) which is used to boot-up your device to S3C6410’s CS(XhiCSn).

(4) Refer the datasheet’s timing specification.

(5) Address connection between MODEM and AP follows the memory controlling policy of MODEM.

72


24. HOST INTERFACE Host I/F is same as Modem I/F except XhiADDR[6:3]. These signals are not used for Host Interface. So you may leave these signals as no connect.

73


25. USB Host

25.1 Power Domain VDD_UH is for USB Host power supplied with 3.3V

25.2 Circuit Diagram Example

R701 15K

C_PWR_5V

R703 33

CON7A

Dual USB Port - A ty pe

1234

VBUSD-D+GND

DN and DP should be routed evenly

XuhDPXuhDN

USB(HOST)SOCKET

R704 15K

R702 33

Figure 25_1) USB circuit example

25.3 USB Host connection

Power Domain VDDUH

Signal XuhDN, XuhDP

Others Connect to 15Kohms series resistor to GND.

25.4 Caution The S3C6410X USB system can be configured as following

1. USB 1.1 Host 1 Port & USB 2.0 OTG 1 Port

2. USB 1.1 Host 2 Ports

For detail, refer to S3C6410X User’s Manual.

74


26. USB 2.0 HS OTG

26.1 Power Domain VDD_OTG is for USB OTG phy power supplied with 3.3V and VDD_OTGI is for phy logic power supplied with 1.2V.

VDD_OTG and VDD_OTGI can be off to reduce power consumption if USBOTG function is not used.

26.2 Circuit Diagram Example To minimize power consumption in USB block, SEC recommends that user should use external regulators for VDD_OTG and VDD_OTGI. For implementing this scheme, user should consider following circuit.

(1) use regulator with enable function pin. S3C6410X can control usb power block freely using GPIO.

(2) use Charge Pump Circuit in order to supply VBUS to a bus-powered USB device.

To use Only Device mode but OTG mode.

(1) XusbID : leave as a no connect(Device mode)

(2) XusbDRVVBUS : leave as a no connect (The charge pump circuit should be removed)

(3) Refer to following circuit diagram about other signals.

RA12169K 1%

RA1524.3K 1%

JA0712

VDD_OTGI(1.1V)

C_PWR_5V

(3.3V)

USB20_EN

C_PWR_5V

+CTA10

10uF/16V

+CTA07

10uF/16V

JA0612

UA04

MAX1806EUA15

1

3

2

8

6

4

7

5

IN

POK

IN

OUT

SET

SHDN

OUT

GND

RA13 100K

+CTA08

10uF/16V

RA11 42.2K 1%

RA09

10K

OTGI

OTG

VDD_OTG

RA14 75.0K, 1%

VDD_D

RA10 100K

Vout=0.8(1+R2/R1)

+CTA09

10uF/16V

Vout=0.8(1+R2/R1)UA05

MAX1806EUA33

1

3

2

8

6

4

7

5

IN

POK

IN

OUT

SET

SHDN

OUT

GND

Figure 26_1) USB OTG Power Example

75


U701

MAX682

1

2

3

4 5

6

7

8nSKIP

nSHDN

IN

GND PGND

CXN

CXP

OUT

XotgDRV_VBUS C707

0.47uF

R707 0

R708 110K

XVBUSC_PWR_5V

C706

1uF

C708

2.2uF

Figure 26_2) Charge pump circuit example

XotgDP

XVBUS

CON8

USB_MINI-AB

12345

VBUSD-D+IDGND

XotgID

XotgDM

+CT701

10uF

C705

100nF

Figure 26_3)2 USB Otg Connector

XotgTO

C704

15pF

12

VDD_D

XotgTO

X70148MHz(N.C)

C703

15pF

12

TP703

XotgTOXotgTI

OSC2

OSCILLATOR 48Mhz

1 2

34

OE GND

OUTVDD

XREXT

R723

44.2ohm 1%

R724

1M ohm

Figure 26_4) Clock input(Oscillator or X-tal) and REXT connection

76


26.3 USB PLL Specification PLL & Clock Generator generally uses the following conditions.

REXT R 44.2 Ω ± 1% 12/24/48 MHz

tolerance +-100ppm External Oscillator frequency - peak jitter 100ps duty cycle 40/60~60/40

CEXT12M/24M - 20 pF External capacitance used for X-tal 48M - 15 pF

Feedback Resistor between XusbTI and XusbTO

1M Ohm

26.4 USB SIGNAL ROUTING 26.4.1 Introduction

This document conducts a guide to integrate a discrete high speed usb device onto a four layer PCB. The board design guidelines handle trace separation, termination placement requirements and overall trace length guidelines

26.4.2 PCB layout guidelines

Routing and placement

When an engineer lays out a new design, the excellent signal quality and minimized EMI problem must be required. That is based on four layer board. The first layer is for signal layer. The second layer is for ground. The third layer is for power and the fourth layer is for signal layer again. We should basically consider the following instruction.

I. HS signals should be placed on top shown in the below figure

II. HS clock and HS USB different pairs should be first routed with minimum trace length. III. Route high-speed USB signals not using vias and stubs with using two 45 degree turns or an arc

instead of making a single 90 degree trun. This reduces signal reflections and impedance changes that affect signal quality.

IV. Do not route usb traces under crystals, oscillators, clock synthesizers, magnetic devices or ICs that use and/or duplicate clocks.

V. Route all traces over continuous planes(VCC and GND), with no interruptions. Avoid crossing over anti-etch if at all possible.

VI. Ther parallelism between USB differential signals with the trace spacing should be maintained. The deviation should be minimized.

77


VII. The minimized length of high speed clock and periodic signal traces is highly recommended. The suggested spacing to clock signal is 50mils ( 1mils = 0.0254mm)

VIII. To prevent crosstalk, you should 20-mil minimum spacing between HS usb signal pairs. For example, IX. Max trace length mismatch between HS usb signal pairs such as DM and DP should be under

150mils.

X. Poor routing mistake

78


27. SD/MMC HOST CONTROLLER S3C6410X has three slots for supporting high speed SD/MMC interface. SDMMC0 as 4-bit MMC interface, SDMMC1 support 8-bit MMC or two 4-bit MMC interfaces. Every MMC controller belongs to VDD_MMC power.

Case 1 (3 Channel Usage) Case 2 (2 Channel Usage) Channel 0 4-bit mode 4-bit mode Channel 1 4-bit mode 4-bit or 8-bit mode Channel 2* 4-bit mode Not Used

Every controller has up to 52MHz speed. So clock and data line should have same routing path.

(1) Voltage level is same between device and SD/MMC GPIO whether VDD_MMC or not. Confirm the datasheet what you want to use.

(2) Confirm the pull-up resistor value chosen by specification. Refer the datasheet.

(3) MMC Channel 2 and SPI Channel 1 are can’t use at the same time. Refer to below table.

GPIO Name Function 1 Function 2 Function3 Function4 Function5

Function6

GPC4 SPI MOSI[1] MMC CMD2 I2S_V40 DO[0] EINT Input Output GPC5 SPI CLK[1] MMC CLK2 I2S_V40 DO[1] EINT Input Output

(4) MMC channel 0 and MMC channel 1 is shared same card detection pin. If one channel assign card detection pin, the other channel should assign external GPIO for card detection pin.

(5) MMC channel 2 hasn’t card detection pin. So should assign one external GPIO for card detection.

(6) DAT[3] card detection method didn’t recommend.

79


XmmcDATA0_0/ADDR_CF2

R81

810

KR

817

10KMMCDATA & CLK path

must be same lengthand route

XmmcDATA0_3

XmmcDATA0_1R

816

10K

VDD_MMC

XmmcCMD0/ADDR_CF1

R1

10K

VDD_MMC

CON1

SD Socket [Taisol]

12

3

4

56789

101112

131415

16171819202122232425

26

27

28

2930

NCNC

DAT2

DAT3

DAT4NCCMDNCDAT5NCVSSNC

NCVDDNC

NCCLKNCDAT6NCVSSNCDAT7NCDAT0

DAT1

SD_CD

SD_WP

P29/

GN

DP3

0/G

ND

XmmcDATA0_2

R2

10K

XmmcCLK0/ADDR_CF0

Figure 27_1)3 SDMMC0 interface example

80


R8

10K

R12

10K

R7

10K

XmmcDATA1_7/XmmcDATA2_3

CON2

SD Socket [Taisol]

12

3

4

56789

101112

131415

16171819202122232425

26

27

28

2930

NCNC

DAT2

DAT3

DAT4NCCMDNCDAT5NCVSSNC

NCVDDNC

NCCLKNCDAT6NCVSSNCDAT7NCDAT0

DAT1

SD_CD

SD_WP

P29

/GN

DP3

0/G

ND

R14

10K


R10

10KMMCDATA & CLK path

must be same lengthand route

XmmcCLK1


VDD_MMC

R9

10K

R13

10K

XmmcCMD1

XmmcDATA1_3

R6

10K

XmmcDATA1_0

R11

10K

VDD_MMC

R16

NC

XmmcDATA1_1


XmmcDATA1_2

Figure 47_2) SDMMC1 interface example

81


28. MIPI HSI INTERFACE CONTROLLER There are 4 Tx signals and 4 Rx signals

Here is an example to connect MIPI by FPC cable connecter.

rxDATA

Receiver

rxFLAG rxWAKE rxREADY

Transmitter

txDATA

Cellular Modem

txFLAG txWAKE txREADY

Figure 28_1) MIPI HSI connection with FPC Cable connector

82


29. SPI 29.1 EXTERNAL LOADING CAPACITANCE

S3C6410X has two SPI controllers. Both controllers should follow the external loading capacitance below.

Output capacitance must be lower than 10pF at the channel 0, channel1.

29.2 SPI MAXIMUM SPEED

The maximum frequency Master Tx/Master Rx/Slave Rx/Slave Tx(CPHA=0) is up to 50MHz.

The maximum frequency Slave Tx is up to 20MHz(CPHA=1).

29.3 SUPPORTED VOLTAGE RANGE

SPI interface voltage range is 2.5V~3.6V.

SPI channel 0 voltage follow by VDD_EXT and channel 1 voltage follow by VDD_MMC.

29.4 MUXED PIN LIMITATION

MMC Channel 2, I2S and SPI Channel 1 are can’t use at the same time. Refer to below table.

GPIO Name Function 1 Function 2 Function3 Function4 Function5

Function6

GPC4 SPI MOSI[1] MMC CMD2 I2S_V40 DO[0] EINT Input Output GPC5 SPI CLK[1] MMC CLK2 I2S_V40 DO[1] EINT Input Output

83


30. IIC-BUS INTERFACE IIC Bus interface has 2 signals out which are Xi2cSCL and Xi2cSDA. Generally, Each signal need to be

pulled up by 1Kohm resistor to VDDEXT. But this resistor value should be changed by signal bus loading capacitance.

30.1 Pin Description Signal I/O Description

Xi2cSCL IO I2C CH0 bus clock Xi2cSDA IO I2C CH0 bus data XuRXD[3] IO Can select I2C CH1 bus clock. Please refer to datasheet XuTXD[3] IO Can select I2C CH1 bus data. Please refer to datasheet

30.2 Equation of the pull-up resistor value

VBILB = 0.3 VBDDB VBIHB = 0.7 VBDDB

Figure 30_1) Definition of timing for High-Speed mode devices on the IIC –bus

1) tr (Rising time) which depends on Pull- up resistance and bus capacitance affects SCL frequency change ( Higher tr makes slower SCL), especially when it is High-Speed mode (400kHz)

2) tr (Rising time) maximum is 300 ns , minimum is 20 + 0.1 Cb (bus capacitance) 3) When tr (Rising time) is 300ns, SCL might be maximum 13% slower than original setting value 4) To make real SCL within 1% variation of setting value(400kHz) , tr (Rising time) should be less than

80nsec 5) User can use this fomula to determine Rp , Cb and tr

Rp(Pull-up resistance) Max is a function of the rise time minimum (tr) and the estimated bus capacitance(Cb)

RBpB x CBbB = tBrB / 1.2039

84


31. UART

Figure 31_1) UART connection with COM port example

- User must use EPLL or MPLL as a UART source clock to use High-Speed (upto 4Mbps) - User must use EPLL or MPLL as a UART source clock which is higher than baudrate * 16 for high-speed

- Max High speed baudrate is changeable depends on PCLK (System bus clock) which is

‘ Baudrate * 16 ≤ PCLK * ( 5.5 / 3 ) ‘

- Also S3C6410X’s Target Max High speed is 4Mbps, We don’t guarantee above 4Mbps even though a above formula is satisfied

- Max speed table (under using EPLL or MPLL as a UART source clock circumstance)

PCLK Max Baudrate Error tolerance rate

25MHz 2.7Mbps ± 2%

33MHz 3.6Mbps ± 2%

50MHz 4.0Mbps ± 1.8%

66MHz 4.0Mbps ± 1.8%

- Therefore user must make PCLK (System bus clock) higher than 33MHz to use Bluetooth 2.0 (3Mbps baudrate)

- Channel #0,1 supports Auto Flow Control with RTS & CTS signal.

-

85


32. PWM TIMER There are only two output signals, XpwmTOUT0 and XpwmTOUT1.

Note ) XCLKOUT signal which is multiplexed with XpwmTOUT0 is just PLL out and designed for debugging. If you use this signal as an external clock source, it may not be work well. Therefore, this port is appropriate to a test point.

For this reason, we don’t recommend to use these signal as an external clock source.

86


33. RTC

VDDRTC V 1.8~3.0V RTC X-tal frequency - 32.768KHz X-tal capacitance used for X-tal CEXT 15pF Feedback resistor 5M Ohm

87


34. WATCHDOG TIMER


88


35. AC97 CONTROLLER

35.1 AC97 Signal Description

Signal Input(I)/Output(O) Function Description

XpcmDCLK[0] XpcmDCLK[1]

I X97BITCLK 12.288MHz BITCLK from AC97 CODEC

XpcmEXTCLK[0] XpcmEXTCLK[1] O X97RESETn nReset for CODEC

XpcmFSYNC[0] XpcmFSYNC[1] O X97SYNC 48KHz Frame SYNC

XpcmSIN[0] XpcmSIN[1] I X97SDI Serial Data In From AC97 CODEC

XpcmSOUT[0] XpcmSOUT[1] O X97SDO Serial Data OUT to AC97 CODEC

35.2 Audio Ports In S3C6410X, There is one AC97 Controller and two ports are available for AC97 Controller. (Port D, Port E). Thus, it is decided to the Port for the AC97 controller.

35.3 Signal Description S3C6410X AC97 Controller AC97 CODEC(WM9713)

Figure 55_1) AC97 connection example

89


36. IIS BUS CONTROLLER



XpcmDCLK[0] Xi2sCLK[0] XpcmDCLK[1]

I/O Xi2sCLK[1]

IIS-bus serial clock

XpcmEXTCLK[0] Xi2sCDCLK[0] XpcmEXTCLK[1] I/O Xi2sCDCLK[1] IIS CODEC system clock

XpcmFSYNC[0] Xi2sLRCK[0] XpcmFSYNC[1] I/O Xi2sLRCK[1] IIS-bus channel select clock

XpcmSIN[0] Xi2sSI[0] XpcmSIN[1] I Xi2sSI[1] IIS-bus serial data input

XpcmSOUT[0] Xi2sSO[0] XpcmSOUT[1] O Xi2sSO[1] IIS-bus serial data output

36.2 Audio Port There are two IIS Interface Controllers in S3C6410X. Each Controller has a port to accept and drive signals external codec. Controller 0 uses Audio Port 0 (Port D), and Controller 1 uses Audio Port 1 (Port 1).

36.3 External Clock Source S3C6410X provides a master clock to the codec through the Xi2sCDCLK line. This configuration has an advantage that it is not necessary to configure oscillator circuit. For the making Master Clock, S3C6410X uses and divides EPLL, MPLL or PCLK (refer to the User’s Manual). If an oscillator circuit is configured for a precise clock for the Sampling Frequency without PLLs or Internal clocks, there is a way to accept to this frequency as a source of master clock through the Xi2sCDCLK line.

36.4 Connection Example

Figure 66_1) IIS Connection Example with WM8753 (Master Mode)

90


Figure 36_2) External OSC Circuit for IISCDCLK (with WM8753)

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37. PCM BUS CONTROLLER



XpcmDCLK[0] XpcmDCLK [0] XpcmDCLK [1]

I/O XpcmDCLK [1]

PCM Serial Shift Clock

XpcmEXTCLK[0] XpcmEXTCLK [0] XpcmEXTCLK[1] I/O XpcmEXTCLK [1] Optional reference clock

XpcmFSYNC[0] XpcmFSYNC [0] XpcmFSYNC[1] I/O XpcmFSYNC [1] PCM Sync indicating start of word

XpcmSIN[0] XpcmSIN [0] XpcmSIN[1] I XpcmSIN [1] PCM Serial Data Input

XpcmSOUT[0] XpcmSOUT [0] XpcmSOUT[1] O XpcmSOUT [1] PCM Serial Shift Clock

37.2. Audio Port There are two PCM Interface Controllers in S3C6410X. Each Controller has a port to accept and drive signals external codec. Controller 0 uses Audio Port 0 (Port D), and Controller 1 uses Audio Port 1 (Port 1).

37.3 External Clock Source

To make PCM Serial clock and PCM Frame Sync, PCM interface controller divides EPLL, MPLL or PCLK (refer to the User’s Manual). When these clocks are divided, its advantage is that it is not necessary to configure oscillator circuit. If an oscillator circuit is configured for a precise clock for the Sampling Frequency without PLLs or Internal clocks, there is a way to accept to this frequency as source of PCM Serial clock and PCM Frame Sync through the XpcmEXTCLK line.

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Figure 37_1) Internal clocks(ex:EPLL) for PCM master clock (with WM8753)

Figure 37_2) External clocks(ex:16.9344MHz) for PCM master clock (with WM8753)

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38. IRDA CONTROLLER IrDA signals (XirRXD, XirTXD, XirSDBW) are multiplexed with UART and IIC. Therefore it is requisite to set GPIO 's GPB port as a IrDA function.

Refer to GPB0 , GPB1 and GPB4 on GPBCON register.

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39. ADC&TOUCH SCREEN INTERFACE The 10/12bit CMOS ADC is a recycling type device with 8-channel analog inputs. It’s maximum conversion rate of 1Msps with 5MHz A/D converter clock. Touch screen interface can control/select pads (XP,XM,YP,YM) of the touch screen for X,Y position. AIN[4:7] mapped with touch signal like bellows

-AIN[4] = YM,

-AIN[5] = YP,

-AIN[6] = XM,

-AIN[7] = XP,

Note) If not use AIN[7](XP), tie AIN [7] to VDDA_ADC or ADCTSC register must be setting to 0xd3.

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40. KEYPAD INTERFACE Keypad signals(Key_pad_ROW and Key_pad_COL) are multiplexed with MMC channel 1, Host I/F and EINT. Therefore it is requisite to set GPIO ports as keypad function.

Refer to GPH, GPK, GPL and GPN registers.

Figure 40_1) Multi-key input keypad example

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41. IIS MULTI AUDIO INTERFACE


Signal Input(I)/Output(O) Function Description XmmcData[4] I/O I2SMULTI_BCLK IIS-bus serial clock XmmcData [5] I/O I2SMULTI_CDCLK IIS CODEC system clock XmmcData [6] I/O I2SMULTI_LRCLK IIS-bus channel select clock XmmcData [7] I I2SMULTI_DI IIS-bus serial data input XspiMISO[1] O I2SMULTI _DO[0] IIS-bus serial data output XspiCLK [1] O I2SMULTI _DO[1] IIS-bus serial data output XspiCS [1] O I2SMULTI _DO[2] IIS-bus serial data output

41.2 Audio Ports

Port No GPIO Group Signals Controller that can use this port

Audio Port 0 GPD

XpcmDCLK[0],

XpcmEXTCLK[0],

XpcmFSYNC[0],

XpcmSIN[0],

XpcmSOUT[0]

AC97, I2S0, PCM0

Audio Port 1 GPE

XpcmDCLK[1],

XpcmEXTCLK[1],

XpcmFSYNC[1],

XpcmSIN[1],

XpcmSOUT[1]

AC97, I2S1, PCM1

Audio Port 2 GPC, GPH

XspiMISO[1],

XspiCLK[1], XspiCS[1],

XmmcData1[4], XmmcData1[5], XmmcData1[6], XmmcData1[7],

I2S Multi channel*

*Note : When I2S Multi Channel use GPC and GPH, SPI Channel 1 and 8bit MMC1 channel dose not operate.

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41.3 External Clock Source S3C6410X provides a master clock to the codec through the XmmcData[5] line. This configuration has an advantage that it is not necessary to configure oscillator circuit. For the making Master Clock, S3C6410X uses and divides EPLL, MPLL or PCLK (refer to the User’s Manual). If an oscillator circuit is configured for a precise clock for the Sampling Frequency without PLLs or Internal clocks, there is a way to accept to this frequency as a source of master clock through the XmmcData[5] line.


Figure 41_1) IIS Connection Example with WM8753 (Master Mode)

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42. GRAPHIC 3D


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Documents

S3C6410XType Circuit Design Guide Rev1[1].00