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SMART

Atmel-11216A-ATARM-Configuring the LCD Controller of SAMA5D3x devices-Application Note_11-Jul-14

Scope

This application note describes how to use and optimize the LCD Controller(LCDC) embedded in the Atmel® | SMART ARM®-based SAMA5D31,SAMA5D33, SAMA5D34 and SAMA5D36 microcontrollers.

It presents the new characteristics available in this full-featured LCDC.

An LCD example is also provided in the SAMA5D3x Software Package availableon www.atmel.com.

Reference Documents

Type Reference Document

Datasheet SAMA5D3 Series Datasheet

Software Package SAMA5D3x Software Package

APPLICATION NOTE

Configuring the LCD Controller ofSAMA5D3x Devices

Atmel | SMART SAMA5D3 Series

http://www.atmel.com/Images/Atmel_11121_32-bit-Cortex-A5-Microcontroller_SAMA5D3_Datasheet.pdf

http://www.atmel.com/tools/SAMA5D3SOFTWAREPACKAGE.aspx

http://www.atmel.com

1Configuring the LCD Controller of SAMA5D3x devices [APPLICATION NOTE]Atmel-11216A-ATARM-Configuring the LCD Controller of SAMA5D3x devices-Application Note_11-Jul-14

Table of Contents

Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Reference Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1. LCD Controller Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1 Major Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.2 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.3 New Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2. LCDC Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.1 General Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.2 LCDC Timing Parameters Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.3 LCDC Input and Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.4 Typical Usage Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3. Display Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.1 DirectFB tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.2 Lmbench tool. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.3 Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.4 HDMI Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4. Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

1. LCD Controller Overview

The LCD controller consists of logic for transferring LCD image data from an external display buffer to an LCDmodule. The LCD has one display input buffer per overlay that fetches pixels through the dual AHB masterinterface and a lookup table to allow palletized display configurations. The LCD controller is programmable on aper overlay basis, and supports different LCD resolutions, window sizes, image formats and pixel depths.

1.1 Major Features Dual AHB Master Interface

Supports Single Scan Active TFT Display

Supports 12-, 16-, 18- and 24-bit Output Mode using a Spatial Dithering Unit

Supports Asynchronous Output Mode Supported (at synthesis time)

1, 2, 4, 8 bits per pixel (palletized)

12, 16, 18, 19, 24, 25 and 32 bits per pixel (non palletized)

Supports one base layer (background)

Supports two overlay layer windows

Supports one High End Overlay (HEO) window

Supports one hardware cursor, fixed or free Size

Little endian memory organization

Programmable timing engine, with integer clock divider

Programmable polarity for data, line synchro and frame synchro

Hardware cursor fixed size on the following patterns: 32x32, 64x64 and 128x128

Display size up to 1280x720

Color lookup Table with up to 256 entries and predefined 8-bit alpha

Programmable negative and positive row striding for all layers

Programmable negative and positive pixel striding for all overlay1, overlay2 and HEO layers

Horizontal and vertical rescaling unit with edge interpolation and independent non integer ratio

Hidden Layer Removal supported

Integrates fully programmable color space conversion

Overlay1, Overlay2 and High End Overlay integrate rotation engine: 90, 180, 270

Blender function supports arbitrary 8-bit alpha value and chroma keying


1.2 Block Diagram

Figure 1-1. Block Diagram

1.3 New Features

1.3.1 Dual AHB Master Interface

The dual AHB master is an interface unit designed to improve the memory access bandwidth. For Base Layer,Over Layer 1 and HEO layer, users can select the AHB Master suited for their application by setting the SIF field inthe CFG0 register of each layer. This selection allows programmers to balance the memory access load.

1.3.2 Display Resolution of Up to 1280x720

The LCD controller supports a single scan active TFT panel with a resolution of up to 1280x720.

1.3.3 Additional Overlay (OVR2)

Compared with the LCDC in the SAM9x5 series, the LCDC embedded in the SAMA5D3x series provides anadditional overlay layer (OVR2) which has the same features as overlay layer 1 (OVR1). This layer is locatedbelow the Hardware Cursor Channel (HCC) layer and above the other layers. To display the different layers,priority orders can be defined, as shown in Figure 1-2. For further details, refer to the SAMA5D3 Series Datasheet.

ATMEL CONFIDENTIAL

ATMEL CONFIDENTIAL64-bitDualAHBMasterInterface

DEAGUnit

SYSCTRLUnit

32-bitAPB InterfaceConfigurationRegisters

BaseLayer

CLUT

HEOLayer

CLUT

CSC

2DSC

CUE

OVR1Layer

CLUT

HCCLayer

CLUT

GABUnit

LTEUnit

LCD_DAT[23:0]

LCD_VSYNC

LCD_HSYNC

LCD_PCLK

LCD_DEN

LCD_PWM

LCD_DISP

CUE : Chroma Upsampling Engine

HEO : High End Overlay

CSC : Color Space Conversion

2DSC : Two Dimension Scaler

DEAG : DMA Engine Address Generation

HCC: Hardware Cursor Channel

GAB : Global Alpha Blender

LTE: LCD Timing EngineROT : Hardware Rotation

ROT

ROT

AHBBus

OVR2Layer

CLUT

ROT

PPLayer

Configuring the LCD Controller of SAMA5D3x devices [APPLICATION NOTE]Atmel-11216A-ATARM-Configuring the LCD Controller of SAMA5D3x devices-Application Note_11-Jul-14

2

Figure 1-2. Overlay Examples with Two Different Prioritization Algorithms

1.3.4 Post Processing

The output stream of pixels can be either displayed on the screen or written to the memory using the PostProcessing Controller (PPC). When the PPC is used, the screen display is disabled, but synchronization signalsremain active (if enabled).

Priority: HCC > OVR2 > OVR1 > HEO > BASE

Priority: HCC > OVR2 > HEO > OVR1 > BASE


2. LCDC Implementation

2.1 General Configuration

The following procedure describes how to configure the LCD controller. It is based on the base layer example. Thesame procedure is required to configure the display of the other layers. To display more than one layer, the alphablending feature must be enabled.

1. Configure pins.The pins used to interface the LCD Controller are multiplexed with PIO lines. First, the programmer must program the PIO Controller to assign the pins to their peripheral functions. If some I/O lines of the LCD Con-troller are not used by the application, they can be used for other purposes by the PIO Controller.

PIO_Configure(pPins, PIO_LISTSIZE(pPins));

2. Enable the peripheral clock.The LCDCK bit in the PMC_SCER register must be set before using the LCD Controller. It enables the LCD Controller clock.

PMC_EnablePeripheral(ID_LCDC);

3. Configure layer display characters.Each layer has its own configuration registers that define the layer display functions. The following instructions define that:

AHB_INCR4 burst is used

24-bit RGB mode is used

Rotation is disabled (XSTRIDE = 0)

Data is fetched from memory

REG_LCDC_BASECFG0 = LCDC_BASECFG0_DLBO|LCDC_BASECFG0_BLEN_AHB_INCR4;REG_LCDC_BASECFG1 = LCDC_BASECFG1_RGBMODE_24BPP_RGB_888_PACKED;REG_LCDC_BASECF G2 = LCDC_BASECFG2_XSTRIDE(0);REG_LCDC_BASECFG4 = LCDC_BASECFG4_DMA;

4. Configure LCDC display parameters.These parameters include the pixel clock, display mode, synchronization signal pulse width, vertical and horizontal porch width, active row number per frame and active pixel number per line, etc.The instructions given in this example define the following clock configuration:

Clock frequency: pixel_clock = selected_clock / (CLKDIV+2) with selected_clock = system_clock2x when CLKSEL is set to 1

Clock gating is disabled for HCR, HEO, OVR1, OVR2, BASE and post-processor layers

PWM mode is selected

Clock polarity is launched on the falling edge of the Pixel Clock

REG_LCDC_LCDCFG0 = LCDC_LCDCFG0_CLKDIV((BOARD_MCK*2)/BOARD_LCD_PIXELCLOCK-2) |LCDC_LCDCFG0_CGDISHCR |LCDC_LCDCFG0_CGDISHEO |LCDC_LCDCFG0_CGDISOVR1 |LCDC_LCDCFG0_CGDISBASE |LCDC_LCDCFG0_CLKPWMSEL


4

|LCDC_LCDCFG0_CLKSEL |LCDC_LCDCFG0_CLKPOL |LCDC_LCDCFG0_CGDISOVR2 // |LCDC_LCDCFG0_CGDISPP; //

In the following instructions, pulse widths, vertical and horizontal front porch and back porch timings are defined for all layers.

REG_LCDC_LCDCFG1 = |LCDC_LCDCFG1_VSPW(BOARD_LCD_TIMING_VPW-1) |LCDC_LCDCFG1_HSPW(BOARD_LCD_TIMING_HPW-1); REG_LCDC_LCDCFG2 = |LCDC_LCDCFG2_VBPW(BOARD_LCD_TIMING_VBP) |LCDC_LCDCFG2_VFPW(BOARD_LCD_TIMING_VFP-1); REG_LCDC_LCDCFG3 = |LCDC_LCDCFG3_HBPW(BOARD_LCD_TIMING_HBP-1) |LCDC_LCDCFG3_HFPW(BOARD_LCD_TIMING_HFP-1); The following instruction configures the LCD size.

REG_LCDC_LCDCFG4 = |LCDC_LCDCFG4_RPF(BOARD_LCD_HEIGHT-1) |LCDC_LCDCFG4_PPL(BOARD_LCD_WIDTH-1); The following instructions define the guardtime, output mode, display signal polarity, VSYNC and HSYNC configuration and PWM configuration.

REG_LCDC_LCDCFG5 = LCDC_LCDCFG5_GUARDTIME(30) |LCDC_LCDCFG5_MODE_OUTPUT_24BPP |LCDC_LCDCFG5_DISPDLY |LCDC_LCDCFG5_VSPDLYS |LCDC_LCDCFG5_VSPOL |LCDC_LCDCFG5_HSPOL; REG_LCDC_LCDCFG6 = LCDC_LCDCFG6_PWMCVAL(0xF0) |LCDC_LCDCFG6_PWMPOL |LCDC_LCDCFG6_PWMPS(6);

5. Enable the pixel clock and wait until it becomes stable.

REG_LCDC_LCDEN = LCDC_LCDEN_CLKEN;while(!(REG_LCDC_LCDSR&LCDC_LCDSR_CLKSTS));

6. Enable the horizontal and vertical synchronization and wait until synchronization signals are generated.

REG_LCDC_LCDEN = LCDC_LCDEN_SYNCEN;while(!(REG_LCDC_LCDSR&LCDC_LCDSR_LCDSTS));

7. Enable the display power signal and wait until the power signal is asserted.

REG_LCDC_LCDEN = LCDC_LCDEN_DISPEN;while(!(REG_LCDC_LCDSR&LCDC_LCDSR_DISPSTS));


8. Enable backlight.

REG_LCDC_LCDEN = LCDC_LCDEN_PWMEN;

9. Prepare display data in memory.

test_pattern_24RGB (pLcdBuffer);

10. Configure LCDC DMA.Each layer has a dedicated DMA channel.

The following sequence:

disables DMA interrupt

writes in the DMA control register

writes in the LCDC Control, Next and Configuration registers

REG_LCDC_BASEIDR = 0xFFFF;if(REG_LCDC_BASECHSR & LCDC_BASECHSR_CHSR) REG_LCDC_BASECHDR = LCDC_BASECHDR_CHDIS;testDscr.addr = (unsigned int)lcd_buffer;testDscr.ctrl = (LCDC_BASECTRL_ADDIEN |LCDC_BASECTRL_DSCRIEN|LCDC_BASECTRL_DMAIEN |LCDC_BASECTRL_DFETCH);testDscr.next = (unsigned int)&testDscr;;REG_LCDC_BASEADDR = (unsigned int)lcd_buffer;REG_LCDC_BASECTRL = (LCDC_BASECTRL_ADDIEN |LCDC_BASECTRL_DSCRIEN|LCDC_BASECTRL_DMAIEN |LCDC_BASECTRL_DFETCH);REG_LCDC_BASENEXT = (unsigned int)&testDscr;REG_LCDC_BASECFG0 = LCDC_BASECFG0_DLBO |LCDC_BASECFG0_BLEN_AHB_INCR16;REG_LCDC_BASECFG1 = LCDC_BASECFG1_RGBMODE_24BPP_RGB_888_PACKED;REG_LCDC_BASECFG2 = LCDC_BASECFG2_XSTRIDE(0);REG_LCDC_BASECFG4 = LCDC_BASECFG4_DMA;

11. Enable DMA to start the display.

REG_LCDC_BASECHER = LCDC_BASECHER_UPDATEEN | LCDC_BASECHER_CHEN;


6

2.2 LCDC Timing Parameters Configuration

Four timing parameters are critical to get a correct LCD panel display: Sync, Front Porch, Back Porch and ActiveVideo. Refer to Figure 2-1.

Figure 2-1. Definition of Timing Parameters

These four parameters can be configured in the LCDCFGx(1-4) registers.

To be able to configure these registers, the typical values of the LCD panel parameters must be known.

Table 2-1 shows the LCD panel timing parameters for the SAMA5D3x-EK evaluation kit.

Table 2-1. LCD Panel Timing Parameters

Parameter

Values

UnitMin Typ Max

CLK frequency - 33.26 - MHz

CLK period (tCPH) - 30.06 - ns

CLK pulse duty 40 50 60 %

HS period (tH) - 1056 - tCPH

HS pulse width 1 128 - tCPH

HS-first horizontal data time

STHD[7:0]+88 tCPH

HS active time - 800 - tCPH

VS period - 525 - tH

VS pulse width 1 2 - tH

VS-DEN time STVD[6:0]+8 tH

VS Active Time - 480 - tH

Video

HSync

VSync

“Active” Video Blanking

Blank start

Sync start Sync Time

Blank Time

SyncBackPorch

Top/LeftBorder

“Addressable” Video(Addr Time)

Bottom/RightBorder

FrontPorch Sync Back

Porch


From Table 2-1, the typical values of the following parameters can be found:

Note: If the LCD panel display is not correct with these typical values, users may need to adjust the porch and synchroniza-tion values.

2.3 LCDC Input and Output

The LCD Controller is used to fetch the data in the external SDRAM memory and transmit it to the LCD panel thatdisplays this data. It supports several input data storage formats and output transmit modes.

2.3.1 LCDC Input

For the HEO layer, three data storage types are available: YUV, RGB and Color Lookup.

For the other layers, only the RGB and Color Lookup types are available.

Each data storage type has many kinds of formats and each format has its own data storage and data alignmentmethod. For more detailed information, refer to the SAMA5D3 Series Datasheet.

2.3.2 LCDC Output

Table 2-2 shows the supported LCDC output modes.

Parameter Value

Sync (LCDCFG1)Horizontal synchronization pulse width 128 tCPH

Vertical synchronization pulse width 2 tH

Vertical porch (LCDCFG2)Vertical back porch width (525-480-2)/2 = 21 tH

Vertical front porch width 525-480-2-21 = 22 tH

Horizontal porch (LCDCFG3)Horizontal back porch width (1056-800-128)/2 = 64 tCPH

Horizontal front porch width (1056-800-128-64) = 64 tCPH

Active video (LCDCFG4)Number of active rows per frame 480

Number of pixels per line 800

Table 2-2. LCD Controller Data Output Mode

Value Name Description

0 OUTPUT_12BPP LCD output mode is set to 12 bits per pixel





8

2.4 Typical Usage Example

The LCD Controller can be programmed in 24-bit, 18-bit, 16-bit and 12-bit display modes. For each mode, the pinsare assigned as shown in Table 2-3. The LSB pins are always used for output.

Table 2-3. LCDC Pin assignment for Each Display Mode

Pin ID TFT 24 bits TFT 18 bits TFT 16 bits TFT 12 bits

LCD_DAT[23] R[7] – – –

LCD_DAT[22] R[6] – – –

LCD_DAT[21] R[5] – – –

LCD_DAT[20] R[4] – – –

LCD_DAT[19] R[3] – – –

LCD_DAT[18] R[2] – – –

LCD_DAT[17] R[1] R[5] – –

LCD_DAT[16] R[0] R[4] – –

LCD_DAT[15] G[7] R[3] R[4] –

LCD_DAT[14] G[6] R[2] R[3] –

LCD_DAT[13] G[5] R[1] R[2] –

LCD_DAT[12] G[4] R[0] R[1] –

LCD_DAT[11] G[3] G[5] R[0] R[3]

LCD_DAT[10] G[2] G[4] G[5] R[2]

LCD_DAT[9] G[1] G[3] G[4] R[1]

LCD_DAT[8] G[0] G[2] G[3] R[0]

LCD_DAT[7] B[7] G[1] G[2] G[3]

LCD_DAT[6] B[6] G[0] G[1] G[2]

LCD_DAT[5] B[5] B[5] G[0] G[1]

LCD_DAT[4] B[4] B[4] B[4] G[0]

LCD_DAT[3] B[3] B[3] B[3] B[3]

LCD_DAT[2] B[2] B[2] B[2] B[2]

LCD_DAT[1] B[1] B[1] B[1] B[1]

LCD_DAT[0] B[0] B[0] B[0] B[0]


2.4.1 24-bit Display Mode

2.4.1.1 Hardware Connection

Figure 2-2, Figure 2-3 and Figure 2-4 illustrate the hardware connection in 24-bit display modes.

Figure 2-2. 24-bit TFT Panel Hardware Connection in 24-bit Mode

Instance Signal I/O Line Peripheral LCDC LCDDAT0 PA0 A LCDC LCDDAT1 PA1 A LCDC LCDDAT2 PA2 A LCDC LCDDAT3 PA3 A LCDC LCDDAT4 PA4 A LCDC LCDDAT5 PA5 A LCDC LCDDAT6 PA6 A LCDC LCDDAT7 PA7 A LCDC LCDDAT8 PA8 A LCDC LCDDAT9 PA9 A LCDC LCDDAT10 PA10 A LCDC LCDDAT11 PA11 A LCDC LCDDAT12 PA12 A LCDC LCDDAT13 PA13 A LCDC LCDDAT14 PA14 A LCDC LCDDAT15 PA15 A LCDC LCDDAT16 PA16 A LCDC LCDDAT16 PC14 LCDC LCDDAT17 PA17 A LCDC LCDDAT17 PC13 LCDC LCDDAT18 PA18 A LCDC LCDDAT18 PC12 LCDC LCDDAT19 PA19 A LCDC LCDDAT19 PC11 LCDC LCDDAT20 PA20 A LCDC LCDDAT20 PC10 LCDC LCDDAT21 PA21 A LCDC LCDDAT21 PC15 LCDC LCDDAT22 PA22 A LCDC LCDDAT22 PE27 LCDC LCDDAT23 PA23 A LCDC LCDDAT23 PE28 LCDC LCDDEN PA29 A LCDC LCDDISP PA25 A LCDC LCDHSYNC PA27 A LCDC LCDPCK PA28 A LCDC LCDPWM PA24 A LCDC LCDVSYNC PA26 A

C

C

C

C

C

C

C

C

B0B1B2B3B4

G0G1G2G3G4G5

R0

R1

R2

R3

R4

LCDDEN

LCDVSYNC

LCDHSYNCLCDDISP

LCDPCKLCDPWM

LCDpanel


10



B0B1B2B3B4

G0G1G2G3G4G5

R1

R2

R3

R4

R5

LCDDEN

LCDVSYNC

LCDHSYNCLCDDISP

LCDPCKLCDPWM

C

C

C

C

C

C

C

C

LCDpanel

B5

R0



Note: For LCDDAT16 to LCDDAT23, either PIOA or PIOC can be used.

2.4.1.2 Software Configuration

The LCD must be configured in 24-bit output mode with LCDC_LCDCFG5_MODE_OUTPUT_24BPP define value.REG_LCDC_LCDCFG5 = LCDC_LCDCFG5_GUARDTIME(30) |LCDC_LCDCFG5_MODE_OUTPUT_24BPP |LCDC_LCDCFG5_DISPDLY |LCDC_LCDCFG5_VSPDLYS |LCDC_LCDCFG5_VSPOL |LCDC_LCDCFG5_HSPOL;


C

C

C

C

C

C

C

C

B0B1B2B3B4

G0G1G2G3G4G5

R0

R1

R2

R3

R4

LCDDEN

LCDVSYNC

LCDHSYNCLCDDISP

LCDPCKLCDPWM

LCDpanel


12

2.4.2 18-bit Display Mode

2.4.2.1 Hardware Connection

Figure 2-5, Figure 2-6 and Figure 2-7 illustrate the hardware connection in 18-bit display mode.

Figure 2-5. 24-bit TFT Panel Hardware Connection in 18-bit ModeInstance Signal I/O Line Peripheral LCDC LCDDAT0 PA0 A LCDC LCDDAT1 PA1 A LCDC LCDDAT2 PA2 A LCDC LCDDAT3 PA3 A LCDC LCDDAT4 PA4 A LCDC LCDDAT5 PA5 A LCDC LCDDAT6 PA6 A LCDC LCDDAT7 PA7 A LCDC LCDDAT8 PA8 A LCDC LCDDAT9 PA9 A LCDC LCDDAT10 PA10 A LCDC LCDDAT11 PA11 A LCDC LCDDAT12 PA12 A LCDC LCDDAT13 PA13 A LCDC LCDDAT14 PA14 A LCDC LCDDAT15 PA15 A LCDC LCDDAT16 PA16 A LCDC LCDDAT16 PC14 LCDC LCDDAT17 PA17 A LCDC LCDDAT17 PC13 LCDC LCDDAT18 PA18 A LCDC LCDDAT18 PC12 LCDC LCDDAT19 PA19 A LCDC LCDDAT19 PC11 LCDC LCDDAT20 PA20 A LCDC LCDDAT20 PC10 LCDC LCDDAT21 PA21 A LCDC LCDDAT21 PC15 LCDC LCDDAT22 PA22 A LCDC LCDDAT22 PE27 LCDC LCDDAT23 PA23 A LCDC LCDDAT23 PE28 LCDC LCDDEN PA29 A LCDC LCDDISP PA25 A LCDC LCDHSYNC PA27 A LCDC LCDPCK PA28 A LCDC LCDPWM PA24 A LCDC LCDVSYNC PA26 A

C

C

C

C

C

C

C

C

B2B3B4B5B6B7G2G3G4G5G6G7

R2R3R4

R5

R6

R7

LCDDEN

LCDVSYNC

LCDHSYNCLCDDISP

LCDPCKLCDPWM

B0B1

B0B1

B0B1

LCDpanel


Figure 2-6. 18-bit TFT Panel Hardware Connection in 18-bit ModeInstance Signal I/O Line Peripheral LCDC LCDDAT0 PA0 A LCDC LCDDAT1 PA1 A LCDC LCDDAT2 PA2 A LCDC LCDDAT3 PA3 A LCDC LCDDAT4 PA4 A LCDC LCDDAT5 PA5 A LCDC LCDDAT6 PA6 A LCDC LCDDAT7 PA7 A LCDC LCDDAT8 PA8 A LCDC LCDDAT9 PA9 A LCDC LCDDAT10 PA10 A LCDC LCDDAT11 PA11 A LCDC LCDDAT12 PA12 A LCDC LCDDAT13 PA13 A LCDC LCDDAT14 PA14 A LCDC LCDDAT15 PA15 A LCDC LCDDAT16 PA16 A LCDC LCDDAT16 PC14 LCDC LCDDAT17 PA17 A LCDC LCDDAT17 PC13 LCDC LCDDAT18 PA18 A LCDC LCDDAT18 PC12 LCDC LCDDAT19 PA19 A LCDC LCDDAT19 PC11 LCDC LCDDAT20 PA20 A LCDC LCDDAT20 PC10 LCDC LCDDAT21 PA21 A LCDC LCDDAT21 PC15 LCDC LCDDAT22 PA22 A LCDC LCDDAT22 PE27 LCDC LCDDAT23 PA23 A LCDC LCDDAT23 PE28 LCDC LCDDEN PA29 A LCDC LCDDISP PA25 A LCDC LCDHSYNC PA27 A LCDC LCDPCK PA28 A LCDC LCDPWM PA24 A LCDC LCDVSYNC PA26 A

B0B1B2B3B4

G0G1G2G3G4G5

R1

R2R3

R4

R5

LCDDEN

LCDVSYNC

LCDHSYNCHLCDDISP

LCDPCKLCDPWM

C

C

C

C

C

C

C

C

LCDpanel

B5

R0


14



B0B1B2B3B4G0G1G2G3G4G5

R0R1R2

R3

R4

LCDDEN

LCDVSYNC

LCDHSYNCLCDDISP

LCDPCKLCDPWM

C

C

C

C

C

C

C

C

LCDpanel


2.4.2.2 Software Configuration

The LCD must be configured in 18-bit output mode with LCDC_LCDCFG5_MODE_OUTPUT_18BPP define value.REG_LCDC_LCDCFG5 = LCDC_LCDCFG5_GUARDTIME(30) |LCDC_LCDCFG5_MODE_OUTPUT_18BPP |LCDC_LCDCFG5_DISPDLY |LCDC_LCDCFG5_VSPDLYS |LCDC_LCDCFG5_VSPOL |LCDC_LCDCFG5_HSPOL;

For 16-bit and 12-bit modes, the implementations are the same. If the LCD panel has more pins, the MSB pins ofthe LCD panel must be connected to LCDC and the LSB pins to Ground. If the LCD panel has fewer pins, all pinsmust be connected to the LCDC MSB pins. Then the corresponding display mode must be set.


16

3. Display Performance

Two tests have been performed under Linux environment. They show the 2D graphic performance (Section 3.1”DirectFB tool” ) and the external SDRAM bandwidth used by the LCD (Section 3.2 ”Lmbench tool” ). An analysisof these tests is given in Section 3.3.

The example given in this section is based on a system where the external SDRAM memory is the DDR2-SDRAM.

3.1 DirectFB tool

The DirectFB benchmark tool (http://elinux.org/DirectFB) running on one SAMA5D3x-EK evaluation kit has beenused to test the 2D graphic performance.

The test result is as follows:

~~~~~~~~~~~~~~~~~~~~~~~~~~| DirectFB 1.4.15 |~~~~~~~~~~~~~~~~~~~~~~~~~~ (c) 2001-2010 The world wide DirectFB Open Source Community (c) 2000-2004 Convergence (integrated media) GmbH ----------------------------------------------------------------

(*) DirectFB/Core: Single Application Core. (2012-12-31 09:31) (*) Direct/Memcpy: Using libc memcpy()(*) Direct/Thread: Started 'VT Switcher' (-1) [CRITICAL OTHER/OTHER 0/0] <8388608>...(*) Direct/Thread: Started 'VT Flusher' (-1) [DEFAULT OTHER/OTHER 0/0] <8388608>...(*) DirectFB/FBDev: Found '' (ID 0) with frame buffer at 0x3f000000, 1500k (MMIO 0xf0030000, 0k)(*) Direct/Thread: Started 'Keyboard Input' (-1) [INPUT OTHER/OTHER 0/0] <8388608>...(*) DirectFB/Input: Keyboard 0.9 (directfb.org)(*) Direct/Thread: Started 'Linux Input' (-1) [INPUT OTHER/OTHER 0/0] <8388608>...(*) DirectFB/Input: AT42QT1070 QTouch Sensor (1) 0.1 (directfb.org)(*) Direct/Thread: Started 'Linux Input' (-1) [INPUT OTHER/OTHER 0/0] <8388608>...(*) DirectFB/Input: atmel touch screen controller (2) 0.1 (directfb.org)(*) Direct/Thread: Started 'Hotplug with Linux Input' (-1) [INPUT OTHER/OTHER 0/0] <8388608>...(*) DirectFB/Input: Hot-plug detection enabled with Linux Input Driver (*) DirectFB/Graphics: Generic Software Rasterizer 0.6 (directfb.org)(*) DirectFB/Core/WM: Default 0.3 (directfb.org)(*) FBDev/Mode: Setting 800x480 RGB16(*) FBDev/Mode: Switched to 800x480 (virtual 800x480) at 16 bit (RGB16), pitch 1600(*) Direct/Interface: Loaded 'PNG' implementation of 'IDirectFBImageProvider'.(*) Direct/Interface: Loaded 'FT2' implementation of 'IDirectFBFont'.(*) Direct/Interface: Loaded 'GIF' implementation of 'IDirectFBImageProvider'.

Benchmarking 256x256 on 800x464 RGB16 (16bit)...

Anti-aliased Text 3.032 secs ( 90.237 KChars/sec) [100.0%]Anti-aliased Text (blend) 3.184 secs ( 18.090 KChars/sec) [100.0%]


http://elinux.org/DirectFB

Fill Rectangle 3.017 secs ( 178.122 MPixel/sec) [100.3%]Fill Rectangle (blend) 3.286 secs ( 3.988 MPixel/sec) [100.3%]Fill Rectangles [10] 3.189 secs ( 184.955 MPixel/sec) [100.3%]Fill Rectangles [10] (blend) 16.395 secs ( 3.997 MPixel/sec) [ 99.9%]Fill Triangles 3.022 secs ( 94.335 MPixel/sec) [ 99.6%]Fill Triangles (blend) 3.378 secs ( 3.880 MPixel/sec) [100.0%]Draw Rectangle 3.003 secs ( 11.754 KRects/sec) [100.0%]Draw Rectangle (blend) 3.027 secs ( 1.486 KRects/sec) [100.3%]Draw Lines [10] 3.005 secs ( 36.938 KLines/sec) [100.3%]Draw Lines [10] (blend) 3.151 secs ( 6.347 KLines/sec) [100.0%]Fill Spans 3.002 secs ( 109.153 MPixel/sec) [100.0%]Fill Spans (blend) 3.328 secs ( 3.938 MPixel/sec) [100.0%]Blit 3.031 secs ( 67.027 MPixel/sec) [ 99.6%]Blit 180 3.012 secs ( 52.219 MPixel/sec) [100.0%]Blit colorkeyed 3.043 secs ( 49.534 MPixel/sec) [100.0%]Blit destination colorkeyed 3.485 secs ( 9.402 MPixel/sec) [100.0%]Blit with format conversion 3.082 secs ( 34.022 MPixel/sec) [100.0%]Blit with colorizing 3.856 secs ( 6.798 MPixel/sec) [100.0%]Blit from 32bit (blend) 3.813 secs ( 5.156 MPixel/sec) [100.0%]Blit from 32bit (blend) with colorizing 5.402 secs ( 2.426 MPixel/sec) [100.0%]Stretch Blit 3.005 secs ( 48.713 MPixel/sec) [100.0%]Stretch Blit colorkeyed 3.017 secs ( 41.010 MPixel/sec) [100.0%]

3.2 Lmbench tool

The bw_mem tool, from LMbench (http://www.bitmover.com/lmbench/) has been used to test the effective DDR2-SDRAM bandwidth under three different LCDC configurations.

1. No LCD display: 366 MB/s./bw_mem 16m rd16.78 366.32

2. 800×480 60 Hz RGB16: 347 MB/s


18

http://www.bitmover.com/lmbench/

./bw_mem 16m rd16.78 347.71

3. 1280×720 60 Hz RGB16: 163 MB/s./bw_mem 16m rd16.78 163.58

We know that the LCD bandwidth should not exceed 60% of the effective DDR2 bandwidth to let the overallsystem handle other activities.

From the bw_mem tool results, we can calculate that the DDR2 bandwidth used in 720p mode by the LCD is: (366-163)/366 = 56%, which is less than 60%.

These results show that the 720p mode can be supported.


3.3 Analysis

3.3.1 Definitions

Pixel Clock (PC):It depends on the Image Resolution (IR) of the largest layer, on the blanking (BL) and on the Refresh Rate (RR).

Color Depth (CD):It is the number of bytes used to define the pixel color.

Bandwidth (BW):

For a given IR, the BW is given in Megabytes per second (MB/s) by the formula: PC x CD.

3.3.2 Bandwidth

A DDR2-SDRAM access analysis gives the following results:

For each burst write access, 4 clock edges (out of 9) are used to transmit data. The bandwidth is about 1064×4÷9 = 473 MB/s.

For each burst read access, 4 clock edges (out of 11) are used to transmit data.The bandwidth is about 1064×4/11 = 387 MB/s.

So the average DDR2 bandwidth is about (473+387)÷2 = 430 MB/s.

All results provided in Table 3-2 are based on this average DDR2 bandwidth, with the following configurations:

All calculations given in Table 3-2 are theoretical and the tests are performed without operating system. The HCClayer does not have any impact on the DDR2 bandwidth.

Table 3-1. Configurations used in the tests

Configuration SizeRefresh

Rate Pixel Clock

(MHz)

1 800x480 60 33.264

2 1280x720 60 74.25

Table 3-2. LCD Bandwidth For Configurations 1 & 2

RGB modeCD

(Bits)

DMA Address

Alignment(Bits)

CD(Bytes)

Configuration 1 Configuration 2

800x480 Max. BW (MB/s)

800x480

% DDR2 BW

1280x720 Max. BW (MB/s)

1280x720

% DDR2 BW

12 bpp RGB 444 12 16 2 66 15.5% 148 34.5%

16 bpp ARGB 4444 16 16 2 66 15.5% 148 34.5%

16 bpp RGBA 4444 16 16 2 66 15.5% 148 34.5%

16 bpp RGB 565 16 16 2 66 15.5% 148 34.5%

16 bpp TRGB 1555 16 16 2 66 15.5% 148 34.5%

18 bpp RGB 666 18 32 4 133 31% 296 69%

18 bpp RGB 666 Packed 18 24 3 99 23.2% 222 51.8%

19 bpp TRGB 1666 19 32 4 133 31% 296 69%

19 bpp TRGB 1666 19 24 3 99 23.2% 222 51.8%

24 bpp RGB 888 24 32 4 133 31% 296 69%


20

Table 3-2 also illustrates that many configurations are supported.

For the best performance of the overall system, the user must carefully configure each LCD layer.

3.3.3 Configuration Example

Figure 3-1 and Table 3-3 provide an example of LCD configuration given in the software package.

Figure 3-1. Software Package Example with 800 x 480 LCD Display

The configuration shown in Table 3-1 uses 30% of the DDR2 bandwidth.

24 bpp RGB 888 Packed 24 8 3 99 23.2% 222 51.8%

25 bpp TRGB 1888 25 32 4 133 31% 296 69%

32 bpp ARGB 8888 32 32 4 133 31% 296 69%

32 bpp RGBA 8888 32 32 4 133 31% 296 69%

Table 3-2. LCD Bandwidth For Configurations 1 & 2 (Continued)

RGB modeCD

(Bits)

DMA Address

Alignment(Bits)

CD(Bytes)

Configuration 1 Configuration 2

800x480 Max. BW (MB/s)

800x480

% DDR2 BW

1280x720 Max. BW (MB/s)

1280x720

% DDR2 BW

Table 3-3. LCD Bandwidth Value Examples

Layer Type Layer Size Layer CD (bytes) Maximum BW (MB/s) % DDR2 BW

BASE 800 × 480 3 99.79 23.2%

OVR1 420 × 290 3 21.92 5.1%

OVR2 160 × 120 3 3.46 0.8%

HEO 264 × 96 3 4.56 1.1%

HCC 32 × 32 3 - 0

BASE OVR1

OVR2

HEO

HCC


3.4 HDMI Example

As specified in the SAMA5D3 Series Datasheet, the pixel clock can be calculated using the following formula:

In SAMA5D3 devices, the series master clock (MCK) maximum frequency is 166 MHz. It supports the 720p format.

The LCDC selected clock can be set to 1×MCK or 2×MCK (i.e.166 MHz or 332 MHz).

Therefore, CLKDIV = (selected_clock / pixel_clock) - 2 = (332÷74.25)-2=2.47 or (166÷74.25) -2=0.24.

Since CLKDIV =0.24 cannot be used and CLKDIV must be an integer, only CLKDIV=2 can be selected.

In this case, the pixel clock is 332/4=83 MHz.

We can observe that this pixel clock frequency is supported by most of the HDMI transmitters listed in Table 3-4.The Silicon Image Sil9022A HDMI™ transmitter can be taken as an example since it supports a maximum inputfrequency of 165 MHz. So the LCDC output pixel clock frequency must not be greater than 165 MHz.

pixel_clock = selected_clock / (CLKDIV+2)

Table 3-4. Video Input Feature Comparison of HDMI transmitters

HDMI Transmitter SiI9030 SiI9020 SiI9022 SiI9022-6 SiI9024 SiI9024-6

SiI9022A SiI9024A SiI9022A SiI9024A

VFBGA QFN

Video Input

Clock duty cycle 60/40 60/40 70/30 70/30 70/30 70/30 70/30 70/30 70/30 70/30

Max. pixel clock frequency

150 MHz 84 MHz 82.5 MHz 165 MHz 82.5 MHz 165 MHz 165 MHz 165 MHz 165 MHz 165 MHz

Input signal level

3.3 V 3.3 V 3.3 V or

1.8 V 3.3 V or

1.8 V 3.3 V or

1.8 V 3.3 V or 1.8 V

3.3 V or 1.8 V

3.3 V or 1.8 V

3.3 V or 1.8 V

3.3 V or 1.8 V


22

3.4.1 Hardware Connection

Figure 3-2 illustrates the hardware connection.

Figure 3-2. HDMI Function Connection

3.4.2 Software Configuration

The LCDC must be configured in 24-bit output mode (refer to Software Configuration in Section 2.4.1.2). Then theSil9022A and the TV set must be configured for a 720p operation mode.

1. Configure the display parameter.Sil9022a_InitializeStateVariables();/*Configure display parameters, such as pixel clock and size of LCD panel*/// gvmode: 720PSil9022a_VideoSel( gvmode );/*Configure audio parameters, such as audio mode, channel numbers and I2S format*/// AFS_48K: audio sampling rateSil9022a_AudioSel( AFS_48K);

2. Initialize the SSC and LCDC functions of SAMA5D3x devices./*A general LCDC and SSC configuration*/Sil9022a_test_SSC_Initialize(); // pHdmiBuffer: display data bufferSil9022a_test_pattern_24RGB(pHdmiBuffer); Sil9022a_test_LCDD_Initialize(pHdmiBuffer);

3. Get the TV set type and status./*Read EDI block to get the TV’s information, including manufacturer, sink device type(DVI or HDMI),etc.*/Sil9022a_DoEdidRead();

TFTK

PCK

TD

TWICK

TWID


4. Configure the Sil9022A./*Configure the TV set to display, according to its sink type*/// Set HDMI modeSil9022a_Modify(&twidHdmi, SIL9022A_SLAVE_ADDRESS, TPI_SYSTEM_CONTROL_DATA_REG, OUTPUT_MODE_MASK, OUTPUT_MODE_HDMI); Sil9022a_ReadModifyWriteIndexedRegister(&twidHdmi,SIL90 22A_SLAVE_ADDRESS,INDEXED_PAGE_0, 0x0A, 0x08, 0x08);/*Rx power up and Configure chip*/Sil9022a_OnDownstreamRxPoweredUp();

Note: For further details, please refer to SAMA5D3x Software Package or Sil9022A SDK.

4. Conclusion

The LCDC embedded in the SAMA5D3x devices supports various high-end LCD configurations and videoplayback in 720p resolution.

This application note helps users configure the LCDC in a display mode suitable for their applications.


24

5. Revision History

Table 5-1. Configuring the LCD controller of SAMA5D3x Rev 11216A

Document Rev. Comments

11216A First issue.


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