Semiconductor Industry Sourcebook Staying Connected

Luckily, BPS expects moderate growth

for the year and has increased manpower

to maintain its R&D schedule and

customer support.

The wafer fab equipment market is

expected to shrink by 14% during this

year – after a 12% decrease in 1997 – and

the semiconductor equipment market will

probably remain slow until the end of

1999, as now forecasted by several

industry analysts. Despite the continuing

vigor of markets in North America and

Taiwan, the erosion of many key

currencies in Southeast Asia, the open

questions surrounding the Japanese

economy as well as the enthusiastic capital

spending spree of 1995-96 that left many

manufacturers with extra capacity, all these

make a quick recovery improbable.

Motors for the future

The crash in the DRAM business has

thrown a shadow over many new projects

in the industry. However, most

development projects are being postponed

rather than simply canceled. As these

investments are stretched over a longer

period of time, new developments and

technical innovations are delayed.

We have no doubt that the DRAM

segment will recover, but it will take

longer than for other semiconductor

sectors. The non-DRAM technologies

have proven much more resilient.

According to Jean-Philippe Dauvin of

STMicroelectronics, the new

semiconductor market drivers in the next

five years will be digital video, smart cards,

car multimedia, digital mobile phones,

computer peripherals, power-train devices

for cars and digital networking.

BPS keeps growing

Contrary to the general situation in the

industry, BPS semiconductor activities

remain profitable. Currently, all R&D is on

track for the year. None of our equipment

and process development programs have

been delayed and new product

introductions will be launched on time.

BPS enjoys high involvement

in many non-DRAM

technologies. Currently, our

focus on electronic

components and sensors for

the automotive and

telecommunications industries promise

high growth in the near future.

Another reason for the positive view of

the future at BPS is the noticeable increase

in activity in our major industry segments.

Demand in these areas is expected to be

growing by the end of the year.

Underlining the moderate but steady

growth expectations is the recent hire of

additional product specialists and sales

engineers to provide added support.

Premium on innovation

To take advantage of these

opportunities, BPS is currently expending

great efforts to maintain its No. 1 position

in PVD packaging with a new sputter

process for UBM (for more information,

see page 11) and a new etching tool for

surface preparation. We are following a

similarly ambitious plan for the III-V

market. Our evaporation, sputter, etching,

PECVD and RTP tools and processes now

allow us to offer a “one-stop” production

solution for all III-V applications (see our

report beginning on page 18).

The addition of new processes and

hardware to our cluster tool platform

resulted in the recent launch of an RTP

process module. Additional components will

be added continually. In fact, the ongoing

expansion and optimization of applications

for the cluster tool is one of BPS’ major

priorities. Of course, these development

efforts also include the on-time market

release of our 300mm system.

Downgrading for 300mm

Current economic conditions have led

most semiconductor manufacturers to

delay the introduction of 300mm projects

– the biggest and costliest retooling effort

in the history of the industry. This means

most R&D will continue to take place on

200mm wafers for the time being.

The response from BPS is to offer a

200mm tooling kit to adapt the 300mm

cluster tool to the smaller format. This

“downgrading” avoids any interruption to

200mm wafer pilot production and R&D

projects while leaving the

possibility for ramp-up to

300mm wafers by simply exchanging

the tooling kit. An additional benefit is

that investment costs can be spread over a

larger time frame (see page 24 for more on

our 300mm project).

Service means profitability

With the ever quicker spiral of

technical innovation and shorter product

life cycles, only a comprehensive customer

support offer allows our customers to get

the maximum benefit out of every

generation of production equipment.

Previously considered a check-list of regular

system maintenance visits and a full

inventory of spare parts, today our

customer support teams are even more

closely tied to the success of each

production installation at customer sites

around the world. More than a network of

hot-lines and remote diagnostic reports, our

mandate today is to provide the quickest

possible ramp-up to full production as well

as maintenance and support contracts that

can be tailored to fit customer needs.

Ultimately, this is the surest way to

maximize the bottom line – and that’s the

major part of staying connected.

Editor in Chief:Dr. Martin Bader

Managing Editor:Tammara Umbricht-Boyd

Editorial team:Jurg Steinmann, BPS CommunicationsAlicia Bianchi, BPS Inc.Peter Kraus, REMCOM

Design/Layout:OTM Design, London

Published by:Balzers Process Systems, P.O. Box 1000, 9496 Balzers, Liechtenstein

Photography:Alberto VenzagoJacques Hartmann, Balzers AGErich Marxer, Procolora AG

Printed in England on recycled paper.

Please feel free to contact us:Fax: +41-75 388 6539E-mail: [email protected]

Chip – the Semiconductor Sourcebook is alsoavailable online at our Web site

Chip editorial 2

Staying connected with semiconductors 2

BPS around the semiconductor globe 4

Flip chip technology gains market share 6

On the fast track with C4 technology 6

Setting up a production standard with Motorola 7

Flip chip made by C4 technology 8

Packaging dictionary 9

Under Bump Metallization (UBM)for Flip Chip 10

Coating systems for UBM by evaporation 10

Coating systems for UBM by batch sputtering 11

Coating systems for UBM by cluster tools 12

Packaging matrix 13

Catching the Surface Acoustic Wave 14

SAW matrix 15

Introducing Bulk Acoustic Wave devices 16

One stop for III-V 18

III-V matrix 20

ITRI and compound semiconductortechnology 21

PVD metallization for ICs 22

Integrated vacuum processing 24

Working with the European leader 25

Starting with the end: Failure analysis 26

Process solutions for power devices 28

Powering up at IXYS 30

State of the art through partnership 30

Dear Readers,

Welcome to our first edition of Chip,

the BPS industry sourcebook for the

semiconductor market. Published in time

for the SEMICON West show in

California, Chip is published annually and

highlights some of the newest technologies

and production trends that drive our

business.

As the market leader in flip chip

packaging as well as the provider of

innovative and cost-efficient production

solutions for III-V, etching and

metallization applications, Chip gives you

an informative and colorful overview of

our product and service offer – and

potential solutions to your manufacturing

needs.

In this issue we start out with a look at

the current ups and downs of our market.

We also present the BPS global team

located near your production site, no

matter where you are. Our technical

reports cover flip chip, acoustic wave,

III-V and IC production technology. Each

section also features reports from

well-known manufacturers on the

advantages of BPS solutions. Chip closes

with a look at our R&D network of

partner research institutes from around

the world.

I sincerely hope you enjoy our new

industry sourcebook and look forward to

– similar to our BPS corporate claim –

making IT possible together with you!

Dr. Martin Bader

Vice President Semiconductor Division

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Semiconductor Industry Sourcebook

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Staying Connected with Semiconductors

by Dr. Martin Bader,Vice PresidentSemiconductorsDivision

The volatile semiconductor business cycle has us onceagain hoping for better times. Battered by the Asianfinancial crisis and worldwide production over-capacity, theresulting fall in demand, margins and reduced consumerprices will keep the market sluggish in 1998.

1.20

1.15

1.10

1.05

1.00

0.95

0.90

0.85

0.80

0.75

0.70

0.65

0.60

0.55

0.50

Mar

96

Ap

r 96

May

96

Jun

96

Jul 9

6

Aug

96

Sep

96

Oct

96

Nov

96

Dec

96

Jan

97

Feb

97

Mar

97

Ap

r 97

May

97

Jun

97

Jul 9

7

Aug

97

Sep

97

Okt

97

Nov

97

Dez

97

Jan

98

Feb

98

Mar

98

Ap

r 98

May

98

Jun

98

SEMI B-t-B: Bookings total for April ‘98 is down almost 35 percent from November ‘97VLSI Research Inc.: W.W. equipment bookings for May ‘98 are forecasted to be down over 65 percent since October ‘97

Actual Situation: Book-to-Bill Ratios

SEMI Equipment Book-to-Bill Ratio (N.A. Manufacturers only)

VLSI W.W. Equipment Book-to- Ship Ratio

Forecast

350

300

250

200

150

100

50

0

1975

4

1976

6

1977

7

1978

9

1979

11

1980

14

1981

15

1982

16

1983

22

1984

31

1985

27

1986

34

1987

42

1988

55

1989

59

1990

59

1991

65

1992

71

1993

88

1994

111

1995

151

1996

142

1997

150

1998

159

1999

188

2000

2001

2002

288

$ in

Bill

ions

Source: Dataquest, April 28, 1998

Merchant Semiconductor Market Forecast

Feast or Famine in Global Chip Business

29%

24%27%

5%3%

26%

46%

-17%

24% 24%

39%

7%

2%

8%10%

29%32%

42%

-9%

5%

-2%

17%

Average chip industry growth rate is 17%.

Annual sales never get close to average industry growth rate

Source: IC Insights, WSTS Semiconductor Business News, April 1998

78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 98F

Feast or Famine in Global Chip Business

Merchant Semiconductor Market Forecast

Actual Situation: Book-to-Bill Ratios

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CHINA & HONG KONGJodie SoRegional AdministrativeSupport [email protected]

Mike WangChina and Hong KongRegional Manager for sales and [email protected]

Dr. William ZhuProject Manager (Shanghai)[email protected]

JAPANToshihide HarukiSales Section, Semiconductorand Magnetic Storage [email protected]

Shinsuke KitagawaSemiconductor and MagneticStorage Division [email protected]

TAIWANDr. Hong-Ji ChenCustomer Support [email protected]

Steve KuanAccount Manager for FA,III-V and [email protected]

Dr. Chung-ping LaiNational Sales [email protected]

Christy LiuAdministrative Sales [email protected]

Dr. Gordon ShyuDeputy Sales Manager forsemiconductor [email protected]

KOREAI. C. CheonExecutive Director forsales and [email protected]

Kang-Hoon LeeCustomer Support Engineer forsemiconconductor [email protected]

Onno LootsmaCustomer Support [email protected]

Jason ParkSales Engineer forsemiconductor [email protected]

Terri YuAdministrative Assistant forSales and Customer Support(spare parts)[email protected]

SINGAPOREDr. Wei GuanSales Support Engineer [email protected]

Han Chih HengSales Engineer forsemiconductor products and [email protected]

Julianah KamariSales and Customer [email protected]

Benjamin LohRegional ManagerSales and [email protected]

Remus SimCustomer Support [email protected]

BPS around the semi conductor globe

BPS around the semiconductor globe

Our experienced teams of R&D, sales and

systems support specialists are there where

you need us – close to your production site –

around the world.

EUROPEThierry AbahriIII-V Systems [email protected]

Hans van AgtmaalGeneral Manager [email protected]

Tom BeensNorthern Europe Area SalesManager [email protected]

René BuehlerSouthern EuropeMarketing & Sales Manager [email protected]

Ralf EichertCustomer Support Managerfor Central [email protected]

Günther EllerCentral EuropeSales Manager [email protected]

Sacha HiemstraManagement Assistant forEuropean [email protected]

Alan JaunzensUnited KingdomSales [email protected]

Huub de KleinManager BPS Northresponsible for [email protected]

Gotthard KudlekSales Manager forsemiconductors in [email protected]

Klaus PetersenSales Manager for systemsand coating materials inCentral [email protected]

Fiorenzo SlavieroArea Sales Manager for [email protected]

Bernard StämpfliDirector Marketing and SalesBPS NEXTRAL and FailureAnalysis Systems [email protected]

Jean-Claude Le VelyArea Sales Manager [email protected]

NORTHAMERICAAlicia BianchiStrategic Marketing Managerfor North [email protected]

Gerry BogleOperations and AssemblyManager for [email protected]

Dr. Russ BuckleyPresident of BPS, [email protected]

Tom ChaputLead Engineer forsemiconductor [email protected]

Henry GabathulerNorth American SalesManager for semiconductorand display [email protected]

Michael HelmesSales Engineer forsemiconductor systems,West [email protected]

Hermann ObermoserSouth Western CustomerSupport Manager for electronic [email protected]

Anthony Pino Customer Support Engineerfor semiconductor [email protected]

Ralph TramposchSales Engineer forsemiconductor systems,East [email protected]

Bruno WalserCustomer Support Manager [email protected]

Mark WohlwendLead Engineer forsemiconductor applications [email protected]

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Even though flip chip was seen as the

next generation interconnect method since

the beginning, its total market share for

devices barely reached 1%. Because the

industry has shown little ambition to

establish a flip chip standard, many

manufacturers implemented their own

adaptations of the technology. Today there

are numerous versions of flip chip in use.

Most of these are similar to the controlled

collapsed chip connection (C4) type

originally developed by IBM and

considered the most prevalent

implementation in use today.

Enabling the latest chip technology

Two main types of packaging are used

today for circuit board assembly; the

traditional package and the direct chip

attach of the die to the board. Both

methods have advantages, depending on

their field of use, while the traditional

package is used for the majority of

applications. In the future, the chip scale

package will predominate in the custom

board assembly field while direct chip

attach will be strong in the field of

cost-driven high volume commodity

products. Chip scale packages are

often built by using a flip chip inside,

while in the direct chip attach technique,

the flip chip is placed directly on the

board.

The increased demands of current

device technology has made the

advantages of flip chip technology

apparent. Accelerating clock speeds,

increasing numbers of I/O’s, die shrink

due to sub 0.25 micron technology and

higher integration and miniaturization of

electronic devices all play to the strengths

of flip chip. Acceptance of flip chip has

reached a high point because it provides

the smallest possible component with the

shortest interconnects and the highest I/O

density per surface area, giving the

technology unmatched performance/speed

and miniaturization characteristics.

Especially in the PC market, the

technology has made big gains in the past

two years and soon most CPUs will be flip

chip bonded. Another important

emerging market are telecommunications

devices, computer peripherals and high

performance electronic consumer products

such as video camcorders, digital cameras,

and video game players.

Requirements for the flip chipbumping process

Along with testing, die separation,

re-testing and burn-in – contact

metallization and the formation of the

Pb/Sn solder bumps on the contact pads

are the final steps in wafer fabrication

before packaging. Reliability and

reproducibility in production are key

requirements for these processing steps.

The following parameters must be met for

production of highly reliable

interconnects:

Oxide free IC final metal pads (Al) to

provide low contact resistivity

Good adhesion to chip surface e.g. Al

pad and, more important, the chip

passivation to provide mechanical

robustness

Hermetic seals between chip

passivation and UBM to prevent

corrosion of the IC metals

Good diffusion barrier between solder

bump metals and IC final metal,

especially for eutectic solder

Sufficient wettability of the UBM to

allow stable solder reflow process steps

Low stress metal stack to provide long

term reliability (low amount of brittle

Cu/Sn or Ni/Sn alloys).

Growing market share

The tremendous advantages of flip

chip promise it a great future as the chip

interconnect method. Because of

performance demands and shrinking

dimensions for ICs unimaginable only a

few years ago, the latest market analyses

AMD, the well-known microprocessor

developer and manufacturer, has just given

its “World Class Supplier Extraordinary

Performance” award to BPS. The award

was presented to BPS, Inc. at the

company headquarters in Hudson, NH by

Clayton Stice, Operations Facilitator at

the AMD’s C4 facility in Austin, Texas.

Stice described the award as “recognition

of BPS’ outstanding applications and

service support to AMD for the K6 chip

production for Q4 1997.”

This award is a distinctive

accomplishment for the semiconductor

team at BPS, Inc. In addition to the state-

of-the-art K6 wafer fab, AMD also added

an extensive operation for the deposition

of C4 bumps on the microprocessor. The

incorporation of the C4 production

progressed very quickly from planning to

implementation during 1997. The

support provided by the BPS product and

service teams was crucial for the success of

the C4 operation.

Expansion of AMD’s production

facilities will continue through this year.

Currently, BPS will install additional

evaporation systems at AMD throughout

1998.

gains market shareby Hans Auer, Batch Systems Manager

C4 technologyawards “World

Class Supplier

Extraordinary

Performance”

award to BPS

By Alicia Bianchi,Strategic MarketingManager, BPS, Inc.

predict 30-50% annual growth rates for

flip chip bonded devices. Within the next

five years, flip chip has the opportunity to

grow to 5% of the total device market, a

huge increase over the past three decades.

Flip chip technology was first

developed over 30 years ago –

at a time when the

semiconductor industry was

very different from today.

Until recently, it was used only

for high performance

microprocessors and

sophisticated military devices.

Because of the obvious

reliability and compact

dimensions of flip chip

interconnects, uses in other

industries such as automobiles

and wrist watches are rising

steadily.

Clayton Stice of AMD presents the award to Gerry Bogle of BPS.

On the fast track with

Setting up aProductionStandard with MotorolaBPS helps integrate C4production for thePower PC chip

By Henry Gabathuler, Sales Manager, BPS Inc.

One of the best-known names in the

semiconductor business, Motorola has

worked together with BPS for over

20 years, optimizing evaporation

and metallization processes.

Because of the rising popularity of

C4 flip chip mounting technology,

BPS was able to provide crucial

production equipment, tool know-

how and support to ramp-up use of C4

packaging technology at their new final

manufacturing line BAT-1 in Austin, Texas (USA).

This project began in the early 1990s in preparation for the

Power PC microprocessor and is now a production standard at

Motorola.

Originally developed for high-speed mainframe computers

back in the 1960s by IBM, C4 is now licensed widely.

Motorola took advantage of the substantial amount of reliable

production data on this process, giving a precise idea about

production output and costs to those setting up the new C4

lines for evaporation of 8'' wafers and probably 12'' wafers in

the future.

John Franka, manager of the Bump Engineering and

Services group in Austin, Texas, emphasizes that the decision to

go with C4 was not only a question of reducing production

costs: “It’s a rugged technology and the compact layout allows

you to take advantage of the higher frequencies of today’s ICs.”

F L I P C H I P T E C H N O L O G Y

John Franka and Wilhelm Sterlin in front of theBAT-1 facility in Austin, Texas.

BCA Bare Chip Attach

BGA Ball Grid Array

BLM Ball Limiting Metal

BTAP Bump Tape Automated Bonding

C4 Controlled Collapse ChipConnection

C5 Controlled Collapse ChipConnection on Ceramic

CBGA Ceramic Ball Grid Array

COB Chip on Board

COG Chip On Glass

CQFP Ceramic Quad Flat Package

CSP Chip Scale Package

DBGA Dimpled Ball Grid Array

DCA Direct Chip Attach

DIL Dual Inline

DIP Dual Inline Package

EPBGA Enhanced Plastic Ball Grid Array

FC Flip Chip

FCBGA Flip Chip Ball Grid Array

FCIP Flip Chip In Package

FCM Few Chip Modules

FCT Flip Chip Technology

HDI MCM High Density InterconnectionMulti Chip Module

KGD Known Good Die

LGA Land Grid Array

MCM Multi Chip Module

MLC Multi Layer Ceramic

PBGA Plastic Ball Grid Array

PCB Printed Circuit Board

PGA Pin Grid Array

PLM Pad Limiting Metal

PQFP Plastic Quad Flat Package

PWB Printed Wire Board

QFP Quad Flat Package

SCP Single Chip Packaging

SMD Surface Mount Device

SMT Surface Mount Technology

SOP Small Outline Package

TAB Tape Automated Bonding

TBGA Tape Ball Grid Array

TCB Thermo Compression Bonding

TSM Top Side Metallurgy

UBM Underbump Metallization

WLP Wafer Level Packaging

One of the most confusing things about flip chip

packaging is the wide array of acronyms. Even the basic

terms are sometimes mixed up:

Flip chip – is only the method of interconnection.

The chip is flipped to bond the active side of the chip

to the next interconnect level.

Direct chip attach – is the direct attachment of the

chip to a circuit; either a printed circuit board (PCB)

or a flex circuit. DCA bypasses the first level

interconnect, attaching a chip to a package.

Flip chip on board (FCOB) – direct chip

attached to a PCB. Flip chip is often understood

to mean FCOB.

Flip chip in package (FCIP) – refers to the use of

flip chip attachment into a package. FCIP is used in

single chip packages and multichip modules (MCMs).

The alphabetical list below are the flip chip terms we use.

A BPS Guide to Flip Chip

Abbreviations

PA

CK

AG

ING

DIC

TIO

NA

RY

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While IBM used C4 mainly for

mainframe computer components, it has

now become useful for state-of-the-art

microprocessors used in PCs, due to

higher clock speeds, more efficient

thermal management and continuously

shrinking die sizes. The computer maker

still operates production lines installed in

the early 80s, keeping them up to date

with retrofits of the newest control

systems. Motorola has established C4 for

its Power PC chip and AMD recently

implemented C4 to bump their new K6

chip (see also our reports on Motorola and

AMD on pages 6 and 7). In addition to

microprocessors, telecommunications and

other micro-electronic devices are also

bumped with C4 technology.

Globally installed production capacity

for C4 will be able to process

approximately 10,000 eight inch wafers

per week – amounting to 500,000 wafers

per year or about 70 million

microprocessors (yield assumption ~70%)

by the end of 1998. Over 90% of this

production is done on BPS systems.

Cost-saving potential

Today, C4 bumping typically costs

US$130-$150 per 8'' wafer, a very

economic solution for high-end (and

higher cost) devices since it guarantees

excellent yield and reliability. In the case

of microprocessors, a yield loss of 1% can

represent the total flip chip bumping cost.

The technology still shows great cost saving

potential if taken to a more automated

level, especially important since its use is

being extended into bumping of lower

cost devices such as telecommunications

ICs and other components.

The technology of C4

Production reliability and

reproducibility are key requirements for

the wafer bumping process. The formation

of highly reliable contacts and solder

bumps is done by a dedicated evaporation

method that meets specific requirements.

Native oxide removal is done through an

RF sputter etch cycle followed by a heat

step prior to deposition. This ensures high

conductance and good adhesion. Good

wettability as well as a reliable diffusion

barrier between bump and IC metals is

provided by the Cr-Cu-Au multilayer.

The use of a lift off technology in the

C4 process requires a nearly perpendicular

angle of incidence. This is one of the

reasons why evaporation is used instead of

sputtering. To cost effectively deposit

Pb/Sn solder metals up to 120 microns

(solder balls) is an unusual thin film

process specification. The high rates and

quantities of material needed to meet such

a specification require specialized

evaporation sources.

Usually, masking has been done with a

metal mask. Alternative methods include

the use of resist masks as well as sputtering

the underbump metallurgy either masked

or as a blanket metal film layer. While

IBM has abandoned the use of their

“Riston” laminate resist mask technology,

other manufacturers have successfully

evolved the use of resist masks and,

combined with the newest available

mixtures, brought the technology to

“production worthy” levels.

The main advantages of PVD

technology over electroplating and screen-

printing of the solder materials are:

Excellent control of material thickness

and solder mixture

Good thickness and solder

composition uniformity across wafer

Lift off technique limits mask

stripping to residue removal

No wet etching of plating base

necessary (only for electroplating)

Very small pitch and bump size

possible (with resist mask)

No expensive control measures for

hazardous chemicals needed (only for

electroplating)

Much better bump yield than screen

printing

The threat of a high loss with big

batch sizes can be minimized by designing

fail-safe equipment with a back-up of

virtually every system component (pumps,

sources, sensors, etc.). Reduction of long

cycle times is also possible with the newest

substrate cooling techniques. Even single

wafer concepts are considered by utilizing

the latest achievements in PVD source

technology.

The C4 solutionfrom BPS

The BAK series can be configured for

depositing Cr-Cr:Cu-Cu-Au or Pb/Sn

solder metals. The preceding RF sputter

etch step is done by the dedicated ORF

901 system. Different system sizes are

available to meet various individual

throughput requirements and all offer

high process flexibility. The source-to-

substrate distance can be varied based on

wafer size to maximize material utilization

and the special source technology

accommodates large amounts of materials

required for the Pb/Sn process with the

ability to change alloy mixtures. Specially

developed sources for the underbump

metallurgy Cr-Cr:Cu-Cu-Au provide an

‘overlap step’ between Cr and Cu for

better adhesion and an effective diffusion

barrier. The sources are inductively heated,

therefore, no electrical damage can happen

to sensitive devices compared to e-beam

deposition. The user friendly control

system allows easy operation, helps

monitor process data and has built-in

failure diagnostics.

Flip Chip made by

by Hans Auer, Batch SystemsManager

Famous for its

legendary

reliability (with no

failures due to

wear observed),

C4 is the most

standardized and

commonly used

technology among

the different flip

chip bonding

methods for

high-end devices.

Typical RF etch process sequence

Pump down to 5 E-6 mbar 10 min

Argon inlet to 2 E-3 mbar 1 min

Etch (300 Angstrom at 1.0 kW) 10 min

Venting cycle 6 min

Unload/load of substrates 5 min

Total cycle time approx. 32 min

Throughput for ORF 901:

Capacity 8'' masked wafers 6

Throughput approx. 12 wafers/hour

Typical Cr-Cu-Au deposition process

sequence (UBM)


Substrates heat (200=B0C) 15 min

Cr deposition (1000 A) 3.5 min

Cr/Cu overlap (1200 A) 4 min

Cu deposition (8000 A) 9 min

Au deposition (600 A) 2 min

N2 cool down and vent 30 min

Unload/load 10 min

Total cycle time approx. 95 min

BAK 1131 capacity: 18 eight inch

masked wafers


Typical Pb/Sn deposition process sequence


Pb source preheat 6 min

Pb evaporation (112 µm) 120 min

Preheat Sn 6 min

Sn evaporation 20 min

Cool down/vent 20 min

Unload/load 10 min

Total Cycle time approx. 202 min

Throughput:

BAK 1131 capacity: 18 eight inch

masked wafers


Motorola’s Power PC 620™ microprocessor. Photo courtesy of Motorola Inc.

Source chamber for UBM with two sources forsimultaneous deposition of Cr and Cu with continuouslyvariable evaporation rates.

ORF 900 – closing door of system

Loading the BAK 760

Technology

B

C

D

EF

H

KLM

P

QS

T

UW

Process sequencereliability

The following

processes have been

realized in production scale:

Cr-Cr:Cu-Cu-Au (original C4

concept)

Ti:W(N)-Cu-Au

Ti:W(N)-NiV-Au

Cr-NiV-Au

Cr-Cu-Cr-NiV-Au

Cr-Cu.

The typical process sequence is:

1. Degassing

2. RF sputter clean etch

3. Sputter process with co-sputtering

(including heating) according to the layer

sequence.

Typical process conditions in a batch

sputter system are shown in the chart.

The phasing is realized by passing the

wafers alternatively in front of the Cr and

the Cu target (rotating the drum-type

substrate carrier).

Cu

phasing zone

de

po

siti

on

ra

te

AuCr

time

Sputtering sequences for the phasing from Cr to Cu

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11

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10

The metal layer introduced between

the Al pad and the solder is a key factor

determining the reliability of the solder

bump structure. Under bump

metallization (UBM), also known as Ball

Limiting Metal (BLM), consists of a series

of metal layers. In the original C4 concept

evaporated layers of Cr-Cr:Cu-Cu-Au

were used. Beside this NiCr-Cu-Ni-Au,

Ti-Cu-Ni and Ti:W-Cu-Au are in use.

PVD evaporation and sputteringfor UBM

Depending on the application, BPS

offers the following systems for UBM

production:

1. Batch evaporation systems (BAK, BAV

and SCS series)

2. Batch sputtering systems (LLS series)

3. Cluster tool for single wafer sputtering

(CLUSTERLINE™ 200)

Our batch systems are designed with

drum-type substrate carriers for vertical

wafer loading of various size and shape.

Load-lock and deposition chambers are

vacuum isolated. To avoid contamination,

substrate pre-treatment (wafer degassing

and etch cleaning) is performed in the

lock chamber. In the process chamber up

to five planar magnetrons can be installed.

To avoid cross-contamination during co-

sputtering, parallel sputtering magnetrons

should be placed in an opposite position.

Advantages of batch sputtering

The specific advantages of the batch

sputter systems are:

The flexibility to use different

substrate sizes and geometries (even in

one batch)

The unique process flexibility as

different layer and material sequences

A “nearly unlimited” choice of layer

sequences

Co-sputtering with many options

Material phasing with different

possibilities

The larger (LLS 802) system has a

higher throughput for substrate sizes up to

200mm, whereas the smaller (LLS EVO)

system comes equipped with a cassette-to-

cassette handling module. Both systems

have been proven extremely reliable in

continuous shift production operations.

Co-sputtering of Cr and Cu is a specific

advantage of the LLS sytems. Power

variation on each of the two cathodes

allows the stoichiometry of the Cr:Cu

alloy to be changed.

Under BumpMetallization

(UBM) for

Most of the processes, used with

evaporation are the classical C4 process as

described in the chart or derivatives of it.

Among these processes are Cr-Cu-Au; Cr-

Cu; Ti-Cu or Ti-Cu-Ni. Since a big

advantage of evaporation is the ability for

lift-off processes (directional coating),

most of the evaporators use this process.

Some customers also use metal masks in

combination with lift off.


1. Preheat

2. RF sputter clean etch

3. Evaporation process (including

heating) according to the layer sequence.

Industry standard in evaporation

The choice of a thin film coating

system depends on specific customer

needs such as: process flexibility, substrate

flexibility, throughput, wafer size,

redundancy, etc.

BPS offers a wide range of system

sizes. Known as the BAK evaporation

systems, they are in use around the

world in hundreds of UBM production

lines today. The following BPS system

names refer to the size of the process

chamber in millimeters, i.e. a BAK 640

chamber is 640mm across.

BAK 640

BAK 760

BAV 1250

BAK 1131

SCS 800 series

SCS 1100 series

Specific advantages ofevaporation

An evaporation system used for

UBM provides the following

advantages:

Cr:Cu phasing can be realized in a

continuous gradation/degradation

of both materials.

The flexibility in substrate sizes

allows the change of wafer sizes in

minutes.

Due to the directional coating, lift

off processes are possible.

The nature of evaporation sources

allows highest flexibility in the

processes.

Material changes and the sequence

of materials can be affected within

minutes.

by Albert Koller, Evaporation Systems Manager Andy Hügli, LLS Systems Manager

wettable metallization (e

plating base (Cu

adhesion layer & diffubarrier (Ti:W

passivation (Si02, Si3N4,

VO-pad (AI)

chip (Si)

Pb40Sn60 Pb95Sn5

Coating systems for UBMby evaporation

Coating systems for UBMby batch sputtering

Typical evaporation system (BAK 1131)

process sequence

1. Preheat 250°-300°C

2. RF etching 15nm, at 0.025nm/sec.

3. Evaporation of Cr 100nm, at 0.5nm/sec.

4. Evaporation of Cr:Cu 200nm, at 0.5nm/sec.

5. Evaporation of Cu 800nm, at 1.0nm/sec.

6. Evaporation of Au 50nm, at 0.5nm/sec.

Typical process conditions (LLS)

1. Wafer degassing 150-200° C

2. Sputter etch 5-10 nm, removal of oxides

3. Sputter Cr 100 nm, 30 nm/min at 4kW

4. Sputter Cr:Cu 80 nm co-sputtering

multi-layering of Cr:Cu

( Inter-diffusion)

e.g. Cr – 7nm/min at 1kW

Cu – 12nm/min at 1kW

fast rotation of substrate

carrier drum max.

rotational speed

= 30 rpm

5. Sputter Cu 400nm, at 72nm/min at

6kW.

6. Sputter Au 50nm, at 20nm/min at 2kW

Typical tool configuration for UBM (LLS).

Evaporation Systems - Phasing from Cr to Cu (use of two electron beam guns simultaneously)

Cu

phasing zone

de

po

siti

on

ra

te

AuCr

time

SHUTTER

HEATER WITH SHUTTER

SPUTTER SOURCE

MEISSNER TRAP

Cu

Au

Cr

Evaporation Systems – Phasing from Cr to Cu(use of two electron beam guns simultaneously)

UBM structure with PbSn solder bump structure.

Flip Chip

Typical process configuration in an in-line system, including the application of the roof cathode.

Cost ofownershipfor differentsystems anddifferentwafer sizesfor the Cr-Cu: Cu-Cu-Auprocess.

Sputtering sequence for the phasing from Cr to Cu. The phasing is realized with a proprietary Balzers target.

CLUSTERLINE™ 200 system configuration for UBM.

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12

The use of larger wafer sizes results in

an increasing demand for cluster tools for

UBM. With a long tradition in this field,

BPS developed the CLUSTERLINE™

200 for this important market segment.

Extensive process experience and

application works for different customers

lead to a system, ready for high volume

production with high reliability. The

positive feedback from many clients has

led to development of a 300mm cluster

tool configuration.

High throughput cluster tool

The CLUSTERLINE™ 200 is a

metallization tool that meets current and

future requirements for the advanced

wafer fab. This tool features excellent

automated factory integration, a modular

design for flexibility of process

configuration, low contamination and

superior process control thanks to the

ControlWORKS™ control system.

The greatest advantage of the

CLUSTERLINE™ is high throughput

independent of wafer size. For large

200mm and 300mm wafers, the

CLUSTERLINE™ provides a remarkably

low cost of ownership. For example,

running a typical Cr-Cr:Cu-Cu-Au

process, a throughput of more than 40

wafers/hour can be reached using a

proprietary Balzers target.

UBM process possibilities

The CLUSTERLINE™ 200 is

optimized for all current UBM processes:

Cr-Cr:Cu-Cu-Au (original C4

concept)

Ti:W(N)-Cu-Au

Ti:W(N)-NiV-Au

Ni:Cr-Cu-Ni-Au

Cr-NiV-Au

Cr-Cu-Cr-NiV-Au

Cr-Cu-Au

by Wolfgang Rietzler, Cluster Systems Product Manager, Martin Märk, Product Specialist

& Andreas Dill, Cluster Systems Group Manager

BAK 760

BAK 760

BAK 760

BAK 1131 (high volume)

BAK 1131 (high volume) LLS EVO CLUSTERLINE™ 200

In-line Systems NEXTRAL 100 RL

BAK 1131 (high volume)

ORF 901

LLS EVO In-line Systems

LLS EVO

CLUSTERLINE™ 200

CLUSTERLINE™ 200

BA

K 7

60

Proc

esse

s

Processes

UBM– Sputter Clean

– Sputter deposition

UBM– Sputter Clean

– Evaporation

PbSn Solder Bumps

Rerouting

Carrier preparation

BA

K 1

131

(hig

h vo

lum

e)

OR

F 90

1

LLS

EVO

CLUS

TERL

INE™

200

In-l

ine

Syst

ems

NEX

TRA

L10

0 R

L

ChipsPackagingmatrix

Coating systems for UBMby Cluster Tools

Typical Cr-Cr:Cu-Au UBM process conditions

(CLUSTERLINE™ 200)

1. Wafer degassing 200-300° C

2. ICP soft clean etch 5-10 nm, removal of oxides

3. Sputter Cr 100 nm, 7 nm/sec at 5 kW,

single wafer static

sputtering

4. Sputter Cr:Cu 80 nm; 15 nm/sec at 3.5 kW,

proprietary Balzers target

5. Sputter Cu 400 nm; 30 nm/sec at 10 kW

6. Sputter Au 50 nm; 6nm/sec at 2kW

Cr-sputter Module

ICP-soft etch Module

Degas Module

Cassette Station A

InLigner

Cr:Cu sputter Module

Cassette Station B

InCooler

Marathon MX 800

Proprietary target

Optional module for soft phasing, or add. module for thick Cu layers

Cu-sputter Module

optional PVD

ModuleBuffer

Module

phasing zone

de

po

siti

on

ra

te

Cr

time

Cr:Cu

Cu

Au

CuAuCr Cr:Cu

CrRf etch

Pallet, supporting wafers

sput

ter

rate

Degas

200-300°C

RF-etch

5-10 nm

Sputter 100 nm.

7 nm/sec. at 5 kw

Co-sputtering, variable Cr:Cu

ratio – depending on power settings

Sputter 400 nm,

30 nm/sec. at 10 kW

Sputter 50 nm,

4 nm/sec. at 1.4 kW

Degas Cu

Cr Cu

Au

BAK 1131 LLS EVO LLS 802 CLUSTERLINE

100mm wafer

150mm wafer

200mm wafer

Rel

ativ

e co

st p

er w

afer

Cost of Ownership considerations

The comparison of cost of ownership

models for various process system types is

important for:

Product benchmarking

Technology evaluation

Process optimization

Impact of materials

Competitive analysis

Sales/purchase parameters

Simplified models as a quantitative

management technique are used to analyze

purchasing decisions, standard cost

analysis and equipment prioritization.

They are not suitable for absolute cost

calculation but can be used to compare

different system set-ups and allow valid

comparisons. An example of a simplified

cost of ownership comparison for UBM

processing on different thin film systems is

shown here.

On batch systems (evaporation and

sputtering), the costs per wafer increase

considerably with the wafer size,

depending on batch capacity. With cluster

tools, the cost per wafer remains more or

less independent of wafer size.

Our cluster tool displays the lowest


1. Degassing

2. RF soft sputter etch

3. Sputter process according to the layer

sequence.

Up to four PVD modules can be used

with this process sequence. Depending on

the process needs, an RTP module may be

added to the integration platform.

CLUSTERLINE™ 200 advantages

The high throughput of more than

40 wafers per hour for the UBM process

is independent of wafer size, one of the

advantages of the new cluster tool from

BPS.

In-line systems

BPS In-line systems are designed for

high throughput and feature advantages

such as flexibility in the use of different

substrate sizes and geometries. Substrates

of different shapes and sizes can be loaded

on the same pallet carrier.

With the leading BPS in-line system,

the intermediate Cr:Cu interfacing is

deposited by a roof cathode arrangement

with two planar magnetrons angled

towards each other. The Cr:Cu layer is

deposited with a true phase from 100%

chromium to 100% copper. In addition,

the roof cathode can be used for different

processes, materials and sputtering

configurations. It is also suitable for use

on a cluster tool.

possible cost per wafer for 200mm wafers. For

150mm wafers, the decision between a batch

sputter system and a cluster tool depends primarily

on the required production volume.

SAW element made up of a piezoelectrical substrate with rows of alternating pairs of electrodes at both ends.

Catching

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14

Because of their small size, electrical

performance and extreme sensitivity,

surface acoustic wave components (SAW)

are today’s enabling technology for

countless electronic products. All remote

control units or wireless data

communications components need filters,

resonators and oscillators for signal

matching. Recent improvements in the

thin film coating process have greatly

simplified the production of SAW

components. It is now possible to run

mass-production fabs at a price that

permits the use of SAW technology in

everyday consumer products.

How SAW components work

How surface acoustic waves function

has been known for many decades. What

actually happens with a SAW can be

observed on a small wafer of quartz,

lithium niobat or lithium tantalat,

coated with rows of alternating pairs of

electrodes at both ends. When an

alternating current – the standard

frequency range goes from a few MHz up

to a few GHz – is applied to the

electrodes, a surface deformation of the

substrate between two electrode pairs can

be observed as mechanical waves. These

waves remain on the surface, i.e. the

function of the substrate is not

compromised if attached to a carrier

element. These waves run along the device

and transform into an electrical current

when they reach the electrode pair at the

other end. Depending on the component

design, a wafer can be a propagation delay

element, filter or resonator, just to name a

few.

The velocity of surface acoustic waves

is generally 3000m/second, depending on

the substrate material. At this speed it is

possible to design propagation delay

elements with very long delays within a

very small area. On the other hand, a

frequency of 100MHz gives a resolution

of 10-8. The extreme sensitivity of these

elements to external influences makes

production of highly accurate sensors

attractive and very competitive in terms of

function, reliability and price compared to

state-of-the-art sensors. SAW components

are used as measuring devices for

temperature, mechanical deformation and

elongation, changes in dielectric constants

or for conductivity of liquids. Devices can

be built with antennae mounted on the

electrode pairs at one end of a SAW device

– enabling a bi-directional contactless

signal transmission without any external

connections (i.e. power or sensor lines) to

a carrier. There are no mechanical moving

parts in SAW components, making them

very reliable, even when a combination of

SAW chips are combined to form complex

sensors.

Market demand skyrockets

Half a year ago everyone spoke of

doubling the market size in only five

years. Today’s expectations are even higher.

The cellular phone boom first made SAW

feasible for mass-production

environments. New products such as

automobile navigation systems, the

increased use of sensors in household

appliances, identification systems for

persons and autos and chemical sensors

used in laboratory research will all

contribute to a continually growing

demand for SAW components.

Evaporation is better

Because of the inferior uniformity and

resulting yield previously achieved with

sputter systems, evaporation has turned

out to be the better solution for

production of SAW devices. Evaporation

the Surface Acoustic WaveHow an evaporation process beats sputtering

by Albert Koller, Evaporation Systems Manager

Surface acoustic waves? Everyone benefits from surface

acoustic wave technology, but hardly anyone has heard of

this thin film technology – found in cellular phones, TVs,

video recorders and automobiles, just to note a few

examples. We take a closer look at this technology and a

mass-production solution from BPS.

does not just show excellent uniformity

but combined with lift off it is possible to

produce very accurate and reproducible

flanks. This is extremely important,

because the volume of the Al finger

electrode, which results after the lifting

process, is proportional to the electrical

frequency of the final device. With this

technology, no trimming step by etching

is necessary, even in high volume

production. This is why thickness

uniformity, combined with lift off

technology, must be extremely precise and

consistent to assure a high yield – and

maintain low production costs.

BPS has optimized their well-known

BAK evaporation platforms to come up

with very small thin film uniformity

variances over multiple production

runs. The dedicated system is

called BAK SAW. This system has

integrated all our process

experience. The adjustable throw

distance and greater mechanical

accuracy of the handling

components in the BAK system also

contribute to efficient mass-production of

SAW wafers. In addition, the proven

evaporation source and in situ thickness

measurement technology at BPS contributes

to meeting stringent SAW process

parameters.

For more information on SAW

applications, please contact us at:

[email protected].

BAK SAW BAP 800

BAK SAW BAP 800

NEXTRAL 860

BAP 800 NEXTRAL 860

NEXTRAL 200B

AK

SA

W

Pro

cess

es

Process

SAW AI

Backside antireflection

SAW chipping

SAW trimming

SAW passivation

BA

P 8

00

NEX

TRA

L 20

0

NEX

TRA

L 86

0

ChipsSAWmatrix

Part of a finger structure of a SAW device.

BAK 760: Uniformity over 20 runs(5 wafers per run / 5 measurements per wafer

Standard Deviation over 20 runs

Steinmann Jürg

This image is a BAK 1131

Steinmann Jürg

The image is a BAK SAW

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16

BAW devices exploit longitudinal waves propagating in the

bulk of materials. This is in contrast to surface acoustic waves,

which may exist in a thin surface layer only. Usually, standing bulk

waves are utilized. Their frequencies are given by the shape,

dimensions and elastic properties of the body in which the wave

oscillates, very much analogous to the resonance in tuning forks,

guitar cords, etc. The simplest example is a plate made of a

piezoelectric material, sandwiched between two electrodes, as

sketched in Fig. 1.

An electric field applied to this plate gives rise to an increase or

decrease of the thickness (D) of the plate, depending on whether

the field is parallel or anti-parallel to the internal electric

polarization of the piezoelectric material. If an AC field is applied

whose frequency hits a thickness resonance mode of the plate, the

vibration amplitude is very much increased by the resonance. The

lowest resonance (frequency f0) in such a plate occurs when the

plate thickness D equals half of the wavelength (λ) of the bulk

wave. Knowing the sound velocity vs, the required thickness is

calculated as: D = λ = vs

2 2f0

At resonance, the mechanical-electrical interaction becomes

large, i.e., a substantial part of electrical energy is converted to

mechanical energy and reconverted to electrical energy. The

admittance (Y), which outside the resonance behaves like an

ordinary capacitor (Y = j.2πf .C), exhibits large anomalies at

resonance. In a given frequency interval near the resonance the

imaginary part of the admittance changes sign: the capacitor

behaves like a coil. This behavior allows construction of band pass

filters (only signals with frequencies around F0 may pass) with a

couple of such plate resonators.

The advantage of thin films

In the past, such filters were used for lower frequencies below

100MHz only. With typical sound velocities between 5000 to

10,000m/s, this corresponds to a plate thickness of roughly

0.1mm (or a multiple if overtones are utilized). This is indeed a

limit for precise polishing techniques. With the advent of thin

film materials this limitation does not hold anymore. The

thickness of thin films may be well controlled in the range of 0.1

to 5µm. Thin film BAW devices can thus operate at frequencies

above about 2GHz.

However, there is one problem with thin films: they have to be

grown on a substrate. An ultrasonic wave excited in a piezoelectric

thin film is not totally reflected at the film-substrate interface, but

instead propagates into the substrate, and only a small fraction of

the mechanical energy can be reconverted into electrical energy.

There are two means to prevent the acoustic emission into the

substrate. One consists of etching the substrate locally below the

film, either by bulk micro machining or by surface micro

machining (see Fig. 2). Such devices are usually called “Thin Film

Bulk Acoustic Resonators” (TFBARs). In this way one can build

bridge structures with quasi-freestanding resonators. The second

technique applies an acoustic reflector to send the acoustic power

back into the piezoelectric thin film (see fig. 3). This technique is

usually referred to as SMR (Solidly Mounted Resonator). The

reflector consists of a set of quarter wave layers of alternating high

and low acoustic impedance materials.

BAW – the next big thing

In the past years the potential of such devices has been

demonstrated. While there is a growing interest for thin film BAW

devices, they are not applied yet in current products. The rapid

increase of cellular phone users necessitates the introduction of

new bands at higher frequencies. The current SAW filter

technology applied for signal processing at the carrier frequency is

expected to be insufficient for frequencies above about 3 GHz.

TFBARs and SMRs are a possible solution to the problem. Besides

the frequency aspect they also offer other advantages:

1. BAW devices need much less space. Several thousand filters

can be produced on one 100mm wafer. With increasing

frequency, less space is needed.

2. Standard silicon or GaAs substrates can be used. No special

piezoelectric substrates of LiTaO3 or LiNbO3 are required.

3. There is the possibility to integrate transistors and filters on

the same chip.

The most suitable materials for thin film BAW devices are

aluminum nitride (AlN) and zinc oxide (ZnO). These are polar,

non-ferroelectric materials. Suitable sputter or evaporation

deposition processes obtain growth with preferred texture and

aligned polarization.

Bulk acoustic wave devicesIntroducing

by Dr. Paul Muralt, Swiss Federal

Institute ofTechnology (EPFL),

Lausanne,Switzerland

Bulk acoustic wave (BAW) devices are piezoelectric transducers

applied in signal filtering techniques at ultrasonic and higher

frequencies. They are based on the efficient energy conversion

between electrical and mechanical energy in piezoelectric

materials.

Substrate

cavity layersacrificial

V(t)

Substrate

Acoustic Reflector

V(t)

E(t)P∆D(t)

Fig. 1. Schematic drawing of the piezoelectric effect in a plate of polar material.

Pyro-electric array for infrared detection

Fig. 2: Schematic structure of a TFBAR type BAW device using surfacemicro machining.

Fig. 3: Schematic structure of a SMR type BAW with a set quarterwavelength layers between substrate and active layer.

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18

In particular, the skyrocketing

popularity of cellular communications and

fiber optic data transmission are driving

the demand for III-V semiconductors.

This overview of all critical production

steps for III-V compound manufacturing

– etching, CVD deposition, RTP,

evaporation and sputtering – takes a closer

look at the difficulties and solutions to

high-throughput production.

Etching for III-VWithin the III-V applications, GaN

opto applications are the fastest growing

segment. These are used mainly for high

density disk read/write products. In the

commercial telecommunication industry,

high bandwidth integrated circuits based

on GaAs, AlGaAs and InP materials that

require etching processes increasingly use

high density plasmas.

Based on our High Density Plasma

Etcher (HDP), the NEXTRAL 860L

features a new etching process to meet the

reliability and throughput demands. The

excellent etch uniformity across ∅ 200mm,

combined with the flexibility of our HDP

reactor meets the most stringent

parameters in GaN, InP, GaAs and

GaAlAs compound manufacturing.

Partnership with ITRI/OES to etch GaN

BPS-NEXTRAL has responded to the

particularly high demand for GaN

applications in Southeast Asia by teaming

up with OES/ITRI (see our ITRI report

on page 21) in Taiwan to demo GaN

etching on the NEXTRAL 860L at the

ITRI research site. This system also

features a non-corrosive process (no

chlorinated gases) that provides

anisotropic profiles and very clean etching.

New InP Process

InP applications on the NEXTRAL

860L were improved so that the

microwave coupling device now creates

uniform plasma using low UHF power

levels. Because high plasma density cracks

the SiCl4 molecules into Si and Cl atoms,

resulting in a process conflict between Si

deposition and InP etching, the lower

plasma density is particularly suitable

when etching InP with SiCl4.

This newly developed process gives a

perfectly anisotropic profile, very fast etch

rates (0.5 to 2µm/min) and extremely

smooth etched surfaces. Such results make

the NEXTRAL 860L ideal for production

of opto devices on InP.

Advantages of RIE

Despite the current fashion, High

Density Plasmas (HDP) will not fully

replace Reactive Ion Etching (RIE). When

highest precision etching is required

and/or when the excessive heat produced

by HDP becomes a production factor,

RIE retains significant advantages.

Our RIE system (NEXTRAL 860RL)

features an automatic vacuum load-lock

for up to ∅ 200mm substrates. It uses

CH4/H2 and chlorinated reactive gases for

etching of III-V and II-VI compounds

such as GaAs, GaAlAs, InP, InGaAsP, ZnS,

CdTe and HgCdTe.

Accurate control of the process

parameters, particularly cathode

temperature, allows optimization of

profiles, as demonstrated in the 3µm high

quantum dot shown in the photo.

Via-holes for GaAs

RIE also has advantages over HDP for

etching of deep via-holes (>100µm)

through the GaAs wafer. UMS, a joint

venture between Daimler Benz and

Thomson-CSF, acknowledged the

superiority of our approach for this

application with the following process and

system characteristics:

Wafer processing using a high level of

RF power to obtain such fast etch

rates

Excellent profile control (70° to 85°

slope)

Helium backside cooling of the

substrates evacuates the heat created

by the plasma, maintaining resist

integrity and the selectivity required in

the process

10µm resist mask is used while 100µm

of GaAs are etched into the wafer

CVD depositionOur CVD deposition production

solution is based on the Plasma Box™, an

industry standard PECVD reactor for

mass-production of TFTs used in the FPD

industry. Over 100 of these innovative

reactors from BPS are in use at customer

sites around the world.

This reactor type in the NEXTRAL

D200 uses a confined plasma placed in a

high vacuum vessel. This design ensures

uniform heat distribution in the reactor

for uniform heating of the substrates.

Extremely low levels of cross-contami-

nation are achieved because of the

differential pressure between the Plasma

Box™ and the vacuum vessel.

This configuration deposits films, on

large areas (300mm x 300mm) in a

production environment. The quality is

One STOPfor III-VSolutions for III-V compound manufacturing

by Pierre Parrens, President, BPS-NEXTRAL

Albert Koller, Evaporation Systems Manager

Alex Nef, Batch SputterSystems Product Manager

equivalent to the results obtained in UHV,

which is unsuitable for mass-production.

In addition, the plasma box concept

enables efficient in situ plasma cleaning of

the reactor at deposition temperature,

eliminating manual cleaning.

The Plasma Box™ is a symmetrical

RF reactor which, depending on process

conditions, can lead

to ion

bombardment on

the grounded

electrode (where the

wafer sits). When

adjusting RF power

and working

pressure, induced film stress levels can be

controlled from tensile to compressive.

These zero stress films can be produced

according to the parameters shown below.

Low stress films are deposited with no

reduction in terms of film quality

expressed as buffered HF etch rates for

oxide and nitride, and as film temperature

stability. Oxide and nitride sandwich

layers deposited at 280°C have

demonstrated their ability to withstand

temperature treatment at 600°C, enabling

epitaxial layer growth. Deposition is

monitored by in situ thickness and

deposition rate measurement with a laser

interferometer. The laser beam aims at the

substrates through the cathode and the

shower head. This innovative approach

avoids any disturbance of process gas

distribution and ensures the best

uniformity.

Rapid thermalannealing

Based on 18 years of experience in

RTP technologies, the BPS-NEXTRAL

processors meet the latest requirements of

thermal treatment in III-V compound and

silicon technologies.

One of the most exciting results is the

development of an RTP module for the

BPS cluster tool (see our detailed report on

page 23). BPS-NEXTRAL is also active in

the development and manufacture of

stand-alone systems like the ADDAX 60.

The ADDAX 60 features accurate

temperature calibration (±2°C), excellent

temperature uniformity (±0.5%), unrivaled

stability (±1°C) for more than 1h and high

level repeatability (±2°C), and a wide

temperature range (300 to 1200°C). These

outstanding performance characteristics are

based on the innovative NEXTRAL

numerical PID controller. The system

allows fast processing for applications such

as post implant annealing and ohmic

contact alloying when manufacturing III-V

compound devices.

The excellence of the above

specifications is demonstrated by the

comparison graph between measure and

set point, with no overshoot, and by the

outstanding process specifications (See

below).

Currently, the III-V compound semiconductor industry is experiencing a phenomenal

44% annual growth rate – by far the fastest growing area of the industry. This

trend is expected to continue for at least the next five years.

Material Process System Etch rate Uniformity on(nm/min) ø4” wafer

InP HDP NEXTRAL 860L 1000 ±3%GaN HDP NEXTRAL 860L 100 ±3%GaAs RIE NEXTRAL 860RL 150 ±5%GaAl45As RIE NEXTRAL 860RL 200 ±5%GaAs Via-hole RIE NEXTRAL 860RL 2000 ±5%

2µm of GaN etched at the ITRI research site.

2µm high quantum dot.

An example of excellent profile control.

Material Deposition Uniformity Uniformity Etch rate Stressrate across a wafer to in BOE 725 (Dyne/cm2)

wafer wafer (nm/min)

Si3N4 100 ±3% ±3% <20 <1 x 108

SiO2 200 ±3% ±3% <250 <5 x 108

Evaporation for III-VWhat makes the difference between a

standard metallizing process and a process

for III-V? In fact, it is not the process

itself but the complexity of the production

conditions in III-V, compared to Si

applications. Examples of this added

complexity are: small substrate sizes,

expensive substrates, often small volumes

per substrate size and process, thick Au

layers and the large numbers of processes

possible in III-V.

Box coater an III-V industry favorite

With a field-proven system concept

and comprehensive array of process

options, the BAK evaporation systems

offer an unparalleled degree of flexibility

to meet virtually any III-V process

requirement. For example, with its

segmented dome calotte it is possible to

process different substrate geometries in

one batch. And if this variation is needed

only from batch to batch, no time is lost

with exchanging the calotte segments.

With an electron beam source (max.

two) and a multi pocket crucible, there is

no limitation to the number of different

materials, the material volume, sequential

or simultaneous evaporation, phasing etc.

The system is easily set up to accommodate

differing process requirements that also

reflect costs versus technical specifications.

By changing the throw distance either the

material utilization or the uniformity over

the dome can be optimized.

The modern control system allows

efficient management of all process

recipes. The resulting documentation of

each processed batch helps manage a

variety of processes and fulfill quality

control parameters.

The directional coating allows lift-off

processes without decreasing throughput

or increasing material consumption.

Processes on GaAs Sheet Contact Uniformityresistance resistance on wafer

Ohmic contact alloying 25Ω/square 0,4Ω ±2.5%Post implant anneal 200Ω/square NA ≤1%

5µm high laser structure etched anistropically in InP.

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20

Sputtering for III-VSputtering is an increasingly important

deposition technology used in III-V

manufacturing. BPS offers a field-proven

and remarkably flexible production

solution specifically for III-V applications.

More than 250 BPS batch sputtering

systems (LLS and BAS types) are in use

around the world.

III-V applications with LLS EVO

Continuing a tradition of innovative

batch sputter systems, the newest version,

the LLS EVO is adaptable to a wide range

of R&D applications and can easily be

upgraded to a fully automated cassette to

cassette production tool. Converting to

another substrate size can be done during

the regular unloading/loading phase.

Substrates of differing sizes can also be

simultaneously loaded on the drum for

processing.

The process flexibility of the LLS

EVO allows this system to carry out

almost every conceivable sputter

deposition recipe used for III-V today.

With up to 5 planar magnetron sputtering

sources it is possible to use DC sputtering,

RF sputtering, DC chopper, RF/DC

combined sputtering or co-sputtering

from 2 sources to create individual

mixtures of alloys or interphasing of

layers. The deposited film properties can

be modified by applying reactive gases,

and/or a DC or RF bias to the substrates.

A large number of ports enables the

addition of process equipment such as

Residual gas analyzers (RGA) or a Plasma

emission monitor (PEM).

Pumping configurations are matched

to the applications and typically use cryo

or turbomolecular high vacuum pumps.

The state of the art control system allows

easy production runs and records all

critical process parameters. The PLC

controls all system functions, the

Windows NT-based PC is a modern

graphical interface. Simple menus display

the system status and trending data and

manage all process recipes and alarms.

The LLS EVO delivers high

throughput and yield in conjunction with

good film uniformity and excellent

reproducibility. The batch capacity for

compound semiconductors is 66 three-

inch wafers or 36 four-inch wafers or

12 six-inch wafers. The substrate holders

accept substrate sizes up to 8” in diameter.

Low temperatures for lift off

The LLS is an ideal sputter system for

lift off processes because of its low

substrate temperatures. For example, we

take a close look at the TaN process.

The LLS sputter system is suitable to

produce films for MEMS, MCM, TFH,

UBM, resistors, power devices and other

applications.

by Jean-José Galiano, III-V Systems Manager, BPS NEXTRAL

For over 20 years, the Industrial

Technology Research Institute (ITRI) has

played a central role in promoting the

transfer of advanced technologies to

budding information technology companies

in Taiwan. This includes research for III-V

semiconductor applications done on

NEXTRAL systems from BPS.

ITRI is engaged in applied research and

technical service and is now an important

element of Taiwan’s industrial policies and a

high-tech center for the domestic industry.

Over 6,000 ITRI employees are involved in

information technologies such as components

processing and packaging, opto-electronic

components, optical devices, material

processing, as well as traditional industries.

The Opto-Electronics and Systems

Laboratory (OES) is part of the optical

electronic material and device division within

ITRI and focuses on research into opto-

electronic devices and III-V semiconductor

applications such as GaN laser diodes. OES is

made up of three divisions that work very

closely together: Materials, Technology &

Processes and Packaging. Together, these teams

optimize and prepare the world-class IC

technologies for local implementation.BAK 760

LLS EVO

LLS EVO

NEXTRAL 200

NEXTRAL 860

NEXTRAL 100 RL

BA

K 7

60

Pro

cess

es

Processes

Via holes GaAs

Metallization evaporation

Metallization sputtering

Resistive films

N/Ox deposition

Dielectric etch

LLS

EVO

NEX

TRA

L10

0 R

L

NEX

TRA

L 20

0

NEX

TRA

L 86

0

ChipsIII-Vmatrix

Examples of the wide range of applications

Vias Degas, etching, WTi / Au / Ti or Ti / Au

Resistors Degas, etching, Cerment or TaN or TiWSi(N)

or other

UBM Degas, etching, Cr/NIV/Au or Al/TiW/NiV/Au

OIC In2O3, SiO2, TiN, etc.

Sequence for WTi / Au metallization:

1. Wafer degassing in LC

2. Sputter etch in LC 5-10nm

3. Sputter WTi 100nm, 5nm/min at 1kW

Substrate temp = <70°C

4. Sputter Au 200nm, 22nm/min at 1kW


(Throughput 4'' wafers =

21 wafers/hour)

SHUTTER

HEATER WITH SHUTTER

SPUTTER SOURCE

MEISSNER TRAP

Au

Ti

TiW

Si

WTi

Ta

LLS system configuration for lift off resistorsand metallization

80

70

60

50

40

30

20

10

00 10 20 30 40 50 60 70

Time (min)

Temperature (grd C)

max: 67°C

Sputter-Deposition; LLS502 Ta + N2, AKQ 516

Sta

rt p

ump

Sta

rt Io

n-m

ill

Sta

rt d

epos

ition

Conditions:

Power: 1.5 kW Argon: 3,0e -3 mbar N2: 3,5e -4 mbar time: 135x5 a/P TH: 1100 Å with Ion-mil “low Pow” (9x10 s/P)

Measurements: = Int. sensor = 3" GAs wafer

Sputter Deposition (LLS)

QA

A Q

Q

QA

A A

A

Q

Q

Q

Dr. Jin-Kuo Ho, division manager of the

Technology and Processes group within the

OES spoke to us about the institute’s

cooperation with BPS in compound

semiconductor research.

What is your group at OES involved in?

A lot! Right now we have parallel projects for semiconductor laser

diodes, laser diodes for DVD, blue LEDs for full color FPDs and

LEDs for small volume production. We plan to develop and

demonstrate the potential of these technologies for mass

production.

And the other teams?

The materials division (EPI group) grows the crystals of GaN,

AlInP, etc. We then take the prepared wafer and do lithography,

etching and deposition on the extremely thin layers used in III-V.

These chips are then passed on to the Packaging group, where they

are prepared for testing.

You have a NEXTRAL system in your lab. What are youdoing with it?

Right now the market potential for GaN applications in Asia is

very high. We are setting up GaN etching on the NEXTRAL 860L.

We also have a non-corrosive process (no chlorinated gases) for

anisotropic profiles and very clean etching. Until now, the

system reactor has shown excellent uniformity: ±5% across a

7 (seven) 2” wafer batch.

Has the NEXTRAL 860L met all your specifications?

This system has a very good high density plasma source that is

perfect for very low electron energy processing. We can accurately

control the etch rates while keeping damage to the chip to a

minimum. As the NEXTRAL 860L machine can either operate in

RIE or HDP mode, our existing RIE recipes have been

successfully transferred to the NEXTRAL system. Beyond the

good performance is also equipment support from BPS Taiwan.

They respond very quickly.

In which direction will research go in the next five years?

We are working hard to produce a good blue LED and blue lasers,

both very complex technologies. Another project is VCSEL

(vertical cavity surface emitting laser) lasers for telecommunication

applications within the next three to five years. This will be a big

market.

All within the next 5 years sounds ambitious.

But it’s very exciting work! For example, just before the Chinese

New Year last year, the blue laser I had been working on suddenly

appeared. Wow! I called my boss and all the assistants over and we

celebrated the New Year in the lab. We talked and discussed until

about 3:00 am. Then I went home and slept all day long.

ITRI & CompoundSemiconductorTechnologySequence for TaN resistors for lift off processing:

1. Wafer degassing in LC

2. Sputter etch in LC 5-10nm

3. Sputter TaN reactive 90nm, 8nm / min at 1.5kW


(Throughput 4'' wafers = 31

wafers/hour

Uniformity on SiO2 4'' wafer

with 4 point probe = 1.3%)

BAK 760(low volume)

BAV1250(high volume)

LLS EVO CLUSTERLINE 200

NEXTRAL 100

NEXTRAL 100

NEXTRAL 860

NEXTRAL 860

BAP 800B

AK

760

(low

vol

ume)

Pro

cess

es

Processes

Power devices

FA delayering

Carrier preparation

BAV

1250

(hig

h vo

lum

e)

BA

P 8

00

LLS

EVO

CLUS

TERL

INE™

200

NEX

TRA

L 10

0

NEX

TRA

L 86

0

ChipsICManufacturing

matrix

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22

All these elements must be connected

with some kind of wiring to form a

circuit. More and more levels of ever-

smaller interconnects (0.35 to 0.13µm)

are required to connect the layers because

chip size and integration of the number of

devices are increasing, while the scaling is

shrinking, resulting in four to seven layers

of multi-level metallization (MLM).

Such complex multi-level structures

mean significant process challenges –

including PVD metallization,

pretreatment and annealing steps – for

today’s IC equipment manufacturers.

The metallization sequence

The work starts at the interface

between the silicon devices and the first

level of interconnect metal to ensure an

ohmic contact. In many process flows, the

first step is to form silicides on the source,

drain and gates of the MOS transistors as

well as on parts of the doped silicon films

that may be used as resistors or contacts in

many bipolar circuits. Sputter deposition

is used either for a salicide (self-aligning

silicide) step or for a polycide process,

where a silicide is deposited from usually a

composite target such as TaSix, MoSix, or

WSix on the gate poly-Si. The silicide/

poly-Si stack is then exposed and

patterned with reactive sputter etching.

To separate these silicon and local

interconnect lines from the first metal

interconnect layer, a pre-metal dielectric

layer (PMD) is introduced. Between the

higher metal layers it is called interlevel

dielectric layer (IMD). This is usually a

CVD deposition. The PMD or IMD film

is then patterned and etched to form

contact holes through the oxide.

The next steps are to fill the holes of

the IMD layer with metal, to planarize the

IMD and metal surface and to continue

the deposition of the interconnect metal

layer on top of the IMD. Repeating

metallization and IMD steps builds up a

multilevel metallization scheme.

We find the most challenging

requirements with respect to deposition

technology particularly in the first levels

near to the silicon because of the

shrinking feature size (0.35 to 0.10µm)

and aspect ratios between the depth and

the width of the hole of 4:1 and higher.

For a lot of reasons, aluminum is

widely used as an interconnect material of

choice for ICs. Some of this material’s

weak points include poor electro-

migration, poor stress characteristics and

interactions with silicon at relatively low

temperatures (~=450°C). Adding a small

percentage of silicon improves junction

spiking, adding copper reduces electro-

migration and stress-induced hillocks.

A barrier layer is required between the

metal and the silicon for a metallization

structure with low contact resistance and

no degradation of the shallow junction

device integrity during sequential thermal

cycles. To remove the native oxide from

contact areas prior to the deposition of

barrier and interconnect metal, vacuum

integrated pre-treatment capabilities such

as degassing and soft sputter etch with

very low damage level are essential.

Between Al and Si a thin titanium film,

followed by a titanium nitride layer

(Ti/TiN) or titanium tungsten layer

(TiW) are both reliable barrier layers. To

improve the barrier performance and

reliability, annealing steps in an integrated

RTP module using an Ar/O2 or N2/O2

atmosphere can be introduced.

Planarization and via filling is encouraged

by reflow concepts as well as by two level

processes (cold/hot deposition with high

and low sputter rate).

Today, a CVD tungsten plug is often

used for via filling, where only a thin layer

of Ti or TiW is sputter deposited as a seed

liner either conventional or by collimated

sputtering. However, there is a

considerable interest in filling via-hole and

contact structures with an integrated

aluminum process as replacement of the

expensive tungsten (W) plug and etchback

process.

The possibility to avoid further metal

etching steps using damascene and dual

damascene technologies are also a driving

force to fill high aspect ratios with low

resistivity metals such as aluminum alloys

(AlSiCu, AlSi, AlCu) or copper (Cu). In

combination with low resistivity copper

there is currently a lack of well established

barrier layers. However, there is rising

interest in TaSi(N), TiSi(N) and Wsi(N)

as alternative materials.

Full range of applications

Independent of technology and

material trends, the MESC standard

architecture of our CLUSTERLINE™ 200

poses no limit to current or future process

flows. TFH and packaging activities are a

vital proof of this paradigm. Ultra thin

wafer handling down to 150µm substrate

thickness for backside metallization and

Cr/Cu phasing solutions for UBM are just

two examples that highlight the great

Advanced process technology on the cluster tool

PVD Metallizationfor ICs

by Dr. Joe P. Seidel, Manager Process R&D, BPS& Dr. Reinhard Benz, Cluster Systems Product Manager, BPS

Today’s state-of-the-art integrated circuits contain a

considerable number of active and passive elements

including millions of transistors, capacitors and resistors on a

single chip. This poses considerable production challenges.

0,5

0,4

0,3

0,2

0,1

0

1996 1998 2000 2002 2004

Year

Evolution of the Critical Dimension in µm

2006 2008 2010

variety of applications. Also, the high

reliability in handling of ultra thin wafers

and the extraordinary material efficiency

for sputtering Au or Au-alloys with

backside metallization makes this an

extremely attractive application.

Technology synergy with other BPS

departments (i.e. data storage) lead to

excellent production conditions and a

remarkable low cost of ownership for this

type of metallization.

For more information on IC

production processes, please contact us at:

[email protected].

RTP module for CLUSTERLINE™ 200: Detail of the quartz lamp arrangement.

RTP module of the CLUSTERLINE™ 200: quartz lamp arrangement in the heat up phase.

Evolution of the Critical Dimension in µm

10

8

6

4

2

0

1996 1998 2000 2002 2004

Year

Evolution of the Aspect Ratio

2006 2008 2010

Evolution of the Aspect Ratio

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24

There are a number of good reasons to

integrate two or more process steps in a

single machine with multiple process

stations. Technically, this is a matter of

improved device performance, the

economic factors are higher throughput

and better yield.

The increasing degree of miniaturi-

zation – today we are looking at a line

width below 0.18µm – requires an

improved process and defect control in

terms of metal contamination, chemical

contamination and particle

contamination.

For example, for metallization a short

sputter etch prior to silicide deposition

ensures a good quality film interface free

of native oxides and particles. For similar

reasons we also integrate different

processes such as cleaning, etching, PVD,

CVD, RTP, RIE or photoresist stripping

in manufacturing of aluminum

interconnect stacks, tungsten plugs, dual

damascene structures, gate stacks and

DRAM trench capacitors.

Each of these process steps has specific

vacuum system requirements with respect

to pumping speed, corrosion resistance

and the handling of hazardous substances.

The Cluster Tool concept

Integrated process systems, or cluster

tools, are the result of the concept of

single wafer processing with

process separation. This means all

handling and other key functions are

strictly separated from each other. The

cluster tool concept combines all the

necessary process steps into one tool

without exposing the wafer to ambient

during the complete process sequence.

For metallization processes, the need

to integrate several process steps is very

clear and accepted because the metal

surface is highly reactive between process

steps. For example, for the well known

sequence Ti-TiN-Al, a stuffing step may

be required after Ti, but not even a

minimal contamination with oxygen is

allowed between TiN and Al to enable a

sufficient Al flow.

This production system concept has

found overwhelming acceptance among

manufacturers. About 80% of all tools

used for metallization are cluster tools.

These use either PVD or CVD, and more

recently a combination of both.

General process requirements are

becoming more and more stringent.

Topological considerations and uniformity

needs within a single wafer and from

wafer to wafer, combined with the trend

to larger wafer sizes (such as 300mm)

strengthens the trend away from batch

processing to single wafer processing –

leading straight to the cluster tools

configurations.

In the future, many more process steps

besides metallization will be integrated

into the cluster tool concept. Also, in situ

metrology modules for advanced process

control (APC) will become more and

more important, especially for 300mm

tools.

Cluster tool from BPS

In 1989 BPS successfully

introduced its first cluster tool, the

CLUSTERLINE™ 9000. This tool met

advanced metallization specifications and

offered up to nine process stations, high

throughput and advanced sputtering

processes. In 1996, we introduced our

third generation cluster tool: the

CLUSTERLINE™ 200. Following strict

UHV design rules, this new tool offers

state-of-the-art PVD metallization for

wafers up to Ø200mm. This includes

degas, rapid thermal processing (RTP) and

ICP soft sputter clean etch.

For the near future, the BPS cluster

tool team is integrating chemical vapor

deposition (CVD) and reactive ion

etching (RIE) modules, as well as

dedicated solutions in electrostatic

clamping (ESC).

CLUSTERLINE™ 200 specifications

Low particle density <0.06 pcs/cm2

>0.35µm.

Contamination control concerning

handling, process materials and gases.

Very high vacuum <5.0E-9 mbar in

process chambers, <5.0E-8 mbar in

transport sections.

Uniform films across the wafer, wafer

to wafer <3% (6 sigma), statistical

process control.

Working with cluster tools

IntegratedVacuum Processingby Dr. Joe P. Seidel, Manager Process R&D BPS, & Dr. Reinhard Benz, Cluster Systems Product Manager, BPS

The use of cluster tools for

integrated vacuum

processing – with their low

particle generation and high

throughput – is essential to

meet the demanding

requirements of

semiconductor process

technologies. Cluster tools

are used for several types of

etching processes as well as

for PVD and CVD deposition

and rapid thermal annealing

and cleaning steps.

“Throughput and more

throughput. That’s what we like

about this tool,” explains Hermann

Wolfer, process and systems engineer

at SMST. “It’s one of the fastest

sputtering tools we have.”

Located in Germany, SMST

(Sub-Micron Semiconductor

Technologies) is a joint-venture with

impressive parentage: both Philips

and IBM are partners in the

European semiconductor

manufacturer. SMST employs over

700 people and produces high-level

microprocessors, 16MB DRAM

chips, multi-layer chip interconnects

and ASICs in sub half micron

technologies. Maintaining one of the

largest and most modern wafer fabs

in Europe, SMST has been operating the BPS cluster tools since 1989.

Karl-Heinz Saremski, head of the SMST production facility that

includes etching, implant, CVD and PVD deposition systems, is also

happy with the performance of the cluster tools; “The BPS cluster tools

are the workhorse systems in our production line. We run them 24

hours a day, seven days a week.”

Among the normal metallization applications, further cluster tool

processes include collimated Ti for a contact hole fill process (aspect

ratio 4:1) for silicon and wiring contacts.

Besides maintaining state-of-the-art production output, SMST also

follows an ongoing program of ‘cost of ownership analysis’. The

program helps keep all production stages cost-effective and is done as

part of all system purchases and sporadically over the year for different

sections of the fab. The analysis includes evaluation of energy &

materials consumption, the costs for consumables and spare parts,

maintenance costs, etc. It also factors in a percentage of the initial

investment price and depreciation costs. The analysis helps pinpoint

production areas that might function better through redeployment,

upgrading or replacement.

An essential part of running a world-class semiconductor fab is also

good service. Lothar Hafner, manager of the maintenance group that

keeps the systems at SMST online, points out: “Our goal is to

continually improve uptime. BPS service people and the spare parts

have always been here when we needed them. We’ve worked together

well.”

For more information on SMST contact the company directly:

[email protected] or by telephone at: +49-7031-18-0.

with theEuropeanleader

Working

BPS cluster tools at

by Jörg Spengler, Senior Staff Engineerfor CVD, PVD and CMP, SMST

As a leader in semiconductor

production, SMST counts on

cluster tool technology from

BPS. Five cluster tools from

BPS (CLUSTERLINE) work

around the clock at the

company’s Sindelfingen,

Germany fab.

Ti-TiN Al (Si1%Cu0.5%) Layer Stock – Typical test results

0.1341630.1337460.1333290.1329130.1324960.1320790.131663

Film thickness Ai(Si1%Cu 0.5%) 220nm

Substrate temperature >350°C

Power 1.0kW

Time 90 sec

Deposition rate 2.4nm/sec

Mean square resistivity 0.1332 Ohm/sq.

Standard deviation 0.41%

Min., Max. 0.13166, 0.13414 Ohm/sq.

Uniformity ±0.94%

(150mm wafer, test diameter 138mm,

69 points, 3 sigma)

Specific resistance 2.93µOhm.cm

Mean square resistivity 0.04204 Ohm/sq.

Standard deviation 0.431%

Min., Max. 0.04168, 0.04241 Ohm/sq.

Uniformity ±0.87%

(150mm wafer, test diameter

138mm, 69 points, 3 sigma)

Good bottom coverage to barriers.

Good sidewall and bottom coverage

for liners.

Metal planarization.

Low thermal stress <450°C for logic

and DRAM applications.

High percentage of wafer coverage,

minimal edge exclusion.

Al (Si1%Cu0.5%) Process – Typical test results for second (hot) step of a cold/hot 2-step process

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26

Backside etching

Further challenges for FA are: devices

with a power bus covering a large portion

of the front side of the die, the large

number of new materials in use and a

more pro-active emphasis on yield

improvement and device debug. For an

increasing number of semiconductor

manufacturers and their suppliers, coming

up with innovative solutions and new

techniques to analyze circuits from the

backside of the die is essential.

When integrated circuits fail, labs use

a variety of FA methods to determine the

cause. Many types of failures will emit

metal levels on today’s advanced ICs, the

detection of light issued from defects is

next to impossible. This means the

emitted light cannot reach the chip surface

due to obstruction of the multiple metal

levels. Therefore, backside emission

microscopy is fast becoming the latest way

to locate faults on multi-metal level

circuitry.

The example of backside etching

Flip chip packaging is a well-known

example where backside analysis is the

only choice. A flip chip is a specific type

of package where the front side of the die

be opened from the backside – the silicon

substrate side – and be thinned down in

order to allow the emission to pass

through. This demands a quick and

dependable method of backside etching.

At NEXTRAL, we came up with the

idea of thinning the thick silicon on the

backside of the die using a dry plasma

process over two years ago. To reduce the

total investment cost, the system thins

silicon on the backside of packaged dies in

the same high density vacuum chamber

(HDP) we had already designed for multi-

metal-level deprocessing while

maintaining the electrical integrity of the

circuit. This request posed a challenge for

our engineers, since the frontside

deprocessing and backside silicon thinning

applications require 2 completely different

reactor configurations.

Two reactors for one

With front side deprocessing, the

NEXTRAL process uses a microwave

high-density plasma source with RF

biasing polarization, for anisotropic

etching. The backside thick silicon

thinning process requires very fast

isotropic etching which we obtain using

an ECR reactor configuration with

magnets. Initially, a compromise could

have been possible between the two

applications developed in the same reactor.

However, the results that have been

churned out for both applications are

impressive. Currently, we have silicon etch

rates higher than 10µm/min, a uniformity

of ±3% measured 0.5mm from the edge

of the die, and a very shiny surface after

thinning. This system can handle

frontside deprocessing on up to 5 metal

level devices that no other system has been

capable of reproducing.

Compared to other techniques such as

backside mechanical polishing, dry etch

for silicon backside thinning is an ideal

solution because of higher throughput

capability, less damage to the device,

precise control of the fast etch rates and

surface polishing to enable further optical

analysis.

Frontside etching

Full electrical functionality of the

devices or avoidance of any electrical or

physical damage during etching is

maintained by a unique cooling

mechanism to prevent metal lifting.

Starting with the End:Failure Analysisby Marnie Gaubert, Failure Analysis

Product Engineer, BPS-NEXTRAL

The NEXTRAL 860 system is designed to treat wafers up to ø200mm.

Mechanical clamping in the NEXTRAL

860 optimizes cooling during the etching

while helium is injected up through the

cathode and into small ducts in the shuttle

assembly where the samples are

positioned. The cathode is cooled by

means of a dielectric liquid, and the

helium injection facilitates the thermal

transfer between the cooled cathode and

the shuttle assembly, thus maintaining the

samples at temperatures less than 100°C.

Temperature also plays a role in etch

cleanliness. Too low a temperature gives

rise to grass by condensation of polymers

on top of the etched surface. In fact, the

temperature process window to achieve

electrical functionality and lean etching

simultaneously is narrow.

Wide range of applications

The HDP gives excellent etch

uniformity of ±5% over Ø200mm

wafers. This helps meet the advanced

failure, construction, and yield analysis

needs for both frontside and backside

applications – in one system.

The NEXTRAL 860 has thefollowing plasma modes:

Frontside applications:

microwave + RF biasing (anisotropic)

pure microwave (isotropic)

RIE

Backside application:

ECR/microwave

For further information on failure

analysis applications, contact us at:

[email protected].

Failure analysis (FA) plays an important role in the

semiconductor business. Because more and more IC

manufacturers are moving to flip chip/MCM packaging

technology and complex device architecture with up to 5 and 6

metal levels, FA is also more challenging.

Deprocessing of a 3-metal level IC using microwavewith RF biasing

Examples of deprocessing of 5 metal level devices on packaged dies.

small amounts of light where the failure

occurs. Frontside light emission

microscopy is commonly used in FA

laboratories as a technique to locate such

device failures quickly and accurately.

However, with the increasing number of

is “flipped” (face down) and bonded on

the package, leaving the substrate side

facing up. To be able to analyze this type

of package FA techniques must study the

circuit from the silicon side; the backside

of the die.

Backside emission microscopy requires

the sample to be prepared in a completely

different way from regular frontside

deprocessing. The packaged device must

Documents

Semiconductor Industry Sourcebook Staying Connected