SEMINAR FINAL.docx

FREQUENCY SYNTHESIZERS FOR 4G APPLICATIONS

A SEMINAR REPORT ON


Submitted to

JAWAHARLAL NEHRU TECHNOLOGYICAL UNIVERSITY, ANANTHAPUR

In partial fulfilment of the requirement for the award of degree of

BACHELOR OF TECHNOLOGY

IN

ELECTRONICS AND COMMUNICATION ENGINEEING

BY

R.Lathasri 11691A0447

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

MADANAPALLE INSTITUTE OF TECHNOLOGY AND SCIENCE,

(Approved by AICTE, New Delhi, Affiliated to JNTU, Ananthapur)

Madanapalle–517325, Andhra Pradesh.

ELECTRONICS AND COMMUNICATION ENGINEERING Page 1


MADANAPALLE INSTITUTE OF TECHNOLOGY & SCIENCE

(Approved by AICTE, New Delhi, Affiliated to JNTU, Ananthapur)

BONAFIDE CERTIFICATE

This is to certify that this technical seminar report “FREQUENCY SYNTHESIZERS FOR 4G APPLICATIONS ” submitted in partial fulfilment of the requirement for the award of the degree for bachelor technology in electronics and communication engineering is a result of the bonafide work carried out by R.LATHASRI (11691A0447). He is bonafide student of this college studying IV year B.Tech during academic year 2011-2015.

Prof. A R REDDY, M.Tech, Ph.D

Head of the department,

Dept. of ECE.



Acknowledgement

I extend my sincere gratitude towards Prof.Dr.A.R.REDDY, Head of the Department, Dept of E.C.E for giving me his valuable knowledge and wonderful technical guidance. I also thank all the other faculty members of ECE department and my friends for their help and support.



ABSTRACT

The growing importance of wireless media for voice and data communications is

driving a need for higher integration in personal communications transceivers in order to

achieve lower cost, smaller form factor, and lower power dissipation. One approach to this

problem is to integrate the RF functionality in low-cost CMOS technology together with the

baseband transceiver functions. This in turn requires integration of the frequency

synthesizer with enough isolation from supply noise to allow the synthesizer to coexist with

other on-chip transceiver circuitry and still meet the phase noise performance requirements

of the application.

A differential synthesizer for block-down-convert receivers that achieves improved

levels of phase noise and supply rejection performance through the use of fully differential

architecture and a wide abstract Design Techniques for High Performance Integrated

Frequency Synthesizers for Multi-standard Wireless Communication Applications.

A prototype systems embodying the design principles, and also embodying new

differential circuit configurations which minimize supply coupling is designed, laid out and

fabricated. The performance of the prototype synthesizer as a stand alone device is

evaluated. The synthesizer is embodied in a complete integrated radio system and the

performance of the synthesizer in the complete radio system is also evaluated.



CONTENTS

Chap.1: 4G communications

1.1: Introduction

1.2: Features of 4G

1.3: Applications of 4G

Chap.2: Fundamentals of frequency synthesis

2.1: Frequency synthesizer

2.1.1: Role of frequency synthesizer

2.2: Frequency synthesizer parameters

2.2.1: Effect of phase noise and spurious tones on transceiver and receiver performance

2.3: Synthesizer alternatives

2.3.1: Direct digital frequency synthesizer

2.3.2: phase-locked-loop frequency synthesizer

2.3.3: Fractional-N frequency synthesizer

2.3.4: Delay-locked loop frequency synthesizer

Chap.3: Wide band PLL frequency synthesizer

3.1: Noise shaping of the wide band PLL

3.2: Loop bandwidth optimization

3.3: effect of wideband PLL on receiver architecture

Chap.4: Design techniques for low noise synthesizer

4.1: Introduction

4.2: Low noise integrated VCO design

4.3: Prototype design

4.3.1: Frequency plan

Conclusion

References



CHAPTER 1

4G communications

1.1 Introduction to 4G:

The wireless personal communication market has been growing explosively due to

ever emerging new applications and dropping prices. A low cost, small, long-battery-life

solution has been the dream for decades. Many efforts have been devoted to the integration of

such circuits in low-cost technology in order to reach the goal.

The applications of wireless communication devices include pagers, cordless phones,

cellular phones, global positioning systems and wireless local area networks, transmitting

either voice or data[1]. A standard tells how devices talk to each other. Numerous standards

exist which are optimized for different implementations. For voice, examples include DECT,

AMPS, GSM, DCS, PCS, CDMA, and so on. For data, there are 802.11 WLAN, Bluetooth,

Home RF and so on. The rapidly growing market and ever emerging new applications create

a high demand for a low cost, low power, high portability transceiver solution. Current

commercial approaches utilize several high quality discrete components to provide high

performance required by transceiver. High component counts and multiple chips in various

technologies increase the cost and form factor. A higher integration level is required to lower

the cost and form factor.

In telecommunications, 4G is the fourth generation of cellular wireless standards. It is

a successor to the 3G and 2G families of standards. In 2008, the ITU-R organization specified

the IMT-Advanced (International Mobile Telecommunications Advanced) requirements for

4G standards, setting peak speed requirements for 4G service at 100 Mbit/s for high mobility

communication (such as from trains and cars) and 1 Gbit/s for low mobility communication

(such as pedestrians and stationary users).

A 4G system is expected to provide a comprehensive and secure all-IP based mobile

broadband solution to laptop computer wireless modems, smart phones, and other mobile



devices. Facilities such as ultra-broadband Internet access, IP telephony, gaming services,

and streamed multimedia may be provided to users.

Pre-4G technologies such as mobile WiMAX and first-release 3G Long term

evolution (LTE) have been on the market since 2006 and 2009 respectively, and are often

branded as 4G. The current versions of these technologies did not fulfill the original ITU-R

requirements of data rates approximately up to 1 Gbit/s for 4G systems. Marketing materials

use 4G as a description for Mobile-WiMAX and LTE in their current forms.

IMT-Advanced compliant versions of the above two standards are under

development and called LTE Advanced and Wireless MAN-Advanced respectively. ITU has

decided that LTE Advanced and Wireless MAN-Advanced should be accorded the official

designation of IMT-Advanced. On December 6, 2010, ITU announced that current versions

of LTE, WiMax and other evolved 3G technologies that do not fulfill "IMT-Advanced"

requirements could be considered "4G", provided they represent forerunners to IMT-

Advanced and "a substantial level of improvement in performance and capabilities with

respect to the initial third generation systems now deployed.

The approaching 4G (fourth generation) mobile communication systems are projected

to solve still-remaining problems of 3G (third generation) systems and to provide a wide

variety of new services, from high-quality voice to high-definition video to high-data-rate

wireless channels. The term 4G is used broadly to include several types of broadband

wireless access communication systems, not only cellular telephone systems. One of the

terms used to describe 4G is MAGIC—Mobile multimedia, anytime anywhere, Global

mobility support, integrated wireless solution, and customized personal service.

The 4G systems, that is, cellular broadband wireless access systems has been

attracting much interest in the mobile communication area. The 4G systems not only will

support the next generation of mobile service, but also will support the fixed wireless

networks. This article presents an overall vision of the 4G features, framework, and

integration of mobile communication.

The features of 4G systems might be summarized with one word- Integration. The

4G systems are about seamlessly integrating terminals, networks, and applications to satisfy

increasing user demands. The continuous expansion of mobile communication and wireless

networks shows evidence of exceptional growth in the areas of mobile subscriber, wireless

network access, mobile services, and applications. An estimate of 1 billion users by the end

of 2013 justifies the study and research for 4G system.



Table 1: comparision

Technology 1G 2G 2.5G 3G 4G

Design Began 1970 1980 1985 1990 2000

Implementation 1984 1991 1999 2002 2010?

Service Analog

voice,

synchron-

ous data to

9.6 kbps

Digital voice,

short

messages

Higher

capacity,

packetized

data

Higher

capacity,

broadband data

up to 2 Mbps

Higher

capacity,

completely IP-

Oriented,

multimedia,

data to

hundreds Of

megabits

Standards AMPS,

TAGS,

INMT, etc.

TDMA,

CDMA, GSM

PDC

GPRS,

EDGE,

1XRTT

WCDMA,

CDMA2000

Single standard

Data Bandwidth 1.9 kbps 14.4 kbps 384 kbps 2 Mbps 200 Mbps

Multiplexing FDMA TDMA,

CDMA

TDMA

CDMA

CDMA CDMA?

core Network PSTN PSTN P3TK,

packet

network

Packet network internet



1.2 FEATURES OF 4G:

The 4G will have broader bandwidth, higher data rate, and smoother and quicker

handoff and will focus on ensuring seamless service across a multitude of wireless systems

and networks. The key concept is integrating the 4G capabilities with all of the existing

mobile technologies through advanced technologies. Application adaptability and being

highly dynamic are the main features of 4G services of interest to users.

. These features mean services can be delivered and be available to the personal

preference of different users and support the users traffic, air interfaces, radio environment,

and quality of service. Connection with the network applications can be transferred into

various forms and levels correctly and efficiently. The dominant methods of access to this

pool of information will be the mobile telephone, PDA, and laptop to seamlessly access the

voice communication, high-speed information services, and entertainment broadcast services.

The fourth generation will encompass all systems from various networks, public to

private; operator-driven broadband networks to personal areas and ad hoc networks. The 4G

systems will interoperate with 2G and 3G systems, as well as with digital (broadband)

broadcasting systems. In addition, 4G systems will be fully IP-based wireless Internet. This

all- encompassing integrated perspective shows the broad range of systems that the fourth

generation intends to integrate, from satellite broadband to high altitude platform to cellular

3G and 3G systems to WLL (Wireless Local Loop) and FWA (Fixed Wireless Access) to

WLAN (Wireless Local Area Network) and PAN (Personal Area Network),all with IP as the

integrating mechanism. With 4G, a range of new services and models will be available. These

services and models need to be further examined for their interface with the design of 4G

systems.



Figure 1: 4G Mobile Communication Visions[from communication systems by professor Mohammed]

1.3 Applications of 4G:

(a) VIRTUAL PRESENCE: This means that 4G provides user services at all times,

even if the user is off-site.

(b) VIRTUAL NAVIGATION: 4G provides users with virtual navigation through

which a user can access a database of the streets, buildings etc.

(c) TELE-GEOPROCESSING APPLICATIONS: This is a combination of GIS

(Geographical Information System) and GPS (Global Positioning System) in which a

user can get the location by querying.

(d) TELE-MEDICINE AND EDUCATION: 4G will support remote health

monitoring of patients. For people who are interested in lifelong education, 4G

provides a good opportunity.

(e) CRISIS MANAGEMENT: Natural disasters can cause breakdown in

communication systems. In today's world it might take days or 7 weeks to restore the

system. But in 4G it is expected to restore such crisis issues in a few hours.



Chapter 2

Fundamentals of Frequency Synthesis

2.1 Frequency synthesizer:

A frequency synthesizer is an electronic system for generating any of a range of

frequencies from a single fixed time base or oscillator. They are found in many modern

devices, including radio receivers, mobile telephones, radio telephones, walkie-talkies, CB

radios, satellite receivers, GPS systems, etc. A frequency synthesizer can combine frequency

multiplication, frequency division, and frequency mixing (the frequency mixing process

generates sum and difference frequencies) operates to produce the desired output signal.

A frequency synthesizer is a device that provides a choice of a large number of

different frequencies by combining frequencies selected from groups of independent crystals,

frequency dividers and frequency multipliers[2]. This is a device for obtaining sinusoidal

electrical oscillations at desired frequencies through the linear conversion of fixed frequency

oscillations provided by one or more reference generators. The conversion may involve

multiplication by a constant coefficient, division by a constant coefficient, addition, or

subtraction.

2.1.1 Role of Frequency Synthesizer:

The role of a frequency synthesizer is to provide the reference frequency for

frequency translation. Fig. 2.1 shows the typical block diagram of a cellular phone RF

section. An RF synthesizer and an IF synthesizer are used for the frequency translation.



[Radio frequency integrated CI by RB Staszewski]

2.2 FREQUENCY SYNTHESIZER PARAMETERS:

a. Frequency range: This specifies the output frequency range, including the lower and higher frequencies

that can be obtained from the FS. The units of frequency are hertz (Hz), or cycles per second.

b. Frequency resolution:

This parameter is also referred to as the step size, and it specifies the minimum step

size of the frequency increment. In many applications, the step size is not fixed. This happens

when a part of the synthesizer is generated by dividing a fixed frequency by a range of

numbers.

c. Output level:

The output power level is usually expressed in decibels (0 dBm is 1 mW). The output

power can either be fixed, say, 110 dBm, or can cover a range, say, 2120 to 115 dBm. This

specification will also include the output power resolution.



d. Control and interface:

This parameter specifies the control methodology and the interface to the FS. The

control can be binary-coded decimal (BCD) or binary; it can be parallel or via a bus (usually

an 8-bit bus) or serial; it can be transparent or latched. When the control is latched, there is a

register that receives the control word and upon activation loads the control word into the FS

(also referred to as double buffering). Some FS use positive logic and others use negative;

and in many general-purpose instruments, GPIB or IEEE-488 is currently the standard

interference.

e. OUTPUT IMPEDENCE:

This parameter specifies the nominal output impedance of the FS and usually is also

the recommended load impedance. In most radio-frequency and microwave equipment, this is

50 ohms (V). In video it is usually 75 V and in audio equipment 600 V.

f. Switching speed:

This parameter specifies the speed at which the FS can hop from frequency to

frequency. There are many definitions for this parameter. In some applications the

requirement is to settle to within a specific frequency from the desired new frequency

g. Harmonics:

This parameter specifies the level of harmonics of the output frequency and depends

on many components inside the FS. It is expressed in decibels relative to the output frequency

(carrier) output power.

h. Spurious output:

This specification defines the level of any discrete output frequency spectral line not

related to the carrier. Most users do not consider harmonics as spurious signals. However, sub

harmonics, because of either multiplications or those that appear as DDS artifacts, are

considered spurious signals even though they are sometimes specified separately. This

parameter is expressed in decibels relative to the carrier output power. Unlike noise, spurious



signals are only discrete spectral lines not related to the carrier, meaning that they exhibit

periodicity.

Phase noise:

From the purist’s standpoint, there are no deterministic signals in the real world. All

real signals are narrow-band noise. Every signal we generate is derived from an oscillator.

Oscillators are positive feedback amplifiers with a resonance circuit in their feedback path.

Since noise always exists in the circuit, upon power up this noise is amplified in the resonator

band until a level of saturation is achieved. Then the oscillator passes from the transient to its

steady state. Thus, the quality of the signal is mainly determined by the resonator Q. The

signal that we usually refer to as a “sinewave” is actually narrow-band noise. The quality of

the signal is determined by how much of its energy is contained close to the carrier. The

center frequency is actually the average the mean of the noise frequency. Phase noise in a

way is the standard deviation of the noise.

2.2.3 Effect of Phase Noise and Spurious Tones on Transceiver and receiver Performance:

Phase noise and spurious tones are the two key performance parameters of a

frequency synthesizer. In a receiver, the spurious tones and phase noise of the frequency

synthesizer can mix with the undesired signal and produce noise in the desired channel. This

reduces the sensitivity and selectivity of a receiver.

Similarly, in a transmitter, the spurious tones and the phase noise of the frequency

synthesizer can mix with the modulated baseband signal and produce undesired spectral

emissions, increase adjancent channel interference, and reduce the modulation accuracy.



Fig a: Effect of phase noise and spurious tones in a receiver

[ieeexplore.ieee.org ]

Fig b: Effect of phase noise and spurious tones in a transmitter



2.3 Synthesizer Alternatives :

There are many ways to implement a frequency synthesizer. For an integrated multi-

standard radio transceiver, we want the synthesizer to be able to generate a tunable frequency

in the gigahertz range with low phase noise and low spurious tones using minimum power.

2.3.1 Direct Digital Frequency Synthesizer: ` A direct digital frequency synthesizer is best known for its fast switching and very

fine frequency resolution. It can also easily be integrated because no off chip components are

required. But due to technology limitations, it takes large power consumption to synthesize

very high frequencies directly. Direct digital frequency synthesis (DDFS) is a technique to

synthesize frequencies and achieve a very fast settling time. A DDFS is composed of an

accumulator, a ROM-based lookup table, and a digital-to-analog converter (DAC), and is

usually, followed by a low-pass filter. A block diagram of a typical direct digital frequency

synthesizer (DDFS) is shown in Fig. 4

Fig : Direct digital frequency synthesizer[Digital frequency synthesis by Goldberg]

The phase accumulator accumulates its output with the frequency setting word at

every clock cycle. The output increases linearly until the accumulator maximum count is

reached and the accumulation starts from zero again. Hence the phase accumulator output



follows a periodical sawtooth pattern. The frequency of this sawtooth pattern is the

synthesizer output frequency fout. It is determined by the frequency setting word length Lset,

the accumulator length Lacc, and the clock frequency fclk, as

A ROM converts the digital phase value at the output of the phase accumulator to a

digital amplitude value according to the lookup table stored in the ROM. In a typical case, the

conversion is cosine. A DAC then converts the digital amplitude value into an analog

waveform. The waveform goes through a low-pass filter so that the output spectral purity is

improved.

Because the DDFS is an open-loop structure, output frequency switching can be

done in a few clock cycles. This fast switching capability is one of the reasons that DDFS is

preferred in an extremely agile system, such as a frequency-hopped spread- spectrum system.

Both frequency and phase modulation can be implemented by simply modulating Lset in

digital domain. Very small frequency increments can be achieved. In fact, the minimum

frequency increment is the clock frequency divided by the accumulator length. Fractional Hz

can easily be achieved. DDFS is also amenable to integration because no off chip

components are required.

However, the spectral purity of the DDFS is limited by the DAC speed and resolution

because the finite resolution in quantization leads to inaccurate representation of the sinusoid

and hence spurious outputs. If the output frequency is a sub harmonic of the clock frequency,

then the output is free of spurious tones and a 9 bit DAC is required. However, it is difficult

to build a 9- bit DAC in the GHz range with current technology. High power consumption is

needed for high frequency operation.

2.3.2 Phase-Locked-Loop Frequency Synthesizer:

A PLL is one of the most common ways to synthesize a frequency using a reference

signal A phase-locked loop (PLL) is an electronic circuit with a voltage- or current-driven

oscillator that is constantly adjusted to match in phase (and thus lock on) the frequency of an

input signal[3]. In addition to stabilizing a particular communications channel (keeping it set



to a particular frequency), a PLL can be used to generate a signal, modulate or demodulate a

signal, reconstitute a signal with less noise, or multiply or divide a frequency.

PLLs are frequently used in wireless communication, particularly where signals are

carried using frequency modulation (FM) or phase modulation (PM). PLLs can also be used

in amplitude modulation (AM). PLLs are more commonly used for digital data transmission,

but can also be designed for analog information. Phase-locked loop devices are more

commonly manufactured as integrated circuits (ICs) although discrete circuits are used for

microwave.

A PLL consists of a voltage-control oscillator(VCO) that is tuned to a special

semiconductor diode called a varactor . The VCO is initially tuned to a frequency close to the

desired receiving or transmitting frequency. A circuit called a phase comparator causes the

VCO to seek and lock onto the desired frequency, based on the output of a crystal-controlled

reference oscillator. This works by means of a feedback scheme. If the VCO frequency

departs from the selected crystal reference frequency, the phase comparator produces an error

voltage that is applied to the varactor, bringing the VCO back to the reference frequency. The

PLL, VCO, reference oscillator, and phase comparator together comprise a frequency

synthesizer. Wireless equipment that uses this type of frequency control is said to be

frequency-synthesized.

Since a PLL requires a certain amount of time to lock on the frequency of an

incoming signal, the intelligence on the signal (voice, video, or data) can be obtained directly

from the waveform measured error voltage, which will reflect exactly the modulated

information on the signal.

A PLL circuit synchronizes an output signal with an input reference signal generated

by a reference frequency source, e.g. a crystal oscillator, by executing a feedback mechanism

where the output frequency of a voltage-controlled oscillator (VCO) is locked to the

reference frequency. Thereby, an error signal is produced which is proportional to the phase

difference of the reference signal and the output signal. The error signal is then filtered in

order to generate the VCO's control voltage. The loop is set up in a negative feedback fashion

such that the control voltage fed to the input port of the VCO will force the oscillator's output

to lock with the input reference signal within certain frequency limits. The rapid advance in



integrated circuit technology has led to the use of PLL circuitries in many areas such as

wireless communication systems, consumer electronics, and motor control.

Fig 5: Bloch diagram of basic integer PLL[ D. Wolaver, Phase-Locked

Loop Circuit Design]

It consists of a phase-frequency detector (PFD), a charge-pump, a loop filter, and a

voltage-controlled oscillator (VCO) in the forward path, and a frequency divider in the

feedback path. The PLL aims to lock the phase of the feedback signal to the phase of the

reference signal. Therefore, a phase detector is required to compare the phases of these two

signals. However, a PFD can also be used to enable frequency detection as well. The output

of the PFD determines the control voltage of the VCO through a charge-pump and loop filter.

An Overview of PLL Frequency Synthesis:

At the most fundamental level, the goal of any frequency synthesizer is, based on a

given reference frequency, to generate a desired output frequency. That is, solve:

where κ is the frequency scaling constant, sometimes referred to as the normalized frequency.

Any frequency synthesizer circuit is simply a mechanism for approximating κ. A PLL

frequency synthesizer approximates κ by inserting divide blocks between the reference

oscillator and the output clock. Then, using a feedback loop with a phase detector to maintain

phase coherence between the two dividers, the desired frequency is generated.

2.3.3 Fractional-N Frequency Synthesizer:

The fractional N frequency synthesizer is a modified version of the PLL based synthesizer

where the integer frequency divider is replaced by a fractional frequency divider. Fig. 6



shows the simplified block diagram of a fractional N synthesizer. The only difference from

Fig: Fractional N frequency synthesizer block [fully integrated cmos

fractional-N frequency divider by chirn chye]

the PLL based synthesizer is that the frequency divider has a choice between two integers, N and

N+1.

The reference clock also provides the clock signal for the phase accumulator. The

phase accumulator accumulates its output with a divider ratio setting the word of length Ldiv

at each clock cycle. The dual-mode divider divides its input by N when the phase

accumulator is not overflowed. When an overflow signal from the phase accumulator

appears, the dual-mode divider divides its input by N+1. On average, the divider divides its

input by a fractional value between N and N+1. To calculate the exact divider ratio, we

assume the accumulator length to be Lacc. For every Lacc clock cycles, the accumulator

overflows Ldiv times. That means for every Lacc clock cycles, the divider divides its input

by N+1 Ldiv times, and divides by N for the rest of the times.

The fractional divider ratio makes it possible to have a much smaller frequency step

with the same reference frequency comparing to the PLL based synthesizer. In other words,

the fractional N synthesizer can have a higher reference frequency and hence higher loop

bandwidth without compromising the stability of the loop. But the fractional divider ratio is

achieved through an averaging process. The alternating N, N+1 divide numbers cause the

output frequency to vary between N*fref and (N+1)*fref. This periodically alternating



process generates spurious tones at the fractional offset frequency. If the fractional frequency

falls inside the loop bandwidth, a very large spurious tone appears.

2.3.4 Delay-Locked Loop Frequency Synthesizer :

Recently a new approach to a frequency synthesizer using a Delay Locked Loop

(DLL) has been proposed[4] . A DLL is a PLL with the voltage controlled oscillator replaced

by a voltage controlled delay line. Fig shows the block diagram of a frequency synthesizer

with a DLL core. When the loop is locked, the output of the delay line is a one reference

period Tref delayed version of the input of the delay line. For a total of N delay stages, each

delay stage has a delay of Tref/N. An edge combiner generates a transition for each delay

stage output transition. The output frequency of the edge combiner is N times the reference

frequency.

Fig: Block diagram of a Delay-Locked Loop frequency synthesizer[digital

frequency synthesis by gloonberg]

The advantage of the DLL frequency synthesizer is that the jitter does not accumulate from

cycle to cycle as in the ring oscillator and thus lower phase noise at close-in frequencies can be

achieved. The major disadvantage of the DLL is that the output frequency is fixed by the number of

delay stages in the delay line and not suitable in applications where freq tuning is required.



Chapter 3

Wideband PLL Frequency Synthesizer

A new architecture that facilitates the integration of the frequency synthesizer and is

capable of high performance required in a typical cellular application. This architecture is

called wideband PLL. In this architecture, the noise contributed by the resonator can be

suppressed at the synthesizer output. Because a wide PLL bandwidth requires a high

comparison frequency, this type of synthesizer is most amenable to the synthesis of a few

widely spaced frequencies, and is thus most compatible with block-down-convert receiver

architectures such as the wideband IF double conversion architecture .

3.1 Noise Shaping of the Wideband PLL:

The noise from different blocks of a PLL goes through different transfer functions to

the output of the PLL[5]. By selecting a different loop bandwidth, their magnitude at the

output can be varied. The transfer function from the VCO to the PLL output approaches unity

at frequencies above loop bandwidth, i.e., noise from the VCO goes to the PLL output

without much suppression at offset frequencies above the loop bandwidth.

Fig (a) shows a plot of a typical VCO noise and its contribution at the narrow-loop-

bandwidth PLL output. In order to preserve good spectral purity, an off-chip high-Q

resonator is needed in the conventional PLL implementation for cellular applications. To

completely integrate the frequency synthesizer, the off-chip high-Q resonator must be

replaced with on-chip components, such as on-chip spiral inductors and varactors.



Fig 8: Noise shaping of VCO phase noise in (a) narrow band PLL (b) wideband

[www.circitstoday.com]

Due to the substrate loss and the relatively high resistivity of aluminium compared to

other metals such as copper or gold that are readily available off chip, the Q of the on chip

components are usually an order of magnitude smaller than their off-chip counterparts. As a

result, circuits using the low-Q on-chip components tend to have higher noise levels. In order

to obtain good spectral purity, we must find an architecture that gives good spectral purity at

the frequencies of interest using noisy on-chip components. One possible solution is a PLL

with a wide loop bandwidth. In this architecture, the VCO noise is suppressed at frequencies

below the wide loop bandwidth so that good spectral purity at frequencies below the loop

bandwidth can be obtained. Fig. 3.3(b) shows the plot of typical VCO noise and its

contribution at the wideband PLL output. Usually the noise from the reference and loop filter

are less than the noise contributed by the noisy onchip resonator.

3.2 Loop Bandwidth Optimization:

If VCO noise is the only noise source in a PLL, then a very large loop bandwidth can

potentially be used to obtain an output signal with very high spectral purity. However the

reference, usually a crystal oscillator, has some noise generated by its active circuits. The

loop filter also generates noise. This goes through low-pass and band-pass filtering which is

different from the VCO noise which goes through the high-pass filtering. This difference

suggests an optimal loop bandwidth exists for a specific application. Depending on the level

of the different noise sources and the location of the frequency of interest, the optimal loop

bandwidth can be different. The goal is to find the optimal loop bandwidth so that the total



noise contributed by all noise sources is minimum at the output of the PLL at the frequency

of interest.

We can choose an optimal loop bandwidth by varying those parameters. Enough

phase margin should be designed in to guarantee the stability of the loop. The actual

optimization requires a knowledge of the noise spectrum from each individual noise source.

This noise spectrum sometimes also depends on the choice of those parameters. Thus the

optimization is an iterative process.

3.3 Effect of the Wideband PLL on Receiver Architecture:

In a conventional superheterodyne receiver architecture, the received signal spectrum is

mixed down to baseband in two steps. During the first step, a HF synthesizer signal is mixed with the

RF signal, shifting the information signal to a fixed IF frequency. To do this, the RF synthesizer needs

to be tunable and the minimum frequency step must be smaller or equal to the channel spacing of

the standard. Then a fixed-frequency synthesizer at IF is mixed with the mixed-down version of the

received signal and finally shifts it to baseband.

Fig 9: Spectrum translation in the Wideband IF Double Conversion Receiver Architecture[www.springer.com]



With the wideband PLL architecture, it is possible to obtain a good spectral purity

with a noisy on-chip resonator as the VCO. But in order to have a stable loop, the reference

frequency must be larger than the loop bandwidth if integer frequency division is assumed.

This means the frequency step of a wideband PLL is large. In cellular applications, the

required frequency step is the reference frequency must be larger than the loop bandwidth if

integer frequency division is assumed. This means the frequency step of a wideband PLL is

large. In cellular applications, the required frequency step is usually very small. For example,

GSM has channel spacing of 200kHz. The wideband PLL based frequency synthesizer cannot

produce frequencies with a step of 200kHz because the loop bandwidth may be in the MHz

range and the reference frequency may be in tens of MHz range.

To solve this problem, a Wideband IF Double Conversion receiver architecture is proposed.

In this architecture, the entire signal band at RF is mixed down to the IF with a fixed RF

frequency synthesizer, and a variable frequency synthesizer at IF is used to tune the desired

channel from IF to the baseband. The IF synthesizer can tune the channels and still achieve

low phase noise because it is generating outputs at lower frequencies.



Chapter 4

Design Techniques for Low Noise Synthesizers

4.1 Introduction

A low-noise VCO is crucial in achieving a high performance frequency synthesizer.

The phase/frequency detector, loop filter, and frequency divider are also important in

realizing a high performance frequency synthesizer. The noise from the PFD and frequency

divider is multiplied by the divider ratio at the output of the PLL. When a wideband PLL is

used, the divider ratio may be reduced. However, because the loop bandwidth is very wide,

noise is not suppressed until the frequency is above the loop bandwidth, which is usually

above the frequency of interest. A low-noise latch clocked by the VCO can be placed at the

divider output so that the noise from the divider does not contribute at the output of the

PLL[6]. The noise from loop filter also has a peak gain depending on the VCO gain and loop

bandwidth.

4.2 Low-Noise Integrated VCO Design:

There are basically two types of VCO, tuned and untuned. Untuned oscillators have

inferior spectral purity compared to tuned oscillator for the same power consumption. The

performance of a tuned oscillator depends on the quality factor Q of the tuned element. A

typical example of an untuned oscillator is a ring oscillator[7]. It consists of n inverters in a

ring as shown in fig .

Fig : Block diagram of a ring oscillator[ring oscillator by mandel]



The end of the ring is 180o out of phase from the beginning of the ring. The logic

level propagates through the ring and there are no stable DC points. If each inverter stage has

a delay of tp, then the oscillation period is 2Ntp and the oscillation frequency is 1/2Ntp. The

most attractive feature of a ring oscillator is that it is fully integrable because of its digital-

like building blocks. It also has a wide tuning range. A frequency tuning range of 2:1 is easy

to obtain. But for a given level of power consumption, it has worse spectral purity.

Fig : Tuned oscillator model[www.circuitstoday.com]

A tuned oscillator can be modeled as a gain stage with a bandpass filter in the

feedback path as shown in Fig. It has lower phase noise because of the bandpass

characteristics of the feedback loop. In this context, we interpret the Q factor as the ratio of

the carrier frequency to the 3-dB bandwidth of the bandpass filter. The larger the Q is, the

better the output spectral purity. The tuned element is usually a passive resonator, such as an

LC tank, but these resonators are not integrable. Recently, on-chip inductors have been the

focus of many research efforts. The simplest way to realize such elements is the planar spiral

inductor, implemented with the metal layers available in any standard process. A suspended

inductor is a spiral inductor with its underlying substrate etched away. Bond wires have also

been used as inductors. The Q factor of the spiral inductor has been reported to be from 3 to

20, while bond wires have a Q factor of about 50. An on-chip varactor can be implemented

with the p+/nwell junction also available in standard process. The series resistance of the

junction can be minimized by minimizing the distance between the junctions, which is

limited by the available technology. In 0.35µm CMOS technology, the minimum distance is

0.35µm and the quality factor ranges from 10 to 20 at GHz frequencies.



4.3 Prototype Design:

A prototype based on the wideband PLL architecture was fabricated in a 0.35µm 2-

poly 5-metal CMOS process, intended as the RF synthesizer or Local oscillator a 1.8GHz

DCS1800/DECT transceiver using a wideband IF double-conversion architecture. For many

applications transceiver integration levels will be such that the receiver path, transmit path,

the complete synthesizer, and perhaps the RF power amplifier will coexist on a single

integrated circuit, along with a significant amount of A/D conversion and baseband

processing. This in turn requires the synthesizer maintain its phase noise and spurious tone

performance in the presence of components which deliver significant current and voltage

perturbations to both the substrate GND and supply. Fully differential implementation of the

complete PLL path is important for this reason. This prototype is implemented as a wideband

PLL based frequency synthesizer that is fully differential and fully integrated.

Fig : PLL block diagram

Fig shows the block diagram of the prototype. Each block has differential input and

differential output. The VCO is differentially controlled and the low-noise buffer is

differentially clocked.

4.3.1 Frequency Plan:

A good frequency plan is crucial to achieving all the specifications of different

standards, with a minimal amount of hardware and power consumption. The frequency plan

determines how the frequency translation of the carrier is performed in both the receive and

transmit paths. Therefore, the frequency plan determines the amount of hardware and power

it takes to generate the reference frequency with the frequency synthesizer and has a

significant impact on the overall synthesizer performance, namely, phase noise, spurious



tones and the required power consumption. The first design choice is the reference frequency.

It is desirable to develop a frequency plan where only one external crystal reference oscillator

is used.

The phase noise performance of the external crystal oscillator also influences the

choice of the reference frequency. Currently, the available crystal oscillators on the market

below 200MHz typically have a phase noise level below -145dBc/Hz at 50kHz offset

frequency. With a low phase noise option added to the crystal oscillator a phase noise

performance of -160dBc/Hz at 50kHz offset frequency may be obtained.

When DECT and DCS1800 are the target applications, a reference frequency that is a

multiple of 1.728MHz (channel spacing of DECT) and a multiple of 0.2MHz is needed. The

minimum value of such frequencies is 43.2MHz. If a 43.2MHz reference is used, the

frequency step of the RF synthesizer or LO1 is 43.2MHz and the minimum IF range that LO2

must be able to generate is 43.2MHz. The phase noise of the crystal oscillator and phase

detector and the divider is amplified by N, e.g., 31dB. With a 31dB noise enhancement from

the divider it is virtually impossible to meet the phase noise requirement for cellular

applications using a wideband PLL with an integrated VCO. Therefore, the crystal reference

frequency is chosen as 86.4MHz. With an 86.4MHz crystal reference frequency, the divider

ratio N is significantly reduced from 36 to 16 with a 400MHz IF. If the divider ratio is

reduced to 16, the noise amplification of the crystal oscillator, phase detector, and dividers

are reduced to 24dB, making it possible to implement a wide band PLL for the first local

oscillator (LO1) using an external low phase noise crystal oscillator.

The narrow-band PLL approach is used for the IF synthesizer or LO2 to suppress the

spurious tones generated by the loop. Therefore, with a narrow loop bandwidth, the phase

noise from the crystal oscillator, the phase detector and the divider will also be suppressed by

the loop filter at the output of the LO2 PLL. The overall phase noise profile of LO2 outside

the loop bandwidth is dominated by the VCO. However, the phase noise requirements of the

VCO for LO2 is relaxed by 12dB because the VCO output is divided by 4 to obtain the IF5.2

Prototype Design 76 frequency. The required tuning range of LO2 can be approximated as

the crystal reference frequency divided by the IF frequency. For an 80MHz crystal reference

frequency and a 400MHz IF frequency, the tuning range is about 20%. Only one external

crystal reference is needed. The overlap of the IF range for both standards makes it possible.



Conclusion

The main points of note are:

Among several frequency synthesizer architectures, e.g., DDFS, narrow band PLL,

Fractional-N PLL, and wideband PLL, the wideband PLL is the most amenable to

integration while still capable of high performance. In this architecture, the noise

contribution from the VCO is suppressed within the loop bandwidth. This allows a

relative noisy on-chip VCO to be used.

Because noise from the VCO is suppressed in wideband PLL architectures, other

noise sources become more important in the overall synthesizer performance. Noise

from the crystal oscillator reference, buffer, and phase/frequency detector become the

most important contributors within the loop bandwidth and are referred to the output

enhanced in effect by the divider ratio N.

Noise from the charge pump and loop filter is amplified by the VCO gain around the

loop bandwidth. For an integrated wideband PLL, the VCO gain is usually large

because of the limited control voltage range and large frequency range required by the

application. Thus the charge pump and loop filter are significant noise contributors at

the offset frequency around the loop bandwidth.

For many applications, transceiver integration levels will be such that the receiver

path, transmit path, the complete synthesizer, and perhaps the RF power amplifier will

coexist on a single integrated circuit, along with a significant amount of A/D

conversion and baseband processing. This in turn requires the synthesizer maintain its

phase noise and spurious tone performance in the presence of components which

deliver significant current and voltage perturbations to both the substrate GND and

supply. Fully differential implementation of the complete PLL path is important for

this reason.

A differentially-controlled VCO with differential outputs is proposed to realize the

fully differential PLL.

A low-noise charge pump with active loop filter is proposed to minimize spurious

tones due to the frequency comparison process and to maximize the frequency tuning

range of VCO.

A low-noise buffer clocked by the VCO is proposed to remove noise from the

frequency divider.



Reference

[1] J. C. Rudell, J. J. Ou, T. Cho, G. Chien, F. Brianti, J. A. Weldon and P. R. Gray, "A 1.9GHz Wide-Band IF Double Conversion CMOS Receiver for Cordless Telephone Applications," IEEE J. of Solid-State Circuits, vol. 32, no. 12, pp. 2701-2088, December 1997.

[2] Kroupa, venceslav F.(1973),Frequency synthesis: Theory, design and applications,

Griffin, ISBN 0-470-50855-8.

[3] D. Wolaver, Phase-Locked Loop Circuit Design, Prentice Hall, New Jersey, 1991.

[4] G. Chien, and P. R. Gray, “A 900-MHz Local Oscillator using a DLL-based Frequency Multiplier Technique for PCS Applications,” Digest of Technical Papers, International Solid-State Circuit Conference, pp. 202- 203, February 2000.

[5] B. Razavi, “A Study of Phase Noise in CMOS Oscillators,” IEEE J. Solid State Circuits, vol. 31, no. 3, pp. 331-343, March 1996.

[6] F. M. Gardner, “Charge-Pump Phase-Locked Loops,” IEEE Transactions On. Communications, vol. COM-28, pp. 1849-1858, November 1980.

[7] T. C. Weigandt, B. Kim, and P. R. Gray, “Analysis of Timing Jitter in CMOS Ring Oscillator,” Proceedings of the International Symposium on Circuits and Systems, June 1994.




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