SerDes Presentation

8/17/2019 SerDes Presentation

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Presented By:-

Mohit Singh Choudhary

M.Tech. Communication and Signal Processing

Discipline of Electrical Engineering

IIT Indore

IIT-Indore | EE 799 | M.Tech. Project Stage 1

Guided By:-

Dr. Santosh Kum

Assistant Profes

Discipline of Ele

IIT Indore

CML-SerDes


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IIT-Indore |

Contents

Introduction

Motivation

Literature Review

Implementation

Application

Future Work

References


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Motivation

Parallel Interconnections• Large I/O Pins

• More Power consumed

•

Problem in meeting timing requirement• On Chip-area is more

Sender Receiver

IIT-Indore |

David Robert Stauffer, 2008. High Speed Serdes Devices and Applications. 2009 Edition. Springer

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Motivation

Large Distance Transmission• Infeasible to transmit parallel data to a large distance.

IIT-Indore |


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Introduction

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SerDes ( Serializer and Deserializer)• Multiplexing bit data to bit of interconnect and at receiver demultiplexing

interconnect to bit data(< ).

Serializer Deserializer /


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Introduction

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SerDes

Types of SerDes on the basis of design techniques.

Introduction

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Introduction

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Serialization• Serializer uses mux to convert parallel data into serial output.

Safwat, Sally; Hussein, E.E.; Ghoneima, M.; Ismail, Y., "A 12Gbps all digital low power SerDes transceiver for on-chip netwo

(ISCAS), 2011 IEEE International Symposium, pp.1419-1422, 15-18 May 2011

Introduction

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Introduction

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Deserialization• Deserializer uses DFF to deserialize input bits.

DFF DFF DFF DFF DFF DFF DF

Introduction

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Introduction

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CML (Current Mode Logic)• Current mode logic provides true differential operation, low noise level and no

immunity with low dynamic power dissipation.

− = ≤ ,

1.2

1.2

0

0.7

Jaiswal, A.; Walk, D.; Yuan Fang; Hofmann, K., "Low-power high-speed on-chip asynchronous Wave-pipelined CML SerDes,

(SOCC), 2014 27th IEEE International , pp.5-10, 2-5 Sept. 2014

Introduction

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Literature Review

IIT-Indore |

1. Safwat, Sally; Hussein, E.E.; Ghoneima, M.; Ismail, Y., "A 12Gbps all digital low power SerDes transceiver for on-chip net

and Systems (ISCAS), 2011 IEEE International Symposium, pp.1419-1422, 15-18 May 2011.

2. Hussein, Ezz El-Din; Safwat, Sally; Ghoneima, M.; Ismail, Y., "A 16Gbps low power self-t imed SerDes transceiver for mult

in Circuits and Systems (ISCAS), 2012 IEEE International Symposium, pp.1660-1663, 20-23 May 2012

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DETFF

DETFF

DETFF

DETFF

DETFF

DETFF

DETFF

VDD/2

"1"

VDD

0

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Literature Review

IIT-Indore |



a). Serializer b). Deserializer

Literature Review

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Literature Review

IIT-Indore |

Tondo, D.F.; Lopez, R.R., "A low-power, high-speed CMOS/CML 16:1 serializer," in Micro-Nanoelectronics, Technology and A

Argentine School of Micro-Nanoelectronics, Technology and Application, pp.81-86, 1-2 Oct. 2009

Serializer Architecture

Literature Review

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Implementation

IIT-Indore |

Serializer• We have implemented serializer using CML.

• Input CMOS data is converted into CML.

• Then CML mux is used to serialize data.

• CML serialized output is converted back into CMOS for transmission.

CMOS to CML MUX CML to C



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Implementation

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Serializer• Serializer is implemented in 65nm UMC CMOS technology.

Implementation

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Implementation

IIT-Indore |

Serializer• Serialization we got at 16.64Gbps speed.

Implementation

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Implementation

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Deserializer• At the receiver deserialization is done using two parallel chain of DFF.

• Half clock is used and bits are shifted at both edges

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DFF DFF DFF DFF

DFF DFF DFF DFF

Implementation

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Implementation

IIT-Indore |

Deserializer• Deserializer we have implemented with the help of CML DFF which is build us

latch.

CML Latch



Implementation

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Implementation

IIT-Indore |

Deserializer• Deserializer is implemented in 65nm UMC CMOS technology.

Implementation

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Implementation

Implementation


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Implementation

IIT-Indore |

Results

Implementation

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() (℃) −

1.08 125 11.49 / 15.36 /

1.2 27 12.67 / 16.64 /

ff 1.32 −45 13.75 / 16.96 /

ℎ ℎ () ()

− [4] 65 16 18.1 − [2] 65 12.67 14.3

CMOS − CML[5] 45/65 10 50/106

ℎ 65 16.64 9.29

PVT Corners of various SerDes techniques

Comparison of various SerDes techniques

Submitted: Mohit Singh Choudhary, Mahesh Kumawat, Pramod Kumar Bharti and Dr. S. K. Vishvakarna, “Power Optimized

CML SerDes Transceiver Design with Process Corner Variation” IET Electronics Letter

Application


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Application

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Application• Telecom wireless communication

• In video transmission (FlatLink)

• Transceiver Devices

• Telecom Switching Applications

• 8b/10b SerDes are used in Ethernet, Fiber optics, InfiniBand

Dave Lewis, “SerDes Architectures and Application”, National Semiconductor Corporation

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Future work


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Future work

IIT-Indore |

Dynamic CML• Reduced swing logic style that reduces both gate and interconnect power diss

• DyCML circuits combines the advantages of CML with those of dynamic logic f

achieve high performance at a low-voltage with low-power dissipation.

Asynchronous Circuits• Asynchronous circuits since does not require clock thus saves lot of power con

oscillators and CDR.

Encoding• Serial data can be encoded to 3-level, 8b/10b etc so that speed can be increas

1 . Allam, M.W.; Elmasry, M.I., "Dynamic current mode logic (DyCML): a new low-power high-performance logic style," in S

Journal of , vol.36, no.3, pp.550-558, Mar 2001.

2. Jaiswal, A.; Walk, D.; Yuan Fang; Hofmann, K., "Low-power high-speed on-chip asynchronous Wave-pipelined CML SerD

Conference (SOCC), 2014 27th IEEE International , pp.5-10, 2-5 Sept. 2014.

3. Hussein, Ezz El-Din; Safwat, Sally; Ghoneima, M.; Ismail, Y., "A 16Gbps low power self-timed SerDes transceiver for mul

in Circuits and Systems (ISCAS), 2012 IEEE International Symposium, pp.1660-1663, 20-23 May 2012.

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References


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References

IIT-Indore |

References[1]. David Robert Stauffer, 2008. High Speed Serdes Devices and Applications. 200

Springer

[2]. Jaiswal, A.; Walk, D.; Yuan Fang; Hofmann, K., "Low-power high-speed on-chip

asynchronous Wave-pipelined CML SerDes," in System-on-Chip Conference (SOCC27th IEEE International , pp.5-10, 2-5 Sept. 2014

[3]. Safwat, Sally; Hussein, E.E.; Ghoneima, M.; Ismail, Y., "A 12Gbps all digital low

SerDes transceiver for on-chip networking," in Circuits and Systems (ISCAS), 2011

International Symposium on , pp.1419-1422, 15-18 May 2011

[4]. Hussein, Ezz El-Din; Safwat, Sally; Ghoneima, M.; Ismail, Y., "A 16Gbps low po

timed SerDes transceiver for multi-core communication," in Circuits and Systems

2012 IEEE International Symposium on, pp.1660-1663, 20-23 May 2012[5]. Tondo, D.F.; Lopez, R.R., "A low-power, high-speed CMOS/CML 16:1 serializer,

Nanoelectronics, Technology and Applications, 2009. EAMTA 2009. Argentine Sch

of Micro-Nanoelectronics, Technology and Application, pp.81-86, 1-2 Oct. 2009

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Thanks

Documents

SerDes Presentation