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Microprocesslng and Micropmgramming32 (~.991) 539-540 539 North-Holland Pushed forward by the ever increasing number of transistors that may be assembled on a single chip special purpose processors have become available. Among them digital signal processors play an important role. Intended to evaluate algorithms with inherent parallelism and possible asynchronous data flow, the programming of these processors needs new languages adapted to describe algo- rithms of this kind. There are numerous new fields of appl/cafions for processors of this kind i.e. speech synthesis and recognition, where this parallelism may be exploited in algorithms, or in alguritluns for finite impulse response fdter systems. According to an algorithm a special DSP-chip may be designed with an optimal architecture for this purpose. Any such design needs careful simulation before frozen into silicon, and this should be supported by suitable software took. The four papers in this session bring contri- butions for the fields mentioned above: The first paper is "An Applicative Real-Time Language for DSP-Prograw~ning Supporting AsyI~- chronous Data-Flow Concepts" by M. Freericks and A. Knoll from Technische Universitiit Berlin, G e ~ y the second paper deals with algodLhms for speech recognition "Temporal Control Improvement of Hidden Marker Models for Amomafic Speech Recognition" by Christine Dours-Senac from Laboratory IRIT URA-CNRS, University Paul Sabefier, Toulouse Cedex, France a third paper describes an array procvssor "Array Processor for LS FIR Sys~m Identification" Its authors are S.S. Nikola/dis from Dept° of Elec~cal Engineering, University of Pa~'as, Greece O.G. Koufopavlou from IBM Watson Res. Center, Yorktown Heights, USA S. Thcodefid/s from Dept. of Computer Engineering, University of PaStas, Greece and C.E. Gougs from Dept. of Electrical Enginee~ng, Un~versRy of Patras, Greece the tcuah paper to be presemeC~is on "DgP-Architecture Design ~v~th a Pe~- r,et-ba~d Simulator" by K. Raufiola and P. Jokita~o from ~"echnical Research Centre of Finland, O)flu, Finland

Session F1: Digital signal processing

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Page 1: Session F1: Digital signal processing

Microprocesslng and Micropmgramming 32 (~.991) 539-540 539 North-Holland

Pushed forward by the ever increasing number of transistors that may be assembled on a single chip special purpose processors have become available.

Among them digital signal processors play an important role.

Intended to evaluate algorithms with inherent parallelism and possible asynchronous data flow, the programming of these processors needs new languages adapted to describe algo- rithms of this kind.

There are numerous new fields of appl/cafions for processors of this kind i.e. speech synthesis and recognition, where this parallelism may be exploited in algorithms, or in alguritluns for finite impulse response fdter systems.

According to an algorithm a special DSP-chip may be designed with an optimal architecture for this purpose.

Any such design needs careful simulation before frozen into silicon, and this should be supported by suitable software took.

The four papers in this session bring contri- butions for the fields mentioned above:

The first paper is "An Applicative Real-Time Language for DSP-Prograw~ning Supporting AsyI~- chronous Data-Flow Concepts" by M. Freericks and A. Knoll from Technische Universitiit Berlin, G e ~ y

the second paper deals with algodLhms for speech recognition

"Temporal Control Improvement of Hidden Marker Models for Amomafic Speech Recognition" by Christine Dours-Senac from Laboratory IRIT URA-CNRS, University Paul Sabefier, Toulouse Cedex, France

a third paper describes an array procvssor "Array Processor for LS FIR Sys~m Identification" Its authors are S.S. Nikola/dis from Dept° of Elec~cal Engineering, University of Pa~'as, Greece O.G. Koufopavlou from IBM Watson Res. Center, Yorktown Heights, USA S. Thcodefid/s from Dept. of Computer Engineering, University of PaStas, Greece and C.E. Gougs from Dept. of Electrical Enginee~ng, Un~versRy of Patras, Greece

the tcuah paper to be presemeC~ is on "DgP-Architecture Design ~v~th a Pe~- r,et-ba~d Simulator" by K. Raufiola and P. Jokita~o from ~"echnical Research Centre of Finland, O)flu, Finland