1. An electronic system designed to perform a specific function
and is a combination of both hardware and software.
2. A system which is a combination of a generic hardware and a
general purpose operating system for executing a variety of
applications.
3. The non functional aspects that need to be addressed in
embedded system design.
4. A system that accept inputs from external world, process them
and give desired outputs. It produces changes in output in response
to the changes in the input (events).
5. A system that responds to requests or events in a known
amount of time.
6. They represent the relevant quality attributes related to the
ES when it is in the operational mode or online mode.
7. An important factor considered while designing an ES. Care
must be taken so that designed ES consumes less power and
dissipates less heat.
8. It is defined as the rate of production or operation of a
defined process over a stated period of time. 9. Protection of data
and application from unauthorized disclosure, from un authorized
modification and
unauthorized user.
10. It describes how much the designed system is flexible in its
hardware and software. 11. It checks whether the system can
function correctly in various environments and various platforms.
12. A silicon chip representing a Central Processing Unit (CPU),
which is capable of performing arithmetic as
well as logical operations according to a pre-defined set of
Instructions, which is specific to the
manufacturer.
13. It contains all the necessary functional blocks for
independent working. 14. It implement algorithms in hardware which
speeds up the execution. 15. It is used as replacement to
conventional general purpose logic chips. 16. It offers customers a
wide range of logic capacity, features, speed, and voltage
characteristics and these
devices can be re-configured to perform any number of functions
at any time.
17. It offers the highest amount of logic density, the most
features, and the highest performance. 18. It offers very
predictable timing characteristics and are therefore ideal for
critical control applications. 19. The major advantage of it is
that they are readily available in the market, cheap and a
developer can cut
down his/her development time to a great extend.
20. It incorporates a processor and on-chip peripherals,
demanded by the application requirement, program and data
memory.
21. It specifies the order in which the data is stored in the
memory by processor operations in a multi byte system
22. It is masked by creation of an enhancement or depletion mode
transistor through channel implant. 23. It is programmed
selectively burning the fuses according to the bit pattern to be
stored. 24. It stores the bit information by charging the floating
gate of an FET. 25. These chips include a chip erase mode and in
this mode they can be erased in a few milliseconds. 26. Memory that
stores information in an array of floating gate MOSFET transistors.
27. It is the data memory or working memory of the
controller/processor. 28. It is the fastest form of RAM available.
29. It stores data in the form of charge. 30. The memory and
battery are packed together in a single package. 31. It can be used
as an indicator for the status of various signals or situations.
32. It is used for displaying alpha numeric characters. 33. It
combines an LED and a photo-transistor in a single housing. 34. It
is widely used in robotics to convert applied dc voltage to
corresponding mechanical motion. 35. An electro mechanical device
which acts as dynamic path selectors for signals and power. 36. It
is a device for generating audio indications in embedded
application. 37. In embedded application it is generally used as
reset and start switch and pulse generator. 38. It refers to the
control algorithm or the configuration settings that an embedded
system developer dumps
into the code memory of the embedded system.
39. It is essential to ensure that the device is not operating
at a voltage level where the device is not guaranteed to operate,
during system power ON.
40. It prevents the processor/controller from unexpected program
execution behavior when the supply voltage to the
processor/controller falls below a specified voltage.
41. In embedded system it is responsible for generating the
precise clock for the processor 42. It is intended to function even
in the absence of power. 43. It is used for monitoring the firmware
execution. 44. Activated using PCO.0 45. Terminated by reset signal
only. 46. It is essential for communicating with various subsystems
of the embedded system and with the external
world.
47. It is a synchronous bi-directional half duplex two wire
serial interface bus. 48. It works on the principle of Shift
Register. 49. A communication interface where the start and stop of
communication is indicated through inserting
special bits in the data stream.
50. It is capable of carrying power to the slave device apart
from carrying the signals. 51. it is normally used for
communicating with peripheral devices which are memory mapped to
the host of
the system.
52. It is a full duplex, wired, asynchronous serial
communication interface. 53. It is a wired high speed serial bus
for data communication which uses star topology. 54. A wired,
isochronous high speed serial communication bus. 55. it supports
point-point and point-to-multipoint communication, provided all
devices involved
a. in the communication are within the line of sight. 56. It
supports a theoretical maximum data rate of up to 1Mbps and a range
of approximately 30
a. feet for data communication. 57. It is intended for network
communication and it supports Internet Protocol based
Communication. 58. Low power, low cost, wireless network
communication protocol based on the IEEE 802.15.4-2006
standard.
59. It supports Internet Protocol (IP), Point to Point Protocol
(PPP) and X.25 protocols for communication. 60. It has a built in
JTAG debug port and on chip embedded ICE. 61. It is a hardware
component that preprocesses one of the input registers before it is
used by an instruction. 62. It is an on-chip bus used by ARM
processors. 63. It provides an overall increase in performance but
with a loss of predictable execution time. 64. The erasing and
writing of it is completely software controlled with no additional
hardware circuitry
required.
65. It is one of many subcategories of DRAM and can run at much
higher clock speeds than conventional memory.
66. It provides a programmable governing policy that allows
software to determine which peripheral or device can interrupt the
processor at any specific time by setting the appropriate bits in
the interrupt controller
registers.
67. It provides an infrastructure to control applications and
manage hardware system resources. 68. It provides a consistent
software interface to the peripherals on the hardware device. 69.
It takes the processor from the reset state to a state where the
operating system can run. 70. It tests the system by exercising the
hardware target to check if the target is in working order. 71. It
involves loading an image and handing control over to that image.
72. It provides guaranteed response times to events. 73. It is used
to calculate the address in ARM core processor. 74. For load and
store instructions it updates the address register before the core
reads or writes the next
register value from or to the next sequential memory
location.
75. It is the register where the core puts the return address
whenever it calls a subroutine. 76. The ARM core uses it to monitor
and control internal operations. 77. It contains the processor
mode, state, and interrupt mask bits. 78. It allows full read-write
access to the cpsr. 79. It is a special version of user mode that
allows full read-write access to the cpsr. 80. It suspends the
normal execution of sequential instructions and jump to a specific
location. 81. It controls whether or not the core will execute an
instruction. 82. It is a state when bits T and J are zero. 83. It
is a flag used to indicate overflow condition when ARM executes DSP
instructions. 84. It is the mechanism a RISC processor uses to
execute instructions.
