Simulated Annealing for Placement Problem to minimise the ...ags55111/doc/624/report.pdfSimulated Annealing Before we understand the Algorithm lets try to understand the Randomized

Simulated Annealing for Placement Problemto minimise the wire length

Ajay Sharma

2nd May 05

Contents

1 Algorithm 31.1 Definition of Algorithm . . . . . . . . . . . . . . . . . . . . . . 3

1.1.1 Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Simulated Annealing 42.1 Randomized Algorithm . . . . . . . . . . . . . . . . . . . . . . 42.2 Simulated Annealing . . . . . . . . . . . . . . . . . . . . . . . 4

2.2.1 Basic Iteration . . . . . . . . . . . . . . . . . . . . . . 62.2.2 Neighbours of the state . . . . . . . . . . . . . . . . . . 62.2.3 Transition Probability . . . . . . . . . . . . . . . . . . 62.2.4 Annealing schedule . . . . . . . . . . . . . . . . . . . . 62.2.5 PSEUDO CODE . . . . . . . . . . . . . . . . . . . . . 62.2.6 Parameters . . . . . . . . . . . . . . . . . . . . . . . . 72.2.7 State Neighbours . . . . . . . . . . . . . . . . . . . . . 72.2.8 Transition Probability . . . . . . . . . . . . . . . . . . 82.2.9 Classical Formula . . . . . . . . . . . . . . . . . . . . . 82.2.10 Annealing Schedule . . . . . . . . . . . . . . . . . . . . 8

3 C++ Based Implementation 93.1 BDNET File . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4 Circuit: Sample1 134.1 Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134.2 Initial Placement . . . . . . . . . . . . . . . . . . . . . . . . . 144.3 Final Placement . . . . . . . . . . . . . . . . . . . . . . . . . . 154.4 Cost Function Plot . . . . . . . . . . . . . . . . . . . . . . . . 164.5 VERILOG CODE . . . . . . . . . . . . . . . . . . . . . . . . . 164.6 BDNET NETLIST . . . . . . . . . . . . . . . . . . . . . . . . 16

1

5 Sample Circuit 2: 8 bit Full Adder with Register 205.1 Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205.2 Final Placement . . . . . . . . . . . . . . . . . . . . . . . . . . 215.3 Cost Function Plot . . . . . . . . . . . . . . . . . . . . . . . . 215.4 VERILOG CODE . . . . . . . . . . . . . . . . . . . . . . . . . 21

6 Sample Circuit 3 226.1 Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226.2 Final Placement . . . . . . . . . . . . . . . . . . . . . . . . . . 236.3 Cost Function Plot . . . . . . . . . . . . . . . . . . . . . . . . 236.4 VERILOG CODE . . . . . . . . . . . . . . . . . . . . . . . . . 23

7 Sample Circuit 4: ALU 247.1 Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247.2 Final Placement . . . . . . . . . . . . . . . . . . . . . . . . . . 247.3 Cost Function Plot . . . . . . . . . . . . . . . . . . . . . . . . 257.4 VERILOG CODE . . . . . . . . . . . . . . . . . . . . . . . . . 257.5 BDNET File . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

8 Sample Circuit 5: 8x8 Bit Multiplier 268.1 Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268.2 Final Placement . . . . . . . . . . . . . . . . . . . . . . . . . . 268.3 Cost Function Plot . . . . . . . . . . . . . . . . . . . . . . . . 278.4 VERILOG CODE . . . . . . . . . . . . . . . . . . . . . . . . . 278.5 BDNET File . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

9 Final Analysis 289.1 Cost Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289.2 Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

2

Chapter 1

Algorithm

1.1 Definition of Algorithm

A step by step procedure to solve any problem is called as Algorithm

1.1.1 Algorithm

An example of such an algorithm is Adding members of an array. The algo-rithm for such an example would be:

start

integer i;

integer result;

array S[n];

result = 0;

for (i=1;i<=n;i++)

result=result+ S[i];

return result;

end

We will talk about Simulated Annealing in detail and use it for solving VLSICAD problems.

3

Chapter 2

Simulated Annealing

Before we understand the Algorithm lets try to understand the Randomizedalgorithm.

2.1 Randomized Algorithm

A Randomized Algorithm is an algorithm uses random bits as an auxillaryinput to guide its behaviour, in the hope of achieving a good performance inthe ”average case”.

An Example of this would be finding ’a’ in an array of ’n’ elements giventhat half of them are ’a’s and half are ’b’s . The obvious approach is to lookfor all elements of array but that will take ’n/2’ operations. But at randomwe can find ’a’ at a much higher probability than other method.

Lets now begin with Simulated annealing.

2.2 Simulated Annealing

In Short ,Simulated Annealing(SA) is a generic probabilistic meta-algorithmfor the global optimization problem namely locating a good approximationto the global optimum of a given function in a large search space. By globaloptimum i mean selection from a domain that yeilds a highest value when aspecific function is given. For example the function : f(x)=-x2 +2, is definedover the real number axis and has the highest value when x=0, ie: f(x)=2.

4

The search space is the set of all posible solutions to the problems.The Simulated Annealing algorithm is written by S. Kirkpatrick, C.D.Gelatt

and M.P.Vecchi in 1983, and by V.Cerry in 1985.The inspiration comes from mettalurgy where we do a lot of annealing.

In annealing we heat a solid and do controlled cooling to increase the size ofthe crystals and reduce their defects. The heat causes the atoms to becomeunstuck from their initial positions and wander randomly through states ofhigher energy; slow cooling gives them chance to come to a state of lowerenergy than the initial one.

5

2.2.1 Basic Iteration

We decide between moving the system to the neighbouring state s’ from thestate s based on the probability that the system ultimately reaches the lowestpossible energy state.

We do it till we get the best possible solution or when the time bound isover or reources exausted.

2.2.2 Neighbours of the state

The neighbours of the state are specified by the user.

2.2.3 Transition Probability

Probability of making a transition is decided based on the function P(∆E,T)where ∆E=E(S’)-E(S) ..... T :- Temperature.

Sometimes we swap the system state from S to S’ evenif the next state isnot having lower energy level which means we donot stay at a false minimum.Where the neihbours are at high energy level but we still swap in the hopethat eventually we may reach a lower energy state. We see that as:Temp - 0P(∆E,T) —- 0 if ∆E = +ve ie: Increasing of the Temperature.P(∆E,T) —- 1 if ∆E = -ve ie: Decreasing Temperature.

For small values of T the system prefers to go downhill than uphill.When Time=0, the system is gready algorithm, ie: moves to the next

state iff the next state is of lower energy level. At higher Temperature coarseenergy variation cause system change and at lower temperature finer energyvariation cause system change.

2.2.4 Annealing schedule

Initially the system assumes the highest possible energy level and then it isgradually decreased.

2.2.5 PSEUDO CODE

1. S=S0 – Initial state ’S’ = S0 (state 0)

6

2. e=E(S) – Energy is equal to energy of the state

3. k=0 – step = 0 ie. initial step.

4. while k(less than)Kmax & e:- emax – Repeat the loop till max stepsand lowest possible energy.

5. sn:= neighbours(S) – this should generate randomly generated nigh-bour. Sn :- neighbour’s state.

6. en=E(Sn) – Energy is the nighbours energy. E(sn) is the energy of theneighbour state ..

7. if random() (lessthan) P(en -e,temp(K/Kmax) then – means randomcalls generates random values between [0,1] so check for change in en-ergy over the over the chahge in temperature.

8. s=sn; e=en ; – state is the next state , energy is the next state.

9. k=k+1 ; – step increase.

10. return S; – return the current state as output of the algorithm

2.2.6 Parameters

1. 1. State Space: The State machine or the perhaps the state.

2. 2. Neighbour selection method: Enumerating the next state candidate.

3. 3. Probability Transition Function: The probability of Transition.

4. 4. Annealing Schedule: Temperature decrease schedule.

Its more of an Art than Science.

2.2.7 State Neighbours

Choosing the neighbours is very critical, always swap adjacent neighboursstate not any arbitrary state.

Chances are more likely that energy increases when we swap any arbitrarystate, rather than adjacent swap.

More than that at Higher temperature coarser moves allowed and at lowertemperature narrower moves allowed.

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2.2.8 Transition Probability

It is not as critical as the neighbourhood graph provided follows the require-ment of SA.

2.2.9 Classical Formula

If ∆E = -ve (energy is reduced) then the probability of P(∆E,T) is ac-

cepted is ’1’ the move is accepted . Otherwise the Probability is = edeltaE

T .from metropolis-Hastings theorom used to generate samples from Maxwell’sBoltzman distribution.

2.2.10 Annealing Schedule

The initial temperature should be large enough so that probability of accept-ing uphill/downhill moves are same. At any random state , deltaE should beestimated .

The temperature should be finally decreased to 0 or nearly zero. Popularchoice is the Exponential schedule ie. temperature decrease by a fixed factor. Alpha¡1.

8

Chapter 3

C++ Based Implementation

The following is the program that i am working on . It has the following :

1. Input

(a) BDNET file

(b) No of iterations at each temperature

(c) No of Temperature points to try

2. Output

(a) Placement of the optimized Cells

(b) Plot of the Cost function

9

3.1 BDNET File

Netlist files are listed in this form. This is the sample BDNET ckt and theBDNET file is given below.

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MODEL sample:unplaced;

TECHNOLOGY scmos;

VIEWTYPE SYMBOLIC;

EDITWTYLE SYMBOLIC;

INPUT clk,a1;

OUTPUT z<1:0>;

SUPPLY Vdd;

GROUND GND;

INSTANCE "$OCTTOOLS/tech/scmos/msu/stdcell2_2/nanf251": physical NAME: "u1"

"GND!" : UNCONNECTED;

"Vdd!" : UNCONNECTED;

"O" : "n0";

"A1" : "a1";

INSTANCE "$OCTTOOLS/tech/scmos/msu/stdcell2_2/anf251": physical NAME: "u2"


11


"O" : "z0";

"A1" : "clk";

"B!" : "n0";

INSTANCE "$OCTTOOLS/tech/scmos/msu/stdcell2_2/anf251": physical NAME: "u3"



"O" : "z1";

"A1" : "n0";

"B!" : "clk";

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Chapter 4

Circuit: Sample1

We start with testing the circuits and finding the cost reduction and CPUtime required. The first circuit is the smallest and the last is the biggest.

These Tests are performed on the Test Computer with Linux OS/intel1.7GHZ Celeron/128 MB RAM/845 Chipset Motherboard.

4.1 Specification

1. Total Size : 14 Cells.

2. Total Nets : 17

3. Initial Cost : 29

4. Final Cost : 23,22,23

5. Initial temperature: 10000

6. Percent Reduction in Cost = 26 percent

7. Iteration = 150

8. Temperature Steps : 100

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4.2 Initial Placement

This is the initial plot and the wire length is marked on the nets. TotalLength is 29 initially.

14

4.3 Final Placement

This is the Final plot and the wire length is reduced from 29 to 23.

15

4.4 Cost Function Plot

4.5 VERILOG CODE

module sample2(A,B,C,F,G);

input A,B,C;

output F,G;

wire n1,n2,n3,n4,n5,n6,n7,n8,n9,n10,n11,n12;

not u1(n1,A);

not u2(n2,B);

or u3(n3,n1,n2);

and u4(n4,A,n3);

and u5(n5,n3,B);

or u6(n6,n4,n5);

not u7(n7,n6);

not u8(n8,C);

or u9(n9,n7,n8);

and u10(n10,n6,n9);

and u11(n11,n9,C);

and u12(n12,n9,n3);

or u13(F,n10,n11);

not u14(G,n12);

endmodule

4.6 BDNET NETLIST

MODEL "sample":unplaced;

16

TECHNOLOGY scmos;

VIEWTYPE SYMBOLIC;

EDITSTYLE SYMBOLIC;

OUTPUT "F" : "F";

OUTPUT "G" : "G";

INPUT "A" : "A";

INPUT "B" : "B";

INPUT "C" : "C";

INSTANCE "$OCTTOOLS/tech/scmos/msu/stdcell2_2/invf101":physical NAME = "U1"



"O" : "n1";

"A1" : "A";




"O" : "n2";

"A1" : "B";

INSTANCE "$OCTTOOLS/tech/scmos/msu/stdcell2_2/norf201":physical NAME = "U3"



"O" : "n3";

"A1" : "n1";

"B1" : "n2";

INSTANCE "$OCTTOOLS/tech/scmos/msu/stdcell2_2/blf00001":physical NAME = "U4"



"O" : "n4";

"A1" : "A";

"B1" : "n3";



17


"O" : "n5";

"A1" : "n3";

"B1" : "B";




"O" : "n6";

"A1" : "n4";

"B1" : "n5";




"O" : "n7";

"A1" : "n6";




"O" : "n8";

"A1" : "C";




"O" : "n9";

"A1" : "n7";

"B1" : "n8";




"O" : "n10";

"A1" : "n6";

"B1" : "n9";

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"O" : "n11";

"A1" : "n9";

"B1" : "C";




"O" : "n12";

"A1" : "n9";

"B1" : "n3";




"O" : "nF";

"A1" : "n10";

"B1" : "n11";




"O" : "G";

"A1" : "n12";

ENDMODEL;

19

Chapter 5

Sample Circuit 2: 8 bit FullAdder with Register

5.1 Specification


2. Total Nets : 91


4. Final Cost : 154,158,153



7. Iteration = 150


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5.2 Final Placement

x reg1 reg2 u32 u51 u25 u15 xu34 u14 u35 u10 u52 u48 u47 xu20 u27 u36 u50 u53 u7 u30 reg3x u5 u49 u41 u40 u55 u23 u54u19 u57 u38 u13 u39 u56 u45 u16u26 u58 u37 u21 u28 reg0 u46 xu33 reg6 reg7 u4 reg5 u62 reg4 u59u8 u12 u24 u31 u63 u44 u29 u66u67 u68 u18 u65 u9 u17 u22 u65u11 u61 x u60 u64 u43 u42 x


5.4 VERILOG CODE

The verilog Code can be found at the website : www.csun.edu/ ags55111.Its too bog to be included in the project report.

21

Chapter 6

Sample Circuit 3

6.1 Specification


2. Total Nets : 114


4. Final Cost : 138,144,140



7. Iteration = 150


22

6.2 Final Placement

u8 u6 u15 u5 u11 u18 u12 u2 u13u16 u7 u21 u4 x u24 u38 u40 u1u22 u20 u25 u14 u3 u37 u47 u48 u39x u26 u28 u56 u27 u60 u71 u61 u39u19 u33 x u57 u23 u82 u76 u70 u58u34 u45 u55 u69 u17 u88 u83 u62 u59u31 u54 u68 u75 u9 u91 x u63 u36u44 u32 u80 u81 u10 u89 u84 u72 u46u30 u29 u43 u87 u90 u92 u85 u77 u41u52 u51 u50 u78 u86 x u42 u49 u41u53 u67 u66 u74 u79 x u65 u73 u64


6.4 VERILOG CODE

The verilog Code can be found at the website : www.csun.edu/ ags55111.Its too bog to be included in the project report.

23

Chapter 7

Sample Circuit 4: ALU

7.1 Specification


2. Total Nets : 400


4. Final Cost : 1633,1624,1688



7. Iteration = 150


7.2 Final Placement

The final placement file is the alu.dat and can be found at www.csun.edu/ ags55111It again is too big to be included in the project report.

24


7.4 VERILOG CODE

The verilog Code can be found at the website : www.csun.edu/ ags55111.Its too big to be included in the project report.

7.5 BDNET File

Can be found at www.csun.edu/ ags55111

25

Chapter 8

Sample Circuit 5: 8x8 BitMultiplier

8.1 Specification


2. Total Nets : 457


4. Final Cost : 1366,1409,1324



7. Iteration = 150


8.2 Final Placement

The final placement file is the alu.dat and can be found at www.csun.edu/ ags55111It again is too big to be included in the project report.

26


8.4 VERILOG CODE

The verilog Code can be found at the website : www.csun.edu/ ags55111.Its too big to be included in the project report.

8.5 BDNET File

Can be found at www.csun.edu/ ags55111

27

Chapter 9

Final Analysis

I have used the Pentium Celeron 1.7GHz/Linux/128 RAM/845 chipset com-puter for all the test simulation. The summary of results is as follows:Ckt 1 2 3 4 5Cells 14 74 93 439 441Nets 17 91 114 480 441Time 1 2 2 20 21Gain 26 225 189 355 420

9.1 Cost Gain

I have tried to analyse the algorithm with various sizes of ckt . I observethat as the no:of cells increase the cost gain also increase.

28

9.2 Speed

The Speed required is calculated by taking smaller ckts first and then biggerckts. The time required for the algorithm increases as the size of the cktincreases.

Lets assume the Pentium 4 processor has 55 million transistors and eachtransistor takes 1 cell then in that case my algorithm took 21 seconds for 441cells. So for 55x106 cells it will take 30 days.

Consider this: 55000000x

= 44121

sox = 55000000∗21

441

x = 2619047.6 secondsx = 727 hoursx = 30 days

29

30

Documents

Simulated Annealing for Placement Problem to minimise the ...ags55111/doc/624/report.pdfSimulated Annealing Before we understand the Algorithm lets try to understand the Randomized