10
IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. IA-19, NO. 4, JULY/AUGUST 1983 6 Snubber Circuit for High-Power Gate Turn-Off Thyristors HIROMICHI OHASHI, MEMBER, IEEE Abstract-A snubber circuit calculation model for high-power gate turn-off thyristors (GTO's) was proposed to consider problems which must be investigated for snubber circuit design. The calculated GTO waveforms showed good agreement with experimental values obtained by a GTO chopper circuit for both a resistive and inductive load case. Problems to be considered for the snubber design, such as voltage spike reduction, maximum GTO anode current, and switching power, were discussed using the calculation model. Design criteria for the snubber circuit were successfully established, introducing allowable maximum voltage spikes to avoid failures due to current crowding during the GTO interval and excessive voltage applied over maximum blocking voltage rating. Minimum switching power loss dissipated inside the GTO and the snubber resistor was also calculated, taking the design criteria into consideration. As results of the calculations, the snubber circuit stray inductance was found to play an important role in optimizing the minimum switching power loss, especially for large anode current and large stray inductance in a main circuit. sirable to include more device characteristics and circuit pa- rameters for the GTO snubber circuit design consideration. This paper proposes a GTO snubber circuit calculation model and considers problems which must be investigated in the snubber circuit design. II. CALCULATION MODEL A. Fundamental Equations A simple GTO chopper circuit, shown in Fig. 1, was used for the GTO snubber circuit study. Anode voltage and current waveforms that result in such a circuit are similar to those that result in most GTO power conversion circuits as well. Applying Kirchihhoffs law to the circuit in Fig. 1, the fol- lowing fundamental equations are obtained: I. INTRODUCTION IT IS generally necessary to connect a snubber circuit across a power rectifier or thyristor to absorb the energy associated with the recovery current in the devices and limit the resulting voltage spike and rate of rise dv/dt. A snubber circuit also plays an important role in determining the full capability of a high-power gate turn-off thyristor (GTO). Although many studies have been made on the snubber circuit for a conven- tional rectifier or thyristor [1], [21, it is difficult to apply the results of these studies directly to GTO snubber circuit analy- sis because of the following. 1) Voltage polarities across the devices during the turn- off interval are opposite because of the differences in turn-off mechanisms, that is, forced commutation and the GTO method. 2) In addition to the purposes already mentioned, the GTO snubber circuit has another important purpose: to protect GTO's from failure due to current crowding during the GTO interval. While a high-power GTO has been regarded as a new switch- ing device for many power conversion apparatuses, almost no attempt has been made to analyze the GTO snubber circuit, except the study made by Steigerwald, who discussed analyti- cally the voltage spike and rate of rise during the GTO interval and related the energy dissipation in the snubber circuit to di/dt and dv/dt ratings for GTO's [3]. However, it seems de- Paper IPCSD 83-8, approved by the Static Power Converter Com- mittee of the IEEE Industry Applications Society for publication in this TRANSACTIONS. Manuscript released for publication February 1, 1983. The author is with Electron Devices Laboratory, Toshiba Research and Development Center, Toshiba Corporation, 1, Komukai Toshiba cho, Saiwai-Ku, Kawasaki 210, Japan. di EB =ez+Lsl * -+ea dt di1 el = - dil+ R - i, dt ea =S2 dt± Reff ' is-L di+ (1) (2) (3) (4) ii = la ± Is ± Id (5) R5*.Rd eR --Rs + Rd (6) Here, the diode D, in the snubber circuit is divided into two parts, i.e., an ideal diode and an effective resistance Rd. The Reff value is an equivalent resistance in the snubber circuit which consists of Rs and Rd connected in parallel. The Qs value is a charge in the snubber capacitance Cs and is written as dQs dt s Substituting (3) and (5) into (1) yields ~di Q (L,±LS2) -s+Reff i~s + dt Cs dia =EB-Ls, *- --el. dt (7) (8) Anode voltage ea is given by solving differential equations 0093-9994/83/0700-0655$0l .00 © 1983 IEEE 655 I =ia~+is

Snubber Circuit for High-Power Gate Turn-Off Thyristors

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Page 1: Snubber Circuit for High-Power Gate Turn-Off Thyristors

IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. IA-19, NO. 4, JULY/AUGUST 1983 6

Snubber Circuit for High-Power Gate Turn-Off ThyristorsHIROMICHI OHASHI, MEMBER, IEEE

Abstract-A snubber circuit calculation model for high-power gateturn-off thyristors (GTO's) was proposed to consider problems whichmust be investigated for snubber circuit design. The calculated GTOwaveforms showed good agreement with experimental values obtainedby a GTO chopper circuit for both a resistive and inductive load case.Problems to be considered for the snubber design, such as voltagespike reduction, maximum GTO anode current, and switching power,were discussed using the calculation model. Design criteria for thesnubber circuit were successfully established, introducing allowablemaximum voltage spikes to avoid failures due to current crowdingduring the GTO interval and excessive voltage applied over maximumblocking voltage rating. Minimum switching power loss dissipatedinside the GTO and the snubber resistor was also calculated, takingthe design criteria into consideration. As results of the calculations,the snubber circuit stray inductance was found to play an importantrole in optimizing the minimum switching power loss, especially forlarge anode current and large stray inductance in a main circuit.

sirable to include more device characteristics and circuit pa-rameters for the GTO snubber circuit design consideration.This paper proposes a GTO snubber circuit calculation modeland considers problems which must be investigated in thesnubber circuit design.

II. CALCULATION MODEL

A. Fundamental EquationsA simple GTO chopper circuit, shown in Fig. 1, was used for

the GTO snubber circuit study. Anode voltage and currentwaveforms that result in such a circuit are similar to those thatresult in most GTO power conversion circuits as well.

Applying Kirchihhoffs law to the circuit in Fig. 1, the fol-lowing fundamental equations are obtained:

I. INTRODUCTIONIT IS generally necessary to connect a snubber circuit across

a power rectifier or thyristor to absorb the energy associatedwith the recovery current in the devices and limit the resultingvoltage spike and rate of rise dv/dt. A snubber circuit alsoplays an important role in determining the full capability of ahigh-power gate turn-off thyristor (GTO). Although manystudies have been made on the snubber circuit for a conven-tional rectifier or thyristor [1], [21, it is difficult to apply theresults of these studies directly to GTO snubber circuit analy-sis because of the following.

1) Voltage polarities across the devices during the turn-off interval are opposite because of the differences in turn-offmechanisms, that is, forced commutation and the GTO method.

2) In addition to the purposes already mentioned, the GTOsnubber circuit has another important purpose: to protectGTO's from failure due to current crowding during the GTOinterval.

While a high-power GTO has been regarded as a new switch-ing device for many power conversion apparatuses, almost noattempt has been made to analyze the GTO snubber circuit,except the study made by Steigerwald, who discussed analyti-cally the voltage spike and rate of rise during the GTO intervaland related the energy dissipation in the snubber circuit todi/dt and dv/dt ratings for GTO's [3]. However, it seems de-

Paper IPCSD 83-8, approved by the Static Power Converter Com-mittee of the IEEE Industry Applications Society for publication inthis TRANSACTIONS. Manuscript released for publication February 1,1983.

The author is with Electron Devices Laboratory, Toshiba Researchand Development Center, Toshiba Corporation, 1, Komukai Toshibacho, Saiwai-Ku, Kawasaki 210, Japan.

diEB =ez+Lsl * -+eadt

di1el = - dil+ R - i,dt

ea =S2 dt± Reff ' is-Ldi+

(1)

(2)

(3)

(4)ii = la ± Is± Id

(5)

R5*.RdeR --Rs + Rd (6)

Here, the diode D, in the snubber circuit is divided into twoparts, i.e., an ideal diode and an effective resistance Rd. TheReff value is an equivalent resistance in the snubber circuitwhich consists of Rs and Rd connected in parallel. The Qsvalue is a charge in the snubber capacitance Cs and is written as

dQsdt s

Substituting (3) and (5) into (1) yields

~di Q(L,±LS2)-s+Reff i~s +dt Cs

dia=EB-Ls, *---el.dt

(7)

(8)

Anode voltage ea is given by solving differential equations

0093-9994/83/0700-0655$0l .00 © 1983 IEEE

655

I =ia~+is

Page 2: Snubber Circuit for High-Power Gate Turn-Off Thyristors

IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. IA-19, NO. 4, JULY/AUGUST 1983

Fig. 1. GTO chopper circuit used for snubber circuit investigations.

I t=o

V2e.

a~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~stE

i -s t,-

the initiation of negative gate current to the time, t = t3 inFig. 2, at which the voltage across inductance L becomes largerthan the voltage across resistance R. Since el > 0 during thisperiod, the Df is reverse biased, and the current (id = Ird)through the Df is negligibly small. Thus (4) and (5) are simpli-fied, as follows:

11 =1 =1a ±s

Using (2) and (1 1), (8) is changed into

(L +Ls1 +LS2) - ds +(R±Reff)* is+dt CffCs

dia-EB R ia (L±+Ls,)

dt

(11)

(12)

2) Period B (el < 0): Period B is defined as the time fromt = t3. As diode Df is forward biased during this period, (8) isalso changed into the following under the assumption that el =Vf=O:

(Ls, +LS2) dt+Reff °is+Cdt Cs

Fig. 2. Typical voltage and current waveforms during gate turn-offinterval.

(7) and (8) for iS and Q5 and by substituting the solutionsinto (3). Switching power P0ff and switching power lossQ0ff dissipated inside the GTO are written as

Poff = ea ' ia (9)

Qoff Poff dt. (10)

Snubber circuit operations can be described with these funda-mental equations.

Values el, ia, and R,ff, in addition to the other circuit pa-

rameters, must be given to solve (7) and (8) for Qs and is. Forthis purpose, as is shown in Fig. 2, the GTO interval is dividedinto two periods, corresponding to the free-wheel diode Dfbias conditions and is also divided into five periods, corre-

sponding to GTO and Ds characteristics.

B. Free- Wheel Diode Bias Conditions

Equation (8) is changed into the following two forms, as

the el polarities for each perio-d (Period A and Period B in Fig.2). It is postulated, for simplicity, that reverse current Ird andforward voltage drop Vf for the free-wheel diode, Df, are neg-

ligible (Ird = 0, Vf = 0).1) Period A (el > 0): Period A is defined as the time from

(13)

C. CalculationProcedure

In addition to the free-wheel diode bias conditions, the po-

larity for el, anode current ia, and equivalent resistance Reffmust be given for the calculations. As previously mentioned,the whole GTO interval is divided into five periods, as is shownin Fig. 2 for the descriptions of ia and Reff. The given ia andReff values for each period are substituted into (12) or (13),according to the polarity of el, which is given by (2). Thesefundamental equations were numerically solved with theRunge-Kutta method. The calculation procedures for eachperiod are described in the following.

1) Period I (to t< tl): The time from t = to to t= t1 inFig. 2 is defined as Period I and is usually termed the storagetime. As anode current ia remains unchanged during thisperiod, no changes occur in is and Q5, as well as ea. There-fore, the numerical calculation was carried out from the nextperiod.

2) Period II (t1 S t < t2): GTO saturation fails at t = tl,with rapid anode current fall. This rapid decrease in the anodecurrent continues until t = t2, at which time the gate-cathodejunction recovers. This period, from t = t1 to t = t2, is definedas Period II and is usually referred to as the fall time. Since theanode current is shunted into capacitance Cs through diodeD., anode voltage ea rises rapidly from this period.

The value Rd in this period is negligibly small, in compari-son with R., because diode D5 is forward biased. Hence (6) issimplified, as follows:

IATO

to0 'I I,3 t4 5; To

I , x m ,A B

F ~~~~~~~~~of4

diadt

V

656

t

It.

Reff = °0- (14)

Page 3: Snubber Circuit for High-Power Gate Turn-Off Thyristors

OHASHI: SNUBBER CIRCUIT FOR HIGH-POWER GATE TURN-OFF THYRISTORS

Anode current ia for this period was formulated with acurve fitting method. As a result of many curve fitting trials,the quadratic regression curve showed a good agreement withexperimental data on ia, for various GTO driving conditions.The experimental data were gathered using a high-power GTO,capable of turning off 600-A anode current [4] . An empiricalequation, given with this method, is as follows:

ia IATOt2)

To2

where IATO is an anode current to be interrupted with nega-tive gate current and To is defined as

To tf/ (IrO/'ATO) (16)

Here tf = t2 - t, as is shown in Fig. 2, and JrO is an anode cur-

rent at t = t2. As is obvious from (16), the time t2 is writtenby t2 = To* l - (IrO/IATO).

3) Period III (t2 < t < t4): When the energy trapped in in-ductance L is completely transfered to capacitance C. at t =t4, the current flow into C. stops, and then C. begins to dis-charge back to the dc supply. The time from t = t2 to t= t4is defined as Period III. As diode D. is kept forward biasedduring this period, Reff is still given by (14).

Because the gate-cathode junction recovers voltage block-ing capability at t = t2, the cathode current stops after thisperiod, but the anode-to-gate current continues to flow, de-caying exponentially as carrier concentration in the N-baseregion is reduced by recombination. Thus the anode currentafter this period is written as follows (see Appendix I)

ia = IrO exp (-t2), (17)

where 'Tr is the anode current decay time and is closely relatedto carrier lifetime in the N-base region.

4) Period IV(t4 < t < t5): As Period IV corresponds to thediode D. storage time, Reff and ia are still governed by (15)and (17). The numerical calculation for this period ends whenis satisfies

rt5Qr fisdt, (18)

t4

where Qr is storage charge removed from diode D. during thisperiod.

5) Period V (t > t5): Because diode D, begins to recover att = t5, the current through Rs increases rapidly with a de-crease in the current through D. and Rd. From a practicalpoint of view, it was postulated that Reff changes exponentiallyfrom zero at t = t5 to the final value Rs. The Reff formulatedfor this period is

Reff =RS I - exp -t5

'rd/

where rd =n-(t5 - t4) and constant n depends on diode char-acteristics [5].

D. Comparison with ExperimentsIn order to examine the calculation model validity, anode

voltage and current and switching power waveforms were cal-culated and compared with experimental data obtained withthe simple GTO chopper circuit shown in Fig. 1, using pre-viously mentioned high-power GTO's. One of the calculatedand measured waveforms for a resistive load case is shown inFig. 3. An input data list for the calculation is as follows:

* circuit parameters: EB = 600 V, R = 1 Q2 (IATO = 600A, L = 0 ,uH), Ls1 = 1.5 pH (measured), Ls 2 = 0.6 pH(measured), R, = I0 Q;

* GTO and Ds characteristics: tf = 2.5 ps, I0 = 80 A,Tr = 5 Ps, Qr = 100 C (n = 0.5).

As is obvious in the figure, both results show good agreementwith each other. The calculations for an inductive load casewere carried out and also showed good agreements with theexperimental results.

III. MODEL APPLICATIONS

In the following, let us consider the problems which mustbe investigated for determining the GTO snubber circuit de-sign such as the anode voltage waveform, the maximum anodecurrent to be interrupted, and the switching power loss dis-sipated at the turn-off interval.

A. Anode Voltage CalculationsVoltage spikes V1, V2, and V3 shown in Fig. 2 are impor-

tant ones for the snubber circuit design considerations. Aswill be described later, V1 is closely related to the maximumanode current to be interrupted.

V2 has to be limited to within maximum blocking voltageratings. The smaller V2 results in a lower voltage stress onGTO. The negative voltage spike peak V3, during Period V,should be suppressed to as low a point as possible, to limitthe voltage rise rate for retriggering prevention. In the fol-lowing, anode voltages for an inductive load case are numeri-cally investigated. Unless otherwise specified, calculationswill be carried out under the conditions of EB = 600 V andIATO = 600 A.

Anode voltage waveforms for various Cs values are illus-trated in Fig. 4. As will be shown later, when Qr and Rs aresufficiently small, such as Qr = 1 MiC and Rs= 10 Q2 for thiscase, no negative voltage spike is observed. Hence most cal-culations are carried out under the foregoing conditions forconvenience, because differences between individual calcu-lated curves become easy to compare. As is obvious in the.figure, V1 and V2 dependence on Cs becomes noticeablewith a decrease in Cs, especially when C5 is less than around2 pF. On the contrary, a further increase in Cs, to more thanaround 2 jiF for this case, produces no appreciable effects onboth V1 and V2 suppression.

Fig. 5 shows changes in anode voltage waveforms for var-

657

Page 4: Snubber Circuit for High-Power Gate Turn-Off Thyristors

IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. IA-19, NO. 4, JULY/AUGUST 1983

0r,

x

r,

x

0

(Ua)

t [ts IFig. 3. Calculated anode voltage, current, and switching power waveforms for resistive load GTO chopper

circuit used for experiments.

Es 60OV 1800 E8=600VLs220.512H 1600 Cs 2osF

CSZO5SMF L -2mH L =2mH1400

I,aF 1200 L82:.IH0.3MLH

3juF r000 Q8MuH

4MpF >I /H

A Rnn -~~~~~~~~~~

0 2 4 6 8 10 12 14

Fig. 4. Calculated

t [/AS)anode voltage waveforms for various snubbercapacitance conditions Ct.

t tELSI

Fig. 5. Calculated anode voltage waveforms for various snubbercircuit stray inductance conditions LS2.

ious stray inductance Ls2 values in the snubber circuit, in-dicating that V1 increases with increase in Ls2 and V2, on

the contrary, increases with LS2 reduction.Rs influences on anode voltage waveforms are shown in

Fig. 6. Negative voltage spike V3 is seen to increase with R.,showing more than 1000 V/,us rate of voltage rise for thecase of R3 = 30 Q2 in the figure. This figure also indicates thatV3 becomes negative whenRs exceeds 30 Q2. This phenomenonis undesirable not only for retriggering prevention but alsofor a GTO whose reverse blocking voltage rating is notguaranteed.

Calculated anode voltage waveforms for various Qr condi-tions are illustrated in Fig. 7, indicating that the negative volt-age spike reduces with a decrease in Qr. In this case, the nega-tive voltage spike completely disappears when Qr is less than

I MC. Hence a high-speed diode is advisable for the negativevoltage spike reduction.

IATO influences on ea were calculated and are illustratedin Fig. 8. Fall time tf used for calculations is given by tf = A +B In (IATO), where A and B are constant. This empirical equa-

tion is formulated with the curve fitting method. It is seen thatV1 and V2 are almost in proportion to the increase in IATO-

In addition to IATO, tf varies with gate driving conditions.Fig. 9 shows anode voltage waveform variations with tf forIATO = 600 A. As is shown in the figure, V1 is greatly in-fluenced by tf, whereas V2 is almost not affected by tf.

As far as an inductive load is concerned, analytical solutionsfor ea give fairly good agreement with the detailed numericalsolutions, as is shown in Fig. 10. Curve A in the figure showsthe anode voltage waveform for an inductive load case, which

0>)

658

Page 5: Snubber Circuit for High-Power Gate Turn-Off Thyristors

OHASHI: SNUBBER CIRCUIT FOR HIGH-POWER GATE TURN-OFF THYRISTORS

12001

1000[a)

6001

400

2001

Fig. 6. Calculated

EB=600VCs =2pFLs, 1.5pHLS2=Q5,uHL =2mHQ, =1Q,Lc

> 1000 2~~~800 ~ ~ ~ 00

600~ ~ ~ ~ ~ ~ 30

t E[.s) t £MsJanode voltage waveforms for various snubber Fig. 8. Calculated anode voltage waveforms for various 'ATO condi-

resistor conditions Rs. tions.

1800

1600

1400

EB =600VCs =2/LFLs,= 1.5MHLS2-0.4jtH-L =2mH

1200 Rs =10Q

a)

4 6 8 10 12 14

*i SIFig. 7. Calculated anode voltage waveforms for various storage charge

conditions Qr removed from diode Dt.

t cps]Fig. 9. Calculated anode voltage waveforms variations with fall time.

looc

00)

60C

40C

20C

I .Lc105pc.Lc

50p,cOr = Ooptc

I

659

-

80C

w0 2C

Page 6: Snubber Circuit for High-Power Gate Turn-Off Thyristors

IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. IA-19, NO. 4, JULY/AUGUST 1983

800F

6003 Numerical (trr = 5ps)

C50QljsF

0.5FF 2F

4O -A 1.4Uu r. -g. -vi imax)*... .........t...

200-

OOC

-rSafe Operating Area

IL200 400 600 800

2 4 6 8 10 12 14

-- IATO [A]Fig. 11. Experimental relations between IATO and V1 for various C.

conditions. Symbols *, A, and * denote gate turn-off failure points.

t [pslFig. 10. Comparison of analytical solution for ea with numerical

solution.

is calculated with the analytical method described in AppendixIL. Numerically calculated ea' which corresponds to curve A, isshown as curve B. Obviously, from comparison of the twocurves, both curves agree well with each other until t = t2.After t = t2, the difference gradually becomes large, becausethe I40 and rT effects are not taken into account for the curve

A calculations.This comparison shows that the analytical method de-

scribed in Appendix II is widely suitable for an inductive loadapplication if a precise solution is not necessary.

B. Maximum Gate Turn-OffAnode Current

The snubber circuit plays an important role, protectingGTO's from gate turn-off failure. The relations between maxi-mum GTO anode current without failure, IATO (max), andsnubber circuit conditions will be discussed in the following.

First of all, it is necessary to explain briefly the experi-mental results on the GTO failure which are used for snubbercircuit design. The GTO failure was observed using a resistiveload GTO chopper circuit in such a way that IATO was in-creased until the turn-off failure occurs by adjusting dc powersupply voltage under constant resistive load conditions. Theexperimental relations between IATO and V1 for various C.conditions are shown in Fig. 11. Solid lines in the figure showmeasured V1 dependence on IATO for the C. conditions. Inthe figure, symbols 0, A, and * indicate GTO failure points;IATO (max) for the sample under test. As is obvious in the fig-ure, measured failure points are distributed in the V1 rangefrom 400 V to 600 V, indicating that V1 shows a close rela-tion to the failure.

According to other investigations made using an infraredmicroscopic technology and an exact one-dimensional model,failure occurs when the temperature rise for the currentcrowding region, just after the fall time, exceeds allowablemaximum temperature AT (max), which is approximatelyproportional to V1 under almost the same tf condition [6].

Since tf is almost constant for a rather wide range ofIATO (tf = 2 3 ,ls for IATO from 200 A to 800 A forthe GTO's under test), it seems reasonable to limit V1 towithin a certain maximum voltage V1 (max), which allows

1000

0

I-

E

_0

800

600

400

200-

&,

O Experimental Data

Calculated Result

- ~~~~~0

-8

0

-o~~~~~

oSafe Operating Area

2 3 4 5

Cs CEF]Fig. 12. Calculated safe operating area for resistive load testing circuit.

Symbol o, denotes failure point.

GTO's to turn off in safety without a failure. V1 (max) forthe GTO's under the test may be 400 V.

Taking condition V1 < V1 (max) into consideration, therelation between IATO (max) and Cs for the resistive loadtesting circuit is numerically calculated and illustrated in Fig.12, where the measured failure points are shown by the symbolo. Most of the failure points, except one, are located outsidethe shaded numerically calculated safe operating area. Hencewe conclude, from the practical point of view, that the methodwhich prescribes V1 (max) is useful for safe operating area

calculations.Let us consider safe operating area for an inductive load

case. Since V1 for an inductive load is given by substitutingt = tf into (31), the design criterion for safe operation is givenby

V, (max) > (2 LS2 tf 3 *)To (20)

Relations between IATO (max) and Cs for various Ls2 valueswere calculated using (20) and the results are illustrated inFig. 13. As is obvious from the figure, when Ls2 is sufficientlysmall, IATO (max) increases alnost proportionally with an in-crease in C, Meanwhile, large LS2 and small Cs values greatlyreduce IATO (max). Note that a large C, is useless forIATO (max) enlargement without lowering LS2 .

0V)

mn.1A I%

660

)

Page 7: Snubber Circuit for High-Power Gate Turn-Off Thyristors

OHASHI: SNUBBER CIRCUIT FOR HIGH-POWER GATE TURN-OFF THYRISTORS

1000

EB=600VLSI= 23aHtf =3/AsL

800k<~~0.6,pLH

o 600_-F

400 _

200 Safe Operating Area

O 2 3 4 5

Cs EpF]Fig. 13. Calculated safe operating area for various snubber circuit

stray inductance, LS2 values for inductive load GTO chopper cir-cuit.

0I-

600k

400k Safe Operating Area(V2 (max)= 1200V)

200 F

%.O0 1 2 3 4 5

Cs [EfFJFig. 14. Calculated allowable maximum IATO limited by rated block-

ing voltage as function of Cs for various LS2 conditions.

In addition to the turn-off failure protection purpose, V2has to be limited to at least within maximum blocking voltagerating VD RM . Since V2 for an inductive load case is given by(41), the requirement for voltage stress removal from the GTOis formulated into

VDRM >EB +IATO (-SC *LS2). (21)

These two equations are snubber circuit design criteria for aninductive load GTO chopper.

Under the condition of V2 < 1200 V and with the same in-put parameters as shown in Fig. 13, the relations betweenIATO and Cs for various LS 2 values are calculated using (21)and the results are shown in Fig. 14. As is apparent from com-paring Figs. 13 and 14, C, is determined by (21), when Ls2 issufficiently small; that is, Ls2 is less than 0.2 ,F for this ex-ample.

C. Power Loss Estimations

Power loss problems related to the snubber circuit designare power loss estimations inside the GTO and in the snubbercircuit itself. The calculated switching power waveforms in-side the GTO are shown in Fig. 15. As is shown in the figure,switching power loss Q0ff is divided into two parts, QA duringPeriod II and power loss QB after Period LI. The relations be-tween Q,ff and C, for various LS2 values were calculated andare illustrated in Fig. 16. The symbol + shows Q0ff for theminimum snubber capacitance Cs (min), which simultaneouslysatisfied (20) and (21), indicating almost the same Q,ff. Sincea large C. value accompanies much power loss in the snubbercircuit, as will be described later, for further decrease in Qoffit is necessary to make device characteristics such as tf, 1r, andI,O as small as possible.

Hereafter, let us consider the power loss Qsb dissipated inthe snubber circuit. The energy trapped in Ls1 just before theGTO interval and the energy stored in C5 during GTO off-stateare mainly dissipated by Rs in the snubber circuit. Thus Q5bis written as follows [3]:

Qsb=I LS IATO2+ * CS *EB2.

E B = 600VIATO = 600ALSI =22LHLS2 =0.6$H

2 8 / 2MF-,9

2/(: AAL

0 2 4 6 8 10 12 14

Fig. 15. Calculated switching power waveforms inside GTO's for var-ious C5 conditions.

05F

EB =600V

IATO =600AL =2mH

0.4k

caO0.3k

0.2k

0. V

1%

N.\"s~ ~ ~ 4~"..N,+,+-LS2=02o62H

0.4pH0.2,LH

0 1 l.-0 1 2 3 4 5

Cs tELF)

Fig. 16. Calculated switching power loss inside GTO for various LS2conditions. Symbol + denotes Qoff for the allowable minimum Cs,C. (min).

661

r - =[.. F

(22)

Page 8: Snubber Circuit for High-Power Gate Turn-Off Thyristors

IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. IA-19, NO. 4, JULY/AUGUST 1983

IATO=600A

L-

Ecna,

L- >K-,-e200A-0

" IOOA0 0.2 0.4 0 0 I.2

0 0.2 0.4 0.6 0.8 1.0 1.2

LS2 EuH]Fig. 17. Calculated relations between LS2 and minimum allowable

switching power loss Qsb (min) inside snubber circuit for variousIATO values.

As is obvious from the equation, making Ls, and Cs as smallas possible for Qsb reduction is desirable. From this standpoint,minimum snubber circuit power loss Qsb (min) determined by(20) and (21) was investigated.

The relations between Qsb (min) and LS2 for various IATOand Ls, conditions were calculated and results are illustratedin Figs. 17 and 18. In both figures, Regions A and B corre-spond to the area where Qsb (min) is determined by (20) and(21), respectively. For large IATO and Ls, values, as shownin the figures, Qsb (min) values rapidly decrease with LS2 inRegion A and, in turn, slightly increase with reduction in Ls2in Region B. However, on the contrary, when IATO and Ls1are small, Qsb (min) is mostly determined by (20). Note alsothat Qsb (min) greatly decreases with reduction in Ls2 bymaking Ls, as small as possible. These results show that LS2plays an important role in optimizing Qsb (min), especiallyfor the cases of large IATO and large Ls,.

IV. CONCLUSION

A snubber circuit calculation model for high-power GTOthyristors was proposed to consider problems which must beinvestigated for the snubber circuit design. Fundamental equa-tions which describe the snubber circuit operation were solvednumerically, dividing the GTO interval into two periods, cor-responding to free-wheel diode bias conditions, and alsodividing them into five periods, corresponding to GTO andsnubber diode characteristics. Results of experiments using asimple GTO chopper circuit showed good agreement with cal-culated results for both inductive and resistive load cases.

Problems to be considered for the snubber design, such asvoltage spike reduction, maximum GTO anode current, andswitching power, were discussed using the calculation model.Design criteria for the snubber circuit were successfullyestablished, introducing allowable maximum voltage spikesV1 (max) and V2 (max) to avoid failures due to current crowd-

0.nC-,

*'S 0.6-

en

O 0.4

0.2

0-0

Fig. 18. Calculated

02 0.4 0.6 0.8 1.0 1.2

LS2 [pHJrelations between Qsb (min) and LS2 for vari-

ous LSI conditions.

ing during the GTO interval and excessive voltage applicationover a maximum blocking voltage rating.

Minimum switching power loss, dissipated inside the GTOand the snubber resistor, was also calculated, taking the de-sign criteria into consideration. As the result of the calcula-tions, it was found that the snubber circuit stray inductanceplays an important role in optimizing the minimum switchingpower loss, especially for the case of large anode current andlarge stray inductance in a main circuit.

APPENDIX IANODE CURRENT DESCRIPTION AFTER t = t3

The GTO reaches the nonsaturation condition at t = t1, thusexcess minority charges Q1 and Q2 in the P andN base layers,respectively, are written after t = t, by the following chargecontrol equations [7] as

dQ, Q1 Q2_~ =i--2-~-ig

dt T1 Tc2

dQ2 Q2 Q=dt r2 Tcl

Ql Q2la= J Ig+ik,

Tci Tc2

(23)

(24)

(25)

where

T1, 72 minority carrier lifetime in both base layers,c 17,,c2 minority carrier transient time in both base layers.

Subscriptions 1 and 2 denote P andN base layers, respectively.As the gate-cathode junction recovers at t= t2 and rI <

r2, it is assumed that ik = 0 and Q1 0 (Q2 > Ql) after t =t2. Equations (23) and (24) are simplified, under these assump-tions, as follows:

(26)ia = =-'72

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OHASHI: SNUBBER CIRCUIT FOR HIGH-POWER GATE TURN-OFF THYRISTORS

dQ2 Q2 0 (27)dt r2

Equation (27) is solved for Q2 . Substituting Q2 into (26) yields

ia = exp (- ) (28)Ti T~~2

Since ia = Q20/r2 at t-t2,

Q20Iro Q=

72

APPENDIX IIANALYTICAL SOLUTIONS FOR AN INDUCTIVE

LOAD CASE

EB into (32) and using (33) lead to

t3 =t2 (EB- A )-- (34)- ~~3CS IATO

As Df is forward biased after t= t3, el can be assumednegligibly small. Combining (1) with (3), under the assump-tions that Re =Oand el Vf =0 for t3 t t5, we obtain

di5 QS

EB (Ls, +LS2)+- (35)dt Cs

where

dOsis (36)

dt

As QS = fi,.dt and Reff = 0 until t = t5, (3) is rearranged These equations can be solved for i5 asas

dis 1 rea =Ls2-- + C isdt.

is =IATO cos (co(t t3)),

(29) where

Initial load current il (=IATO) remains unchanged during theturn-off interval, due to load inductance filtering action, andDf is reverse biased until t = t3, thus is is written as

1c (=

NALS 1 +LS2)Cs

Substituting (37) into (29), we get(30)Is=IATO la,

where ia is governed by (15) during Period II. Substituting(30) into (29) yields ea for Period II:

ea= (zLs2 * t +±;)j T 2 (31)

ea =EB +IATO( -coLs2) sin (co(t-t3)). (39)

The t4 is given in the following, noting that is = 0 at t = (4in (3 7):

ITt4 = t3 +

2wAlthough ia for t > t2 is written by (17), it is postulated, forsimplicity, that ia = IO = ° at t =t2 in (30), thenisIATO.Equation (29) is rearranged into the foUlowing under this as-sumption:

By substituting (40) into (39), we obtain

(40)

(32)e C+IATO * (t t2)

ea =EC+ 0Cs

Here Ec is voltage across C5 at t = t2. As voltage across Cs isgiven by the second term in (31), EC is written as follows:

V2 =EBs +IATO (y-LS2ut )

The ts is also given by substituting (37) into (18) as

± 1 -i1 (it 4I2 co

+ - Qr'IATO,

(33)IATO . 't2EC =

3Cs

Equation (32) describes ea from t = t2 to t = t3, at which Dfbecomes forward biased because ea = EB. Substituting ea =

After t = t5, C5 discharges back through RS, LS 1, LSI2, and Dfto the dc power supply. Since the voltage values across LS1,LS2, and Df are negligible, anode voltage across GTO approxi-mately equals EB.

(37)

(38)

(41)

(42)

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IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. IA-19, NO. 4, JULY/AUGUST 1983

ACKNOWLEDGMENT

The author wishes to thank Dr. K. Kishi and Dr. M. Kuratafor their support of this work, and Mr. K. Takigami and Mr. Y.Yamaguchi for their cooperation in carrying out the experi-ments. The author also wishes to thank Dr. K. Imai for hisvery informative discussions during the work.

REFERENCES[11 W. McMurray, "Optimum snubbers for,power semiconductors,"

IEEE Trans. Ind. Appi.. pp. 593-600, Sept./Oct. 1972.[21 T. H. Barton, "Snubber circuits'for thyristor converters," in IEEE

Conf. Rec. 1978 IAS Annu. Meeting. pp. 1086-1089.[3] R. L. Steigerwald, "Application techniques for high power gate

turn-off thyristors, " in IEEE Conf. Rec. 1975 IAS Annu. Meeting,pp. 165-174.

[4] H. Ohashi, M. Azuma, and T. Utagawa, "High voltage, highcurrent gate turn-off thyristor," Toshiba Rev., pp. 23-27, Nov.-Dec. 1977.

[5] G. N. Revankar and P. K. Srivastava, "Turn-off model of anSCR," IEEE Trans. Ind. Electron. Contr. Instrum., vol. IECT-22,no.. 4, pp. 507-510, 1975.

[6] H. Ohashi and A. Nakagawa, "A study of GTO turn-off failuremechanism," in 1981 IEDM Tech. Dig., pp. 414-417.

[7] M. Kurata, "A new CAD-model of a gate turn-off thyristor," inIEEE Conf. Rec. Annu. IEEE Power Electronics Specialists Conf.,1974, pp. 125-133.

.l _ll Hiromichi Ohashi (M'8 1) was born in Hama-matsu, Japan., on August 14, 1941. He receivedthe B.S. degree in electrical engineering fromHosei University, Tokyo, Japan, and the M.S.degree in electrical and electronics engineeringfrom Sophia University, Tokyo, in 1965 and1969, respectively.

In 1969, he joined the Toshiba Research andDevelopment Center, Kawasaki, Japan, where hewas initially concerned with optical sensing de-vices development for an artificial satellite. Since

1972, he has been engaged in developing new high-power semiconductordevices, such as gate turn-off thyristors and light triggered thyristors. Heis presently the Senior Researcher in the Power Semiconductor DevicesGroup of the Electron Devices Laboratory.

Mr. Ohashi is a member of the Institute of Electrical Engineers ofJapan.

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