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Some thoughts on “ART2GBT” ASIC. Sorin Martoiu, IFIN-HH. De-serialize. Data formatting. Hit Selection. De-serialize. Hit Sel. Data formatting. De-serialize. Hit Sel. Data formatting. How fast the hit selection can be?. 1. (Asynchronous) Smart Token:. FLAG_IN. FLAG_IN. FLAG_IN. - PowerPoint PPT Presentation
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Some thoughts on “ART2GBT” ASIC
Sorin Martoiu, IFIN-HH
De-serialize Hit Selection
Data formatting
De-serialize
Hit Sel Data formatting
De-serialize
Hit Sel
Data formatting
FLAG_IN
FLAG_IN
FLAG_IN
FLAG_IN
Token stops when SUM = MAX_HIT_LIST
1. (Asynchronous) Smart Token:
2. Cascaded Priority Encoders:
How fast the hit selection can be?
FLAGS_IN
ARTIX7 SPARTAN6 ASIC*
(ns)* (ns)* (ns)*
(Asynchronous) Smart Token synth 6.5 9.876
P&R 11.04 12.2
Cascaded Priority Encoders Synth 3.18 4.506 6.5
P&R 5.25 5.045
How fast the hit selection can be?
* MAX_HITS = 8
** Very preliminary. 0.18 um tech MOSIS SCMOS (tsmc) (not IBM 0.13) / OSU FreePDK
How big the ASIC can be?
• Full layout (fast attempt, not fully tested, …)• De-serializers• Hit selection• Data formatting (simple
mux with pass- transistors)• (very) crude estimation:
• 700 x 700 um2
• No triplication (x4)• 0.18 -> 0.13 (x 0.7)• tech, std. cells, pads…
How big the ASIC can be?
Number of I/O pads:•Inputs: 32 x 2•Outputs: 40 x 2•Total: 144 + pwr, clk, …
Options:•Reduce GBT i/f
• 10 elinks@320MHz•Staggered pads•C4 ball bonds
BCID/ARTA12 – 5+6 bitsA5 – 5+6 bitsA2 – 5+6 bits
BCID/ARTemptyemptyA16 – 5+6 bits
DOUT[39:0]
DOUT[79:40]
VMM 0, STRIP 0
“000....00000” “000....00000”
BCID/ART B..DOUT[39:0]
..CID/ART ART-6bits ART-6bits ART-6bits ART-6bits emptyDOUT[79:40]
32-bit hit list
2 5 12 16
5-bit Chip ID:max hits = 7 (80 bits = 7x11 + 3 spare)
ambiguity
32-bit Hit List:max hits = 8 (80 = 8x6 + 32)
Preliminary Conclusions
• Hit selection can be done in 0.5 BC, possibly even less (FPGA and ASIC)
• Design fits well in low-range FPGAs (SPARTAN6 or ARTIX7 – probably valid for Altera devices too)
• ASIC implementation looks feasible in <0.18um tech
• Final chip area is governed by the number of pads/packaging solution
• Power?
Spare Slides
ART2GBT/VMM
GBT (TX)
GBT (RX)
TRIGGER PROC
Fixed Latency
BCID counter
BCID counter
Cavern USA15
123
TTC SYSTEM
123
BCID transmission
8 hits 8 hits
4+4 hits
4+4 hits
Drift gap timing variation turned off…
2 of 4 traces partially lost 1 of 4 trace lost
2 of 8 trace lost
