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R Spartan-3 / 3E / UMC-12A 90 nm Qualification Report RPT012 (v2.0.2) October 7, 2009

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Page 1: Spartan-3 / 3E / UMC-12A 90 nm...Spartan-3 / 3E / UMC-12A 90 nm RPT012 (v2.0.2) October 7, 2009 7 R Spartan-3 / 3E / UMC-12A 90 nm Overview This report presents general process qualification

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Spartan-3 / 3E / UMC-12A 90 nm

Qualification Report

RPT012 (v2.0.2) October 7, 2009

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Spartan-3 / 3E / UMC-12A 90 nm www.xilinx.com RPT012 (v2.0.2) October 7, 2009

Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the Documentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errors contained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information.

THE DOCUMENTATION IS DISCLOSED TO YOU “AS-IS” WITH NO WARRANTY OF ANY KIND. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE DOCUMENTATION, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NONINFRINGEMENT OF THIRD-PARTY RIGHTS. IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES, INCLUDING ANY LOSS OF DATA OR LOST PROFITS, ARISING FROM YOUR USE OF THE DOCUMENTATION.

© 2005–2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners.

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Spartan-3 / 3E / UMC-12A 90 nm www.xilinx.com RPT012 (v2.0.2) October 7, 2009

Revision History

Spartan-3 / 3E / UMC-12A 90 nm, RPT012 (v2.0.2) October 7, 2009

The following table shows the revision history for this document.

Version Revision

05/05/05 1.0 Initial Xilinx release.

08/05/05 1.1 Added Phase II Production data

12/14/05 1.2 Added Spartan-3E FPGA information

03/06/06 1.3 Updated wear out table.

01/26/07 1.4 Updated Mask Qualification Summary (Table 5).

03/16/07 1.4.1 Changes to Table 4.

07/15/07 1.4.2 Typographical errors corrected.

08/24/07 1.4.3 Added a fourth and changed other footnotes in Table 15.

08/07/08 2.0 Replaced Table 26 and Figure 1, Figure 2, Figure 3, and Figure 4.

02/04/09 2.0.1 Typographical errors corrected.

10/07/09 2.0.2 Typographical updates.

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Spartan-3 / 3E / UMC-12A 90 nm www.xilinx.com RPT012 (v2.0.2) October 7, 2009

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5Executive Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5Product Qualification Requirement and Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Engineering Sample (ES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Phase I Production Release . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Phase II Production Release . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Process Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Product/Package Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Qualification Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Generic Process Qualification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Mask Qualification Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Package Qualification Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Life and Environmental Stress Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Wear Out Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Drift Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table of Contents

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Spartan-3 / 3E / UMC-12A 90 nm www.xilinx.com RPT012 (v2.0.2) October 7, 2009

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Spartan-3 / 3E / UMC-12A 90 nm

OverviewThis report presents general process qualification data for the 90 nm Spartan®-3 and Spartan-3E families, mask qualification for the individual Spartan-3 and Spartan-3E devices, package qualification data for FG320, FG1156, and Pb-free package qualification data for Spartan-3 and Spartan-3E packages.

Executive Summary• Product high-temperature operating life (HTOL) test successfully completed 1,000

hours and 7 lots completed 2,000 hours. Based on the HTOL data, 22 FIT failure rate at junction temperature (TJ) of 55° C and 60% confidence level (C.L.) was demonstrated.

• The technology wear-out data demonstrate the production lifetime, meeting minimum 10-year lifetime requirement at 100° C or 20-year lifetime requirement at 85° C.

• Based on the data available to date, all of the Spartan-3 and Spartan-3E FPGA products/packages listed in the following table have been released to Phase-II production.

Table 1: Phase 2 Production Devices

Device Package

3S50 CP132, VQ100, TQ144, PQ208

3S200 VQ100, TQ144, PQ208, FT256

3S400 TQ144, PQ208, FT256, FG320, FG456

3S1000 FT256, FG320, FG456, FG676

3S1500 FG320, FG456, FG676

3S2000 FG456, FG676, FG900

3S4000 FG676, FG900, FG1156

3S5000 FG900, FG1156

3S100E VQ100, TQ144

3S250E VQ100, TQ144, CP132, PQ208, FT256

3S500E CP132, PQ208, FT256, FG320

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Product Qualification Requirement and PhaseR

Product Qualification Requirement and PhaseAs a new process and new product are introduced, a full set of reliability stress and wear-out tests (process qualification) are applied for reliability qualification. After the process qualifies, the qualification for other additional devices from the same product family is reduced to ESD and latch-up tests (mask qualification).

Similarly, as a new package is introduced, a full set of environmental stress tests is applied for reliability qualification (package qualification). For the existing qualified packages, only the die package interaction (DPI) qualification test, temperature cycling, is required.

Engineering Sample (ES)Before a product is fully qualified, an engineering sample is available to meet customers' design-in and prototyping needs and to provide early application feedback. Products at the ES stage are considered medium risk and should not be used for customer end product qualification. There can also be limitations (errata) associated with ES products that customers should be made aware of.

3S1200E FT256, FG320, FG400

3S1600E FG320, FG400, FG484

Table 2: Phase 2 Lead-Free Production Devices

Device Lead-Free Package

3S50 CPG132, VQG100, TQG144, PQG208

3S200 VQG100, TQG144, PQG208, FTG256

3S400 TQG144, PQG208, FTG256, FGG320, FGG456

3S1000 FTG256, FGG320, FGG456, FGG676

3S1500 FGG320, FGG456, FGG676

3S2000 FGG456, FGG676, FGG900

3S4000 FGG676, FGG900, FGG1156

3S5000 FGG900, FGG1156

3S100E VQG100, TQG144

3S250E VQG100, TQG144, CPG132, PQG208, FTG256

3S500E CPG132, PQG208, FTG256, FGG320

3S1200E FTG256, FGG320, FGG400

3S1600E FGG320, FGG400, FGG484

Table 1: Phase 2 Production Devices (Cont’d)

Device Package

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Process AttributesR

Phase I Production ReleaseProducts at Phase I production release are considered low risk. Manufacturing volume is generally ramped at this time. Although not all of the qualification testing may be completed, there is sufficient data to indicate that the product can meet customer application needs with low risk. Decreased risk and, therefore, increased confidence in the product's health, is paralleled by increases in production shipments.

♦ HTOL data demonstrate failure rate ≤ 200 FIT

♦ Wear-out test complete on ≥ 1 lot and meeting minimum 10-year requirement

♦ Pass 1,000 temperature cycles

♦ Pass 500 hours of other environmental tests

Phase II Production ReleaseA product reaches Phase II Production Release when all assessments have been completed and formal risk assessment shows that all risks are negligible. This means that sufficient data exists to demonstrate that the product meets the production qualification requirements of each of the validation plans. Closure of all corrective actions is complete or imminent and validated adequately. Product will perform as designed in customers' use environments. The product responsibilities are transferable to sustaining or manufacturing engineering.

♦ HTOL data demonstrate failure rate ≤ 50 FIT

♦ Wear-out test complete on 3 lots and meeting minimum 10-year requirement

♦ Complete and pass environmental tests

Process Attributes• Wafer Fab Location

♦ UMC 12A, 300 mm, Tainan, Taiwan

• Process Technology

♦ 90 nm 1P8M CMOS logic process

♦ Dual gate oxide

♦ 7 layers copper for Spartan-3 devices, 8 layers of copper for Spartan-3E devices

♦ FSG inter metal dielectric (IMD)

♦ 1 layer aluminum for bond pad and redistribution layer (RDL)

• Package

♦ All wire bond package

♦ Both Pb and Pb-Free packages

♦ Assembly at Silicon Precision Industries (SPIL), Taiwan

♦ Amkor for FG(G)320 & CP(G)132

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Product/Package MatrixR

Product/Package Matrix

Device 3S50 3S200 3S400 3S1000 3S1500 3S2000 3S4000 3S5000

CP132

VQ100

TQ144

PQ208Process

QualProcess

Qual

FT256

FG320 TCB & TH

FG456Process

QualProcess & Pack Qual

FG676

FG900 TC

FG1156 TCB & TH

= by extension = actual test done

Device 3S50 3S200 3S400 3S1000 3S1500 3S2000 3S4000 3S5000

CPG132 HTS, TC

VQG100 TC

TQG144

PQG208

FTG256

FGG320 TC, TH TC, TH

FGG456

FGG676

FGG900

FGG1156TC, HTS,

TH TC

= by extension = actual test done

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Spartan-3 / 3E / UMC-12A 90 nm www.xilinx.com RPT012 (v2.0.2) October 7, 2009 11

Qualification SummaryR

Qualification Summary

Generic Process Qualification

Product Stress Test Summary

Device 3S100E 3S250E 3S500E 3S1200E 3S1600E

VQG100 TC TC

TQG144

CPG132TC, HTS, TH, THB

PQG208

FTG256

FGG320 TC

FGG400

FGG484

= by extension = actual test done

Table 3: Product Stress Test Summary

Test Conditions Test Vehicles Lot QtyCumulative

Device-Hr/Cyc# of Failures

HTOL (Static/Dynamic)

Ta = 125° C, VCCMAX

3S1000

3S1500

3S2000

3S4000

3

9

1

1

1,391,1972(3)

(22 FIT)(2)

HTS Ta = 150° C 3S1500 2 239,729 0

THB(1) 85° C, 85%RH, Bias VCCMAX

3S1500 4 223,216 0

TH w/o B(1) 85° C, 85%RH 3S1500 2 310,076 0

TC-B(1) -55° C/+125° C 3S1500 2 227,140 0

Notes: 1. Level-3 reconditioning applied to THB, TH and TC samples prior to the stress tests.2. The failure rate is calculated based on 0.7 eV, Tj of 55° C and 60% C.L.3. Basic Functional VCC sensitive (soft) failure @ 1000 hrs, FA results - no defect found; 1 Basic Functional (soft)

failure @ 61 hrs, HTOL continued to 2000 hrs & electrical signature not changed.

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12 RPT012 (v2.0.2) October 7, 2009 www.xilinx.com Spartan-3 / 3E / UMC-12A 90 nm

Qualification SummaryR

Wear Out Test Summary

Table 4: Wear Out Test Summary

MechanismSample

Size

Conditions of Stress

Test

Conditions of Quoted

Results

Failure Criterion

CommentsProduct Lifetime@85° C

Product Lifetime@100° C

Product Lifetime@125° C

Hot Carrier Injection

20 per condition

3 Voltages, 25° C

≥1.05 VCC, 125° C for

Core, -55° C for IO NMOS

ΔIdsat > 10%

Worst at cold for IO NMOS &

hot for others

150 yrs for IO PMOS

141 yrs for IO PMOS

129 yrs for IO PMOS

Vt stability 10 per condition

3 Voltages @ 125° C 1.05 VCC

100 mV for Core

Oxide; 110 mV for

2.5V device;

200 mV for 3.3V device

Verified by product HTOL

216 yrs 95 yrs 18 yrs

Gate Oxide TDDB

20 per condition

3 Voltages/3 temp., 100 to 160° C

1.05 VCC

Ign/Ign-1>1.2 for

Core NMOS & 2

for Core PMOS, >10 for IO CDF

= 0.1%

Equivalent to 11 FIT’s

after 10 years

49 yrs for 3S5000

15 yrs for 3S5000

3 yrs for 3S5000

Electro-migration

20-24 per condition

250 to 350° C

design rule

Juse

ΔR/R>20% CDF = 100

PPM

Equivalent to 1 FIT’s after 10 years

105 yrs 34 yrs 6 yrs

VRDB

Total test areas > 0.2cm2

for area; > 1E3cm for STI edge; > 1E4cm for poly

edge

Voltage Ramp @25° C

DD

Ign/Ign-1 >1.2 for

core, >10 for IO

B mode 1.1VCC <

VBD < 2.3VCC

pass pass pass

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Qualification SummaryR

Mask Qualification SummaryThe Latch-Up, HBM, and CDM tests are performed according to the following industrial standard specifications

• Latch-Up: JESD-78, ± 200mA and 1.5 x VDD at 125° C.

• HBM: JESD-22-A114, ESDA STM5.1

• CDM: JESD-22-A115, ESDA STM5.3.1

• MM: EIA/JESD22-A115-A

SM 20-30 per condition

3 Tempera-

tures 1,000 hrs

pass or fail

ΔR/R > 20% or

EDR for single via;

ΔR/R > 2.5% for

Via Chains

No sample stress fail allowed

pass pass pass

BEOL TDDB

16-20 per condition 125-200° C 1.1VCC

line to line leakage >

1μA CDF=0.01

%

Equivalent to 1 FIT’s after 10 years

795 yrs 646 yrs 214 yrs

Table 4: Wear Out Test Summary (Cont’d)

MechanismSample

Size

Conditions of Stress

Test

Conditions of Quoted

Results

Failure Criterion

CommentsProduct Lifetime@85° C

Product Lifetime@100° C

Product Lifetime@125° C

Table 5: Mask Qualification Summary

Device Latch-UpHBM Passing

Voltage

CDM Passing Voltage

MM Passing Voltage

Package

XC3S50 Pass +/-2,000V(1) +/-500V +/- 200V PQ208

XC3S200 Pass +/-2,000V +/-500V +/- 200V PQ208, FT256(2)

XC3S400 Pass +/-2,000V +/-500V +/- 200V PQ208, FG456(2)

XC3S1000 Pass +/-2,000V +/-500V +/- 200V PQ208, FG676(2)

XC3S1500 Pass +/-2,000V +/-500V +/- 200V FG456

XC3S2000 Pass +/-2,000V +/-500V +/- 200V PQ208, FG900(2)

XC3S4000 Pass +/-2,000V +/-500V +/- 200V FG900, FG1156(2)

XC3S5000 Pass +/-2,000V +/-500V +/- 200V FG1156

XC3S100E Pass +/-2,000V +/-500V +/- 200V PQ208, TQ144

XC3S250E Pass +/-2,000V +/-500V +/- 200V PQ208, FT256

XC3S500E Pass +/-2,000V +/-500V +/- 200V PQ208, FG320

XC3S1200E Pass +/-2,000V +/-500V +/- 200V FG320

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Qualification SummaryR

Package Qualification Summary

XC3S1600E Pass +/-2,000V +/-500V +/- 200V FG484

Notes: 1. The HBM passing voltage for XC3S50 has been revised from the previous 1500V to 2000V when No Connect (NC)

pins are not tested per JEDEC 22A114D and ESD Association bulletin.2. These packages were tested for CDM only and passed.

Table 5: Mask Qualification Summary (Cont’d)

Device Latch-UpHBM Passing

Voltage

CDM Passing Voltage

MM Passing Voltage

Package

Table 6: FG1156 Package Qualification Summary

Test Conditions Device SSDuration

Hrs/Cycles# of

Failures

TC-B -55 to +125° C XC3S5000 77 1,000 0

TH 85° C, 85%RH, VDDMAX

XC3S5000 77 1,000 0

Table 7: FG320 Package Qualification Summary

Test Conditions Device SSDuration

Hrs/Cycles# of

Failures

TC-B -55 to +125° C XC3S1500 76 1,500 0

TH 85° C, 85%RH, VDDMAX

XC3S1500 73 1,000 0

Table 8: FG900 Package Qualification Summary

Test Conditions Device SSDuration

Hrs/Cycles# of

Failures

TC-B -55 to +125° C XC3S4000 61 2,000 0

Table 9: CPG132 Package Qualification Summary

Test Conditions Device SSDuration

Hrs/Cycles# of

Failures

TCB -55 to 125° C XC3S50 77 1,000 0

HTS 150oC XC3S50 77 1000 0

TCB -55oC to 125oC XC3S500E 77 2000 0

HTS 150oC XC3S500E 77 1000 0

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Qualification SummaryR

TH 85oC,85%RH XC3S500E 80 1000 0

THB 85oC,85%RH XC3S500E 77 1000 0

Table 10: FGG1156 Package Qualification Summary

Test Conditions Device SSDuration

Hrs/Cycles# of

Failures

TCB -55 to 125° C XC3S4000 45 1,000 0

HTS 150° C XC3S4000 49 1,000 0

TH 85° C, 85%RH XC3S4000 50 1,000 0

TCB -55 to 125° C XC3S5000 72 1,000 0

Table 11: FGG320 Package Qualification Summary

Test Conditions Device SSDuration

Hrs/Cycles# of

Failures

TCB -55 to 125° C XC3S400 53 1,000 0

TCB -55 to 125° C XC3S1500 77 1,000 0

TH 85° C, 85%RH XC3S400 53 1,000 0

TH 85° C, 85%RH XC3S1500 77 1,000 0

TCB -55oC to 125oC XC3S1600E 77 1,000 0

Table 12: PQ208 Package Qualification Summary

Test Conditions Device SSDuration

Hrs/Cycles# of

Failures

TCB -55 to 125° C XC2S200E 76 1,000 0

TH 85° C, 85%RH XC2S200E 76 1,000 0

HTS 150° C XC2S200E 32 1,000 0

Table 13: TQG144 Package Qualification Summary

Test Conditions Device SSDuration

Hrs/Cycles# of

Failures

TCC -65° C to 150° C XC2S50E 38 1,000 0

TH 85° C, 85%RH XC2S50E 76 1,000 0

Table 9: CPG132 Package Qualification Summary (Cont’d)

Test Conditions Device SSDuration

Hrs/Cycles# of

Failures

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Qualification SummaryR

Table 14: VQG100 Package Qualification Summary

Test Conditions Device SSDuration

Hrs/Cycles# of

Failures

TCB -55° C to 125° C XC3S200 76 1,000 0

TCB -55° C to 125° C XC3S100E 82 2,000 0

TCB -55° C to 125° C XC3S250E 77 1,000 0

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AppendixR

Appendix

Life and Environmental Stress Data

Table 15: Life and Environmental Stress Data

Test Conditions Device Package SSDuration

(hrs)# of

FailuresCumulative

Hours

HTOL

Ta = 125° C, VCCMAX, Static or

Dynamic(4)

3S1500 FG456 72 2,000 1(2)

1,391,197

3S1500 FG456 31 2,000 0

3S1500 PQ208 54 2,004 0

3S1500 FG456 56 1,609 0

3S1500 PQ208 78 1,500 0

3S1500 FG456 76 2,014 0

3S1500 FG456 77 2,004 0

3S1500 FG456 77 2,003 0

3S1500 PQ208 6 47 0

3S2000 PQ208 36 1,033 0

3S4000 PQ208 55 1,500 1(3)

3S1000(4) PQ208 76 2,004 0

3S1000(4) FG456 59 1,000 0

3S1000(4) FG456 77 1,000 0

HTS Ta = 150° C3S1500 FG456 42 2,010 0

239,7293S1500 FG456 77 2,017 0

THB(1)85° C,

85%RH, Bias VCCMAX

3S1500 PQ208 42 1,678 0

223,2163S1500 PQ208 36 1,147 0

3S1500 PQ208 72 1,409 0

3S1500 PQ208 10 1,000 0

TH w/o B(1) 85° C, 85%RH

3S1500 FG456 76 2,001 0310,076

3S1500 FG456 79 2,000 0

TC-B(1) -55° C/+125° C

3S1500 FG456 37 2,000 0227,140

3S1500 FG456 76 2,015 0

Notes: 1. Level-3 preconditioning applied to THB, TH, and TC samples prior to the stress tests.2. Basic Functional VCC sensitive (soft) failure @ 1,000 hours, FA results – no defect found.3. Basic Functional (soft) failure @ 61 hours, HTOL continued to 2,000 hrs and electrical signature not changed.4. HTOL test was done in dynamic.

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AppendixR

Wear Out Data

Hot Carrier Injection

Negative Bias Temperature Instability

Table 16: Wear Out Data, Hot Carrier Injection

Transistor Device Type Lot Tox (A)Worst

ConditionsLifetime (yrs)

NMOS

1.2V NMOS

KN192

16 1.32V; 125° C

4.51E+02

KP013 4.42E+02

KN350 5.44E+02

1.2V NMOS low Vt

KN192

16 1.32V; 125° C

5.86E+02

KP013 1.52E+03

KN350 1.57E+03

2.5V NMOS

KN192

52 2.625V; -40° C

1.10E+02

KP013 3.89E+02

KN350 2.19E+02

3.3V NMOS KN308 52 3.45V; -40° C 8.61E+01

PMOS

1.2V PMOS

KN192

16 1.32V; 125° C

6.42E+03

KP013 4.91E+02

KN350 1.14E+03

2.5V PMOS

KN192

52 2.625V; 125° C

1.73E+04

KP013 6.89E+03

KN350 1.41E+04

3.3V PMOS KN308 52 3.45V; 125° C 1.29E+02

Table 17: Wear Out Data, Negative Bias Temperature Instability

PMOS Lot Tox (A) Worst ConditionsLifetime (yrs) @

125C

1.2V PMOS

KN192

16 1.32V; 125° C

3.75E+01

KP013 2.83E+01

KN350 2.77E+01

2.5V PMOS

KN192

52 2.625V; 125° C

2.05E+01

KP013 1.77E+01

KN350 1.84E+01

3.3V PMOS KR308 52 3.45V; 125° C 3.19E+01

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AppendixR

Gate Oxide TDDB

• Weibull Distribution: CDF = 1 - exp [-(t / to)m]

• For thin oxide (16A core), power law model: to = Co V-n exp(Ea/kT) A-(1/m)

• Failure criterion: 1.2 x current change (soft breakdown) for NMOS & 2X for PMOS

• For thick oxide (52A I/O), E-field model: to = Co exp(-γ V) exp(Ea/kT) A-(1/m)

• Failure criterion: 10x current change

Product's TDDB lifetime is limited by PFET core and the above TDDB lifetime is calculated based on gate oxide area of 10 mm2 for core and 3 mm2 for IO. Table 19 shows the detail TDDB lifetimes of each devices.

Table 18: Gate Oxide TDDB, Inversion Mode

Test Items

Tox Use Cond. Lot IDQualification Results (yrs)

Specification Pass/Fail

Thin Oxide Nwell

16Å 1.32V, 125° C

KN192 1.74E+01

Lifetime > 10 yrs Pass

KP013 1.56E+01

KP014.15 1.81E+01

Thin Oxide Pwell

16Å 1.32V, 125° C

KN192 8.27E+02

KP013 8.02E+02

KP014.15 3.26E+02

Mid Oxide Nwell

22Å 1.65V, 125° C

KN192 2.36E+04

KP013 1.15E+05

KP014.15 1.11E+04

Mid Oxide Pwell

22Å 1.65V, 125° C

KN192 1.67E+06

KP013 2.76E+06

KP014.15 6.03E+04

Thick Oxide Nwell

52Å 3.45V, 125° C

KN192 2.54E+04

KP013 9.10E+03

KP014.15 2.27E+03

Thick Oxide Pwell

52Å 3.45V, 125° C

KN192 1.33E+02

KP013 3.36E+02

KP014.15 1.46E+02

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AppendixR

Electromigration

• Black's Equation and lognormal distribution: MTTF = A J-n exp(Ea/kT)

• Failure criterion: (Rfinal -Rinitial)/Rinitial= 20%; Lifetime calculation with CDF=100 ppm

• Parameters: Ea = 0.87 eV, n = 1.1

Table 19: Detail of TDDB Lifetime in Years of Each Device

Lifetime (yrs) XC3S XC3SE

Lot Temp. 50 200 400 1000 1500 2000 4000 5000 100E 250E 500E 1200E 1600E

KN192

85° C 423 255 181 118 85 66 55 49 290 163 114 80 60

100° C 131 79 56 36 26 21 17 15 90 51 35 25 19

125° C 23 14 10 6 5 4 3 3 16 9 6 4 3

KP013

85° C 567 341 243 158 115 89 73 66 389 219 153 107 80

100° C 175 106 75 49 35 27 23 20 120 68 47 33 25

125° C 30 18 13 8 6 5 4 3 21 12 8 6 4

KP014

85° C 665 401 285 185 134 104 86 77 456 256 179 126 94100° C 206 124 88 57 42 32 27 24 141 79 56 39 29125° C 35 21 15 10 7 6 5 4 24 14 10 7 5

Table 20: Electromigration

Interconnect Structure Design Usage Lot IDLifetime (yrs) 100 ppm @

100° CSigma

CA/M1

M1

KSA45.02 348.24 0.20

KM917.05 319.81 0.22

KN146.02 223.14 0.22

CA/M1 (wide line)

KSA45.02 2705.97 0.22

KM917.05 2930.20 0.19

KN146.02 2832.95 0.19

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AppendixR

V1/M1

1X: M2 - M6

KSA45.02 363.10 0.16

KM917.05 37.12 0.63

KN146.02 85.86 0.38

V1/M1 (wide line)

KSA45.02 71.88 0.78

KM917.05 34.99 0.90

KN146.02 61.79 0.79

V1/M2

KN146.02 51.68 0.50

KSB46/7 53.32 0.84

KP655/2 273.48 0.82

V2/M2

KSB46/7 33.67 0.41

KP655/2 54.97 0.52

KSH34.02/3 39.55 0.56

V1/M2 (wide line)

KN146.02/3 422.68 0.65

KSB46/7 182.66 0.85

KP655/2 406.93 0.65

V2/M2 (wide line)

KSB46/7 127.91 0.52

KP655 56.24 0.94

KSH34 165.73 0.59

V6/M7

2X: M7, M8

KL359 547.32 0.38

KSA45 480.92 0.40

KM917 800.05 0.28

V7/M7

KL359 51.96 0.75

KSA45 93.89 0.55

KM917 78.04 0.66

V6/M7 (wide line)

KL359 1191.58 0.30

KSA45 162.81 0.83

KM917 1083.31 0.34

V7/M7 (wide line)

KL359 40.93 0.85

KSA45 57.91 0.78

KM917 96.82 0.66

Table 20: Electromigration (Cont’d)

Interconnect Structure Design Usage Lot IDLifetime (yrs) 100 ppm @

100° CSigma

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AppendixR

V8/M9

4X: M9, M10

KL359 288.31 0.16

KSA45 102.12 0.39

KM917 130.60 0.53

M11/V10/M10

KL359 522.93 0.23

KSA45 370.24 0.39

KM917 680.63 0.28

L1L2 RDL

KL359 104.34 0.31

KSA45 55.05 0.43

KM917 91.9 0.20

Table 20: Electromigration (Cont’d)

Interconnect Structure Design Usage Lot IDLifetime (yrs) 100 ppm @

100° CSigma

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AppendixR

Area/Edge Intensive Vbd (Breakdown Voltage for Gate Oxide Integrity)

Table 21: Area/Edge Intensive Vbd (Breakdown Voltage for Gate Oxide Integrity)

Test Items Lot ID Tox (Å)Qualification

ResultsSpecification Pass/Fail

Area Intensive

NW/SG

KN864

16

DD<2.97/cm2

DD< 5 /cm2 Pass

KQ593 DD<3.3/cm2

KQ829 DD<3.3/cm2

PW/SG

KN864

16

DD<2.96/cm2

KQ593 DD<3.3/cm2

KQ829 DD<3.3/cm2

NW/MG

KN864

22

DD<1.59/cm2

KQ593 DD<1.77/cm2

KQ829 DD<1.77/cm2

PW/MG

KN864

22

DD<1.59/cm2

KQ593 DD<1.77/cm2

KQ829 DD<1.77/cm2

NW/TG

KN864

52

DD<1.59/cm2

KQ593 DD<3.54/cm2

KQ829 DD<1.77/cm2

PW/TG KN864

52

DD<1.59/cm2

KQ593 DD<1.77/cm2

KQ829 DD<1.77/cm2

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AppendixR

Poly Edge

Intensive

NW/SG

KN864

16

DD<0.00009/cm

DD<0.0001/cm Pass

KQ593 DD<0.0001/cm

KQ829 DD<0.0001/cm

PW/SG

KN864

16

DD<0.00009/cm

KQ593 DD<0.00049/cm

KQ829 DD<0.00049/cm

NW/MG

KN864

22

DD<0.00009/cm

KQ593 DD<0.0001/cm

KQ829 DD<0.0001/cm

PW/MG

KN864

22

DD<0.00009/cm

KQ593 DD<0.00049/cm

KQ829 DD<0.00049/cm

NW/TG

KN864

52

DD<0.00009/cm

KQ593 DD<0.00009/cm

KQ829 DD<0.00009/cm

PW/TG

KN864

52

DD<0.00009/cm

KQ593 DD<0.00009/cm

KQ829 DD<0.00009/cm

Table 21: Area/Edge Intensive Vbd (Breakdown Voltage for Gate Oxide Integrity) (Cont’d)

Test Items Lot ID Tox (Å)Qualification

ResultsSpecification Pass/Fail

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AppendixR

BEOL (Backend of line) TDDB at 100° C

STI Edge Intensive

NW/SG

KN864

16

DD<0.00009/cm

DD<0.001/cm Pass

KQ593 DD<0.00009/cm

KQ829 DD<0.00009/cm

PW/SG

KN864

16

DD<0.00009/cm

KQ593 DD<0.00009/cm

KQ829 DD<0.00009/cm

NW/MG

KN864

22

DD<0.00009/cm

KQ593 DD<0.00009/cm

KQ829 DD<0.00009/cm

PW/MG

KN864

22

DD<0.00009/cm

KQ593 DD<0.00009/cm

KQ829 DD<0.00009/cm

NW/TG

KN864

52

DD<0.00009/cm

KQ593 DD<0.00009/cm

KQ829 DD<0.00009/cm

PW/TG

KN864

52

DD<0.00009/cm

KQ593 DD<0.00009/cm

KQ829 DD<0.00009/cm

Table 22: Backend of line TDDB at 100oC

Test Items Lot ID Lifetime (yrs) @ 100oC

Intra-Level M1

KSA45.02 3.47E+08

KM917 1.15E+06

KN146 6.46E+02

Intra-Level M2

KSA45.02 1.33E+03

KM917 4.91E+03

KN146 9.19E+02

Intra-Level M7

KSA45.02 5.93E+09

KM917 4.44E+09

KN146 1.12E+10

Table 21: Area/Edge Intensive Vbd (Breakdown Voltage for Gate Oxide Integrity) (Cont’d)

Test Items Lot ID Tox (Å)Qualification

ResultsSpecification Pass/Fail

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AppendixR

Stress Migration

• Stress conditions: 175oC, 225oC, 275oC, 500/1,000 hrs

• Test structures & failure criterion

♦ Via chain: (Rfinal-Rinitial)/Rinitial = 2.5%

♦ 1K, 10K, stacked, plate, design variations

♦ Single via (Kelvin): Rf = design corner (EDR limit)

♦ Via at line edge vs. center

Table 23: Stress Migration

Test Items Lot ID Qualification Status Specification Pass/Fail

Via Chain

KSA45/KSC06/KN192 No fail @ 1,000 hrs

No sample fail is allowed Pass

KSA45/KSC06/KN192 No fail @ 1,000 hrs

KSA45/KSC06/KN192 No fail @ 1,000 hrs

Stack Via Chain

KSA45/KSC06/KN192 No fail @ 1,000 hrs

KSA45/KSC06/KN192 No fail @ 1,000 hrs

KSA45/KSC06/KN192 No fail @ 1,000 hrs

Single Via

KSA45/KSC06/KN192 No fail @ 1,000 hrs

KSA45/KSC06/KN192 No fail @ 1,000 hrs

KSA45/KSC06/KN192 No fail @ 1,000 hrs

Plate Structure

KSA45/KSC06/KN192 No fail @ 1,000 hrs

KSA45/KSC06/KN192 No fail @ 1,000 hrs

KSA45/KSC06/KN192 No fail @ 1,000 hrs

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AppendixR

Temperature Cycling Test under Stress Condition of -55° C to +150° C

Table 24: Temperature Cycling Test under Stress Condition of -55° C to +150° C

Test Items Lot ID Qualification Status Specification Pass/Fail

Via Chain

KSA45/KSC06/KN192

No fail after 500 cycles

No sample fail is

allowedPass

KSA45/KSC06/KN192

No fail after 500 cycles

KSA45/KSC06/KN192

No fail after 500 cycles

Stack Via Chain

KSA45/KSC06/KN192

No fail after 500 cycles

KSA45/KSC06/KN192

No fail after 500 cycles

KSA45/KSC06/KN192

No fail after 500 cycles

Single Via

KSA45/KSC06/KN192

No fail after 500 cycles

KSA45/KSC06/KN192

No fail after 500 cycles

KSA45/KSC06/KN192

No fail after 500 cycles

Plate Structure

KSA45/KSC06/KN192

No fail after 500 cycles

KSA45/KSC06/KN192

No fail after 500 cycles

KSA45/KSC06/KN192

No fail after 500 cycles

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AppendixR

Drift Analysis• HTOL: 125oC ambient, 1.26V VCCINT, 3.45V VCCO

• Conclusion: Parametric drifts are covered by test guard band

Table 25: Drift Analysis for Spartan-3 Devices

Parameters Definition Device 0 hrs 1,000 hr% of

Change

Test Guard Band or

Limit

TILO_rDelay rise time,

PMOS dominated

3S1500 15.98 16.45 2.90% Limited by TILO_f

TILO_fDelay fall time,

NMOS dominated

3S1500 19.57 19.5025 -0.40% 3%

Icc max Gross Icc unconfigured 3S1500 42.54 42.49 -0.1% 100 mA

Icc standbyQuiescent

supply current (configured)

3S1500 31.21 31.29 0.2% 80 mA

Table 26: Drift Analysis for Spartan-3E Devices

Parameters Definition Device 0 hr1,500 hrs

% of Change(1)

Test Guardband or

limit

TILO_rDelay rise

time PMOS dominated

3S500E 15.49 ns 16.21 ns 4.65% Limited by TILO_f

TILO_fDelay rise

time NMOS dominated

3S500E 17.16 ns 17.18 ns 0.12% 3%

Icc Core Gross Icc unconfigured 3S500E 23.23

mA23.33 mA 0.43% 82 mA @

25oC

Icc StdbyQuiescent

supply current

3S500E 11.73 mA

11.95 mA 1.87% 55 mA @ 25oC

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AppendixR

Figure 1: 3S500E 1,500 hrs TILO_r vs. 0hr TILO_r

Figure 2: 3S500E 1,500 hrs TILO_f Vs. 0hr TILO_f

Figure 3: 3S500E 1,500 hrs Icc_core (mA) Vs. 0hr Icc_core (mA)

3S500E 1500hrs TILO_r vs. 0hr TILO_r

y = 1.0636x - 0.393R2 = 0.9775

12.5

13

13.5

14

14.5

15

15.5

16

16.5

12.5 13 13.5 14 14.5 15 15.5 16 16.5

0hr TILO_NW_r (ns)15

00hr

s TI

LO_N

W_r

(ns

)

3S500E 1500hrs TILO_f Vs. 0hr TILO_f

y = 0.9972x - 0.0367R2 = 0.985

15.5

16

16.5

17

17.5

18

18.5

19

19.5

15.5 16 16.5 17 17.5 18 18.5 19 19.5

0hr TILO_NW_f (ns)

1500

hrs

TILO

_NW

_f (

ns)

3S500E 1500hrs Icc_core (mA) Vs. 0hr Icc_core (mA)

y = 0.8832x + 2.4977R2 = 0.9333

21

21.5

22

22.5

23

23.5

24

24.5

25

21 21.5 22 22.5 23 23.5 24 24.5 25

0hr Icc_Max (mA)

1500

hrs

Icc_

Max

(mA

)

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AppendixR

Figure 4: 3S500E 1,500 hrs Icc_stdby (mA) vs. 0hr_Icc_stdby (mA)

3S500E 1500hrs Icc_stdby (mA) vs. 0hr_Icc_stdby (mA)

y = 0.9713x + 0.2809R2 = 0.9103

9

9.5

10

10.5

11

11.5

12

12.5

13

9 9.5 10 10.5 11 11.5 12 12.5 13

0hr_Icc_Standby (mA)15

00hr

s_Ic

c_St

andb

y (m

A)