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Spartan-6 Memory ResourcesBasic FPGA Architecture
Xilinx Training
After completing this module you will be able to…
Fully utilize the Spartan-6 distributed and block memory resources
Understand the features and limitations of the Spartan-6 dedicated memory controller block (MCB)
Use the Memory Interface Generator (MIG) to build your custom memory controller and design an appropriate interface to your off-chip memory component
Objectives
On-chip block RAM and ROM– Frequently used for…
• Finite State Machines• FIFO• Large/local data storage
External memory for larger data storage– Dedicated Memory Controller Block (MCB)– Supports evolving controller standards
All memory solutions– Must be fast and flexible– Bitstream can pre-loaded with fixed data for a
ROM or RAM
External memory
External memory
Spartan-6Spartan-6
Fast on-chip memory
Fast on-chip memory
Every Design Uses Memory
On-chip Block RAMDistributed RAM/SRL32
• Very granular, localized memory• Minimal impact on logic routing• Great for small FIFOs
Fast Memory Interfaces
• Efficient, on-chip blocks• Ideal for mid-sized buffering
• Cost-effective bulk storage• Various memory controller cores• For large memory requirements• Memory Controller Block
CapacityCapacityGranularity
RA
M /
SRL
32 DRAM
SRAM
FLASH
EEPROM
Spartan-6Spartan-6BRAMLOGICLOGIC BRAM
DRAM • SDRAM• DDR• DDR3• FCRAM• RLDRAMSRAM• Sync SRAM• DDR SRAM• ZBT• QDRFLASHEEPROM
Memory Options
MCB supports many standards– 1.5 V to 2.5 V– Single or double data rate– Different protocols
High performance – With advanced ChipSync™ technology
• This is the Select I/O functionality that enables the FPGA to be directly connected to memory specific I/O standards
DDR/DDR-II/DDR3
QDR/QDR-II
RLDRAM
FCRAM
ZBT/NoBL
FIFOs
Dual-Ports
CAMs
Spartan-6Spartan-6
SDR SDRAM
Interfacing to External Memories
Distributed LUT memory– 64-bit blocks throughout the FPGA
available in 25% of the slices– Single-port, dual-port, multi-port– Can be used as 32-bit shift register– Very fast (sub-nanosecond)
Ideal for small and fast memories– Coefficient storage– Small data buffers– Small state machines– Small FIFOs – Shift registers
RAM
RAM
RAM
Slice3Logic
Slice3Logic
Slice3Logic RAM
Shift Register
Slice3Logic RAM
Shift Register
Slice3Logic
Slice3Logic
Slice3Logic RAM
Shift Register
Slice3Logic RAM
Shift Register
Slice3Logic
Slice3Logic
Slice3Logic RAM
Shift Register
Slice3Logic RAM
Shift Register
Slice3Logic
Slice3Logic
Slice3Logic RAM
Shift Register
Slice3Logic RAM
Shift Register
Slice3Logic
Slice3Logic
Slice3Logic RAM
Shift Register
Slice3Logic RAM
Shift Register
Slice3Logic
Slice3Logic
Slice3Logic RAM
Shift Register
Slice3Logic RAM
Shift Register
RAM
RAM
Distributed RAM
Distributed LUT memory– Can be loaded by configuration
Synchronous (clocked) write operation– But asynchronous (combinatorial) read
• Can make synchronous read when you
use the neighboring flip-flop
Easiest to build with the Core Generator– Automatically builds the necessary input
decode and output multiplexer logic
Memories can be initialized– Text I/O code in VHDL
– Coefficient file
– Or an initialization file placed in HDL code if inferring the memory
RAM
RAM
RAM
Slice3Logic
Slice3Logic
Slice3Logic RAM
Shift Register
Slice3Logic RAM
Shift Register
Slice3Logic
Slice3Logic
Slice3Logic RAM
Shift Register
Slice3Logic RAM
Shift Register
Slice3Logic
Slice3Logic
Slice3Logic RAM
Shift Register
Slice3Logic RAM
Shift Register
Slice3Logic
Slice3Logic
Slice3Logic RAM
Shift Register
Slice3Logic RAM
Shift Register
Slice3Logic
Slice3Logic
Slice3Logic RAM
Shift Register
Slice3Logic RAM
Shift Register
Slice3Logic
Slice3Logic
Slice3Logic RAM
Shift Register
Slice3Logic RAM
Shift Register
RAM
RAM
LogicLogic
Distributed RAM Features
Dual-Port BRAM
Dual-Port BRAM
Multiple configuration options– True dual-port, simple dual-port, single-port
Two independent ports address common data– Individual address, clock, write enable, clock enable– Independent widths for each port
300-MHz operation when using data pipeline option – All operations are synchronous; all outputs are latched– Data output has an optional internal pipeline register
• Faster clock rate, but increased latency
Byte-write enable – Enhances processor memory interfacing
Load block RAM during configuration– Reset during operation clears the registers, not the data content
Do not violate address setup time while enabled– Disable memory when address timing might be unpredictable– This also saves power
18Kb Memory
Block RAM Features
Each block RAM block can be used as
• One 18 Kb Block RAM
oror
9 Kb Block RAM
9 Kb Block RAM
9 Kb Block RAM
9 Kb Block RAM
• Two independent 9 Kb block RAMs
18 KbBlockRAM
18 KbBlockRAM
Spartan-6 FPGA Block RAM Block
True dual-port flexibility– Can perform read and write operations
simultaneously and independently on port A and port B
– Each port has its own clock, enable, and write enable– Every write also performs a read operation
• Read before write, write before read, or no output change
– Simultaneous read + write or write + write to the same location can cause data corruption• Make sure that the address and control signals are stable
during operation
Block RAM configurations – One block RAM: 16Kx1, 8Kx2, 4Kx4, 2Kx9, 1Kx18, 512x36– Or two independent 9K block RAMs: 8Kx1, 4Kx2, 2Kx4, 1Kx9, 512x18– Each port can have its own depth x width within that range
3636 Wdata A
Addr AAddr A
3636 Rdata A
Port A
3636 Wdata B
Addr BAddr B
3636 Rdata B
Port B
18 KbMemory
Array
True Dual-Port Block RAM
One read port and one write port– Natural structure for FIFOs
Allows widest implementation– 72-bit data width on 18K block RAM
• Up to a 72-bit read and write in one cycle
– 36-bit data width for 9K block RAM– Doubles the memory bandwidth per block
“Parity bits” are not dedicated for parity– All byte-wide data has an extra ninth storage bit– Can be used for parity or for any other purpose– Parity generation / checking would need LUT
logic
3636
Wdata A
Addr AAddr A
3636 Rdata A
Port A
3636
Wdata B
Addr BAddr B
3636 Rdata B
Port B
18 KbMemory
Array
Simple Dual-Port Block RAM
Each 9 K 18 K
True dual-port 8Kx1, 4Kx2, 2Kx4, 1Kx9, 512x18
16Kx1, 8Kx2, 4Kx4, 2Kx9,
1Kx18, 512x36Two fully independent read and write operations
Simple dual-port8Kx1, 4Kx2, 2Kx4,
1Kx9, 512x18, 256x36
16Kx1, 8Kx2, 4Kx4, 2Kx9,
1Kx18, 512x36, 256x72
1 read & 1 write portRead AND write in 1 cycle
Single-port8Kx1, 4Kx2, 2Kx4,
1Kx9, 512x18, 256x36
16Kx1, 8Kx2, 4Kx4, 2Kx9,
1Kx18, 512x36,256x72
1 read & 1 write portRead OR write in 1 cycle
Block RAM Configurations
Controls which byte is being written– One write enable for each byte of data and its parity bit– Useful when interfacing with processors
a0a0
10011001
ABCDABCD
AFFDAFFD
AFFDAFFDFFFFFFFF
clk
address
data
we[3:0]
memory @a0
output
Byte-write operation during write-first mode– Bytes not being written will show
an undefined value on the output
– The output truly reflects the new memory content
– Writing always implies a read• Be careful of reading when
writing
Byte-Wide Write Enable
Spartan-6 Device Distr. RAM (Kb) Block RAM (Kb) 18-Kb Block RAM Blocks
XC6SLX4 32 144 8
XC6SLX9 90 576 32
XC6SLX16 136 576 32
XC6SLX25 229 936 52
XC6SLX45 401 2,088 116
XC6SLX100 930 4,824 268
XC6SLX150 1,355 4,824 268
XC6SLX25T 229 936 52
XC6SLX45T 401 2,088 116
XC6SLX100T 930 4,824 268
XC6SLX150T 1,355 4,824 268
Spartan-6 FPGA Memory Capacity
Spartan-6 has a New dedicated memory controller block– Up to four controllers per device– Saves between 500 and 2000 LUTs and
registers versus a soft implementation
Why a hard block?– Very common design component– Benefits of a hard block
• Higher performance: 800 Mbps• Lower cost: smaller than soft logic• Lower power: compared to soft logic
– Easy to design• Abstracts away complexity of memory interfacing• CORE Generator™ tool / MIG wizard and EDK
support
*For all speed grades, except -1L
Interface Spartan-6 FPGA
DDR3 SDRAM 800 Mbps*
DDR2 SDRAM 800 Mbps*
DDR SDRAM 400 Mbps*
LP DDR 400 Mbps*
DDRDDR2DDR3LP DDR
MCBBlk
Memory Controller Block (MCB)
Memory support– DDR, DDR2, DDR3, LP DDR
standardsSimple, multi-port user interface– Six 32-bit wide user ports
• Can be concatenated up to 128 bits• Each port has 64-deep data FIFO and
4-deep command FIFO
Simple… but also programmable– Controller options
• Set user interface, calibration, addressing, and arbitration schemes
– Memory device options• Control features and timing
parameters
Automatic calibration– DQS centering– DQ per-bit de-skew– FPGA on-chip input termination
Memory Controller Block
Arbiter Controller
Data Path
PHY
Ded
icat
ed R
ou
tin
g
32-bitUni-directional
32-bitBi-directional
32-bitBi-directional
32-bitUni-directional
32-bitUni-directional
32-bitUni-directional
CMD FIFO 1CMD FIFO 2CMD FIFO 3CMD FIFO 4
CMD FIFO 0
CMD FIFO 5
MCB Features
Number of memory controllers– 2 for medium-sized devices, 4 for the two largest devices
I/O interface to a single external DRAM device: 4, 8, or 16 bits wide Internal “user interface” bus width is programmable: 32 to 128 bits
wide
LX4 LX9
LX16 LX25/T LX45/T
LX100/T LX150/T
MCB3
MCB1
MCB3
MCB1
MCB3
MCB1
MCB3
MCB1
MCB3
MCB1
MCB4
MCB5
MCB3
MCB1
MCB4
MCB5
DRAM size DRAM bus width LP DDR DDR DDR2 DDR3
128Mbx16x8x4
256Mb
x16x8
x4
512Mbx16x8x4
1Gbx16x8x4
2Gbx16x8x4
4Gb x16
MCB Options
Higher data rates than with soft-core implementations– Data rates up to 800 Mbps (DDR2, DDR3)– Maximum theoretical bandwidth up to 12.8 Gbps– Max values are for all speed grades in standard voltage devices
MemoryType
Data Rate Max Theoretical Bandwidthper Memory Controller Interface
Min Max 4-bit 8-bit 16-bit
DDR TBD * 400 Mbps(200 MHz) 1.6 Gbps 3.2 Gbps 6.4 Gbps
DDR2 TBD * 800 Mbps(400 MHz) 3.2 Gbps 6.4 Gbps 12.8 Gbps
DDR3 TBD * 800 Mbps(400 MHz) 3.2 Gbps 6.4 Gbps 12.8 Gbps
LPDDR TBD * 400 Mbps(200 MHz) 1.6 Gbps 3.2 Gbps 6.4 Gbps
MCB Performance
Calibration Module (RTL)
Simple user interface abstracts away complexity MIG / EDK wrapper delivers complete interface solution
– Internal block assembly and signal connectivity is transparent to the user
Spartan-6 FPGA
Off-Chip Memory
Spartan-6 FPGA Memory Controller Block
Arbiter Controller
Data Path De
dic
ate
d R
ou
tin
g
I/O
Clo
ck
Ne
two
rk
32-bitUni -directional
32-bitBi -directional
32-bitBi -directional
32-bitUni- directional
32-bitUni -directional
32-bitUni -directional
CMD FIFO 1CMD FIFO 2CMD FIFO 3CMD FIFO 4
CMD FIFO 0
CMD FIFO 5
p0_rd_errorp0_rd_count
p0_rd_overflowp0_rd_full
p0_rd_emptyp0_rd_data
p0_rd_enp0_rd_clk
p0_rd_errorp0_rd_count
p0_rd_overflowp0_rd_full
p0_wr_errorp0_wr_count
p0_wr_underrunp0_wr_full
p0_wr_empty
p0_wr_maskp0_wr_data
p0_wr_enp0_wr_clk
p0_wr_errorp0_wr_count
p0_cmd_enp0_cmd_clk
p0_cmd_emptyp0_cmd_full
p0_cmd_addrp0_cmd_instr
p0_cmd_bl
mcbx_dram_ckemcbx_dram_clk_nmcbx_dram_clk
mcbx_dram_dqsmcbx_dram_dqmcbx_dram_addrmcbx_dram_bamcbx_dram_ddr3_rst
mcbx_dram_udmmcbx_dram_ldm
mcbx_dram_dqs_n
mcbx_dram_odtmcbx_dram_we_nmcbx_dram_cas_nmcbx_dram_ras_nmcbx_dram_ckemcbx_dram_clk_nmcbx_dram_clk
mcbx_dram_dqsmcbx_dram_dqmcbx_dram_addrmcbx_dram_bamcbx_dram_ddr3_rst
mcbx_dram_udmmcbx_dram_ldm
mcbx_dram_dqs_n
mcbx_dram_odtmcbx_dram_we_nmcbx_dram_cas_nmcbx_dram_ras_n
IP Wrapper
I O B
P HY
User Interface
Block Diagram
PLL creates two phases of MCB system clock– SYSCLK_2X & SYSCLK_2X_180– Operate at 2X memory clock frequency
• Used for DDR I/O• Divide by 2 in MCB creates memory
clock frequency for other logic (1X clocks)
– Place MCBs on same side of device must share system clocks = same data rate
ControllerArbiter
Data Path
ControllerArbiter
Data Path
PH
Y L
aye
rP
HY
La
yer
IOB
IOB
UserInterface Memory
Interface
PLLPLL
FB
CLKIN
CLKOUT0
CLKOUT1
IBUFDS BUFPLL_MCB
: 2
2X Clks
SYSCLK_2X
SYSCLK_2X_180
: 21X Clks
MCB Block
2nd MCB BlockOn the same side of device
(Only in larger parts)
IO Clock Network
UserClks
CLK
CLKB
User interface clocks– Port clocks for command, write, and read path– Asynchronous to system clocks– FIFOs handle clock domain transfer
Clock Example:DDR2 800 Mbps2X clk = 800 MHz1X clk = 400 MHz
Design Considerations
I/O pins for MCBs are predefined– But are general-purpose I/O when a particular MCB is not used
Package selection determines access to MCBs– Higher pin count packages have more MCB blocks bonded out
Migration across devices within same package – Up or down one device density in most cases– Applies only within a device family (LX or LXT, for example)
The left and lower left MCB has the best migration path– MCB pins shared less with other functions compared to right side
Design Considerations
MCB blocks can be connected in parallel to create wider interfaces
This will require extra CLB logic
MCB blocks interface to a SINGLE memory device (x4, x8, or x16)
There is No support for two x8 MC interfacing to a x16 memory
Even for LPDDR, use an external VREF supply in the bank Supports soft calibration module input termination tuning
Use a PLL nearest the center of the device to drive the BUFPLL_MCB
Design Considerations
For ISE® tool design flow– Memory Interface Generator (MIG) wizard within the CORE Generator tool– Best for non-embedded applications– Simple GUI-driven tool for configuring MCB block– Supports all MCB memory standards (DDR3, DDR2, DDR, LPDDR)
For EDK design flow – Multi Port Memory Controller (MPMC)– Best for Embedded applications– MCB block is underlying hardware implementation of the MPMC peripheral– Simple GUI-driven tool within EDK / XPS– Supports all MCB memory standards (DDR3, DDR2, DDR, LPDDR)
Two MCB Design Flows
Easy to customize your memory controller and interface design– Memory architecture, data rate, bus width– CAS latency, burst length– I/O bank assignments– Generates RTL source code and UCF from hardware-verified IP– Delivered as part of the ISE software (CORE Generator utility)– MCB supports DDR, DDR2, DDR3, and LPDDR
Soft Memory Controller supports other additional memory interfaces
Memory Interface Generator (MIG)
Perform functional simulation
Run MIG, choose your memory parameters and generate rtl and ucf files
Optional RTL customization
Integrate/customize MIG memory RTL testbench
Customize MIG design
Open CORE Generator™
Place and route design
Timing simulation
Synthesize design
Import RTL and build options into ISE project
Verify in hardware
Integrate MIG .ucf constraints to overall design constraints file
MIG Design Flow
Enables you to customize your memory controller– Some options are specific to the
memory controller standard (such as DDR2 and DDR3)
Options for the physical layer and the FPGA controller– Debug signals– IOB options for power or speed
MIG bank selection options– Displays pins required– Restricted I/O columns are
disabled
MIG
UCF file folder– Pinout and clocking constraints– Batch file (ise_flow.bat) with
recommended build options
RTL file folder– Functional modules (physical layer, user
interface, controller, testbench)– Unencrypted for ease of customization
Simulation file folder– HDL simulation files including memory
device models Synthesis files folder
MIG Output Files
Distributed LUT RAM– Fast, localized memories– Great for small FIFOs
Block RAM– Bigger on-chip memories– Great for mid-sized buffering
Dedicated Memory Controller (MCB)– Fast connection to popular standard RAMs– Memory controller cores– Ideal for large memory requirements
Memories can be built with the Core Generator or Memory Interface Generator (MIG)
FPGAFPGA
External Memory InterfacingExternal Memory Interfacing
Distributed LUT RAMDistributed LUT RAM
High-Performance Block RAM High-Performance Block RAM
Summary
User Guides– Spartan-6 FPGA User Guide
• Describes the complete FPGA architecture, including distributed memory, block memory and the MCB
– Sparfan-6 FPGA Memory Controller User Guide• Detailed description of all MCB functionality
Xilinx Education Services courses– www.xilinx.com/training
• Xilinx tools and architecture courses• Hardware description language courses• Basic FPGA architecture, Basic HDL Coding Techniques, and other Free
videos!
Where Can I Learn More?
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