Bridging the Gap Between Design and Mask
Physics-based Model for OPC Verification
Yung Feng Cheng, Yueh lin Chou, Chuen Huei Yang and CL Lin, UMC Corporation
Bo Su, Gaurav Verma, William Volk, Mohsen Ahmadian, Hong Du, Abhishek Vikram, Scott Andrews, KLA-Tencor Corporation
Disparate inspection strategies have given way to various approaches for verifying post-OPC designs for manufacturing. However, a new paradigm has emerged in design verification that moves OPC verification from the design plane to the wafer plane, where it really matters. KLA-Tencors DesignScan system inspects the OPC decorated design by simulating how the design will be transferred to the reticle layer and how that reticle will be imaged into resist across the full focus-exposure calibration window. Building on this paradigm is a new methodology on process window monitoring for OPC databases using DesignScan and report results for a chip. This methodology will be explored in this article, along with new applications in areas such as reticle target CD specification.
IntroductionAs technology progresses towards 65 nm and beyond, optical lithography faces in-creased difficulties, and reticle enhancement techniques (RET) become imperative for multiple process layers. With RET imple-mentation, especially the optical proximity correction (OPC) technique, the mask layout deviates further from the design-intended layout. Thus, the need for linking design space with process space to ensure design-intended device integrity is even greater. For the OPC decorated design database, it is important to verify the OPC before the mask-making step. This verification step can help ensure that there are no design-re-lated defects, and it can provide a reasonable process window for a given process. Design rule or optical rule checkers have typically been used successfully to find design-related defects at best focus and exposure condi-tions. However, for full chip process window verification, there was no such system avail-able until now. The main requirements for process window monitoring are good resist modeling and inspection speed.
We previously reported an integrated ap-proach using DesignScan. In the article, we detail DesignScans defect detection capabil-
ity, model accuracy by comparison to wafer scanning electron microscopy (SEM) images, and simulation speed1. We also propose new use cases for DesignScan for design-based process monitoring and control, as well as process window impact-based mask specifications.
Uncovering pattern-dependent systematic defectsDesignScan 290 is a new inspection system from KLA-Tencor that detects pattern-dependent (feature-based) systematic defects in the lithography process window of the post-RET design. The inspection is accomplished by simulating the transfer of the design to the reticle plane and subsequently projecting the reticle image onto the photoresist. The simulations are conducted at nominal condition and at user-defined off focus-exposure conditions through the process window and beyond. The normal DesignScan inspection is a two-step process. First comes the best focus and exposure (F
0) inspection (the simulated
image to database inspection), in which the simulated resist images at the best focus and exposure condition are compared to the pre-OPC design database (design intent) to detect possible defects due to OPC decoration. Second is the process window inspection (the simulated image to simulated image inspection), which uses the best focus and exposure condition resist images as the refer-ence. In this phase, each simulation within the process window is compared to the one at nominal conditions to detect any unacceptable variation in pattern fidelity.
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The DesignScan system consists of hardware and software components, many of which are based on the KLA-Tencor TeraScan die-to-database reticle inspection system and the KLA-Tencor PROLITH simulation software. The system is confi gurable for a selected throughput target. Prior to the DesignScan inspection, the post-RET/OPC designs are converted to a proprietary KLA-Tencor format optimized for inspection throughput. During inspection, the converted design is segmented into patches and fed to the proprietary image computer, which is used for both the simulation of the design patches and the detection of defects. The image computer is a multiple processor-based supercomputer capable of simulating multiple jobs simultaneously. Design patches that fail within the process window are noted as defective not only within the process window, but anywhere in the FE space which is simulated. Defect reports are sent to the operator con-sol, which is also used for inspection setup and review.
The simulation models three distinct steps in the lithog-raphy process: the transfer of the pattern to the reticle, the formation of the aerial image, and the formation of the resist image. The models for the reticle manufac-turing process and aerial image formation, which uses vector imaging, are based on mature TeraScan technol-ogy used for die-to-database reticle inspection. The resist image formation and development are based on a proprietary fast resist model and PROLITH technology, also well developed and tested.
Each of the three models is calibrated or specifi ed sepa-rately and could be decoupled, due to the physics-based nature of those models. Physics-based models are used to simulate reticle images from the design. The aerial image model is specifi ed by providing the following basic illumination parameters: illumination wavelength, parametric or measured source shape, and objective lens NA. The resist model is calibrated by matching physi-cal parameters to tuning data. The tuning data consists of focus-exposure matrix (FEM) critical dimension (CD) data from one-dimensional lines and spaces at various pitches and sizes. Due to physics-based resist modeling, any FE condition can be selected for simulation within the calibration space (tested up to 2x process window). By contrast, empirical models have to be calibrated at each FE condition at which the simulation has to be done. Also, physics-based models require recalibration only if the physics of the process is changed, the poly-gons can be changed arbitrarily, and no recalibration is required. For empirical models used by other OPC veri-fi cation tools, a recalibration is required if the physics or the polygons are changed. This leads to a signifi cantly
reduced calibration burden for physics-based models as compared to the burden required for maintaining empirical models.
Creating the right recipeAt runtime, the user creates an inspection recipe through a menu-driven graphical user interface (GUI) shown in Figure 1. It is at this point that the design database to be inspected and the previously calibrated or specifi ed models are recalled. The user also selects the range of focus and exposure conditions to be used in the inspection during this step. Each focus and exposure condition to be simulated can be defi ned individually and need not be a regular array of points. Any segment of the design that has been converted to the DesignScan format can be inspected. The system supports the defi ni-tion of multiple inspection areas, each of which can have independent defect sensitivity settings. The sensitivity setting can be changed for each detector and each area independently. The runtime setup process typically takes less than 10 minutes.
Once the recipe is defi ned, the inspection process begins and each patch of the design is processed through the simulation and defect detection models. It is at this stage that the various simulations for each design patch are compared to the simulation at nominal conditions. The defect detection algorithm checks for the follow-ing types of defects: bridges, breaks, extra and missing printed features, minimum resist width and minimum space width (CD variation defects), line-end shortening
Figure 1: The DesignScan setup GUI. The recipe is created in a series of steps
that begin by selecting the design to be inspected.
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(LES), and interlayer overlap (ILO) defects. The defect detection is based on any topographical change between a test resist profile and the reference resist profile
A proprietary defect binning model is used to group all lithographically identical defects. This greatly improves review efficiency. During inspection, DesignScan applies lithography hierarchy to perform binning, i.e., patterns are compared within the lithographically significant dis-tance for matching and binning. The efficiencies gained by the defect binning system will be dependent on how the pattern repeats in the design, among other factors. The binning is particularly useful when certain defective pattern is repeating, like in memory devices. In the ex-ample shown below, using the SRAM design database, a reduction in the number of unique defects by a factor of one and half order of magnitude has been observed.
Review can occur after or concurrent with the inspec-tion. The defect review application shown in Figure 2 can be used to display a wide range of defect-related information, such as database images, mask images, aerial images, and resist images. The display is user-configurable and a configuration can be saved as a template and recalled later. The defects can be sorted by process window impact, as well as defect type or defect ID. It is very useful for process window monitoring to sort defects based on the process window impact. Such capability is only possible by DesignScan because one can select any FE grid for simulati