Stellaris® LM4F120H5QR Microcontroller Data Sheet

TE X AS INS TRUM E NTS - ADVANCE INFO R MAT ION

Stellaris LM4F120H5QR MicrocontrollerD ATA SHE E T

D S -LM4F 120H5 Q R- 1 2 4 5 4 . 2 4 8 0

C o p yri g h t 2 0 07-2012 Te xa s In stru me n ts In co rporated

CopyrightCopyright 2007-2012 Texas Instruments Incorporated All rights reserved. Stellaris and StellarisWare are registered trademarks of Texas Instruments Incorporated. ARM and Thumb are registered trademarks and Cortex is a trademark of ARM Limited. Other names and brands may be claimed as the property of others. ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Texas Instruments Incorporated 108 Wild Basin, Suite 350 Austin, TX 78746 http://www.ti.com/stellaris http://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm

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Stellaris LM4F120H5QR Microcontroller

Table of ContentsRevision History ............................................................................................................................. 34 About This Document .................................................................................................................... 38Audience .............................................................................................................................................. About This Manual ................................................................................................................................ Related Documents ............................................................................................................................... Documentation Conventions .................................................................................................................. 38 38 38 39 41 44 47 47 49 51 55 61 63 64 64

11.1 1.2 1.3 1.3.1 1.3.2 1.3.3 1.3.4 1.3.5 1.3.6 1.3.7 1.4

Architectural Overview .......................................................................................... 41Stellaris LM4F Series Overview ..................................................................................... LM4F120H5QR Microcontroller Overview ....................................................................... LM4F120H5QR Microcontroller Features ........................................................................ ARM Cortex-M4F Processor Core .................................................................................. On-Chip Memory ........................................................................................................... Serial Communications Peripherals ................................................................................ System Integration ........................................................................................................ Analog .......................................................................................................................... JTAG and ARM Serial Wire Debug ................................................................................ Packaging and Temperature .......................................................................................... LM4F120H5QR Microcontroller Hardware Details ...........................................................

22.1 2.2 2.2.1 2.2.2 2.2.3 2.2.4 2.3 2.3.1 2.3.2 2.3.3 2.3.4 2.3.5 2.3.6 2.4 2.4.1 2.4.2 2.4.3 2.4.4 2.4.5 2.4.6 2.4.7 2.5 2.5.1 2.5.2 2.5.3 2.5.4

The Cortex-M4F Processor ................................................................................... 65Block Diagram .............................................................................................................. 66 Overview ...................................................................................................................... 67 System-Level Interface .................................................................................................. 67 Integrated Configurable Debug ...................................................................................... 67 Trace Port Interface Unit (TPIU) ..................................................................................... 68 Cortex-M4F System Component Details ......................................................................... 68 Programming Model ...................................................................................................... 69 Processor Mode and Privilege Levels for Software Execution ........................................... 69 Stacks .......................................................................................................................... 70 Register Map ................................................................................................................ 70 Register Descriptions .................................................................................................... 72 Exceptions and Interrupts .............................................................................................. 88 Data Types ................................................................................................................... 88 Memory Model .............................................................................................................. 88 Memory Regions, Types and Attributes ........................................................................... 90 Memory System Ordering of Memory Accesses .............................................................. 91 Behavior of Memory Accesses ....................................................................................... 91 Software Ordering of Memory Accesses ......................................................................... 92 Bit-Banding ................................................................................................................... 93 Data Storage ................................................................................................................ 95 Synchronization Primitives ............................................................................................. 96 Exception Model ........................................................................................................... 97 Exception States ........................................................................................................... 98 Exception Types ............................................................................................................ 98 Exception Handlers ..................................................................................................... 102 Vector Table ................................................................................................................ 102

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Table of Contents

2.5.5 2.5.6 2.5.7 2.6 2.6.1 2.6.2 2.6.3 2.6.4 2.7 2.7.1 2.7.2 2.7.3 2.8

Exception Priorities ...................................................................................................... Interrupt Priority Grouping ............................................................................................ Exception Entry and Return ......................................................................................... Fault Handling ............................................................................................................. Fault Types ................................................................................................................. Fault Escalation and Hard Faults .................................................................................. Fault Status Registers and Fault Address Registers ...................................................... Lockup ....................................................................................................................... Power Management .................................................................................................... Entering Sleep Modes ................................................................................................. Wake Up from Sleep Mode .......................................................................................... The Wake-Up Interrupt Controller ................................................................................. Instruction Set Summary ..............................................................................................

103 104 104 107 108 108 109 109 110 110 110 111 111

33.1 3.1.1 3.1.2 3.1.3 3.1.4 3.1.5 3.2 3.3 3.4 3.5 3.6 3.7

Cortex-M4 Peripherals ......................................................................................... 118Functional Description ................................................................................................. 118 System Timer (SysTick) ............................................................................................... 119 Nested Vectored Interrupt Controller (NVIC) .................................................................. 120 System Control Block (SCB) ........................................................................................ 121 Memory Protection Unit (MPU) ..................................................................................... 121 Floating-Point Unit (FPU) ............................................................................................. 126 Register Map .............................................................................................................. 130 System Timer (SysTick) Register Descriptions .............................................................. 133 NVIC Register Descriptions .......................................................................................... 137 System Control Block (SCB) Register Descriptions ........................................................ 152 Memory Protection Unit (MPU) Register Descriptions .................................................... 181 Floating-Point Unit (FPU) Register Descriptions ............................................................ 190

44.1 4.2 4.3 4.3.1 4.3.2 4.3.3 4.3.4 4.4 4.5 4.5.1 4.5.2

JTAG Interface ...................................................................................................... 196Block Diagram ............................................................................................................ Signal Description ....................................................................................................... Functional Description ................................................................................................. JTAG Interface Pins ..................................................................................................... JTAG TAP Controller ................................................................................................... Shift Registers ............................................................................................................ Operational Considerations .......................................................................................... Initialization and Configuration ..................................................................................... Register Descriptions .................................................................................................. Instruction Register (IR) ............................................................................................... Data Registers ............................................................................................................ Signal Description ....................................................................................................... Functional Description ................................................................................................. Device Identification .................................................................................................... Reset Control .............................................................................................................. Non-Maskable Interrupt ............................................................................................... Power Control ............................................................................................................. Clock Control .............................................................................................................. System Control ........................................................................................................... Initialization and Configuration ..................................................................................... 197 197 198 198 200 200 201 203 203 204 206 208 208 208 209 213 214 215 222 225

55.1 5.2 5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 5.2.6 5.3

System Control ..................................................................................................... 208


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5.4 5.5 5.6

Register Map .............................................................................................................. 226 System Control Register Descriptions ........................................................................... 231 System Control Legacy Register Descriptions ............................................................... 415

66.1 6.2 6.3

System Exception Module ................................................................................... 472Functional Description ................................................................................................. 472 Register Map .............................................................................................................. 472 Register Descriptions .................................................................................................. 472

77.1 7.2 7.3 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.3.6 7.3.7 7.3.8 7.3.9 7.3.10 7.3.11 7.3.12 7.4 7.4.1 7.4.2 7.4.3 7.4.4 7.4.5 7.5 7.6

Hibernation Module .............................................................................................. 480Block Diagram ............................................................................................................ Signal Description ....................................................................................................... Functional Description ................................................................................................. Register Access Timing ............................................................................................... Hibernation Clock Source ............................................................................................ System Implementation ............................................................................................... Battery Management ................................................................................................... Real-Time Clock .......................................................................................................... Battery-Backed Memory .............................................................................................. Power Control Using HIB ............................................................................................. Power Control Using VDD3ON Mode ........................................................................... Initiating Hibernate ...................................................................................................... Waking from Hibernate ................................................................................................ Arbitrary Power Removal ............................................................................................. Interrupts and Status ................................................................................................... Initialization and Configuration ..................................................................................... Initialization ................................................................................................................. RTC Match Functionality (No Hibernation) .................................................................... RTC Match/Wake-Up from Hibernation ......................................................................... External Wake-Up from Hibernation .............................................................................. RTC or External Wake-Up from Hibernation .................................................................. Register Map .............................................................................................................. Register Descriptions .................................................................................................. 481 481 482 482 483 484 485 486 487 487 488 488 488 488 488 489 489 490 490 490 491 491 492

88.1 8.2 8.2.1 8.2.2 8.2.3 8.2.4 8.3 8.4 8.5 8.6

Internal Memory ................................................................................................... 510Block Diagram ............................................................................................................ 510 Functional Description ................................................................................................. 511 SRAM ........................................................................................................................ 511 ROM .......................................................................................................................... 512 Flash Memory ............................................................................................................. 514 EEPROM .................................................................................................................... 518 Register Map .............................................................................................................. 523 Flash Memory Register Descriptions (Flash Control Offset) ............................................ 525 EEPROM Register Descriptions (EEPROM Offset) ........................................................ 543 Memory Register Descriptions (System Control Offset) .................................................. 559

99.1 9.2 9.2.1 9.2.2

Micro Direct Memory Access (DMA) ................................................................ 568Block Diagram ............................................................................................................ Functional Description ................................................................................................. Channel Assignments .................................................................................................. Priority ........................................................................................................................ 569 569 570 571


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9.2.3 9.2.4 9.2.5 9.2.6 9.2.7 9.2.8 9.2.9 9.2.10 9.3 9.3.1 9.3.2 9.3.3 9.3.4 9.3.5 9.4 9.5 9.6

Arbitration Size ............................................................................................................ 571 Request Types ............................................................................................................ 571 Channel Configuration ................................................................................................. 572 Transfer Modes ........................................................................................................... 574 Transfer Size and Increment ........................................................................................ 582 Peripheral Interface ..................................................................................................... 582 Software Request ........................................................................................................ 582 Interrupts and Errors .................................................................................................... 583 Initialization and Configuration ..................................................................................... 583 Module Initialization ..................................................................................................... 583 Configuring a Memory-to-Memory Transfer ................................................................... 584 Configuring a Peripheral for Simple Transmit ................................................................ 585 Configuring a Peripheral for Ping-Pong Receive ............................................................ 587 Configuring Channel Assignments ................................................................................ 589 Register Map .............................................................................................................. 589 DMA Channel Control Structure ................................................................................. 591 DMA Register Descriptions ........................................................................................ 598

1010.1 10.2 10.2.1 10.2.2 10.2.3 10.2.4 10.2.5 10.2.6 10.3 10.4 10.5

General-Purpose Input/Outputs (GPIOs) ........................................................... 632Signal Description ....................................................................................................... 632 Functional Description ................................................................................................. 634 Data Control ............................................................................................................... 636 Interrupt Control .......................................................................................................... 637 Mode Control .............................................................................................................. 638 Commit Control ........................................................................................................... 639 Pad Control ................................................................................................................. 639 Identification ............................................................................................................... 639 Initialization and Configuration ..................................................................................... 639 Register Map .............................................................................................................. 640 Register Descriptions .................................................................................................. 643

1111.1 11.2 11.3 11.3.1 11.3.2 11.3.3 11.3.4 11.3.5 11.3.6 11.3.7 11.4 11.4.1 11.4.2 11.4.3 11.4.4 11.4.5 11.5 11.6

General-Purpose Timers ...................................................................................... 686Block Diagram ............................................................................................................ 687 Signal Description ....................................................................................................... 688 Functional Description ................................................................................................. 689 GPTM Reset Conditions .............................................................................................. 690 Timer Modes ............................................................................................................... 690 Wait-for-Trigger Mode .................................................................................................. 700 Synchronizing GP Timer Blocks ................................................................................... 701 DMA Operation ........................................................................................................... 702 Accessing Concatenated 16/32-Bit GPTM Register Values ............................................ 702 Accessing Concatenated 32/64-Bit Wide GPTM Register Values .................................... 702 Initialization and Configuration ..................................................................................... 704 One-Shot/Periodic Timer Mode .................................................................................... 704 Real-Time Clock (RTC) Mode ...................................................................................... 705 Input Edge-Count Mode ............................................................................................... 705 Input Edge Timing Mode .............................................................................................. 706 PWM Mode ................................................................................................................. 706 Register Map .............................................................................................................. 707 Register Descriptions .................................................................................................. 708


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1212.1 12.2 12.2.1 12.3 12.4 12.5

Watchdog Timers ................................................................................................. 756Block Diagram ............................................................................................................ Functional Description ................................................................................................. Register Access Timing ............................................................................................... Initialization and Configuration ..................................................................................... Register Map .............................................................................................................. Register Descriptions .................................................................................................. 757 757 758 758 758 759

1313.1 13.2 13.3 13.3.1 13.3.2 13.3.3 13.3.4 13.3.5 13.3.6 13.3.7 13.4 13.4.1 13.4.2 13.5 13.6

Analog-to-Digital Converter (ADC) ..................................................................... 781Block Diagram ............................................................................................................ 782 Signal Description ....................................................................................................... 783 Functional Description ................................................................................................. 784 Sample Sequencers .................................................................................................... 784 Module Control ............................................................................................................ 785 Hardware Sample Averaging Circuit ............................................................................. 788 Analog-to-Digital Converter .......................................................................................... 788 Differential Sampling ................................................................................................... 791 Internal Temperature Sensor ........................................................................................ 793 Digital Comparator Unit ............................................................................................... 794 Initialization and Configuration ..................................................................................... 798 Module Initialization ..................................................................................................... 798 Sample Sequencer Configuration ................................................................................. 799 Register Map .............................................................................................................. 799 Register Descriptions .................................................................................................. 801

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Universal Asynchronous Receivers/Transmitters (UARTs) ............................. 861862 862 863 863 864 865 865 866 866 867 869 869 870 871 871 871 872 874 925 925 926 926 927

14.1 Block Diagram ............................................................................................................ 14.2 Signal Description ....................................................................................................... 14.3 Functional Description ................................................................................................. 14.3.1 Transmit/Receive Logic ............................................................................................... 14.3.2 Baud-Rate Generation ................................................................................................. 14.3.3 Data Transmission ...................................................................................................... 14.3.4 Serial IR (SIR) ............................................................................................................. 14.3.5 ISO 7816 Support ....................................................................................................... 14.3.6 Modem Handshake Support ......................................................................................... 14.3.7 LIN Support ................................................................................................................ 14.3.8 9-Bit UART Mode ........................................................................................................ 14.3.9 FIFO Operation ........................................................................................................... 14.3.10 Interrupts .................................................................................................................... 14.3.11 Loopback Operation .................................................................................................... 14.3.12 DMA Operation ........................................................................................................... 14.4 Initialization and Configuration ..................................................................................... 14.5 Register Map .............................................................................................................. 14.6 Register Descriptions ..................................................................................................

1515.1 15.2 15.3 15.3.1 15.3.2

Synchronous Serial Interface (SSI) .................................................................... 924Block Diagram ............................................................................................................ Signal Description ....................................................................................................... Functional Description ................................................................................................. Bit Rate Generation ..................................................................................................... FIFO Operation ...........................................................................................................


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15.3.3 15.3.4 15.3.5 15.4 15.5 15.6

Interrupts .................................................................................................................... Frame Formats ........................................................................................................... DMA Operation ........................................................................................................... Initialization and Configuration ..................................................................................... Register Map .............................................................................................................. Register Descriptions ..................................................................................................

927 928 935 936 937 938

1616.1 16.2 16.3 16.3.1 16.3.2 16.3.3 16.3.4 16.3.5 16.4 16.5 16.6 16.7 16.8

Inter-Integrated Circuit (I2C) Interface ................................................................ 967Block Diagram ............................................................................................................ 968 Signal Description ....................................................................................................... 968 Functional Description ................................................................................................. 969 I2C Bus Functional Overview ........................................................................................ 969 Available Speed Modes ............................................................................................... 973 Interrupts .................................................................................................................... 974 Loopback Operation .................................................................................................... 975 Command Sequence Flow Charts ................................................................................ 976 Initialization and Configuration ..................................................................................... 984 Register Map .............................................................................................................. 985 Register Descriptions (I2C Master) ............................................................................... 986 Register Descriptions (I2C Slave) ............................................................................... 1001 Register Descriptions (I2C Status and Control) ............................................................ 1011

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Controller Area Network (CAN) Module ........................................................... 1014

17.1 Block Diagram ........................................................................................................... 1015 17.2 Signal Description ..................................................................................................... 1015 17.3 Functional Description ............................................................................................... 1016 17.3.1 Initialization ............................................................................................................... 1017 17.3.2 Operation .................................................................................................................. 1017 17.3.3 Transmitting Message Objects ................................................................................... 1018 17.3.4 Configuring a Transmit Message Object ...................................................................... 1019 17.3.5 Updating a Transmit Message Object ......................................................................... 1020 17.3.6 Accepting Received Message Objects ........................................................................ 1020 17.3.7 Receiving a Data Frame ............................................................................................ 1021 17.3.8 Receiving a Remote Frame ........................................................................................ 1021 17.3.9 Receive/Transmit Priority ........................................................................................... 1021 17.3.10 Configuring a Receive Message Object ...................................................................... 1022 17.3.11 Handling of Received Message Objects ...................................................................... 1023 17.3.12 Handling of Interrupts ................................................................................................ 1025 17.3.13 Test Mode ................................................................................................................. 1026 17.3.14 Bit Timing Configuration Error Considerations ............................................................. 1028 17.3.15 Bit Time and Bit Rate ................................................................................................. 1028 17.3.16 Calculating the Bit Timing Parameters ........................................................................ 1030 17.4 Register Map ............................................................................................................ 1033 17.5 CAN Register Descriptions ......................................................................................... 1034

1818.1 18.2 18.3 18.3.1

Universal Serial Bus (USB) Controller ............................................................. 1064Block Diagram ........................................................................................................... Signal Description ..................................................................................................... Functional Description ............................................................................................... Operation .................................................................................................................. 1064 1065 1065 1065


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18.3.2 18.4 18.4.1 18.5 18.6

DMA Operation ......................................................................................................... 1070 Initialization and Configuration .................................................................................... 1071 Endpoint Configuration .............................................................................................. 1071 Register Map ............................................................................................................ 1072 Register Descriptions ................................................................................................. 1075

1919.1 19.2 19.3 19.3.1 19.4 19.5 19.6

Analog Comparators .......................................................................................... 1121Block Diagram ........................................................................................................... Signal Description ..................................................................................................... Functional Description ............................................................................................... Internal Reference Programming ................................................................................ Initialization and Configuration .................................................................................... Register Map ............................................................................................................ Register Descriptions ................................................................................................. 1122 1122 1123 1123 1126 1126 1127

20 2121.1

Pin Diagram ........................................................................................................ 1136 Signal Tables ...................................................................................................... 1137Connections for Unused Signals ................................................................................. 1156

22 23

Operating Characteristics ................................................................................. 1157 Electrical Characteristics .................................................................................. 1158

23.1 Maximum Ratings ...................................................................................................... 1158 23.2 Recommended Operating Conditions ......................................................................... 1159 23.3 Load Conditions ........................................................................................................ 1160 23.4 JTAG and Boundary Scan .......................................................................................... 1161 23.5 Power and Brown-Out ............................................................................................... 1162 23.6 Reset ........................................................................................................................ 1163 23.7 On-Chip Low Drop-Out (LDO) Regulator ..................................................................... 1164 23.8 Clocks ...................................................................................................................... 1165 23.8.1 PLL Specifications ..................................................................................................... 1165 23.8.2 PIOSC Specifications ................................................................................................ 1166 23.8.3 Internal 30-kHz Oscillator Specifications ..................................................................... 1166 23.8.4 Hibernation Clock Source Specifications ..................................................................... 1166 23.8.5 Main Oscillator Specifications ..................................................................................... 1167 23.8.6 System Clock Specification with ADC Operation .......................................................... 1170 23.8.7 System Clock Specification with USB Operation .......................................................... 1170 23.9 Sleep Modes ............................................................................................................. 1171 23.10 Hibernation Module ................................................................................................... 1171 23.11 Flash Memory and EEPROM ..................................................................................... 1172 23.12 Input/Output Characteristics ....................................................................................... 1173 23.13 Analog-to-Digital Converter (ADC) .............................................................................. 1174 23.14 Synchronous Serial Interface (SSI) ............................................................................. 1176 23.15 Inter-Integrated Circuit (I2C) Interface ......................................................................... 1178 23.16 Universal Serial Bus (USB) Controller ......................................................................... 1178 23.17 Analog Comparator ................................................................................................... 1178 23.18 Current Consumption ................................................................................................. 1180 23.18.1 Preliminary Current Consumption ............................................................................... 1180

A B

Register Quick Reference ................................................................................. 1182 Ordering and Contact Information ................................................................... 1224


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B.1 B.2 B.3 B.4

Ordering Information .................................................................................................. Part Markings ............................................................................................................ Kits ........................................................................................................................... Support Information ...................................................................................................

1224 1224 1224 1225

CC.1 C.1.1

Package Information .......................................................................................... 122664-Pin LQFP Package ............................................................................................... 1226 Package Dimensions ................................................................................................. 1226


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List of FiguresFigure 1-1. Figure 1-2. Figure 2-1. Figure 2-2. Figure 2-3. Figure 2-4. Figure 2-5. Figure 2-6. Figure 2-7. Figure 3-1. Figure 3-2. Figure 4-1. Figure 4-2. Figure 4-3. Figure 4-4. Figure 4-5. Figure 5-1. Figure 5-2. Figure 5-3. Figure 5-4. Figure 5-5. Figure 5-6. Figure 7-1. Figure 7-2. Figure 7-3. Figure 7-4. Figure 8-1. Figure 8-2. Figure 9-1. Figure 9-2. Figure 9-3. Figure 9-4. Figure 9-5. Figure 9-6. Figure 10-1. Figure 10-2. Figure 10-3. Figure 10-4. Figure 11-1. Figure 11-2. Figure 11-3. Figure 11-4. Figure 11-5. Figure 11-6. Figure 11-7. Stellaris LM4F Block Diagram .............................................................................. 42 Stellaris LM4F120H5QR Microcontroller High-Level Block Diagram ........................ 46 CPU Block Diagram ............................................................................................. 67 TPIU Block Diagram ............................................................................................ 68 Cortex-M4F Register Set ...................................................................................... 71 Bit-Band Mapping ................................................................................................ 95 Data Storage ....................................................................................................... 96 Vector Table ...................................................................................................... 103 Exception Stack Frame ...................................................................................... 106 SRD Use Example ............................................................................................. 124 FPU Register Bank ............................................................................................ 127 JTAG Module Block Diagram .............................................................................. 197 Test Access Port State Machine ......................................................................... 200 IDCODE Register Format ................................................................................... 206 BYPASS Register Format ................................................................................... 206 Boundary Scan Register Format ......................................................................... 207 Basic RST Configuration .................................................................................... 211 External Circuitry to Extend Power-On Reset ....................................................... 211 Reset Circuit Controlled by Switch ...................................................................... 212 Power Architecture ............................................................................................ 215 Main Clock Tree ................................................................................................ 218 Module Clock Selection ...................................................................................... 225 Hibernation Module Block Diagram ..................................................................... 481 Using a Crystal as the Hibernation Clock Source with a Single Battery Source ...... 483 Using a Dedicated Oscillator as the Hibernation Clock Source with VDD3ON Mode ................................................................................................................ 484 Using a Regulator for Both VDD and VBAT ............................................................ 485 Internal Memory Block Diagram .......................................................................... 510 EEPROM Block Diagram ................................................................................... 511 DMA Block Diagram ......................................................................................... 569 Example of Ping-Pong DMA Transaction ........................................................... 575 Memory Scatter-Gather, Setup and Configuration ................................................ 577 Memory Scatter-Gather, DMA Copy Sequence .................................................. 578 Peripheral Scatter-Gather, Setup and Configuration ............................................. 580 Peripheral Scatter-Gather, DMA Copy Sequence ............................................... 581 Digital I/O Pads ................................................................................................. 635 Analog/Digital I/O Pads ...................................................................................... 636 GPIODATA Write Example ................................................................................. 637 GPIODATA Read Example ................................................................................. 637 GPTM Module Block Diagram ............................................................................ 687 Reading the RTC Value ...................................................................................... 694 Input Edge-Count Mode Example, Counting Down ............................................... 696 16-Bit Input Edge-Time Mode Example ............................................................... 697 16-Bit PWM Mode Example ................................................................................ 699 CCP Output, GPTMTnMATCHR > GPTMTnILR ................................................... 699 CCP Output, GPTMTnMATCHR = GPTMTnILR ................................................... 700


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Figure 11-8. Figure 11-9. Figure 12-1. Figure 13-1. Figure 13-2. Figure 13-3. Figure 13-4. Figure 13-5. Figure 13-6. Figure 13-7. Figure 13-8. Figure 13-9. Figure 13-10. Figure 13-11. Figure 13-12. Figure 13-13. Figure 13-14. Figure 14-1. Figure 14-2. Figure 14-3. Figure 14-4. Figure 14-5. Figure 15-1. Figure 15-2. Figure 15-3. Figure 15-4. Figure 15-5. Figure 15-6. Figure 15-7. Figure 15-8. Figure 15-9. Figure 15-10. Figure 15-11. Figure 15-12. Figure 16-1. Figure 16-2. Figure 16-3. Figure 16-4. Figure 16-5. Figure 16-6. Figure 16-7. Figure 16-8. Figure 16-9. Figure 16-10. Figure 16-11. Figure 16-12.

CCP Output, GPTMTnILR > GPTMTnMATCHR ................................................... 700 Timer Daisy Chain ............................................................................................. 701 WDT Module Block Diagram .............................................................................. 757 Implementation of Two ADC Blocks .................................................................... 782 ADC Module Block Diagram ............................................................................... 783 ADC Sample Phases ......................................................................................... 786 Doubling the ADC Sample Rate .......................................................................... 787 Skewed Sampling .............................................................................................. 787 Sample Averaging Example ............................................................................... 788 ADC Input Equivalency Diagram ......................................................................... 789 ADC Voltage Reference ..................................................................................... 790 ADC Conversion Result ..................................................................................... 791 Differential Voltage Representation ..................................................................... 793 Internal Temperature Sensor Characteristic ......................................................... 794 Low-Band Operation (CIC=0x0) .......................................................................... 796 Mid-Band Operation (CIC=0x1) .......................................................................... 797 High-Band Operation (CIC=0x3) ......................................................................... 798 UART Module Block Diagram ............................................................................. 862 UART Character Frame ..................................................................................... 864 IrDA Data Modulation ......................................................................................... 866 LIN Message ..................................................................................................... 868 LIN Synchronization Field ................................................................................... 869 SSI Module Block Diagram ................................................................................. 925 TI Synchronous Serial Frame Format (Single Transfer) ........................................ 929 TI Synchronous Serial Frame Format (Continuous Transfer) ................................ 929 Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................... 930 Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................. 930 Freescale SPI Frame Format with SPO=0 and SPH=1 ......................................... 931 Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............... 932 Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........ 932 Freescale SPI Frame Format with SPO=1 and SPH=1 ......................................... 933 MICROWIRE Frame Format (Single Frame) ........................................................ 934 MICROWIRE Frame Format (Continuous Transfer) ............................................. 935 MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ............ 935 I2C Block Diagram ............................................................................................. 968 I2C Bus Configuration ........................................................................................ 969 START and STOP Conditions ............................................................................. 970 Complete Data Transfer with a 7-Bit Address ....................................................... 970 R/S Bit in First Byte ............................................................................................ 971 Data Validity During Bit Transfer on the I2C Bus ................................................... 971 High-Speed Data Format ................................................................................... 973 Master Single TRANSMIT .................................................................................. 977 Master Single RECEIVE ..................................................................................... 978 Master TRANSMIT with Repeated START ........................................................... 979 Master RECEIVE with Repeated START ............................................................. 980 Master RECEIVE with Repeated START after TRANSMIT with Repeated START .............................................................................................................. 981


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Figure 16-13. Master TRANSMIT with Repeated START after RECEIVE with Repeated START .............................................................................................................. 982 Figure 16-14. High Speed Mode Master Transmit ..................................................................... 983 Figure 16-15. Slave Command Sequence ................................................................................ 984 Figure 17-1. CAN Controller Block Diagram .......................................................................... 1015 Figure 17-2. CAN Data/Remote Frame ................................................................................. 1016 Figure 17-3. Message Objects in a FIFO Buffer .................................................................... 1025 Figure 17-4. CAN Bit Time ................................................................................................... 1029 Figure 18-1. USB Module Block Diagram ............................................................................. 1064 Figure 19-1. Analog Comparator Module Block Diagram ....................................................... 1122 Figure 19-2. Structure of Comparator Unit ............................................................................ 1123 Figure 19-3. Comparator Internal Reference Structure .......................................................... 1124 Figure 20-1. 64-Pin LQFP Package Pin Diagram .................................................................. 1136 Figure 23-1. ESD Protection on GPIOs and XOSCn Pins ...................................................... 1159 Figure 23-2. ESD Protection on Non-Power, Non-GPIO, and Non-XOSCn Pins ...................... 1159 Figure 23-3. Load Conditions ............................................................................................... 1160 Figure 23-4. JTAG Test Clock Input Timing ........................................................................... 1161 Figure 23-5. JTAG Test Access Port (TAP) Timing ................................................................ 1162 Figure 23-6. Power-On and Brown-Out Reset and Voltage Parameters .................................. 1163 Figure 23-7. Brown-Out Reset Timing .................................................................................. 1163 Figure 23-8. External Reset Timing (RST) ............................................................................ 1164 Figure 23-9. Software Reset Timing ..................................................................................... 1164 Figure 23-10. Watchdog Reset Timing ................................................................................... 1164 Figure 23-11. MOSC Failure Reset Timing ............................................................................. 1164 Figure 23-12. Hibernation Module Timing ............................................................................... 1172 Figure 23-13. ADC Input Equivalency Diagram ....................................................................... 1176 Figure 23-14. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .................................................................................................. 1177 Figure 23-15. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............... 1177 Figure 23-16. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................... 1177 Figure 23-17. I2C Timing ....................................................................................................... 1178 Figure C-1. Stellaris LM4F120H5QR 64-Pin LQFP Package ................................................ 1226


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List of TablesTable 1. Table 2. Table 1-1. Table 1-2. Table 1-3. Table 1-4. Table 2-1. Table 2-2. Table 2-3. Table 2-4. Table 2-5. Table 2-6. Table 2-7. Table 2-8. Table 2-9. Table 2-10. Table 2-11. Table 2-12. Table 2-13. Table 3-1. Table 3-2. Table 3-3. Table 3-4. Table 3-5. Table 3-6. Table 3-7. Table 3-8. Table 3-9. Table 3-10. Table 4-1. Table 4-2. Table 4-3. Table 5-1. Table 5-2. Table 5-3. Table 5-4. Table 5-5. Table 5-6. Table 5-7. Table 5-8. Table 6-1. Table 7-1. Table 7-2. Table 7-3. Table 7-4. Table 7-5. Revision History .................................................................................................. 34 Documentation Conventions ................................................................................ 39 Stellaris LM4F Device Series ................................................................................ 42 Stellaris LM4F12x Series ..................................................................................... 43 Stellaris LM4F Family of Devices .......................................................................... 43 Stellaris LM4F120H5QR Microcontroller Features ................................................. 45 Summary of Processor Mode, Privilege Level, and Stack Use ................................ 70 Processor Register Map ....................................................................................... 71 PSR Register Combinations ................................................................................. 77 Memory Map ....................................................................................................... 88 Memory Access Behavior ..................................................................................... 91 SRAM Memory Bit-Banding Regions .................................................................... 93 Peripheral Memory Bit-Banding Regions ............................................................... 93 Exception Types .................................................................................................. 99 Interrupts .......................................................................................................... 100 Exception Return Behavior ................................................................................. 107 Faults ............................................................................................................... 108 Fault Status and Fault Address Registers ............................................................ 109 Cortex-M4F Instruction Summary ....................................................................... 111 Core Peripheral Register Regions ....................................................................... 118 Memory Attributes Summary .............................................................................. 122 TEX, S, C, and B Bit Field Encoding ................................................................... 124 Cache Policy for Memory Attribute Encoding ....................................................... 125 AP Bit Field Encoding ........................................................................................ 125 Memory Region Attributes for Stellaris Microcontrollers ........................................ 126 QNaN and SNaN Handling ................................................................................. 129 Peripherals Register Map ................................................................................... 130 Interrupt Priority Levels ...................................................................................... 160 Example SIZE Field Values ................................................................................ 188 JTAG_SWD_SWO Signals (64LQFP) ................................................................. 197 JTAG Port Pins State after Power-On Reset or RST assertion .............................. 198 JTAG Instruction Register Commands ................................................................. 204 System Control & Clocks Signals (64LQFP) ........................................................ 208 Reset Sources ................................................................................................... 209 Clock Source Options ........................................................................................ 216 Possible System Clock Frequencies Using the SYSDIV Field ............................... 219 Examples of Possible System Clock Frequencies Using the SYSDIV2 Field .......... 219 Examples of Possible System Clock Frequencies with DIV400=1 ......................... 220 System Control Register Map ............................................................................. 226 RCC2 Fields that Override RCC Fields ............................................................... 251 System Exception Register Map ......................................................................... 472 Hibernate Signals (64LQFP) ............................................................................... 481 Counter Behavior with a TRIM Value of 0x8003 ................................................... 486 Counter Behavior with a TRIM Value of 0x7FFC .................................................. 487 Hibernation Module Clock Operation ................................................................... 490 Hibernation Module Register Map ....................................................................... 491


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Table 8-1. Table 8-2. Table 8-3. Table 9-1. Table 9-2. Table 9-3. Table 9-4. Table 9-5. Table 9-6. Table 9-7. Table 9-8. Table 9-9. Table 9-10. Table 9-11. Table 9-12.

Flash Memory Protection Policy Combinations .................................................... 515 User-Programmable Flash Memory Resident Registers ....................................... 518 Flash Register Map ............................................................................................ 523 DMA Channel Assignments .............................................................................. 570 Request Type Support ....................................................................................... 572 Control Structure Memory Map ........................................................................... 573 Channel Control Structure .................................................................................. 573 DMA Read Example: 8-Bit Peripheral ................................................................ 582 DMA Interrupt Assignments .............................................................................. 583 Channel Control Structure Offsets for Channel 30 ................................................ 584 Channel Control Word Configuration for Memory Transfer Example ...................... 584 Channel Control Structure Offsets for Channel 7 .................................................. 585 Channel Control Word Configuration for Peripheral Transmit Example .................. 586 Primary and Alternate Channel Control Structure Offsets for Channel 8 ................. 587 Channel Control Word Configuration for Peripheral Ping-Pong Receive Example ............................................................................................................ 588 Table 9-13. DMA Register Map .......................................................................................... 590 Table 10-1. GPIO Pins With Non-Zero Reset Values .............................................................. 633 Table 10-2. GPIO Pins and Alternate Functions (64LQFP) ..................................................... 633 Table 10-3. GPIO Pad Configuration Examples ..................................................................... 639 Table 10-4. GPIO Interrupt Configuration Example ................................................................ 640 Table 10-5. GPIO Pins With Non-Zero Reset Values .............................................................. 641 Table 10-6. GPIO Register Map ........................................................................................... 641 Table 10-7. GPIO Pins With Non-Zero Reset Values .............................................................. 653 Table 10-8. GPIO Pins With Non-Zero Reset Values .............................................................. 659 Table 10-9. GPIO Pins With Non-Zero Reset Values .............................................................. 661 Table 10-10. GPIO Pins With Non-Zero Reset Values .............................................................. 664 Table 10-11. GPIO Pins With Non-Zero Reset Values .............................................................. 670 Table 11-1. Available CCP Pins ............................................................................................ 687 Table 11-2. General-Purpose Timers Signals (64LQFP) ......................................................... 688 Table 11-3. General-Purpose Timer Capabilities .................................................................... 690 Table 11-4. Counter Values When the Timer is Enabled in Periodic or One-Shot Modes .......... 691 Table 11-5. 16-Bit Timer With Prescaler Configurations ......................................................... 692 Table 11-6. 32-Bit Timer (configured in 32/64-bit mode) With Prescaler Configurations ............ 692 Table 11-7. Counter Values When the Timer is Enabled in RTC Mode .................................... 693 Table 11-8. Counter Values When the Timer is Enabled in Input Edge-Count Mode ................. 695 Table 11-9. Counter Values When the Timer is Enabled in Input Event-Count Mode ................ 696 Table 11-10. Counter Values When the Timer is Enabled in PWM Mode ................................... 698 Table 11-11. Timeout Actions for GPTM Modes ...................................................................... 701 Table 11-12. Timers Register Map .......................................................................................... 707 Table 12-1. Watchdog Timers Register Map .......................................................................... 759 Table 13-1. ADC Signals (64LQFP) ...................................................................................... 783 Table 13-2. Samples and FIFO Depth of Sequencers ............................................................ 784 Table 13-3. Differential Sampling Pairs ................................................................................. 791 Table 13-4. ADC Register Map ............................................................................................. 799 Table 14-1. UART Signals (64LQFP) .................................................................................... 863 Table 14-2. Flow Control Mode ............................................................................................. 867 Table 14-3. UART Register Map ........................................................................................... 873


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Table 15-1. Table 15-2. Table 16-1. Table 16-2. Table 16-3. Table 16-4. Table 16-5. Table 17-1. Table 17-2. Table 17-3. Table 17-4. Table 17-5. Table 18-1. Table 18-2. Table 18-3. Table 18-4. Table 18-5. Table 19-1. Table 19-2. Table 19-3. Table 19-4. Table 19-5. Table 21-1. Table 21-2. Table 21-3. Table 21-4. Table 21-5. Table 21-6. Table 21-7. Table 22-1. Table 22-2. Table 22-3. Table 23-1. Table 23-2. Table 23-3. Table 23-4. Table 23-5. Table 23-6. Table 23-7. Table 23-8. Table 23-9. Table 23-10. Table 23-11. Table 23-12. Table 23-13. Table 23-14.

SSI Signals (64LQFP) ........................................................................................ 926 SSI Register Map .............................................................................................. 937 I2C Signals (64LQFP) ........................................................................................ 968 Examples of I2C Master Timer Period versus Speed Mode ................................... 974 Examples of I2C Master Timer Period in High-Speed Mode .................................. 974 Inter-Integrated Circuit (I2C) Interface Register Map ............................................. 985 Write Field Decoding for I2CMCS[3:0] Field ......................................................... 991 Controller Area Network Signals (64LQFP) ........................................................ 1016 Message Object Configurations ........................................................................ 1021 CAN Protocol Ranges ...................................................................................... 1029 CANBIT Register Values .................................................................................. 1029 CAN Register Map ........................................................................................... 1033 USB Signals (64LQFP) .................................................................................... 1065 Remainder (MAXLOAD/4) ................................................................................ 1070 Actual Bytes Read ........................................................................................... 1071 Packet Sizes That Clear RXRDY ...................................................................... 1071 Universal Serial Bus (USB) Controller Register Map ........................................... 1072 Analog Comparators Signals (64LQFP) ............................................................. 1122 Internal Reference Voltage and ACREFCTL Field Values ................................... 1124 Analog Comparator Voltage Reference Characteristics, VDDA = 3.3V, EN= 1, and RNG = 0 .......................................................................................................... 1125 Analog Comparator Voltage Reference Characteristics, VDDA = 3.3V, EN= 1, and RNG = 1 .......................................................................................................... 1125 Analog Comparators Register Map ................................................................... 1126 GPIO Pins With Default Alternate Functions ...................................................... 1137 Signals by Pin Number ..................................................................................... 1138 Signals by Signal Name ................................................................................... 1143 Signals by Function, Except for GPIO ............................................................... 1148 GPIO Pins and Alternate Functions ................................................................... 1152 Possible Pin Assignments for Alternate Functions .............................................. 1154 Connections for Unused Signals (64-Pin LQFP) ................................................. 1156 Temperature Characteristics ............................................................................. 1157 Thermal Characteristics ................................................................................... 1157 ESD Absolute Maximum Ratings ...................................................................... 1157 Maximum Ratings ............................................................................................ 1158 Recommended DC Operating Conditions .......................................................... 1159 GPIO Current Restrictions ................................................................................ 1160 GPIO Package Side Assignments ..................................................................... 1160 JTAG Characteristics ....................................................................................... 1161 Power Characteristics ...................................................................................... 1162 Reset Characteristics ....................................................................................... 1163 LDO Regulator Characteristics ......................................................................... 1164 Phase Locked Loop (PLL) Characteristics ......................................................... 1165 Actual PLL Frequency ...................................................................................... 1165 PIOSC Clock Characteristics ............................................................................ 1166 30-kHz Clock Characteristics ............................................................................ 1166 HIB Oscillator Input Characteristics ................................................................... 1166 Main Oscillator Input Characteristics ................................................................. 1167


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Table 23-15. Table 23-16. Table 23-17. Table 23-18. Table 23-19. Table 23-20. Table 23-21. Table 23-22. Table 23-23. Table 23-24. Table 23-25. Table 23-26. Table 23-27. Table 23-28. Table 23-29. Table 23-30.

Crystal Parameters .......................................................................................... 1169 Supported MOSC Crystal Frequencies .............................................................. 1169 System Clock Characteristics with ADC Operation ............................................. 1170 System Clock Characteristics with USB Operation ............................................. 1170 Sleep Modes AC Characteristics ....................................................................... 1171 Hibernation Module Battery Characteristics ....................................................... 1171 Hibernation Module AC Characteristics ............................................................. 1171 Flash Memory Characteristics ........................................................................... 1172 EEPROM Characteristics ................................................................................. 1172 GPIO Module Characteristics ............................................................................ 1173 ADC Electrical Characteristics .......................................................................... 1174 SSI Characteristics .......................................................................................... 1176 I2C Characteristics ........................................................................................... 1178 Analog Comparator Characteristics ................................................................... 1178 Analog Comparator Voltage Reference Characteristics ...................................... 1179 Analog Comparator Voltage Reference Characteristics, VDDA = 3.3V, EN= 1, and RNG = 0 .......................................................................................................... 1179 Table 23-31. Analog Comparator Voltage Reference Characteristics, VDDA = 3.3V, EN= 1, and RNG = 1 .......................................................................................................... 1179 Table 23-32. Preliminary Current Consumption ..................................................................... 1180 Table B-1. Part Ordering Information ................................................................................. 1224


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List of RegistersThe Cortex-M4F Processor ........................................................................................................... 65Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Cortex General-Purpose Register 0 (R0) ........................................................................... 73 Cortex General-Purpose Register 1 (R1) ........................................................................... 73 Cortex General-Purpose Register 2 (R2) ........................................................................... 73 Cortex General-Purpose Register 3 (R3) ........................................................................... 73 Cortex General-Purpose Register 4 (R4) ........................................................................... 73 Cortex General-Purpose Register 5 (R5) ........................................................................... 73 Cortex General-Purpose Register 6 (R6) ........................................................................... 73 Cortex General-Purpose Register 7 (R7) ........................................................................... 73 Cortex General-Purpose Register 8 (R8) ........................................................................... 73 Cortex General-Purpose Register 9 (R9) ........................................................................... 73 Cortex General-Purpose Register 10 (R10) ....................................................................... 73 Cortex General-Purpose Register 11 (R11) ........................................................................ 73 Cortex General-Purpose Register 12 (R12) ....................................................................... 73 Stack Pointer (SP) ........................................................................................................... 74 Link Register (LR) ............................................................................................................ 75 Program Counter (PC) ..................................................................................................... 76 Program Status Register (PSR) ........................................................................................ 77 Priority Mask Register (PRIMASK) .................................................................................... 81 Fault Mask Register (FAULTMASK) .................................................................................. 82 Base Priority Mask Register (BASEPRI) ............................................................................ 83 Control Register (CONTROL) ........................................................................................... 84 Floating-Point Status Control (FPSC) ................................................................................ 86 SysTick Control and Status Register (STCTRL), offset 0x010 ........................................... 134 SysTick Reload Value Register (STRELOAD), offset 0x014 .............................................. 136 SysTick Current Value Register (STCURRENT), offset 0x018 ........................................... 137 Interrupt 0-31 Set Enable (EN0), offset 0x100 .................................................................. 138 Interrupt 32-63 Set Enable (EN1), offset 0x104 ................................................................ 138 Interrupt 64-95 Set Enable (EN2), offset 0x108 ................................................................ 138 Interrupt 96-127 Set Enable (EN3), offset 0x10C ............................................................. 138 Interrupt 128-138 Set Enable (EN4), offset 0x110 ............................................................ 139 Interrupt 0-31 Clear Enable (DIS0), offset 0x180 .............................................................. 140 Interrupt 32-63 Clear Enable (DIS1), offset 0x184 ............................................................ 140 Interrupt 64-95 Clear Enable (DIS2), offset 0x188 ............................................................ 140 Interrupt 96-127 Clear Enable (DIS3), offset 0x18C .......................................................... 140 Interrupt 128-138 Clear Enable (DIS4), offset 0x190 ........................................................ 141 Interrupt 0-31 Set Pending (PEND0), offset 0x200 ........................................................... 142 Interrupt 32-63 Set Pending (PEND1), offset 0x204 ......................................................... 142 Interrupt 64-95 Set Pending (PEND2), offset 0x208 ......................................................... 142 Interrupt 96-127 Set Pending (PEND3), offset 0x20C ....................................................... 142 Interrupt 128-138 Set Pending (PEND4), offset 0x210 ...................................................... 143 Interrupt 0-31 Clear Pending (UNPEND0), offset 0x280 ................................................... 144 Interrupt 32-63 Clear Pending (UNPEND1), offset 0x284 .................................................. 144 Interrupt 64-95 Clear Pending (UNPEND2), offset 0x288 .................................................. 144

Cortex-M4 Peripherals ................................................................................................................. 118


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Register 22: Register 23: Register 24: Register 25: Register 26: Register 27: Register 28: Register 29: Register 30: Register 31: Register 32: Register 33: Register 34: Register 35: Register 36: Register 37: Register 38: Register 39: Register 40: Register 41: Register 42: Register 43: Register 44: Register 45: Register 46: Register 47: Register 48: Register 49: Register 50: Register 51: Register 52: Register 53: Register 54: Register 55: Register 56: Register 57: Register 58: Register 59: Register 60: Register 61: Register 62: Register 63: Register 64: Register 65: Register 66: Register 67: Register 68: Register 69:

Interrupt 96-127 Clear Pending (UNPEND3), offset 0x28C ............................................... 144 Interrupt 128-138 Clear Pending (UNPEND4), offset 0x290 .............................................. 145 Interrupt 0-31 Active Bit (ACTIVE0), offset 0x300 ............................................................. 146 Interrupt 32-63 Active Bit (ACTIVE1), offset 0x304 ........................................................... 146 Interrupt 64-95 Active Bit (ACTIVE2), offset 0x308 ........................................................... 146 Interrupt 96-127 Active Bit (ACTIVE3), offset 0x30C ........................................................ 146 Interrupt 128-138 Active Bit (ACTIVE4), offset 0x310 ....................................................... 147 Interrupt 0-3 Priority (PRI0), offset 0x400 ......................................................................... 148 Interrupt 4-7 Priority (PRI1), offset 0x404 ......................................................................... 148 Interrupt 8-11 Priority (PRI2), offset 0x408 ....................................................................... 148 Interrupt 12-15 Priority (PRI3), offset 0x40C .................................................................... 148 Interrupt 16-19 Priority (PRI4), offset 0x410 ..................................................................... 148 Interrupt 20-23 Priority (PRI5), offset 0x414 ..................................................................... 148 Interrupt 24-27 Priority (PRI6), offset 0x418 ..................................................................... 148 Interrupt 28-31 Priority (PRI7), offset 0x41C .................................................................... 148 Interrupt 32-35 Priority (PRI8), offset 0x420 ..................................................................... 148 Interrupt 36-39 Priority (PRI9), offset 0x424 ..................................................................... 148 Interrupt 40-43 Priority (PRI10), offset 0x428 ................................................................... 148 Interrupt 44-47 Priority (PRI11), offset 0x42C ................................................................... 148 Interrupt 48-51 Priority (PRI12), offset 0x430 ................................................................... 148 Interrupt 52-55 Priority (PRI13), offset 0x434 ................................................................... 148 Interrupt 56-59 Priority (PRI14), offset 0x438 ................................................................... 148 Interrupt 60-63 Priority (PRI15), offset 0x43C .................................................................. 148 Interrupt 64-67 Priority (PRI16), offset 0x440 ................................................................... 150 Interrupt 68-71 Priority (PRI17), offset 0x444 ................................................................... 150 Interrupt 72-75 Priority (PRI18), offset 0x448 ................................................................... 150 Interrupt 76-79 Priority (PRI19), offset 0x44C .................................................................. 150 Interrupt 80-83 Priority (PRI20), offset 0x450 ..................................