(PPT) Studio Session 1: Introduction to VHDL and related Tools EE19D

Studio Session 1: Introduction to VHDL and related Tools EE19D – 25/01/2005

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Studio Session 1: Introduction to VHDL and related Tools

EE19D – 25/01/2005

Topic

Definitions Visual Introduction of VHDL using EVITA (

www.aldec.com) Getting started with Xilinx ISE Tool Simulation of VHDL Models with Moldelsim

Page 3: Studio Session 1: Introduction to VHDL and related Tools EE19D – 25/01/2005

Definition of an HDL

Def: A high level programming language used to model hardware.– special hardware related constructs– digital (now) and analog (near future)– models used for documentation, simulation,

synthesis, and test generation– have been extended to the system design level

Page 4: Studio Session 1: Introduction to VHDL and related Tools EE19D – 25/01/2005

Language Semantics

Semantics: what is the meaning of a language construct? HDLs have different semantics for different applications:

– Simulation– Synthesis– Test

In this course we will be concerned with simulation and synthesis semantics.

Page 5: Studio Session 1: Introduction to VHDL and related Tools EE19D – 25/01/2005

VHDL VHDL = VHSIC Hardware Description Language VHSIC = Very High Speed Integrated Circuit Program DOD began development in 1983

– design exchange among VHSIC contractors– document parts with long functional life

IEEE Standardization– Standardization process began in 1985– IEEE Standard 1076 in 1987– Updated in 1993

Page 6: Studio Session 1: Introduction to VHDL and related Tools EE19D – 25/01/2005

Significance of VHDL

VHDL provides a text based approach to structured hardware modeling and design.

Analogous to high level software languages such as PASCAL, C, C++, and JAVA.

An important tool in managing the complexity of VLSI systems.

Page 7: Studio Session 1: Introduction to VHDL and related Tools EE19D – 25/01/2005

Why Use VHDL?

Reason #1: it allows textual design representation

Reason #2: Ability to model at different levels of abstraction

Page 8: Studio Session 1: Introduction to VHDL and related Tools EE19D – 25/01/2005

Abstraction Levels

SYSTEM

CHIP

GATE

CIRCUIT

SILICON

Page 9: Studio Session 1: Introduction to VHDL and related Tools EE19D – 25/01/2005

SILICON LEVEL

Page 10: Studio Session 1: Introduction to VHDL and related Tools EE19D – 25/01/2005

CIRCUIT LEVEL

SV+

Vin Vout

S Inverter

Page 11: Studio Session 1: Introduction to VHDL and related Tools EE19D – 25/01/2005

GATE LEVEL

Flip Flop

Page 12: Studio Session 1: Introduction to VHDL and related Tools EE19D – 25/01/2005

Select

REG

INC

MUX

CLK B

CLK A

Page 13: Studio Session 1: Introduction to VHDL and related Tools EE19D – 25/01/2005

CHIP LEVEL

RAM

Par.Port

USART

Int.Con.

Page 14: Studio Session 1: Introduction to VHDL and related Tools EE19D – 25/01/2005

SYSTEM LEVEL

A/BComputer

IMU

C/D

RADAR

Page 15: Studio Session 1: Introduction to VHDL and related Tools EE19D – 25/01/2005

– VHDL Provides total modeling capability at the gate level, register level, and chip level.

– It can also be used in many applications at the: system level circuit level Switch level (gate-circuit hybrid)

Page 16: Studio Session 1: Introduction to VHDL and related Tools EE19D – 25/01/2005

VHDL supports very naturally the Design Decomposition process.

Structural

Decomposition

behavioralmodel

Reason #3: Design Decomposition

Page 17: Studio Session 1: Introduction to VHDL and related Tools EE19D – 25/01/2005

•VHDL can be used to validate design at a high level, thus detecting errors early in the design process

•Important, because finding errors later is expensive

Reason #4: Design Validation

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