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International Journal of Advanced Engineering Research and Technology (IJAERT) Volume 3 Issue 3, March 2015, ISSN No.: 2348 8190 88 www.ijaert.org Study of Various ADCs and Compare Their Performance and Parameters 1 Mrs. Jasbir Kaur, 2 Saurabh Kansal 1 Assistant Professor, 2 ME Scholar Electronics (VLSI Design) Electronics and Communication Engineering Department PEC University of Technology, Chandigarh, India Abstract-The performance of the analog to digital converters has become very important in signal processing applications. Most important parameters on which theirperformance depend are: resolution, conversion time and the sampling frequency of input. It became very important to understand the functioning and performance before implementing the ADC in the system. This paper discusses various types of ADCs and compares the commonly used ADCs so that user can conveniently choose between various ADCs available for their application. Keywords- Resolution, Conversion time, Chip area of ADC, sampling frequency. I. COUNTER TYPE ADC It is the basic type of ADC which is also called as digital ramp type ADC or stair case approximation ADC. Fig1: Counter Type ADC The counter generates an N bit digital output which is applied as an input to the DAC. The analog output corresponding to the digital input from DAC is compared with the input analog voltage using an Op- Amp comparator. The Op-Amp compares the two voltages and if the generated DAC voltage is less, it generates a high pulse to the N bit counter as a clock pulse to increment the counter. The same process will be repeated until the DAC output equals to or greater than the input analog voltage. If the DAC output voltage is equal to or greater than the input analog voltage, then it generates low clock pulse and it also generates a clear signal to the counter and load signal to the storage resistor to store the corresponding digital bits. These digital values are closely matched with the input analog values with small quantization error. For every sampling interval, the DAC output follows a ramp fashion that is why, it is called as Digital ramp type ADC, this ramp looks like stair cases for every sampling time so, and it is also called as staircase approximation type ADC. Conversion time of Counter type ADC Conversion time of ADC is the time taken by the ADC to convert the input sampled analog value to digital value. Here the maximum conversion of high input voltage for N bit ADC is the clock pulses required to count its maximum count value. So, the maximum conversion of Counter type ADC is equal to (2 N -1) T where T is the time period of clock pulse. Limitations of Counter type of ADC is thatspeed is less because every time the counter has to start from ZERO.There may be clash or aliasing effect if the next input is sampled before completion of one operation. II. TRACKING TYPE ADC In counter type DAC, the counter has to come to zero for every conversion which is a disadvantageous with respect to high conversion time. To perform operation, instead of using normal counter, this ADC uses up /down counter. After the first sampled value, the up/down counter will tracks the input analog value so that it is called tracking type of ADC [19]. The detailed block diagram of Tracking type ADC is shown in below figure. Fig 2: Tracking Type ADC

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International Journal of Advanced Engineering Research and Technology (IJAERT) Volume 3 Issue 3, March 2015, ISSN No.: 2348 – 8190

88

www.ijaert.org

Study of Various ADCs and Compare Their

Performance and Parameters

1Mrs. Jasbir Kaur,

2Saurabh Kansal

1Assistant Professor,

2ME Scholar Electronics (VLSI Design)

Electronics and Communication Engineering Department

PEC University of Technology, Chandigarh, India

Abstract-The performance of the analog to digital

converters has become very important in signal

processing applications. Most important parameters on

which theirperformance depend are: resolution,

conversion time and the sampling frequency of input. It

became very important to understand the functioning

and performance before implementing the ADC in the

system. This paper discusses various types of ADCs and

compares the commonly used ADCs so that user can

conveniently choose between various ADCs available

for their application.

Keywords- Resolution, Conversion time, Chip area of

ADC, sampling frequency.

I. COUNTER TYPE ADC

It is the basic type of ADC which is also called as digital

ramp type ADC or stair case approximation ADC.

Fig1: Counter Type ADC

The counter generates an N bit digital output which is

applied as an input to the DAC. The analog output

corresponding to the digital input from DAC is

compared with the input analog voltage using an Op-

Amp comparator. The Op-Amp compares the two

voltages and if the generated DAC voltage is less, it

generates a high pulse to the N bit counter as a clock

pulse to increment the counter. The same process will be

repeated until the DAC output equals to or greater than

the input analog voltage.

If the DAC output voltage is equal to or greater than the

input analog voltage, then it generates low clock pulse

and it also generates a clear signal to the counter and

load signal to the storage resistor to store the

corresponding digital bits. These digital values are

closely matched with the input analog values with small

quantization error. For every sampling interval, the DAC

output follows a ramp fashion that is why, it is called as

Digital ramp type ADC, this ramp looks like stair cases

for every sampling time so, and it is also called as

staircase approximation type ADC.

Conversion time of Counter type ADC Conversion time of ADC is the time taken by the ADC

to convert the input sampled analog value to digital

value. Here the maximum conversion of high input

voltage for N bit ADC is the clock pulses required to

count its maximum count value. So, the maximum

conversion of Counter type ADC is equal to (2N-1) T

where T is the time period of clock pulse.

Limitations of Counter type of ADC is thatspeed is less

because every time the counter has to start from

ZERO.There may be clash or aliasing effect if the next

input is sampled before completion of one operation.

II. TRACKING TYPE ADC

In counter type DAC, the counter has to come to zero for

every conversion which is a disadvantageous with

respect to high conversion time.

To perform operation, instead of using normal counter,

this ADC uses up /down counter. After the first sampled

value, the up/down counter will tracks the input analog

value so that it is called tracking type of ADC [19]. The

detailed block diagram of Tracking type ADC is shown

in below figure.

Fig 2: Tracking Type ADC

International Journal of Advanced Engineering Research and Technology (IJAERT) Volume 3 Issue 3, March 2015, ISSN No.: 2348 – 8190

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The N bit up/down counter starts counting according to

the clock pulse and provides a digital input to the DAC.

The DAC converts the digital input intocorresponding

analog output which is applied to Op-Amp. The Op-

Amp compares the DAC analog output with the input

analog sampled value, if the input value greater than the

DAC output it provides a clock pulse to increment the

counter or otherwise if it is lesser than the DAC output it

provides a clock pulse to decrement the counter. But

normally for first sampled value the counter will

incremented to match to the analog value and for

subsequent samples only the counter may get decrement

pulse.

When the DAC output is equal to the sampled value, the

digital output will be taken from the up/down counter

directly. Here shift register is not needed to

capturedigital data because the counter will not go to

reset state. Then, onwards for the next sample value, the

counter will increment or decrement according to the

difference output of Op-Amp. This is also called as

Derivative Counter type ADC because the counter

output depends on difference between the previous and

next sampled value like as differentiator.

Advantages of this ADC are that Shift register is not

needed so the cost is less.Speed is high compared to

digital ramp type as the counter will not reset.

Disadvantages of tracking type ADC is that Up/Down

counter leads to complexity of the circuit. The digital

output will never be constant because of differentiator

effect. i.e., for a constant analog value also the output

will oscillating this is known as bitbobble.

III. SUCCESSIVE APPROXIMATION ADC

One method of addressing the digital ramp ADC’s

shortcomings is successive approximationADC. The

only change in this design is a very special counter

circuit known asSuccessive Approximations

RegisterInstead of counting up in binary sequence, this

register counts by trying all values of bits starting with

the most-significant bit and finishing at the least

significant bit. Throughout the count process, the

register monitor the comparator’s output to see if the

binary count is less than or greater than the analog signal

input, adjusting the bit values accordingly [19].

The advantage to this counting strategy is much faster

results: the DAC output converges on the analog signal

input in much larger steps than with the 0 to full count

sequence of a regular counter.

Important point to note on Successive Approximation

ADC is that in Counter type or digital ramp type ADC

the time taken for conversion dependson the magnitude

of the input, but in SAR the conversion time is

independent of applied input voltage.

Fig 3: Successive Approximation ADC

Advantages of this ADC arespeed is high compared to

counter type ADC.Good ratio of speed to

power.Compact design and inexpensive compared to

flash type.

Disadvantages of successive Approximation ADC Cost

is high as compare to counter type ADC because of SAR

and complexity in design.

Applications of SAR ADC is used widely data

acquisition techniques at the sampling rates higher than

10 KHz.

IV. INTEGRATING ADC

Integrating analog to digital convertersprovide high

resolution analog to digital conversions, with good noise

rejection.

Single-Slope ADC Architecture: The simplest form of

an integrating ADC uses single slope architecture

(Figures 4a and 4b). Here, an unknown input voltage is

integrated and this value is compared against a known

reference value. The time it takes for the integrator to

trip the comparator is proportional to the unknown

voltage. In this case, the known reference voltage must

be stable and accurate to guarantee the accuracy of the

measurement [5].

One drawback to this approach is that the accuracy is

also dependent on the tolerances of the integrator's R and

C values. Thus in a production environment, slight

differences in each component's value change the

conversion result and make measurement repeatability

quite difficult to attain. To overcome this sensitivity to

the component values, the dual-slope integrating

architecture is used.

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Fig 4(a) Single-Slope ADC Architecture, Fig 4(b)

Output of integrator

Dual-Slope ADC Architecture: A dual-slope ADC

integrates an unknown input voltage (Vin) for a fixed

amount of time, then de-integratesusing a known

reference voltage (Vref) for a variable amount of time.

In the dual-slope converter, an integrator circuit is driven

positive and negative in alternating cycles to ramp down

and then up, rather than being reset to 0 volts at the end

of every cycle. In one direction of ramping, the

integrator is driven by the positive analog input signal

(producing a negative, variable rate of output voltage

change, or output slope) for a fixed amount of time, as

measured by a counter with a precision frequency clock.

In the other direction, with a fixed reference voltage

(producing a fixed rate of output voltage change) time is

measured by the same counter. The counter stops

counting when the integrator’s output reaches the same

voltage as it was when it started the fixed-time portion of

the cycle.

The amount of time it takes for the integrator’s capacitor

to discharge back to its original outputvoltage, as

measured by the magnitude accrued by the counter,

becomes the digital outputof the ADC circuit.

Fig 5(a): Dual-Slope ADC Architecture

Advantage of this method is that the input signal

becomes averaged as it drives the integrator during the

fixed-time portion of the cycle. Any changes in the

analog signal during that period of time have a

cumulative effect on the digital output at the end of that

cycle. Other ADC strategies merely capture the analog

signal level at a single point in time every cycle. If the

analog signal is “noisy” (contains significant levels of

spurious voltage spikes/dips), one of the other ADC

converter technologies may occasionally convert a spike

or dip because it captures the signal repeatedly at a

single point in time. A dual-slope ADC, on the other

hand, averages together all the spikes and dips within the

integration period, thus providing an output with greater

noise immunity.

These types of converters ofteninclude built-in drivers

for LCD or LED displays and are found in many

portable instrument applications, including digital panel

meters and digital multi-meters.

Fig 5(b): Integrating and De-integrating action of Dual

slope integrating ADC

Initially, switch S1 is on and S2 and S3 are off.

Theintegrator will integrate a sample of the input

voltage,Vin, for a fixed period of time T1and then, switch

S2 is closed. This disintegrates the input voltage to zero

and time taken by it to come to zero voltage is

proportional to applied input.

The disadvantage of this ADC is it is the slowest of all

ADCs but very chip and mostly used in DVMs.

V. FLASH ADC

Flash ADC is also called as the parallel A/D converter. It

is formed ofa series of comparators, each one comparing

the input signal to a unique reference voltage. The

comparator outputs connect to the inputs of a priority

encoder circuit, which then produces a binary output.

The fig 6(a) shows a 3-bit flash ADC circuit,Vref is a

stable reference voltage provided by a precision voltage

regulator as part of the converter circuit.As the analog

input voltage exceeds the reference voltage at each

comparator, the comparator outputs will sequentially

International Journal of Advanced Engineering Research and Technology (IJAERT) Volume 3 Issue 3, March 2015, ISSN No.: 2348 – 8190

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saturate to a high state. The priority encoder generates a

binary number based on the highest-order active input,

ignoring all other active inputs [2].

Fig 6(a): 3-bit Flash ADC circuit with 8 to 3 line priority

converter

For this particular application, a regular priority encoder

with all its inherent complexity isn’t necessary. Due to

the nature of the sequential comparator output states

(each comparator saturating high in sequence from

lowest to highest), the same effect (highest-order-input

selection) may be realized through a set of Exclusive-OR

gates, allowing the use of a simple encoder:

Fig 6(b): 3-bit flash ADC circuit with a set of Exclusive-

OR gates

Not only is the flash converter the simplest in terms of

operational theory, but it is the most efficient of the

ADC technologies in terms of speed, being limited only

in comparator and gate propagation delays.

And, of course, the encoder circuit itself can be made

from a matrix of diodes, demonstrating just how simply

this converter design may be constructed [19]:

Fig 6(c): 3-bit Flash ADC circuit with a matrix of diodes

Unfortunately, it is the most component-intensive for

any given number of output bits. This three-bit flash

ADC requires seven comparators. A four-bit version

would require fifteen comparators. With each additional

output bit, the number of required comparators doubles.

Considering that eight bits is generally considered the

minimum necessary for any practical ADC (255

comparators needed!), the flash methodology quickly

shows its weakness.For N bits of resolution, it requires

Ncomp. = 2N− 1comparators which require quite a lot of

area for more than 8 bits.

An additional advantage of the flash converter, often

overlooked, is the ability for it to produce a non-linear

output. With equal-value resistors in the reference

voltage divider network, each successive binary count

represents the same amount of analog signal increase,

providing a proportional response. For special

applications, however, the resistor values in the divider

network may be made non-equal. This gives the ADC a

custom, nonlinear response to the analog input signal.

No other ADC design is able to grant this signal-

conditioning behavior with just a few component value

changes [19].

Flash ADCs are suitable for applications requiring very

large bandwidths. However, these converters consume a

lot of power, have relatively low resolution, and can be

quite expensive.

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VI. TWO STEP FLASH ADC The Two Step Flash architecture evolved from the Full

Flash converter. One of the main drawbacks of the latter

is the number of necessary comparators, given by

Ncomp. = 2N− 1, which scales exponentially with the

resolution of the converter (N), making it, in some cases,

impractical to implement due to the necessary die area.

The Two-Step Flash topology alleviates the number of

necessary comparators byquantizing the input in two

steps. The effective reduction factor in the number of

comparators when compared to the Full-Flash ADC, is

exponentially proportional to the converter’s resolution,

and is approximately given by2N/2−1. In other words, the

higher the resolution the more area efficient it becomesto

use a Two-Step topology [18].

Fig 7(a): Two Step FlashADC topology employing

MDAC circuits

As shown in fig 7(a), each step (or stage) is composed of

a quantizer, with a resolution N1and N2inferior to the

resolution (N) of the entire converter, thus, requiring less

reference voltages and comparators, and consequently,

occupying less die area. Between the two steps, an

amplified residue voltage needs to be generated, which is

achieved with a DAC, a subtraction operation block and

a gain block. These three blocks constitute an MDAC

circuit. The principle of operation is as follows: the input

is sampled by the first quantizer during the sampling

phase. During the residue amplification phase, the first

quantizer decides the most significant bits (MSBs),

which are then used to reconstruct a voltage (using the

DAC), that is subtracted from the original sampled input

and then amplified (by 2N1

) to create an amplified

residue voltage. Still during this phase, the second

quantizer samples this residue. The objective of the

amplification is to restore the residue to the full voltage

range of the converter, thus facilitating the

implementation of the second quantizer fig 7(a), or

eventually, reusing the same quantizer in a cyclic way.

During the final phase, the second quantizer (of

resolution N2) quantizes the residue to obtain the least

significant bits (LSBs). The final digital output is

assembled using digital logic, by adding the MSBs

together with the LSBs.

Basically, this topology simplifies the quantization, by

trading comparators with time. The Full-Flash converter

achieves a quantization in two clock phases (one clock

cycle),while the Two-Step needs at least three phases,

i.e., one and a half clock cycles (Fig. 7 (c)).

Fig 7(b): Two stage quantization

Fig 7(c): Timing diagram of Two Step FlashADC

Although the throughput may be similar to that of the

Full-Flash converter (one digital output per clock cycle),

the Two-Step has higher latency.IfN1 is made equal to

N2, then only one quantizerneeds to be designed and,

therefore, both quantizersmay use the same reference

voltages. The latter is also made possible by using a

residue amplification gain of 2N1

.

VII. PIPELINE ADC

The Pipeline converter’s operation is basically the same

as that of the Two-Step Flash. Each stage is responsible

for quantizing Njbits, j=1, 2,… K (Nj< N) and generating

an amplified residue for further quantization (performed

by subsequent stages). However, the first stage does not

have to wait for the residue of a specific sample to reach

International Journal of Advanced Engineering Research and Technology (IJAERT) Volume 3 Issue 3, March 2015, ISSN No.: 2348 – 8190

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the end of the pipeline, to conclude its quantization. As

soon as the first stage has performed its task, it may

quantize the next input sample. This holds for all stages,

which means that at any given time, except at the

beginning when the converter starts its operation, all

stages are processing data. Thus, the throughput

ofPipeline converter may be similar to that of the Full-

Flash ADC, but its latency is high, even higher than that

of the Two-Step Flash converter. The more stages there

are in the pipeline chain, the higher the latency will be

[18].

Fig 8: Pipeline A/D converter with block diagram of a

stage

Normally, all pipeline stages are designed with the same

resolution to simplify the converter’s layout and

implementation, but, design trade-offs may determine

that each stage have different resolutions. It is usual to

find the first stage with a higher resolution. Another

important reason for all stages to be equal (in resolution)

is that the reference voltages are the same for all

quantizers and DAC functions. The pipeline ADC

further reduces the number of comparators and dies area

at the cost of increased latency.

VIII. MULTI-STEP ALGORITHMIC ADC

The Algorithmic (or Cyclic) converter, as the name

indicates, quantizes the input sample in an algorithmic or

repetitive manner [18].

The main difference with the Algorithmic converter is

that the conversion algorithm (sampling, quantization,

and residue amplification) is repeated in the same

physical space (reutilizing the same circuits) or area,

while the Pipeline ADC repeats its operation over more

area. In other words, the Algorithmic converter trades

space for time, which means it has a longer conversion

cycle as shown in Fig. 9(a). The principle of operation is

as follows: the input voltage is sampled by the first

stage. It is then quantized to generate the MSBs. These

bits are used to reconstruct a voltage (using a DAC and

reference voltages) that is subtracted from the input

voltage generating the residue voltage. This residue is

then amplified (and held) to the full scale range of the

converter and sampled by the second stage. This process

repeats itself between the first and second stages until

the LSB is generated. At this point a full digital output is

ready, while the converter is sampling the next input

sample (Fig. 9(b)).

Fig 9(a): The Algorithmic A/D converter: Block diagram

Fig 9(b): Timing diagram of Pipeline A/D converter

IX. TIME-INTERLEAVING ADCS

Time-Interleaving is a technique used to increase the

throughput or conversion rate of a converter. This

technique may be applied to all A/D converter

topologies. It consists of using an array of M parallel

converters multiplexed at the input and at the output.

Fig 10(a): Block diagram of Time-interleaving of A/D

Converters

Each converter operates at a conversion rate Fs/M (where

FSis total conversion rate), making it easier to

International Journal of Advanced Engineering Research and Technology (IJAERT) Volume 3 Issue 3, March 2015, ISSN No.: 2348 – 8190

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implement. The analog input multiplexer, adequately

timed, is responsible for attributing an input sample to

each of the converters over time, when it reaches the last

converter in the array it starts over again. The digital

output multiplexer guarantees that the timing sequence

of digital outputs are in accordance with the sampled

inputs. Each converter added to the array inevitably

increases the die area and the power consumption of the

overall A/D conversion system. The timing diagram of

operation is shown in Fig.10 (b).

Fig 10(b) Timing diagram of Time-interleaving of A/D

converters

Besides the limitations produced by each unit

(multiplexed) ADC, the time interleaved technique

introduces its own limitations. These have mainly to do

with mismatches between the various unit ADCs that

compose the converter. This topology is very sensitive to

mismatches in the offset, gain, timing,and bandwidth of

each unit ADC. All these extra errors (inherent to time-

interleaving) cause a degradation of the converter’s

signal-to-noise ratio (SNR). No matter how large the

error of a unit ADC is, as long as all other unit ADCs

has the same errormagnitude, no mismatch will exist

[18].

X. DELTA-SIGMA ADC

One of the more advanced ADC technologies is the

Delta Sigma [15].

In this converter, the analog input voltage signal is

connected to the input of an integrator, producing a

voltage rate-of-change, or slope, at the output

corresponding to input magnitude. This ramping voltage

is then compared against ground potential (0 volts) by a

comparator. Thecomparator acts as a sort of 1-bit ADC,

producing 1 bit of output (high or low) depending on

whether the integrator output is positive or negative. The

comparator’s output is then latched through a D-type

flip-flop clocked at a high frequency, and fed back to

another input channel on the integrator, to drive the

integrator in the direction of a 0 volt output. The basic

circuit is shown in fig 12. The leftmost op-amp is the

summing integrator. The next op-amp, the integrator

feeds into is thecomparator, or 1-bit ADC. Next come

the D-type flip-flop, which latches the comparator’s

output at every clock pulse, sending either a high or low

signal to the next comparator at the top of the circuit.

This final comparator is necessary to convert the single

polarity 0V /5V logic level output voltage of the flip-

flop into a +V / -V voltage signal to be fed back to the

integrator [19]

Fig 12: Block diagram of Delta Sigma ADC

If the integrator output is positive, the first comparator

will output a high signal to the D input of the flip-flop.

At the next clock pulse, this high signal will be output

from the Q line into the non-inverting input of the last

comparator. This last comparator, seeing an input

voltage greater than the threshold voltage of 1/2 +V,

saturates in a positive direction, sending a full +V signal

to the other input of the integrator. This +V feedback

signal tends to drive the integrator output in a negative

direction. If that output voltage ever becomes negative,

the feedback loop will send a corrective signal (-V) back

around to the top input of the integrator to drive it in a

positive direction. This is the delta-sigma concept in

action: the first comparator senses a difference between

the integrator output and zero volts. The integrator sums

the comparator’s output with the analog input signal.

Advantages of this ADC is that modern Sigma-delta

converters offer high resolution, high integration, low

power consumption, and low cost, making them a good

ADC choice for applications such as process control,

precision temperature measurements, and weighing

scales.

Limitation of this ADC is that higher order (4th order or

higher) and multi-bit feedback DAC requires large area.

International Journal of Advanced Engineering Research and Technology (IJAERT) Volume 3 Issue 3, March 2015, ISSN No.: 2348 – 8190

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Comparison of Various ADCs

FLASH

(Parallel)

SAR

DUAL SLOPE PIPELINE SIGMA DELTA

Conversi

on

Method

For N bits ADC

2N -1

comparators

required, means

increase by a

factor of 2 for

each bit [2]

Binary search

algorithm,

internal

circuitry runs at

higher speed [10]

Unknown input voltage

is integrated and

valuecompared against

known

referencevalue[19]

Small parallel

structure,each stage

works on a few bits

[16]

Comparator senses the

difference and

integrator sums the

comparator’s output

with the analog input

signal,Oversampling

ADC [15]

Selection

of this

architectu

re

Ultra-High Speed

when power

consumptionis not

primary concern?

Medium to high

resolution (8 to

16bit), low

power consumption ,

small size

Monitoring DC

signals, high

resolution, low

power consumption,

good noise

performance

High speeds,

few Msps to

100+ Msps, 8

bits to 16

bits resolution, lower

power

consumption than flash

High resolution, low to

medium speed, no

precision external

components, digital

filter reduces anti-

aliasing requirements

Encoding

Method

Thermometer

Code

Encoding [3]

Successive

Approximation

Analog

Integration

Digital

Correction

Logic

Over-Sampling

Modulator, Digital

Decimation Filter

Resolutio

n

Component

matching

typically limits

resolution to

8 bits

Componentmatchingr

equirementsdouble

withevery bitincrease

inresolution

Componentmatching

doesnot increasewith

increase inresolution

.

Componentmatchingre

quirementsdouble

withevery bitincrease

inresolution

Component matching

requirements double

with

every bit increase in

resolution

Size

Related

2N -1comparators,

Die size and

power

increases

exponentially

with

resolution

Die increaseslinearly

withincrease

inresolution

Core die size

will not

materially

change with

increase in

Resolution

Die increaseslinearly

withincrease

inresolution

Core die size will

notmaterially change

with increase in

resolution

Disadvan

tages

.

High power

consumption,

large size,

Expensive [14]

Speed limitedto

~5Msps.May

requireanti-

aliasingfilter[10]

SlowConversionrate.

Highprecisionexternalc

omponentsrequired

toachieveaccuracy

Parallelismincreasesthr

oughput atthe

expenseof power

andlatency

Higher order (4th order

or higher) and multi-bit

feedback

DAC require large area

XI. CONCLUSION

An ideal ADC has a great many bits for very fine

resolution, samples at lightning-fast speeds, and recovers

from steps instantly. It also, unfortunately, doesn’t exist

in the real world. Of course, any of these traits may be

improved through additional circuit complexity, either in

terms of increased component count and/or special

circuit designs made to run at higher clock speeds.

Different ADC technologies, though, have different

strengths [19]. Here is a summary of them ranked from

best to worst:

Resolution/complexity ratio:

Single-slope integrating, Dual-slope integrating,

Counter, Tracking, Successive approximation, Flash.

Speed:

Flash, Tracking, Successive approximation, Single-

Slope Integrating, Counter, Dual-slope integrating.

Step recovery:

Flash, Successive-approximation, Single-slope

integrating & counter, Dual-slope integrating, Tracking.

The rankings of these different ADC technologies

depend on other factors also. For instance, how an ADC

rates on step recovery depends on the nature of the step

change. A tracking ADC is equally slow to respond to

all step changes, whereas a single-slope or counter ADC

will register a high-to-low step change quicker than a

low-to-high step change. Successive-approximation

ADCs are almost equally fast at resolving any analog

International Journal of Advanced Engineering Research and Technology (IJAERT) Volume 3 Issue 3, March 2015, ISSN No.: 2348 – 8190

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signal, but a tracking ADC will consistently beat a

successive-approximation ADC if the signal is changing

slower than one resolution step per clock pulse.

REFERENCES

[1]. S. Rapuano, P. Daponte, E.Balestrieri, L. D. Vito,

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International Journal of Advanced Engineering Research and Technology (IJAERT) Volume 3 Issue 3, March 2015, ISSN No.: 2348 – 8190

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International Journal of Advanced Engineering Research and Technology (IJAERT) Volume 3 Issue 3, March 2015, ISSN No.: 2348 – 8190

99

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