SuperKEKB 3nd open meeting July 7-9, 2009 Hans-Gnther Moser MPI fr Physik Sensor and ASIC R&D Sensor Prototype Production: running, ASICs: Switcher, DCD Prototypes under test, DHP: design phase More Information: Indico page of Ringberg Workshop:py?confId=466 SuperKEKB 3nd open meeting July 7-9, 2009 Hans-Gnther Moser MPI fr Physik Sensor Production Status Status at 2nd Belle II meeting (March): SOI wafer bonding at Tracit, France 30 SOI wafers received, processing in our own lab has started Presently: cleaning, oxygenation, alignment mask, first implantation: next week. Processed are 6 wafers + dummies SuperKEKB 3nd open meeting July 7-9, 2009 Hans-Gnther Moser MPI fr Physik Wafer layout Small test matrices with various pixel sizes; 50 m x 50 m.. 50 m x 175 m Technology variations (gate length L) 4 module large matrices with most likely pixel sizes 5cm: 50m x 75m 5cm: 50m x 100m 3.5cm 50m x 50m 3.5cm 50m x 75m Important for timing! SuperKEKB 3nd open meeting July 7-9, 2009 Hans-Gnther Moser MPI fr Physik Favorized design (zoom) SuperKEKB 3nd open meeting July 7-9, 2009 Hans-Gnther Moser MPI fr Physik Favorized design (zoom) Pixel Clear Gate Source Drain SuperKEKB 3nd open meeting July 7-9, 2009 Hans-Gnther Moser MPI fr Physik Source (all connected, double pixel share one source) Drain (neighbour pixel share one drain, connected to one DCD channel) Gate (double pixel have gates connected & interleaved connection) To gate switcher To DCD Option: common source/drain: very compact (small pitch) but interleaved readout SuperKEKB 3nd open meeting July 7-9, 2009 Hans-Gnther Moser MPI fr Physik DEPFET parameter model drain current 1. row 0 1 0 2. row3. row clear 1 gate Read-Clear-Read for 3 neighboring matrix rows Including realistic RC loads for control and readout lines RC times critical: 80 ns sample-clear-sample just ok Capacitance depends on sensor length (drain lines) and number of pixels (drain capacitance) SuperKEKB 3nd open meeting July 7-9, 2009 Hans-Gnther Moser MPI fr Physik Changes for final production Thin oxides: for improved radiation hardness: d ox 200nm -> 100nm => small threshold voltage shifts => however: reduction of gain Shorter gates compensate gain loss due to thin oxide -> compensate by reducing L by 0.8 (6 m -> 4.7 m) improve gain (overcompensate) L ~ 4.0m: g q ~ 600 pA/e (instead of 450 pA/e) needs plasma etching Tests/test structures on PXD6 production Extra thin oxide test planned in autumn SuperKEKB 3nd open meeting July 7-9, 2009 Hans-Gnther Moser MPI fr Physik DEPFET Readout and Control ASICs DCD, Switcher: Heidelberg DHP: Bonn, Barcelona SuperKEKB 3nd open meeting July 7-9, 2009 Hans-Gnther Moser MPI fr Physik Switcher 3 Radiation tolerant layout in 0.35 m technology 128 channels + Very fast - Operation up to 11.5 V Novel design: Uses stacked LV transistors, HV twin-wells and capacitors as level- shifters + No DC power consumption Tested up to 22 Mrad 9V out SRAM 3V SRAM 6V SRAM 0V 3V 6V 9V 2ns SuperKEKB 3nd open meeting July 7-9, 2009 Hans-Gnther Moser MPI fr Physik Switcher 4 Uses radiation tolerant high voltage transistors in HV 0.35 m technology 64 channels + fast enough + Possible operation up to 50 V (30V tested) + low DC power consumption Enclosed design of NMOS HV transistors Should be rad hard (to be tested) Final chip: only 16 or 32 channels SuperKEKB 3nd open meeting July 7-9, 2009 Hans-Gnther Moser MPI fr Physik DCD - Technology 0.18 m - 72 Channels - 2 ADCs and regulated cascode/channel - 6 channels multiplexed to one digital LVDS output - ADC sampling period 160 ns (8 bits) - Channel sampling period 80 ns - LVDS output: 600 M bits/s - Chip: 7.2 G bits/s (12 outputs) - Radiation tolerant design - ~ 1mW/ADC SuperKEKB 3nd open meeting July 7-9, 2009 Hans-Gnther Moser MPI fr Physik DCD Layout for Belle II: 160 channel chip, bump bonded Radiation hardness tested up to 7 Mrad SuperKEKB 3nd open meeting July 7-9, 2009 Hans-Gnther Moser MPI fr Physik DCD Tests Works almost at design frequency (540 MHz: 88ns line rate) (works still at nominal 600 MHz, but with higher noise) Noise level: 90nA with 450 pA/e: 200 e ENC (S/N = 20:1) Some bugs discovered, improved version will be submitted Push DEPFET gain (600 pA/e ?) Manuel Koch, Bonn SuperKEKB 3nd open meeting July 7-9, 2009 Hans-Gnther Moser MPI fr Physik DHP Configuration Synchronization DCD/Switcher Data processing (CM, Pedestal 0-Sup) Clustering? Buffering, Trigger handling Being designed, 90nm CMOS SuperKEKB 3nd open meeting July 7-9, 2009 Hans-Gnther Moser MPI fr Physik DHP Signal Rates & Data Flow Assumptions ( extended specs.) 10s r/o time ( 20 s) 128 switcher channels ( 256) 10 kHz trigger (un-triggered r/o) 2-4% occupancy Bonn, Barcelona SuperKEKB 3nd open meeting July 7-9, 2009 Hans-Gnther Moser MPI fr Physik Summary: ASICs - DCD prototype chip has been tested with test signals that correspond to DEPFET currents and irradiated up to 7 Mrad. The chip works fine and has high enough conversion speed. Operation with matrices still to be tested we do not expect problems. Only fine tuning of the design for the super KEKB operation is necessary. - Switcher prototype with LV transistors has been tested and irradiated up to 22 MRad. The chip works fine and has adequate speed for Belle II operation. - Another prototype with HV transistors has been designed and tested. - The irradiation of the chip still has to be done but the basic and most critical part (high- voltage NMOS) has been irradiated up to 600 KRad and no damage has been observed. - DHP chip will be designed using digital design tools in intrinsically radiation hard 90 nm technology. - Choice between 4 different bumping technologies advantages and disadvantages still to be evaluated Planned submissions: Switcher:October 09 DCD:September 09 DHP: October 09 SuperKEKB 3nd open meeting July 7-9, 2009 Hans-Gnther Moser MPI fr Physik Questions General: Radiation: SEU tolerance: what level of background from hadrons? Ground loops? DHP Trigger: max. rate and trigger dead time Interleaved readout: not wanted by ASIC designers Distance DHP-DHH How many (complete) frames to store (for calibration) Switcher: Range of different operation voltages (compatible with internal level shifter)