Tanner Overview

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2010 Tanner EDA

VLSI Back End ASIC Flow

September 2010

Ramesh Reddy B

SriKirti Somanath [email protected]


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2010 Tanner EDA

Outline

Front End Schematic Design With S-Edit

Analog simulation With T-Spice and W-Edit

Back End IC Layout with L-Edit

Schematic Driven Layout, DRC, and Netlist Extraction


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Front-End Tools: S-Edit Integration


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S-Edit Window Regions


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Properties Window


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View Types



Front-End Tools: Data Flow

Cadence EDIF + CDFMentor EDIF + NCF

PSpice Schematics

Agilent ADS

ViewDraw EDIF

Laker EDIF

HSPICE netlist

Verilog-A models

Excel

(CSV)

Manage and View

Results from Multiple Sims

Model Browser

v15

Capture

Simulate

Analyze



Front-End Tools: Data Interoperability

Export Verilog

Export VHDL

Export EDIF

Export TPR

Export

SPICE

for LVS

Flexible NetlistingControl Remote Simulator

(including over network)

ExportSPICEfor sim

?External

Simulator

HSPICE

SmartSpice

EldoSpectre

Verify

SPICE netlist

from Extract

Capture

Simulate


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SPICE Introduction


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SPICE Introduction


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SPICE Flow


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Command Wizard


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Analysis Types

DC Operating Point Calculated For All anaysis Types

.OP

DC Sweep Analysis

.DC

AC Sweep Analysis .AC

Transient Analysis

.TRAN

Temperature Analysis

Monte Carlo Analysis

Noise Analysis

Optimization


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W-Edit Waveform Viewer


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Back-End Tools: L-Edit Integration


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L-Edit Window Regions


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Layer Setup


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Back-End Tools: DRC and Extract

Interactive DRC

Node Highlighting

Standard Extract

Calibre Extract (LVS)

Dracula Extract

Standard DRC

Calibre DRC

Dracula DRC

Assura DRC

Netlist

Extraction

Calibre

DRC rules

v15


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Layout

CaptureSPICE

or CDL

SDL

Router

T-Cells

External

tools

Schematic-Driven

Placementv15

Recognize and

generate:

Differential pairs

Current mirrors

DevGen

T-Cells for:

Transistors

Resistors

Capacitors


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P&R


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Chip Cell Created With SPR


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Core Cell Components


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Global Signal Routing


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Tanner EDA Packages Building Blocks of Innovation

Tanner Tools Pro

L-Edit

S-Edit W-Edit

T-Spice Pro

Interactive DRC Node Highlighting

Extract SDLDev Gen Pad Map

SPRLVS Std.DRC Std.


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Tanner EDA partners with leading foundries to provide PDKs

AMIS (On Semiconductor)

Austria Microsystems

Atmel

Chartered Semiconductor

HP

IBM

Peregrine

Silterra

SMIC

ST Microelectronics

TSMC

Zete

Additional Foundry

Partners

Tanner EDA and xFab work together to offer shared customers cost-efficient mixed signal analog

process design kits utilizing L-Edit, HiPer Silicon and HiPer PX.

Tanner EDA and Tower Semiconductor team up to help reduce design and fabrication cycle timesproviding a competitive advantage to mutual customers.

Headquartered in Seoul, Korea, Dongbu HiTeks best-in-class foundry services encompass Analog,

High Voltage CMOS, CMOS RF and BCDMOS technologies, CMOS Image Sensor(CIS), andDisplay Driver IC (DDI) chips as well as chips that incorporate NOR Flash memory functions at

nodes ranging from 90nm to 0.35um. Highlighting Dongbu HiTek's Analog Foundry Service is

specialized in processing, manufacturing and design support.

Tanner EDA and LFoundry foster high confidence customer partnerships that require flexibility and

technology customization. The comprehensive functionality, productivity and ease of use of the

Tanner EDA IC design tools, in conjunction with LFoundry processes can minimize design time and

risk, thus speeding concept to silicon.

Tanner EDA and MHS Electronics high performance analog design and fabrication solutions that

serve the Telecommunication, Automotive, Medical and Power Management semiconductor

markets.

UMCs customer driven foundry solutions complements Tanner EDAs responsive customer focus.

Together UMC and Tanner EDA provide an affordable and comprehensive solution for analog mix

signal designs and processes.

Foundry Partners

The EUROPRACTICE IC Service, offered by IMEC and Fraunhofer, provides Tanner EDA solutions

to qualified members of Europractice in academic and research institutes throughout

Europe. Design kits are provided in Tanner EDA format.

MOSIS provides access to fabrication of prototype and low-volume production quantities of

integrated circuits. MOSIS lowers the cost of access to fabrication by combining designs from

multiple customers on multi-project wafers (MPW). Design kits are provided in Tanner EDA format.

Foundry Services


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hank You

Documents

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