TDA7317 ECUALIZADOR

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    TDA7317

    FIVE BANDS DIGITAL CONTROLLED GRAPHIC EQUALIZER

    VOLUME CONTROL IN 0.375dB STEPFIVE BANDS STEREO GRAPHIC EQUAL-IZERCENTER FREQUENCY, BANDWIDTH, MAXBOOST/CUT DEFINED BY EXTERNAL COM-PONENTS14dB CUT/BOOST CONTROL IN 2dB/STEPALL FUNCTIONS PROGRAMMABLE VIA SE-

    RIALBUSVERY LOW DISTORTIONVERY LOW NOISE AND DC STEPPING BYUSE OF A MIXED BIPOLAR/CMOS TECH-NOLOGY

    DESCRIPTIONThe TDA7317 is a monolithic, digitally controlledgraphicequalizer realized in BiCMOS mixed technol-ogy. The stereo signal, before any filtering, canbe at-

    tenuated up to -17.625dB in 0.375dB step.All the functions can be programmed via serialbus making easy to build a P controlled system.Signal path is designed for very low noise anddistor-tion.

    November 1999

    SDIP30

    ORDERING NUMBER: TDA7317

    BLOCK DIAGRAM

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    ABSOLUTE MAXIMUM RATINGS

    Symbol Parameter Value UnitVS Supply Voltage 10.2 VTop Operating Temperature Range -40 to +85 CTstg Storage Temperature Range -55 to +150 C

    R tjvins Thermal Resistance Junction pins max 85 C/W

    PIN CONNECTION

    ELECTRICAL CHARACTERISTICS (Tamb = 25 C, V S = 9V, R L = 10K , R g = 600 , f = 1KHz V IN =1Vrms, all controls in flat position (AV = 0dB) unless otherwise specified).

    Symbol Parameter Test Condition Min. Typ. Max. Unit

    SUPPLY

    VS Supply Voltage 6 9 10 VIS Supply Current 8 14 20 mA

    SVR Ripple Rejection f = 300Hz to 10KHz 60 80 dB

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    ELECTRICAL CHARACTERISTICS (continued)

    Symbol Parameter Test Condition Min. Typ. Max. Unit

    INPUT

    R I Input Resistance 20 30 40 K VIN max Max Input Signal THD = 0.3% 2 2.5 V RMS

    IN S Input Separation (1) 80 100 dB

    VOLUME CONTROL

    C RANGE Control Range 17.625 dBAVMIN Min. Attenuation -0.5 0 0.5 dBAVMAX Max. Attenuation 16.7 17.625 18.6 dBASTEP Step Resolution 0.175 0.375 0.575 dB

    EA Attenuation Set Error -1 1 dBE T Tracking Error 0.5 dB

    VDC DC Steps adjacent attenuation steps 0 3 mVGRAPHIC EQUALIZER

    THD Distortion 0.01 0.1 %C s Channel Separation 80 100 dB

    e NO Output Noise BW = 20Hz to 20KHzflat, AV = 0dB

    8 20 V

    A curve 6 VBW = 20Hz to 20KHz AV = 0dBAll bands = max. boostAll bands = max. cut

    246

    VV

    S/N Signal to Noise Ratio A V = 0dB; V ref = 1V RMS 100 dBBstep Step Resolution 1 2 3 dB

    C RANGE Control Range max boost/cut 12 14 16 dBVDC DC Steps Adiacent Control Steps 0.5 3 mV

    AUDIO OUTPUTS

    VO Output Voltage THD = 0.3% 2 2.5 V RMSR L Output Load Resistance 2 K C L Output Load Capacitance 10 nFR O Output Resistance 5 10 20

    VOUT DC Voltage Level 4.2 4.5 4.8 V

    BUS INPUTS

    VIL Input Low Voltage 1 VVIH Input High Voltage 3 VIIN Input Current -5 +5 AVO Output Voltage SDA

    AcknowledgeIO = 1.6mA 0.4 V

    ADDRESS PIN (Internal 50K pull down resistor)

    VIL Input Low Voltage 1 VVIH Input High Voltage V CC -1V V

    NOTE: The input is grounded thru the 2.2 P capacitors

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    DEVICE DESCRIPTIONThe TDA7317 is a five bands, digitally controlledstereo Graphic Equalizer.The device is intended for high quality audio ap-

    plication in Hi-Fi, TV and car radio systems wherefeature like low noise and THD are key factors. Amixed Bipolar Cmos Technology allows:Cmos analog switches for pop free commuta-tions, high frequency op.amp. (GWB = 10MHz)and high linearity polisilicon resistor for THD =0.01 (at Vin = 1Vrms) and a S/N ratio of 102dB.The internal Block Diagram is shown on page 1.The first stage is a volume control. The controlrange is 0 to -17.625dB with 0.375dBstep.The very high resolution (0.375dB step) allowsthe implementation of closed loop amplitude con-trol system completely free from any acustical ef-fect (stepping variation and pumping effect).

    The volume control is followed by a serial fivebands equalizer. Each filtering cell is the biquadcell shown in fig. 1The internal resistor string is fixing the boost/cutvalue while the buffer makes the Q (quality factor)and central frequency, set by external compo-nents, fully indipendentfrom the internal resistors.Each filtering cell is realized using only 4 externalcomponents (2 capacitors and 2 resistors) allow-ing a flexible selection of centre frequency fo, Qfactor and gain. Here below the basic formulaeand the key features of each band pass filter arereported:

    fo = center frequencyGv = gain/loss at the center frequency f oGv = 20log(Av)

    Q = fof2 f1

    where f 2 , f1 = 3dB Bandwidth limits.

    Av = (R2 C2 ) + (R2 C1 ) +(R1 C1 )

    (R2 C1 ) + (R2 C2 )

    Q = (R1 C1 R2 C2 )(R2 C1 ) + (R2 C2 )

    fo = 12 (R1 R2 C1 C2 )

    If C1 is fixed, then:

    C2 = Q2

    Av 1 Q2 C1

    R2 = 1

    2 C1 fo (Av 1 ) Q(Av 1 Q2)

    R1 = (Av 1)2

    Av 1 Q2 R2

    Likewise, the componentsvalues can be deter-mined by fixing one of the other three parameters.Referring to fig. 1 the suggested R2 value shouldbe higher than 2K in order to have a good THD(internal op. amp. current limit).

    Viceversa the R1 value should be equal or lowerthan 51K in order to keep the click(DC step)very low.A typical applicationis shown by fig. 2

    Fig. 1

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    I2C BUS INTERFACEData transmission from microprocessor to theTDA7317 and viceversa takes place thru the 2wires I 2C BUS interface, consisting of the two

    lines SDA and SCL (pull-up resistors to positivesupply voltage must be externally connected).

    Data ValidityAs shown in fig. 3, the data on the SDA line mustbe stable during the high period of the clock. TheHIGH and LOW state of the data line can onlychange when the clock signal on the SCL line isLOW.Start and Stop ConditionsAs shown in fig.4 a start condition is a HIGH toLOW transition of the SDA line while SCL isHIGH. The stop condition is a LOW to HIGH tran-sition of the SDA line while SCL is HIGH.

    Byte FormatEvery byte transferred to the SDA line must con-tain 8 bits. Each byte must be followed by an ac-knowledgebit. The MSB is transferred first.

    AcknowledgeThe master ( P) puts a resistive HIGH level on theSDA line during the acknowledge clock pulse (seefig. 5). The peripheral (audioprocessor) that ac-

    knowledges has to pull-down (LOW) the SDA lineduring the acknowledge clock pulse, so that theSDAline is stable LOW during this clockpulse.The audioprocessor which has been addressedhas to generate an acknowledge after the recep-tion of each byte, otherwise the SDA line remainsat the HIGH level during the ninth clock pulsetime. In this case the master transmitter can gen-erate the STOP information in order to abort thetransfer.

    Transmissionwithout AcknowledgeAvoiding to detect the acknowledge of the audio-

    processor, the P can use a simplier transmis-sion: simply it generates the 9th clock pulse with-out checking the slave acknowledging, and thensends the new data.This approach of course is less protected frommisworking and decreases the noise immunity.

    Figure 3: Data Validity on the I 2CBUS

    Figure 4: Timing Diagram of I 2CBUS

    Figure 5: Acknowledge on the I 2CBUS

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    SOFTWARE SPECIFICATIONInterface ProtocolThe interface protocol comprises:

    A start condition (s)A chip address byte, containing the TDA7317

    address (the 8th bit of the byte must be 0). TheTDA7317 must always acknowledge at the endof each transmitted byte.A sequence of data (N-bytes + acknowledge)

    A stop condition (P)

    TDA7316 ADDRESS

    MSB first byte LSB MSB LSB MSB LSBS 1 0 0 0 0 1 A 0 ACK DATA ACK DATA ACK P

    Data Transferred (N-bytes + Acknowledge)ACK = AcknowledgeS = StartP = Stop

    MAX CLOCK SPEED 100kbits/s

    SOFTWARE SPECIFICATIONChip address (84 or 86 Hex)

    1MSB

    0 0 0 0 1 A 0LSB

    A = Logic level on pin ADDR

    A = 1 if ADDR pin = open

    A = 0 if ADDR pin = connectedto ground

    SOFTWARE SPECIFICATION (continued)DATA BYTES (detailed description)Volume

    MSB LSB FUNCTION0 X B2 B1 B0 A2 A1 A0 Volume 0.375dB steps

    0000

    1111

    0011

    0011

    0101

    0101

    0-0.375-0.75

    -1.125

    -1.5-1.875-2.25

    -2.6250 X B2 B1 B0 A2 A1 A0 Volume -3dB steps

    000011

    001100

    010101

    0-3-6-9

    -12-15

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    APPLICATION INFORMATIONA typical application is indicated in figure 4, while

    the P.C. Board and components layout are re-ported in figure 5. The external components, arecalculatedfor 2 different max boost/cut conditions

    Graphic Equalizer

    MSB LSB FUNCTION1 D3 D2 D1 D0 S2 C1 C0

    00001

    00110

    01010

    Band 1Band 2Band 3Band 4Band 5

    D3D3

    D2D2

    D1D1

    10

    C2C2

    C1C1

    C0C0

    cutBoost

    00001111

    00110011

    01010101

    0dB2dB4dB6dB8dB10dB12dB14dB

    AX = 0.375dB steps, BX = 3dB steps, CX = 2dB steps, X = dontcare

    STATUS AFTER POWER-ON RESETVolume -17.25dBGraphic equalizer bands -12dB

    TABLE 1: Max Boost/cut = 20 dB (each cell = 14dB )

    F (HZ) Q R1 (K ) R2 (K) C1 (nF) C2 (nF) Av max