The Cortex-M3 Embedded Systems:

LM3S9B96 Microcontroller – Interrupts

Refer to Chapter 4 in the reference book“Stellaris® LM3S9B96 Microcontroller - DATA SHEET”

Exceptions are numbered 1 to 15 for system exceptions and the rest 240 for external interrupt inputs.(Total 256 entries in vector table.) In LM3S9B96, 10 system exceptions and 53 interrupts

Most of the exceptions have programmable priority, and a few have fixed priority. Reset, NMI, and Hard Fault have fixed priorities of -3,

-2, and -1, respectively Eight user programmable priority levels; 0 is the

highest and the default priority is 0 for all the programmable priorities

3-bit priority registers are implemented for all the programmable priorities

Exceptions

List of Exceptions

List of Exceptions

List of Exceptions

Setup Exceptions at NVIC

8 exception priorities can be further grouped defined by the Application Interrupt and Reset Control (APINT) register

Only the group priority determines preemption of interrupt exceptions

If multiple pending interrupts have the same group priority, the subpriority field determines the order in which they are processed

If multiple pending interrupts have the same group priority and subpriority, the interrupt with the lowest IRQ number is processed first

Exception Priorities

Application Interrupt and Reset Control (APINT), offset 0xD0C

Provides priority grouping control, endian status for data accesses, and reset control of the system; accessed from privileged mode

For system exceptions, priorities are set with the NVIC System Handler Priority n (SYSPRIn) registers

System Handler Priority 1 (SYSPRI1), offset 0xD18

System Handler Priority 2 (SYSPRI2), offset 0xD1C

System Handler Priority 3 (SYSPRI3), offset 0xD20

Set Exception Priorities

For interrupts, priorities are set with the NVIC Interrupt Priority n (PRIn) registers

Interrupt 0-3 Priority (PRI0), offset 0x400…

Interrupt 52-54 Priority (PRI13), offset 0x434

Set Exception Priorities

…

For system exceptions, the SYSHNDCTRL register enables the system handlers, and indicates the pending and active status of the system handlers; The INCTRL register provides a set-pending bit for the NMI exception, and set-pending and clear-pending bits for the PendSV and SysTick exceptions.

System Handler Control and State (SYSHNDCTRL), offset 0xD24

Interrupt Control and State (INTCTRL), offset 0xD04

Enable and Disable Exceptions

For interrupts, the ENn register enable interrupts and show which interrupts are enabled.

Interrupt 0-31 Set Enable (EN0), offset 0x100

Interrupt 32-54 Set Enable (EN1), offset 0x104

Enable and Disable Exceptions

For interrupts, the DISn register disable interrupts and show which interrupts are disabled.

Interrupt 0-31 Clear Enable (DIS0), offset 0x180

Interrupt 32-54 Clear Enable (DIS1), offset 0x184

Enable and Disable Exceptions

If an interrupt takes place but cannot be executed immediately, it will be pended. The interrupt-pending status can be accessed through the

Interrupt Set Pending (PEND) and Interrupt Clear Pending (UNPEND) registers.

User can set the certain bit of PEND to enter its handler by software.

For each interrupt the NVIC has a PEND and a UNPEND register. PEND0 and PEND1: 0xE000E200-0xE000E204 UNPEND0 and UNPEND1: 0xE000E280-0xE000E284

Similarly, for each interrupt the NVIC has a Active status register. Interrupt 0-31 Active Bit (ACTIVE0), offset 0x300 Interrupt 32-54 Active Bit (ACTIVE1), offset 0x304

Interrupt Pending and Active Status

Software interrupts can be generated by using:1. The PEND register2. The Software Trigger Interrupt Register (STIR)

Software Trigger Interrupt Register (0xE000EF00)

System exceptions (NMI, faults, PendSV, and so on) cannot be pended using STIR.

Bits Name Type Reset Value Description

8:0 INTID W – Writing the interrupt number sets the pending bit of the interrupt; for example, write 0 to pend external interrupt #0

Software Interrupts

Setup Exceptions at a Peripheral

Example: Setting up Interrupt for GPIO

Define Interrupt Conditions GPIO Interrupt Sense (GPIOIS) register: setting a

bit, detect levels on the pin; otherwise, detect edges GPIO Interrupt Both Edges (GPIOIBE) register:

when GPIOIS is set to detect edges, setting a bit in GPIOIBE enables the pin to detect both rising and falling edges; otherwise, the pin is controlled by the GPIOIEV register

GPIO Interrupt Event (GPIOIEV) register: setting a bit, detect rising edges (or high levels); otherwise, detect falling edges (or low levels), depending on the settings of GPIOIS

Other Interrupt Control Registers GPIO Interrupt Mask (GPIOIM) register: setting a bit, allows

the pin to generate interrupts; otherwise, disable interrupts GPIO Raw Interrupt Status (GPIORIS) register: A bit is set

when an interrupt condition occurs on the corresponding GPIO pin; otherwise, RAZ.

GPIO Masked Interrupt Status (GPIOMIS) register: If a bit is set, the corresponding interrupt has triggered an interrupt to the interrupt controller; otherwise, either no interrupt has been generated, or the interrupt is masked

GPIO Interrupt Clear (GPIOICR) register: Writing a 1 to a bit in this register clears the corresponding interrupt bit in the GPIORIS and GPIOMIS registers

GPIO Interrupt Sense (GPIOIS), offset 0x404

The GPIOIS register is the interrupt sense register. Setting a bit in the GPIOIS register configures the corresponding pin to detect levels, while clearing a bit configures the corresponding pin to detect edges. All bits are cleared by a reset.

GPIO Interrupt Both Edges (GPIOIBE), offset 0x408

The GPIOIBE register allows both edges to cause interrupts. When the corresponding bit in the GPIOIS register (see page 320) is set to detect edges, setting a bit in the GPIOIBE register configures the corresponding pin to detect both rising and falling edges. Clearing a bit configures the pin to be controlled by the GPIOIEV register. All bits are cleared by a reset.

GPIO Interrupt Event (GPIOIEV), offset 0x40C

Setting a bit in the GPIOIEV register configures the corresponding pin to detect rising edges or high levels (clearing a bit configures the pin to detect falling edges or low levels), depending on the corresponding bit value in the GPIO Interrupt Sense (GPIOIS) register. All bits are cleared by a reset.

GPIO Interrupt Mask (GPIOIM), offset 0x410

The GPIOIM register is the interrupt mask register. Setting a bit in the GPIOIM register allows interrupts that are generated by the corresponding pin to be sent to the interrupt controller on the combined interrupt signal. All bits are cleared by a reset.

GPIO Raw Interrupt Status (GPIORIS), offset 0x414

The GPIORIS register is the raw interrupt status register. A bit in this register is set when an interrupt condition occurs on the corresponding GPIO pin. A bit in this register can be cleared by writing a 1 to the corresponding bit in the GPIO Interrupt Clear (GPIOICR) register.

GPIO Masked Interrupt Status (GPIOMIS), offset 0x418

The GPIOMIS register is the masked interrupt status register. If a bit is set in this register, the corresponding interrupt has triggered an interrupt to the interrupt controller.

GPIO Interrupt Clear (GPIOICR), offset 0x41C

The GPIOICR register is the interrupt clear register. Writing a 1 to a bit in this register clears the corresponding interrupt bit in the GPIORIS and GPIOMIS registers. Writing a 0 has no effect.

How to configure an Interrupt?

At the NVIC side Set up the priority group register (group 0 by default) Set up the priority level for the interrupt Enable the interrupt

At the peripheral side Enable the peripheral (setup the RCGCn) Configure the interrupt type for the peripheral Enable the interrupt in the peripheral

Write an interrupt service routine (ISR) Identify the interrupt source Clear the interrupt request

Register the ISR in the interrupt vector table

InterruptRequest

InterruptPending Status

InterruptActive Status

ProcessorMode

ThreadMode

Handler Mode

Interrupt request stays active

Interrupt returned

Interrupt re-entered