8
1946 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 39, NO. 8. AUGUST 1992 The Field-Assisted Turn-off Thyristor: A Regenerative Device with Voltage-Controlled Turn-off Christopher J. Petti, Member, IEEE, and James D. Plummer, Fellow, IEEE Abstract-A new solid-state switching element, the Field-As- sisted Turn-off (FATO) thyristor, has been developed. This is a regenerative device, which implies that it is capable of car- rying very large current densities, with a very small forward voltage drop when it is in its on-state. Most regenerative de- vices cannot be turned off with a control signal; however, the structure of the FATO thryistor allows it to be switched off by applying a voltage to a high-impedance, insulated-gate termi- nal. This device can also be fabricated with an insulated-gate turn-on structure, so that it is fully switchable using only low- current control signals. This paper describes the design, fab- rication, and characterization of the FATO thyristor. I. INTRODUCTION HE SOLID-STATE device structure which is most T suitable for high-current applications is the thyristor. This is because, like a p-i-n diode, the highly resistive “drift” region of the device has carriers injected into it from both ends and its conductivity is modulated through- out its width. However, since the regenerative on-state of the thyristor is self-supporting, no controlling signal can switch the device off. Many different variations on the thyristor structure have been developed to overcome this serious limitation. Most rely on the process of removing current from the cathode- anode path and diverting it to another path which is not itself regenerative. One method of diverting current is that used in the gate- turn-off (GTO) thyristor 113; that is, to simply bring the p-type thyristor base to a more negative voltage than the cathode, thus causing holes to exit the device through the p-type base rather than the cathode. A second approach is the MOS-controlled thyristor (MCT) [3], 141 where a MOS device forms a variable resistor which shorts the cathode and the p- base of the structure, effectively in- creasing the holding current of the device while it is in the on-state. The maximum current that this device can tum off is limited by the parasitic resistances in series with Manuscript received October 2, 1990; revised December 3, 1991. The review of this paper was arranged by Associate Editor T. P. Chow. C. J. Petti was with the Center for Integrated Systems, Stanford Uni- versity, CIS 114, Stanford, CA 94305. He is now with Cypress Semicon- ductor, San Jose, CA 95134. J. D. Plummer is with the Center for Integrated Systems, Stanford Uni- versity, CIS 114, Stanford, CA 94305. IEEE Log Number 9201206. the MOS turn-off device, as well as the MOS channel re- sistance itself. The remainder of this paper describes the structure, fabrication, and operation of a new regenerative switch- ing device, the field-assisted turn-off (FATO) thyristor [5], [6]. Like the GTO thyristor and the MCT, the FATO thyristor is able to be switched off with a control signal, and this is accomplished by extracting holes from the heavily injected region. However, holes are attracted away from the regenerative path toward a silicon surface underneath a MOS gate; the gate effectively induces an alternative collector for the p-n-p transistor. Thus very little control current is needed to turn off this thyristor, since the tum-off electrode is an insulated gate. Further- more, the maximum current that can be turned off is not limited by the parasitic resistances in series with this in- duced collector, because the collector is operating as a current source. The prototype devices described here experimentally switched off current densities up to 25 A/cm2, which is relatively small compared to the 1000 A/cm2 usually as- sociated with GTO thyristor applications. However, the concept of turning off regenerative devices by diverting carriers along a silicon-insulator interface is demon- strated. Furthermore, the device operation is analyzed physically, and extensions of this analysis to high-current switching applications are suggested. 11. DEVICE STRUCTURE AND FABRICATION The main characteristic of the FATO thyristor is that it switches out of regeneration by using the electric field generated by a charged insulated gate to attract carriers out of the body of the device to a silicon surface, where they are camed away through a path which does not in- duce regeneration. One possible structure of the device is shown in Fig. 1. The device has a shorted cathode struc- ture with a MOS gate fabricated along the sidewall of a trench close to the cathode edge. This is the tum-off gate; that is, when the thyristor is in its regenerative state and a negative voltage is applied to this gate, holes are pulled from the electron-hole plasma in the body of the device towards an inversion layer formed at the trench sidewall (see Fig. 1). From there, they are collected by a pf region which is shorted to the cathode. 0018-9383/92$03.00 0 1992 IEEE

The field-assisted turn-off thyristor: a regenerative device with voltage-controlled turn-off

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1946 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 39, NO. 8. AUGUST 1992

The Field-Assisted Turn-off Thyristor: A Regenerative Device with Voltage-Controlled Turn-off

Christopher J. Petti, Member, IEEE, and James D. Plummer, Fellow, IEEE

Abstract-A new solid-state switching element, the Field-As- sisted Turn-off (FATO) thyristor, has been developed. This is a regenerative device, which implies that it is capable of car- rying very large current densities, with a very small forward voltage drop when it is in its on-state. Most regenerative de- vices cannot be turned off with a control signal; however, the structure of the FATO thryistor allows it to be switched off by applying a voltage to a high-impedance, insulated-gate termi- nal. This device can also be fabricated with an insulated-gate turn-on structure, so that it is fully switchable using only low- current control signals. This paper describes the design, fab- rication, and characterization of the FATO thyristor.

I. INTRODUCTION HE SOLID-STATE device structure which is most T suitable for high-current applications is the thyristor.

This is because, like a p-i-n diode, the highly resistive “drift” region of the device has carriers injected into it from both ends and its conductivity is modulated through- out its width. However, since the regenerative on-state of the thyristor is self-supporting, no controlling signal can switch the device off.

Many different variations on the thyristor structure have been developed to overcome this serious limitation. Most rely on the process of removing current from the cathode- anode path and diverting it to another path which is not itself regenerative.

One method of diverting current is that used in the gate- turn-off (GTO) thyristor 113; that is, to simply bring the p-type thyristor base to a more negative voltage than the cathode, thus causing holes to exit the device through the p-type base rather than the cathode. A second approach is the MOS-controlled thyristor (MCT) [3], 141 where a MOS device forms a variable resistor which shorts the cathode and the p- base of the structure, effectively in- creasing the holding current of the device while it is in the on-state. The maximum current that this device can tum off is limited by the parasitic resistances in series with

Manuscript received October 2, 1990; revised December 3, 1991. The review of this paper was arranged by Associate Editor T. P. Chow.

C. J. Petti was with the Center for Integrated Systems, Stanford Uni- versity, CIS 114, Stanford, CA 94305. He is now with Cypress Semicon- ductor, San Jose, CA 95134.

J . D. Plummer is with the Center for Integrated Systems, Stanford Uni- versity, CIS 114, Stanford, CA 94305.

IEEE Log Number 9201206.

the MOS turn-off device, as well as the MOS channel re- sistance itself.

The remainder of this paper describes the structure, fabrication, and operation of a new regenerative switch- ing device, the field-assisted turn-off (FATO) thyristor [ 5 ] , [ 6 ] . Like the GTO thyristor and the MCT, the FATO thyristor is able to be switched off with a control signal, and this is accomplished by extracting holes from the heavily injected region. However, holes are attracted away from the regenerative path toward a silicon surface underneath a MOS gate; the gate effectively induces an alternative collector for the p-n-p transistor. Thus very little control current is needed to turn off this thyristor, since the tum-off electrode is an insulated gate. Further- more, the maximum current that can be turned off is not limited by the parasitic resistances in series with this in- duced collector, because the collector is operating as a current source.

The prototype devices described here experimentally switched off current densities up to 25 A/cm2, which is relatively small compared to the 1000 A/cm2 usually as- sociated with GTO thyristor applications. However, the concept of turning off regenerative devices by diverting carriers along a silicon-insulator interface is demon- strated. Furthermore, the device operation is analyzed physically, and extensions of this analysis to high-current switching applications are suggested.

11. DEVICE STRUCTURE AND FABRICATION The main characteristic of the FATO thyristor is that it

switches out of regeneration by using the electric field generated by a charged insulated gate to attract carriers out of the body of the device to a silicon surface, where they are camed away through a path which does not in- duce regeneration. One possible structure of the device is shown in Fig. 1. The device has a shorted cathode struc- ture with a MOS gate fabricated along the sidewall of a trench close to the cathode edge. This is the tum-off gate; that is, when the thyristor is in its regenerative state and a negative voltage is applied to this gate, holes are pulled from the electron-hole plasma in the body of the device towards an inversion layer formed at the trench sidewall (see Fig. 1). From there, they are collected by a pf region which is shorted to the cathode.

0018-9383/92$03.00 0 1992 IEEE

PETTI AND PLUMMER: THE FIELD-ASSISTED TURN-OFF THYRISTOR 1947

(a) (b) Fig. 1, Current flows in the FATO thyristor (a) during the on-state and (b) during the turn-off process. Filled arrows represent hole current: open ar- rows represent electron current.

(b) (a) Fig. 2. Equivalent circuits for the FATO thyristor. (a) Current-triggered

device. (b) Voltage-triggered device.

The device most closely resembles a GTO thyristor in the fact that a hole current is being diverted out of the electron-hole plasma. As in the GTO thyristor, this causes the injected carrier concentration in the n-type base region to decrease, until the anode current level can no longer be supported [ 11. This process takes a definite amount of time (the storage time), which is discussed in more detail be- low. The difference between the FATO thyristor and a standard GTO thyristor is that the gate current in the GTO thyristor flows out to an external circuit, whereas the gate current in the FATO thyristor is entirely internal to the device and flows out the cathode.

The trench-MOS structure can be thought of as induc- ing a second p-type collector for the thyristor’s p-n-p tran- sistor, as shown in the equivalent circuit in Fig. 2. Cur- rent flowing through this collector does not cause the device to latch, therefore if enough current can be di- verted from the main p-n-p collector through this collec- tor, the device will turn off. As implied above, this cur- rent is analogous to the off-gate current in a GTO thyristor. The area of this induced “turn-off” collector, relative to the area of the main p-n-p collector, will determine the maximum current that will flow through it, and therefore the maximum current that can be switched off. That is, a device with a larger off-gate area can turn off a larger cur- rent, even if the resistance of the path diverted holes must take to get to the cathode increases as the off-gate gets larger. In other words, the collector induced by the gate is acting as a bipolar collector in the active region; i .e. , a current source. This is true as long as the resistance of the hole diversion path is low enough so that the voltage at the end of the off-collector far from the cathode short is not more than a few tenths of a volt above the cathode potential.

Prototype devices were fabricated with turn-off gates fabricated on the sidewalls of dry-etched trenches. Since the depth of the trench will determine the area of the turn- off gate of the device, to investigate how the off-gate area affects the device’s maximum switchable current, devices with varying trench depths should be examined. A total of six different trench depths were used in the fabrication of the device; they are shown in Table I , along with the

TABLE I FATO THYRISTOR PROTOTYPE PROCESS PARAMETERS

epi thickness Wep, 20 pm epi doping N E p- -base dose Q,- trench depth d,, p- junction depth xlE n - junction depth x , ~ trench oxide thickness to,

5 x 1 0 ~ ~ c m - ~ 1 , 2 , 5 x 1013 cm-’ 7.4, 8.9, 10.3, 13, 15, 17prn 2.5 pm 1.3 p q 1200 A

values for other important process parameters, and the symbols that represent them throughout this paper.

Note that the addition of a trench MOS structure will affect the voltage blocking capability of the device. When the device is in its off state, the anode is at a high positive voltage with respect to the cathode and the turn-off gate. Since there is no current flowing through the anodeln-base junction, the undepleted portion of the n base is at roughly the same potential as the anode. Therefore, the MOS tran- sistor formed on the trench sidewall (whose source and drain are the p-base regions on either side of the top of the trench) has a gate-source voltage of zero, but a very high body bias. Thus the MOS channel is not inverted (its threshold voltage has been shifted to a high negative value) [8], and the depletion layer that extends underneath the trench is as wide as the depletion layer of the p base/n base junction. Thus the punchthrough of the n base will occur at a lower anode voltage for this device than for a device without a trench.

To avoid this premature breakdown, the n base must be extended; in fact, the distance from the trench bottom to the anode/n base junction must now be as large as the entire n-base width for a device without a trench. This larger drift region will adversely affect the on-state resis- tance of the device, but only slightly [ 101 , [ 1 13.

Several different types of FATO devices were fabri- cated on the prototype wafers. They included current-trig- gered devices, two-gate voltage-triggered devices (where a trench turn-off gate was added to a conventional insu- lated-gate thyristor [7]), and one-gate devices. For these three-terminal devices, shown in Fig. 3 , the on-gate is tied to the off-gate, so that a positive voltage applied to

I

1948 IEFF rRAUSAC'I IOKS O\ ELF-ClKON DFVlCtS. \'OL 34. NO X. AUGUST 1992

niques were used to fomi the various junctions. The trenches were formed using an SF, process [ 121-[ 141. The resulting trench was slightly bowed, with well-rounded bottom comers, which can support high-voltage opera- t ion . The tum-on andoturn-off gate oxides were grown simultaneously: I000 A of oxide was grown on the surd- face turn-on gates. whereas approximately 1100-1200 A was grown on the ( 1 IO) trench sidewalls (turn-off gates). Note that contact to the poly on the trench sidewalls was

Anode 1 2 )

Trench

Actlve Area (P -)

Poly

x+

Meol

Fig. 4. Photomicrograph of a one-gate device with W , = 10 p i l l . The a n - ode conccntration in made to the backside o i the water

this single gate will trigger the device t o the on-state. and a negative voltage will turn the device off. Physically, this merging of two terminals is accomplished by interrupting the trench and placing a turn-on gate section in the re- sulting gap.

All of these devices were laid out in an "open geome- try"; that is. the devices were in the form of parallel fin- gers of active area. The total area of all devices was 0.45 x lo-' cm2. the device cathode finger widths (W,) varied between 10 and 50 pm, and the device width Z varied between 0.09 and 0.45 cm.

A photomicrograph of a fabricated one-gate device is shown in Fig. 4.

These prototype wafers were fabricated on n ~ /p' epi- wafers, with 1 x 10" cni-' boron in the substrate and 5 x 10" cm --' phosphorus in the epilayer. This epilayer was approximately 20 pm thick. Standard ditfusion tech-

made through the ends of the trenches

111. DC MEASLIREMENTS A N D MODEL

Steady-state measurements of the prototype F A T 0 de- \,ices were made under resistive load conditions, with a load resistance RI of 1 kf l . unless otherwise noted. Fig. 5 shows the ofT-gate voltage needed t o tum off the device, plotted against anode current /4 being switched, for one- gate and two-gate voltage-triggered devices. The anode current is normalized to the device holding current ZH, which was 5 to 6 mA. Note that the one-gate device switches substantially more current than the two-gate de- vice. This is because the one-gate device has trenches on both sides of the cathode area, while the two-gate device has a trench on one side only: thus the one-gate device has twice as much off-gate area as the two-gate device. Not only does this demonstrate the functionality of the device. it also indicates that the area of the off-gate is critical in determining the maximum switchable current of the device.

To further investigate the dependence of current switching capability to off-gate area. devices with differ- ent trench depths were measured. The results are plotted in Fig. 6. where the maximum switchable current / A , m d ,

is plotted against the off-gate length W, which is the length of the portion of the trench off-gate that collects holes. This should be equivalent to the portion of the trench off- gate that overlaps the n -base region; it was estimated from off-gate to n --base accumulation capacitance mea- s u remen ts.

A PISCES 19) simulation of the device turning off is shown in Fig. 7 . In this figure. the lines represent the flow of current; 5 % of the total current flows between each pair of lines. The current flowing along the sidewall of the trench at the point at which the device shuts otf can be clearly seen.

To model this behavior, the current flow patterns inside the device are shown schematically in Fig. 8 . For a device in the on-state with no of-gate bias. the hole current pat- tern is shown in Fig. X(a): let I,, be the hole current being collected by the p-base region. Note that, if the central p / n junction is not overly forward-biased, I p = CY^^,^^^^,,. where I, is the anode current and N ~ - ~ ~ . ~ is the common base current gain of the p-n-p transistor. This latter factor represents effects of both hole recombination i n the n base and electron back injection into the p t an- ode. The hole current pattern in a device where the off- gate is biased (negatively with respect to the cathode) to

PETTI A N D PLUMMER: THE FIELD-ASSISTED TURN-OFF THYRISTOR 1949

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

(IA-IH)/I"

Fig. 5 . Off-gate voltage versus normalized anode current being switched for a one-gate device and a two-gate voltage-triggered device (with the trench gate used as an off-gate), both with W, = 20 Fm, trench depths of 13 p n , and a p-base dose Q,- of 5 X l O I 3 cm-2. The holding currents were between 5 and 6 mA.

e

Fig. 8 . Schematic representation of hole current flows in the FATO thy- ristor in the on-state with (a) Vr,R8 = 0 and (b) Voa8 biased negatively to a point just before the device shuts off.

the point just before the device shuts off is shown sche- matically in Fig. 8(b). At this point, the current being collected by the p base is just sufficient to keep the device in the on-state; that is, the current collected by the p base is just ap.n.pZH.

Now, we can assume that the total anode current Z, is the same for the case of Fig. 8(b) as for the case of Fig. 8(a). This implies that the current flowing through the de- vice is held relatively constant as the off-gate is ramped to a negative voltage, which is the case if the load resis- tance is fairly large. Thus for the case of Fig. 8(b), if ZoRg is the total current being attracted towards the off-gate surface

(1)

To continue, we must know something about the rela- tionship between Zp and ZoRg, the two collector currents. If we assume that the average current densities along the two collectors are the same, then

ap-n-pz, = a p - n - p z ~ + zoffg.

0.0 IIIIIIIIIIIIIIIJ 0 1 2 3 4 5 6 7 8 9 1011 12131415

Off gate length W, (km)

Fig. 6. Maximum switchable current represented as ( I , , , , , - IH)/IH, versus turn-off gate length, obtained from capacitance measure- ments, for current-triggered devices, with a p-base dose of 2 x cm-2. The holding currents for these devices ranged between 4 .5 and 1 1 mA, and V,,a, = -25 V .

ap-n-pzH Ioffg -

S WG

(b) Fig. 7. PISCES simulations of current flow lines in the FATO device (a) with Veer = 0 V and (b) with V,n, = -6.7 V . which is just before the device turns off. The total current flowing through the device in this sim- ulation was 0.164 A / p n .

where S is the total width of the p base. This assumption is roughly valid under two conditions: if the resistance to current flow is small within the n-base region (in the on- state), so that the p-n-p base current (electron current) spreads uniformly throughout the area, then the hole cur- rent emitted from the anode also spreads out uniformly. Also, if the "base widths" for the two collectors are not too different from each other; that is, the trench bottom does not come too close to the anode/n base junction; then the fraction of the hole current emitted from the anode that is eventually collected is roughly the same for both collectors. These two conditions will be met if the device is operating at high current levels, so that the n base is heavily conductivity-modulated, and if the device is de- signed for high-voltage operation, so that the bottom of the trench is well separated from the anode/n base junc- tion.

This analysis also assumes that holes are being col- lected along the entire length of the trench gate ( WG). This will depend on the voltage applied to this gate, and is discussed further below.

I950 IEEE TRANSACTIONS ON ELECTRON DEVICES. VOL. 39, NO. 8, AUGUST 1992

One problem with (2) is that, even with 0 V on the turn- off gate, the emitter (anode) and collector of the p-n-p transistors can have different areas, especially for current- triggered and two-gate voltage-triggered devices. The ef- fect of this is that even areas without p-base diffusion (the turn-on gate regions) are effectively “collecting” holes. Thus (2) should be replaced by

Up-n-plH Ioffg

se, WG ( 3 )

where S < Se, < P , and P is half the edge-to-edge dis- tance between trenches (this is similar to the analysis shown in [15] for IGBT’s). This is further illustrated in Fig. 7. Note that current is collected almost throughout the width of the simulated device, not just under the cath- ode. This is less of a problem for the one-gate devices, which have trenches on both sides of the cathode, since the anode area is almost the same as the main collector area.

By combining (1) and (3), we can obtain a simple, first- order expression for Z,,,,,, the maximum current that can be switched off

-

(4)

According to (4), the curves in Fig. 6 should be straight lines, with slopes equal to 1 /SeE. For low values of WG, the curves are indeed straight lines, and the inverses of the slopes are equal to 31 pm for the devices with WK = 10 pm and 37 pm for the devices with WK = 20 pm. Note that, for the devices whose measurements appear in Fig. 6, P = 40 pm and S = 30 pm for the devices with WK = 20 pm, and P = 30 pm and S = 22 pm for the devices with W, = 10 pm. Thus the values of P more closely match the inverse slopes of the lines in Fig. 6 than the values of S (that is, Se, = P ) .

For higher values of WG, the curves in Fig. 6 curve upwards, away from the straight line defined by (4). For these devices, the trench bottoms come very close to the anodeh base junction. Thus the portion of the trench sidewall near the bottom of the trench will collect more current per unit area than the p-base region, and the as- sumption behind (2) is no longer valid. In fact, since the average density of the current being collected along the trench sidewall is higher than the average current density near the p-base region, it is as if the trench collector area were effectively larger than it actually is, and thus (4) underestimates the amount of current that these devices can turn off.

Although the devices with trenches that almost reach the anode junction can switch more current than the off- collector model would predict, they are not very practical devices, since their breakdown voltages will be quite low. Thus the simple model expressed by (4) can explain the basic turn-off behavior of a practical device. Furthermore, it suggests that a device that can switch a large current will have deep, closely spaced trenches; so that the off-

collector area is large compared to the main-collector area (W,/S, , >> 1). Such a device would also have a higher holding current, which would cause a further increase in maximum switchable current, as described below.

The model developed above predicts that the maximum turn-off current should increase linearly with holding cur- rent. This is because the holding current is a measure of how much current is being collected by the main p-n-p collector at the point of turn-off, when the off-gate is biased to the appropriate voltage. It is thus indicative of how much current the off-collector can attract.

To see the actual dependence of the maximum switch- able current ZA,max on holding current Z H , IA, , , , / IH - 1 was plotted versus Z H for two different values of WG (trench depth) in Fig. 9. The different values of I N were produced by varying the boron dose of the p-base region. According to (4), this plot should be a flat line. For higher holding currents, f A , , , , / Z H - 1 is indeed constant with ZH. However, for low values of Z H , the maximum switch- able current is much higher than predicted by (4).

The reason for this anomaly at low holding currents can be explained as follows. When a low-holding-current de- vice is at a point near its holding point, the amount of charge stored in the n-base region is small. This is be- cause the stored charge is proportional to the electron cur- rent via the recombination condition, and this electron current is small. Thus the extent of conductivity modu- lation in the n base is reduced, to the point where our assumption in the previous discussion of uniform electron current spreading no longer holds. That is, the lateral re- sistance to current flow now forces electron current to flow primarily in the area far from the cathode short. The an- ode, then, no longer emits hole current uniformly across its width, and thus the hole current is also bunched up in the area far from the cathode short. Therefore, the effec- tive area of the main collector is reduced (Se , is reduced in (4)), and the maximum switchable current, relative to the holding current, is increased.

Although a device with a low holding current performs better than expected, it is still desirable to have a rela- tively high holding current. This is because, although the relative value of I,,,,, is high, the absolute value is still small. The maximum current that this device can switch off still scales with the holding current.

Next, we discuss how the voltage applied to the off- gate affects the amount of current that can be switched off. Note that, in Fig. 5, the voltage necessary to switch off the device begins to rise rapidly above a certain anode current; eventually, the maximum switchable current is reached, and no applied off-gate voltage will shut off the device. At this point, the entire off-gate area is collecting holes. For currents below this point, only a portion of off- gate area need collect holes for the device to turn off. The off-gate voltage, then, could be thought of as modulating the effective area of the off-gate: at low voltages, the off- gate collection area is small and thus only small currents can be switched off; at higher voltages, the entire off-gate becomes active. Increasing the off-gate voltage still higher

PETTI AND PLUMMER: THE FIELD-ASSISTED TURN-OFF THYRISTOR

0.5 a I I I I I I x Ts 0.4.- 0 WG=5.8pm -.

2 I v

0.3 .- -.

0.2.- -.

0.1 - - _.

I I I I I 0.0 4

1951

L.

+

will not allow the device to switch more current, since the entire off-gate area is already collecting holes.

This makes sense physically: at low gate biases, the resistance of the inversion layer is relatively high and the current flowing through it increases the bias (or, equiva- lently, reduces the band bending) at the end near the trench bottom, which implies that the collected current density will be lower there. At higher gate biases, the inversion layer resistance decreases, so that the potential all along the interface is close to ground, and holes will be col- lected by the entire off-gate area. Thus the off-gate volt- age changes the effective area of the off-collector, until eventually the entire off-gate area collects holes.

Therefore, we can express the anode current being turned off ZA as a function of off-gate voltage, Voffg, by expressing W, in (4 ) as a function of V,,,,

IV. TRANSIENT BEHAVIOR The dynamic turn-on mechanism for insulated-gate

thyristors has been described previously by Scharf [ 1 11, and numerical analyses have been reported by Adler [ 161. The FATO thyristor resembles very much the insulated- gate thyristor when it is being switched on, and we there- fore will concentrate on the turn-off mechanisms inside the device.

The turn-off process for the FATO thyristor is similar to a normal GTO thyristor, in that current is physically pulled from the electron-hole plasma. Thus like in the GTO there are two stages to the turn-off transient, as shown in Fig. 10: a storage time ts, where the anode cur- rent falls only slightly, and a falltime t f , where the anode current falls rapidly.

The storage phase of a GTO thyristor has been ex- plained [ 11, [2] with a charge-control model that can pre- dict the time necessary to “squeeze” the electron-hole plasma into a minimum size, which is assumed to be on the order of one diffusion length in width. Since the dis- tance between gates is much smaller and the diffusion

t I t

r V,:5 Vldiv < . . . . .

0 5 10 15 20 25 30 35 time (Clsec)

Fig. 10. Turn-off waveform for a one-gate voltage-triggered FATO thy- ristor with W , = 20 pm. Qp- = 2 x IO’’ cm-*, V , = 24.2 V, and R, = 3300 Q , The holding current for this device was 3 mA, and the current being switched off is 6.85 mA.

GTO, it is difficult to apply the “squeezing velocity” model here because it is unclear at what point the squeez- ing should end. Instead, we will think of the storage time as the time it takes for the holes to redistribute themselves so that there is a low concentration of holes near the off- collector.

During the storage period, whatever off-gate current (.Ioffg) that flows is generated from this change in n-base charge d Q / d t , instead of from diffusion of holes from the bulk. Thus hole current is not being diverted from the device’s regenerative path. At the end of the storage phase, the maximum hole concentration gradient is set up; holes now flow from the bulk towards the off-collector surface, and the device can come out of regeneration.

These ideas can be expressed in the following equation:

J . = 2 q D - - - - dp dQ dr dt olfg

where Dp is the hole diffusivity. We can use a linear func- tion to approximate the hole distribution, yielding

where po is the average hole concentration in the bulk of the device, and Se, is the total width of the cathode finger. Assuming p S = po at t = 0, the solution of this equation is

where rFL for holes moving laterally across the n base.

for p s to drop to zero, which is given by

S;,/4Dp is the (high-level) diffusion time

The storage time t , can then be taken as the time it takes

This can be rewritten as

Ioffg

roffg - 1off.min t.7 = TFI. log

lengths are longer in the FATO device than in a normal

__

1952

where I,fl, is the minimum off-gate current necessary to turn off the device; that is, the storage time is infinite if IoKK 5 loff,m,n. If we induce an off-gate current greater than this minimum, which we can do by applying an off- gate voltage more negative than is necessary to shut off the device, we can decrease the storage time. This is shown in Fig. 1 I (a), where storage time is plotted versus off-gate voltage for a given anode current. Note that a very small increase in gate voltage can cause a drastic decrease in storage time.

The conventional GTO thyristor exhibits similar behav- ior, in that increasing the gate current will decrease the storage time [I] . However, this has the obvious drawback of increasing the power needed to control the device. The FATO thryistor, on the other hand, needs only a small increase in gate voltage and a very small increase in driv- ing gate current (depending on the ramp rate of the off- gate voltage) to almost eliminate the storage time.

However, for anode currents near the maximum switchable current, increases in off-gate voltage do not produce increases in induced off-gate current lonn. For these currents, the storage time cannot be reduced by in- creasing the gate voltage. This range of currents is very narrow, though. In Fig. 1 l(b), the storage time is plotted against anode current for a fixed off-gate voltage. It is evident from the figure that reducing the anode current by 5 % reduces the storage time by a factor of 50, so a great improvement in speed can be gained with only a small sacrifice in current capability. Thus although the storage times for the FATO thyristor can be long, they can be almost eliminated under the proper conditions.

The fall time of the FATO thyristor can be analyzed in a similar method to other thyristors; that is, to model the fall time as the time it takes for the remaining carriers to be swept from the thyristor base regions and for the n-base/p-base depletion region to be set up [2], [ 171. One difference between FATO devices and other thyristors is that the presence of the trenches increases the area of the depletion region, so that more charge needs to be swept out during the fall time period. This implies that the fall time of the FATO thyristor will be greater than that of a conventional GTO thyristor. However, an optimized FATO thyristor will have the trenches very close to- gether, and if this trench separation is less than the n-base width, the depletion regions extending from the trench sidewalls will touch each other. The amount of charge that has to be swept out is now limited by the small area between the trenches. In the limiting case, only the charge near the bottoms of the trenches needs be removed; this situation resembles that of a planar junction, as if no trenches were present. Thus the fall time of such an opti- mized device would be closer to that of a GTO. More- over, the lifetime reduction methods used to reduce fall time in GTO thyristors will have the same effects for FATO thyristors as well.

An important consideration for the operation of the FATO thyristor is how much current is available to drive (charge up) the off-gate capacitance, and how it affects the switching time of the device. Because an optimized FATO device would have density packed deep trenches,

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 39, NO. 8. AUGUST 1992

- U $2 v

r”

Vdfg-Voffg,0 (VI Anode current (mA)

(a) (b) Fig. 11. Storage times for turn-off transients, plotted versus off-gate volt- age for a fixed anode current in (a) and plotted versus anode current for a fixed off-gate voltage in (b). The minimum off-gate negative biases needed to turn off the device in (a) (Vc, ,rs ,J was - 1.47 V. All measurements were taken on a one-gate voltage-triggered device with W , = 20 pm and Qp- = 2 x 10” cm-’.

h

-5 0 > 25

time (pec)

Fig. 12. Switching waveforms for a one-gate, voltage-triggered device. The device parameters are W , = 20 pm and Qp : 2 X 10’’ cm-*, and the measurement parameters are R , = 3300 Cl and V , = 20 V .

the off-gate capacitance would be quite high. The FATO thyristor would suffer from a reduced switching speed be- cause of this.

For example, a FATO thyristor with a total chip area of 1 cm2 and 20-pm-deep trenches at a pitch of 9 pm, which would probably switch 100 A, would have a total gate area of 2.2 cm2. With an oxide thickness of 1200 A , this means the gate capacitance would be 64 nF. If 10 mA is available to drive this capacitance, and the off-gate voltage needed is 10 V, the time needed to turn off the device would be 64 ps! This far exceeds the duration of any of the transient periods discussed above. With 100 mA of current available to drive the off-gate, the gate charging time becomes 6.4 ps-still larger than any of the storage and fall times discussed above, but a more rea- sonable value, corresponding to an operating frequency of about 150 kHz. However, with this higher driving cur- rent, more power must be dissipated inside the device. Moreover, this current level requirement would preclude the use of normal low-power logic circuitry to control the device. Thus the high gate capacitance of a large FATO thyristor would be the factor that most limits the switch- ing speed of the device, as is true in many other power devices.

The three-terminal operation of the one-gate voltage- triggered devices is shown in Fig. 12. These devices turn on with a positive signal to their single insulated gate, and

i-

PETTl AND PLUMMER THE FIELD-ASSISTED TURN-OFF THYRISTOR

turn off with a negative signal. Note that a very small voltage, on the order of a volt, is needed to turn the device on. The ramp rates in this measurement are low enough to assure that the device is switching off by diverting cur- rent along the sidewall of the trench, rather than by ex- tracting current in the form of displacement current through the insulated gate.

V. CONCLUSION A new regenerative device with voltage-controlled turn-

off has been introduced. The prototype devices fabricated will switch A/cm2 with dc control signals, which was approximately 1.75 times the device’s holding current. The model represented in (4) suggests a way to optimize this device: use deep trenches placed at narrow pitches for the off-gate. In fact, if trenches 20 pm deep are spaced 5 pm apart in a one-gate design (so that each cathode fin- ger has trenches on both sides), W , = 40 pm and &, = 5 pm, so that such a device should be able to switch nine times its holding current.

The dynamic properties of the device are not unlike those of other highly conductivity-modulated devices. The GTO-like storage time can be reduced by overdriving the off-gate electrode. This off-gate, however, does introduce a capacitance charging time to the turn-off time of the de- vice. Finally, the F A T 0 thyristor can be fabricated with a combined on/off gate, so that three-terminal operation can be achieved.

ACKNOWLEDGMENT The authors wish to thank D. K. Y. Liu and D. Boisvert

for their helpful discussions during the course of this work, as well as R. Taft and W. Kavanaugh for their help in the preparation of this paper.

REFERENCES

[ I ] E. D. Wolley. “Gate turn off in p-n-p-n devices,” IEEE Trans. Elec- tron Devices, vol. ED-13, pp. 590-612, 1966.

[2) S . K. Ghandhi, Semiconductor Power Devices. New York: Wiley. 1977,pp. 235-243.

131 V. A. K . Temple, “MOS-controlled thyristors-A new class of power devices,” IEEE Trans. Electron Devices. vol. ED-33, no. 10, pp. 1609-1618. 1986.

[4] M. Stoisiek and H. Strack, “MOS GTO-A turn o f f thyristor with MOS controlled emitter shorts,” in IEDM Tech. Dig., 1985, pp. 158- 161.

[SI C . J . Petti and J . D. Plummer, “The field-assisted turn-off thyristor: A regenerative device with voltage controlled turn-off,” in IEDM Tech. Dig., 1987, pp. 662-665.

161 C. J . Petti, “Physics and technology of the field assisted turn-off thy- ristor: A regenerative device with voltage controlled turn-off,” Ph.D. dissertation, Stanford University, Stanford, CA, 1989.

171 J . D. Plummer and B . W . Scharf, “Insulated gate planar thyristors: I-Structure and basic operation,” IEEE Truns. Electron Drvice.~, vol. ED-27, no. 2, pp. 380-387, 1980.

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(81 S . M. Sze, Physics of Srvniconductor Devices. New York: Wiley, 1981, pp. 442-444.

191 M. R . Pinto. C . S . Rafferty, H . R. Yeager, and R . W. Dutton, “PISCES-IIB supplementary report,’’ Tech. Rep., Stanford Elec- tronics Laboratories, Stanford, CA, 1986.

[IO] S . C. Choo, “Effect of carrier lifetime on the forward characteristics of high power devices,” IEEE Truns. Electron Devices, vol. ED-17, no. 9 , p p . 647-652, 1970.

[ I 1 1 B. W. Scharf, “An insulated gate thyristor structure: Principles of operation and design,” Ph.D. dissertation, Stanford University, Stan- ford, CA, 1979.

[ I21 C. Gonzales and J . P. McVittie, “A study of trenched capacitor struc- tures,” IEEE Elec[ron Dri1ic.e Lctt . , vol. EDL-6, no. 5 , pp. 215-218, 1985.

[ 131 S . D. Leeke, D. K. Y. Liu, and J . P. McVittie. “Plasma mode trench etching with direct hydrocarbon injection,“ in MRS Symp. Proc.,

141 J . P. McVittie, T. A. Lin, and A . J . Bariya, “A new method for analyzing thin sidewall inhibitor layers,” in MRS Symp. Proc., 1987,

151 J . G. Fossum and R. J . McDonald, “Charge-control analysis of the COMFET turn-off transient,” IEEE Truns. Electron Devices. vol. ED-33. no. 9 , pp. 1377-1382, 1986.

161 M. S . Adler and V. A. K . Temple, “The dynamics of the thyristor turn-on process,” IEEE Trans. Elrcrron Devices, vol. ED-27, no. 2,

[ 171 P. A. Gough and J . A . Slatter. ”A model forthe GTO thyristor during switch-off.” IEEE Truns. EIectron Dcl.icr.v, vol. ED-31, no. 12, pp. 1796- 1803. 1984.

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pp. 483-494. 1980.

Christopher J. Petti (S’87-M’89) was born in North Reading, MA, in 1962. He received the B.S. degree in physics from the Massachusetts In- stitute of Technology, Cambridge, in 1984, and the M.S. and Ph.D. degrees from Stanford Uni- versity, Stanford, CA, in 1985 and 1989, respec- tively.

While at Stanford, he investigated MOS-gate thyristor structures, as well as the electrical char- acteristics of devices built on the sidewalls of dry- etched trenches. He is currently with Cypress

Semiconductor Corporation, San Jose, CA, where he is working on ad- vanced static RAM technology development.

James D. Plummer (M’71-SM’82-F’85) was born in Toronto, Ont., Canada. He received the B . S . degree in 1966 from the University of Cali- fornia, Los Angeles, and the M.S.(EE) and Ph.D.(EE) degrees from Stanford University, Stanford, CA, in 1967 and 1971.

He is presently the John M. Fluke Professor of Electrical Engineering and the Director of the In- tegrated Circuits Laboratory at Stanford Univer- sity. His current research interests include mod- eline of semiconductor Drocess technolow. the v -_

physics and technology of scaled bipolar and MOS devices, the develop- ment of CAD tools for silicon and GaAs structures, high-voltage devices and integrated circuits, and manufacturing problems associated with VLSI. He is the author of over 175 technical papers in these areas, has received three best paper awards at the International Solid State Circuits Confer- ence, and was the Technical Program Committee Chairman for the 1980 ISSCC. From 1982 to 1986 he was an Associate Editor of the IEEE TRANS- ACTIONS O N ELECTRON DEVICES, and was Electron Device Society National Lecturer in 1985.

Dr. Plummer is a member of Tau Beta Pi, Sigma Xi, American Physical Society, and The Electrochemical Society.