The Intel Architecture and Windows Internals

Chapter 10 Advanced Operating System

Overview Processor

Fetch instructions, decode instructions into a series of micro-operations, execute micro-operation

Cache: high speed memory sits between processor and primary memory

Accessed instructions and data are copied from primary memory to cache

Transfers from cache are faster than transfers from primary memory

Memory subsystem: primary memory, two integrated caches

Primary cache (L1): Internal cache Secondary cache (L2): External cache

Overview L1: code cache and data cache

Instructions are fetched into L1(code cache) L1(data cache) holds accessed data

L2: data requested but not in L1 Cache hit

When processor request data that already present in L1 data cache

Cache miss When data that requested are not in the cache L1 data cache hands the operation off to L2, which

request data from the system bus

Block Diagram of Pentium

Bus interface unit

L2 cache

L1 data cacheL1 code cache

Core processor

Cache bus

Fetch Load Store

System bus

Intel Execution Environment Intel architecture processor

Eight 32-bit general-purpose registers Six 16-bit segment registers Two 32-bit status and control registers

EIP: instruction pointer register EFLAGS

Intel Execution Environment General purpose register

Storage area for the results of arithmetic, logical operation, address calculation, and memory pointer

Segment register Holds pointer to segment location in memory

Instruction pointer Contain the displacement in the current code

segment for the next instruction to be executed

EFLAGS register Stores the status of most instructions

Intel Execution Environment

Eight 32-bit general purposeregisters

Six 16-bitsegmentregisters

32-bit EFLAGS register

32-bit EIP register

4GB address space

Execution mode Intel architecture supports 4 modes of operation

Real address mode (MS-DOS) is for real systems that still run older 8086 programs

Protected mode (Windows XP, Linux) provides code and data protection that allows multiple programs to run concurrently

Virtual 8086 mode runs under protected mode To provide compatibility with old MS-DOS program while

allowing the concurrent execution of Windows XP or Linux applications

When user open MS-DOS windows in Windows 95, 98, 2000 System management mode is for system security

and power management

Memory addressing Intel uses real memory (physical

memory): each byte is assigned a unique physical address (from 0 to maximum 4G)

Program instructions (software) specify logical address (base address and offset address) Relative to some reference location Need not be associated with a specific

physical address Virtual memory

Memory addressing Physical address

Real memory address Sequence of bytes Hardware requires physical address

Logical address Relative Base plus offset address Software references logical address Translate to physical at execution time

Address Translation All addresses seen by a process is

logical address. To read some data or code from

RAM, the CPU has to submit the physical address (the real one) onto the bus.

The CPU uses the page table of the running process to translate every address used at runtime.

Address Translation

… is done every time the CPU needs to access data/code in RAM when the CPU fetches an instruction when the CPU executes an instruction

that access data in RAM (not present in cache)

Address translation Segmented logical address

the segment selector identifies the segment points to the segment descriptor

which holds the segment’s base address The actual logical address is an offset within

this segment. At execution time

processor translates the logical address to a linear address

adding the offset to the segment’s base address.

Memory protection Memory protection

Prevent task from changing contents of memory Limit checking ensures that a given memory

access is not beyond the segment’s boundaries.

Type checking ensures that only code, data, or stack segment descriptors are used

Segment protection privilege levels Level 0: highest privilege Level 3: lowest privilege Task executing at a lower privilege can not access to

segment of the higher privilege task

Memory protectionLevel 3 (application programs)

Level 2 (operating system services)

Level 1 (operating system services)

Level 0(operating system

kernel)

Highest privilege level

Lowest privilege level

Improving the performance of Intel

Architecture

Pipelining

Pipeline multiple instructions to be processed

simultaneously break up the machine cycle into

multiple stages each stage representing a different

function

Pipelining

Instruction 4 Instruction 3 Instruction 2 Instruction 1

Fetch Decode Execute Write-back

Machine cycle

Fetch: retrieve instruction from memory

Decode: translate into micro-operation

Execute: run micro-operation

Write back: result is written to memory

Pipelining Increase processor’s throughput Superpipelining

Chip uses more than four stages to complete an instruction

Faster clock cycle than pipeline Scalar processor=>use single

pipeline Superscalar processor=>use more

than one pipeline

Hyperthreading Problem: difference between processor

speed and memory speed=>result is waiting

Solution=>using idle latency time of processor to execute other different task Hyperthreading

Execution of tasks in parallel Implements hyperthreading by allowing the

operating system to work on two logical processors The system keeps track of both logical processors’

states and allows them to share the remaining physical execution resources.

Hyperthreading

Logical processor#1 state

Logical processor#2 state

Shared execution resourcesProcessorControl logicBranch predictorsBusesCache

Increasing Clock Speed

B is dependent on A A and B must be

executed in sequence C and D are

independent of A and B and of each other

C and D can execute in any order

A, C, and D can execute in parallel

A R1 = Mem(x)

B R2 = R1 - R3

C R4 = 100

D R5 = R5 - 10

Out-of-order execution

Branch prediction

Out-of-order execution Instructions are

executed sequentially 4 machine cycles

A, C, and D can execute in parallel (first clock)

B is executed in a second clock Result: two machine

cycles

A R1 = Mem(x)

B R2 = R1 - R3

C R4 = 100

D R5 = R5 - 10

Branch prediction Branch instruction: any instruction that

causes a break in the sequential execution of instructions

How to include branches Jump, procedure call, return, interrupt

Try to predict the target instruction for the next jump Correct: processor throughput is increased Incorrect: flush prediction then fetch and

execute the correct instruction

MMX technology MMX (Multimedia extension)

Enhance the performance of multimedia applications

Video, audio, and 3D graphics Manipulate many data in parallel

Extension: new registers, data types, additional instruction to support multimedia

Remove L2 cache from the data transfer path

Read/write directly from memory

Intel 64-bit Architecture

Increasing clock speed Out-of-order- execution Branch prediction

Parallel working EPIC: explicitly parallel instructional

computing Bundle instructions

Intel 64-bit Architecture Bundling

Technique for increasing parallelism

Instructions Template: how to processor handle the

instruction

Instruction 2(41 bits)

Instruction 1(41 bits)

Instruction 0(41 bits)

Template (5 bits)

128-bit (2-word) instruction bundle

Windows XP Internals

Windows XP 32-Bit Windows XP system is divided into the

user mode and kernel mode. User mode

A windows operating mode in which user application and a collection of subsystems execute

Kernel mode The core of the operating system A windows operating mode in which kernel mode

processes have access to the entire system memory and all processor instructions

User Mode Components

Envionment subsystem Integral subsystem

Serverprocess

Systemprocess

Win32subsystem

Win32 DLL

VDM

Kernel mode components

User mode components

Win32application

Win16/MS-DOS

application

Application programs

Kernel Mode

Kernel mode components

Executive services

Hardware abstraction layer (HAL)

Device drivers Kernel

Layer 1

Layer 2

Layer 3

User mode components

Memory management 32-bit addresses Virtual memory manager (VMM)

Paging Swapping between main memory and

disk Clustering

Memory Management Windows XP uses a virtual memory

manager (VMM) to allocate memory to processes and to manage system memory.

When a process or thread references a virtual address on an invalid page, a page fault occurs. The system responds by reading (or swapping)

the requested data (or code) from disk into the first available physical memory location.

Memory Management

Valid

Invalid

Page already inmemory

Swap in

VMM

Swap out

Page file

Virtual addressspace

Physical addressspace

Pages

Pagefault

First in, firstout swap

Disk Management Dynamic storage is a feature that

allows a user to resize a disk without restarting windows XP.

You can divide a dynamic disk into volumes.

Fault tolerance is the ability of the computer to recover data in case of errors.

File Management

Windows XP supports FAT, FAT32 and its native NTFS file system.

NTFS enables the smooth recovery of the file system in case of a system crash or disk failure.

Input/Output manager Manage the system’s device driver Work with virtual memory

manager (VMM) Each service request

Formatted as I/O request packet (IRP) IRP forwarded to device driver On completion, device driver sends

message to I/O manager

Device driver

A software routine that allows the operating system to communicate with a specific piece of hardware.

3 types Hardware device driver File system driver Network driver

Caching Process requests I/O

service. I/O manager sends

IRP to cache manager.

Cache manager copies data to VMM

VMM notifies process data are available

Process

File systemdrivers

Cachemanager

Hardware(disk) drivers

Virtual memorymanager

1

2

3

I/O manager

IRP

Data copy

I/O service request

4

Notify

Caching

If file is not in cache, the cache manager initiates the necessary physical I/O to read a copy from disk.

Process

File systemdrivers

Cachemanager

Hardware(disk) drivers

Virtual memorymanager

1

2 3

4

5

6

Pagefault

Non-cachedservice request

I/O manager

IRP

Data copy

7

8 9

IRP Data

I/O service request

Data

IRP

10

Notify

Registry The registry is a hierarchical database used by

windows XP to keep track of hardware and software settings within the computer.

Registry holds info on System hardware Device drivers Network adaptor User profiles Hardware profiles

Initialized at startup System configuration

Windows 64-Bit Version What does 64-bit mean?

It processes data in chunks The CPU does that processing in chunks of

64 bits at a time What Is x64?

You can, in fact, run 32-bit Windows on an x64 processor without any difficulty

Running 32-bit applications on a 64-bit operating system

Run a 32-bit application in a 64-bit operating system

Translate the 32-bit instructions so that the 64-bit operating system can understand them

Windows 64-Bit Version What’s the difference between 64-bit

and 32-bit? 64-bit processors have a larger address

space. They have the ability to communicate

directly with more memory A 32-bit processor can directly address a

maximum of 4 gigabytes (GB) of memory A 64-bit processor running Windows XP x64

supports 128 GB of physical memory, and 16 terabytes (TB) of virtual memory

Windows XP Pro x64 Architecture

Benefits Compatibility

Windows XP Pro x64 is a natural progression from existing 32-bit Windows XP Pro, and the vast majority of programs written for Windows XP Pro will run in Windows XP Pro x64 without any change or modification.

The mechanism that Windows XP Pro x64 uses to run 32-bit applications is called Windows on Windows 64-bit, better known as WOW64.

Performance support for vastly more memory than

existing 32-bit computing

Benefits Security

Data Execution Prevention (DEP) bit that controls which areas of memory can be used to execute code

Windows XP Pro x64 works with DEP to protect computers against buffer overflow attacks

Support Microsoft Kernel Patch Protection technology, which prevents unauthorized programs from patching the Windows kernel

Reliability Windows XP with Service Pack 2 (SP2), the initial

release of Windows for x64 processors is a highly reliable and secure operating system

Potential

Conclusion Selecting Windows XP Professional x64 Edition

is not the right choice for everyone today, but for those users who are pushing the limits of 32-bit Windows XP, it is the smart choice as long as they understand the current state of application and device support.

As we move forward to Windows Vista, I expect to see 64-bit computing move to the mainstream, especially for those users who demand the highest levels of security, reliability, and functionality.