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18 Computer Published by the IEEE Computer Society A new chipmaking approach marks the biggest change in transistor technology since the introduction of polysilicon-gate, metal- oxide-semiconductor transistors in the late 1960s, according to Intel cofounder and chair emeritus Gor- don Moore. This is how the man for whom Moore’s law was named evaluates a move by three major chipmakers— Advanced Micro Devices (AMD) and IBM working together, and Intel on its own—to change two of the three most important materials used to make the transistors that are at the heart of today’s microprocessors. This could overcome the most substantial roadblock to continuing to use current production processes to shrink transistor elements and thereby increase chip performance, noted University of California, Berkeley, associate professor Vivek Subramanian. Mark Bohr, a Senior Fellow with Intel’s Logic Technology Group, said this will enable chipmakers to scale down feature sizes through several more generations, from the 65 nanometers used today to 22 nm over the next few years. AMD, IBM, and Intel have announced plans to replace the sili- con dioxide insulator layer of pro- cessors with new hafnium-based high-k materials, which increase charge transmission and help reduce electrical leakage. To accommodate this, they will replace the doped polysilicon used in transistor gates with a combination of metals. This solves a key problem: build- ing transistors smaller horizontally so that manufacturers can pack more of them onto chips while increasing energy efficiency and con- tinuing to use current chipmaking techniques, thereby avoiding expen- sive fabrication-plant changes. Until now, as transistors have got- ten smaller, they have faced potential current-flow problems. Also, the transistors’ insulation layers have gotten so narrow—as little as five atoms thick—that they leak enough electrons to increase power con- sumption, generate heat, and hurt performance. Further thinning the insulator layer—called the transistor gate dielectric—to three atomic layers, to continue shrinking transistors, would make this worse, noted Risto Puhakka, president of VLSI Research, a chip-market analysis firm. Use of the new materials, on the other hand, reduces leakage five to 10 times from current levels, said Bohr. The new chips could be used in laptops, PCs, and servers, and, because of their energy efficiency, eventually even in power-con- strained devices like cell phones. The technology faces potential challenges such as production com- plexity and the increased risk of material contamination. Nonetheless, Intel plans to mass- produce chips with 45-nm feature sizes using the new materials during the second half of this year, said Bohr. IBM expects to begin producing 45-nm chips based on the materials next year. “If you are going to move to more advanced processor technology, you will have to consider this approach as one of the most likely options,” said Jim McGregor, market-research firm InStat’s director for semicon- ductors and enabling technologies. A NEW DAY Electrical current flowing at either a high or low level across two gate electrodes on either side of the tran- sistor channel represents the ones and zeros of binary data. The insulating gate dielectric, tra- ditionally made of silicon dioxide, sits below the gate electrode and above the silicon substrate. It trans- mits voltage from the gate electrode to the underlying transistor channel and prevents the leakage of current when the electrode is powered. As chipmakers make transistors smaller so that they can pack more of them onto chips, they have made the gate dielectric thinner. However, this has led to dramatically higher gate leakage and power consumption. “Leakage has been an issue for the last couple of generations of proces- sors, starting at those with 130-nm [feature sizes],” McGregor noted. The technology The AMD, IBM, and Intel chip- making approaches focus on using new materials in the gate dielectric. Different materials must also be used in the gate electrodes so that they can function optimally with the new dielectric. The Next Big Thing in Chipmaking George Lawton

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18 Computer P u b l i s h e d b y t h e I E E E C o m p u t e r S o c i e t y

T E C H N O L O G Y N E W S

A new chipmaking approachmarks the biggest changein transistor technologysince the introduction ofpolysilicon-gate, metal-

oxide-semiconductor transistors inthe late 1960s, according to Intelcofounder and chair emeritus Gor-don Moore.

This is how the man for whomMoore’s law was named evaluates amove by three major chipmakers—Advanced Micro Devices (AMD)and IBM working together, and Intelon its own—to change two of thethree most important materials usedto make the transistors that are atthe heart of today’s microprocessors.

This could overcome the mostsubstantial roadblock to continuingto use current production processesto shrink transistor elements andthereby increase chip performance,noted University of California,Berkeley, associate professor VivekSubramanian.

Mark Bohr, a Senior Fellow withIntel’s Logic Technology Group, saidthis will enable chipmakers to scaledown feature sizes through severalmore generations, from the 65nanometers used today to 22 nmover the next few years.

AMD, IBM, and Intel haveannounced plans to replace the sili-con dioxide insulator layer of pro-cessors with new hafnium-basedhigh-k materials, which increasecharge transmission and help reduceelectrical leakage. To accommodate

this, they will replace the dopedpolysilicon used in transistor gateswith a combination of metals.

This solves a key problem: build-ing transistors smaller horizontallyso that manufacturers can packmore of them onto chips whileincreasing energy efficiency and con-tinuing to use current chipmakingtechniques, thereby avoiding expen-sive fabrication-plant changes.

Until now, as transistors have got-ten smaller, they have faced potentialcurrent-flow problems. Also, thetransistors’ insulation layers havegotten so narrow—as little as fiveatoms thick—that they leak enoughelectrons to increase power con-sumption, generate heat, and hurtperformance.

Further thinning the insulatorlayer—called the transistor gatedielectric—to three atomic layers, to continue shrinking transistors,would make this worse, noted RistoPuhakka, president of VLSI Research,a chip-market analysis firm.

Use of the new materials, on theother hand, reduces leakage five to 10times from current levels, said Bohr.

The new chips could be used in

laptops, PCs, and servers, and,because of their energy efficiency,eventually even in power-con-strained devices like cell phones.

The technology faces potentialchallenges such as production com-plexity and the increased risk ofmaterial contamination.

Nonetheless, Intel plans to mass-produce chips with 45-nm featuresizes using the new materials duringthe second half of this year, said Bohr.

IBM expects to begin producing45-nm chips based on the materialsnext year.

“If you are going to move to moreadvanced processor technology, youwill have to consider this approachas one of the most likely options,”said Jim McGregor, market-researchfirm InStat’s director for semicon-ductors and enabling technologies.

A NEW DAYElectrical current flowing at either

a high or low level across two gateelectrodes on either side of the tran-sistor channel represents the onesand zeros of binary data.

The insulating gate dielectric, tra-ditionally made of silicon dioxide,sits below the gate electrode andabove the silicon substrate. It trans-mits voltage from the gate electrodeto the underlying transistor channeland prevents the leakage of currentwhen the electrode is powered.

As chipmakers make transistorssmaller so that they can pack more ofthem onto chips, they have made thegate dielectric thinner. However, thishas led to dramatically higher gateleakage and power consumption.

“Leakage has been an issue for thelast couple of generations of proces-sors, starting at those with 130-nm[feature sizes],” McGregor noted.

The technologyThe AMD, IBM, and Intel chip-

making approaches focus on usingnew materials in the gate dielectric.Different materials must also beused in the gate electrodes so thatthey can function optimally with thenew dielectric.

The Next Big Thing inChipmakingGeorge Lawton

April 2007 19

Core 2 Duo, Core 2 Quad, and Xeonfamilies of mobile, desktop, andserver multicore processors.

Intel anticipates the first genera-tion of the new 45-nm chips will pro-vide twice the transistor density ofcurrent 65-nm processors, said com-pany spokesperson Kari Aakre.

They will also reduce gate oxideleakage by 90 percent, consume 30percent less transistor-switchingpower, and either decrease source-to-drain leakage by 80 percent oroffer 20 percent more transistor-switching speed.

To improve precision, Intel says,it will build the dielectric usingatomic-layer deposition, in which amachine deposits the high-k mater-ial one layer of atoms at a time.

The company will use traditionaldry lithography to build the 45-nmchips. However, it is consideringimmersion lithography for the nextgeneration of chips, which will have32-nm feature sizes. This techniquefocuses the light that etches the cir-cuit pattern onto the wafer througha thin layer of water. This helps bet-ter focus the light and therebyachieve smaller features.

IBM and AMDIBM and AMD are working with

Sony and Toshiba on their chip-making project.

Gate dielectric. As Figure 1shows, the gate dielectric tradition-ally has been made of silicon diox-ide, a poor conductor of electricitythat prevents the leakage of electronsfrom the gate to the substrate. Overtime, Intel has reduced the silicon-dioxide gate dielectric’s thickness to1.2 nm—five atomic layers—forchips with 65-nm feature sizes.

However, electrons increasinglyleak through such a thin layer. Thiswastes energy. And, when the elec-tron flow hits the dielectric, the resis-tance generates heat.

To cope with these problems,AMD, IBM, and Intel have experi-mented with making gate dielectricsusing high-k materials, includinghafnium. (“k” represents the dielec-tric constant, which describes amaterial’s ability to transmit chargewhen a voltage is applied.)

Jim Hutchby, director of device sciences at Semiconductor ResearchCorp., an industry research-manage-ment consortium, said AMD, IBM,and Intel probably are using nitrideof hafnium silicate consisting ofhafnium, silicon, oxygen, and nitro-gen. However, AMD, IBM, and Intelare not disclosing the exact mix ofmaterials used in their new designs.

As transistors have becomesmaller horizontally, they have alsohad to cope with narrower transis-tor channels. To provide the currentnecessary for the system to accu-rately read high and low levels, thesmaller systems must get more elec-trostatic charge through the dielec-tric layer to the channel.

High-k materials can transmitmore charge than silicon dioxide.And building the dielectric thickervertically would provide more resistance, which reduces leakagewithout making transistors biggerhorizontally.

Scientists have researched the useof high-k materials in transistors for about two decades, noted UCBerkeley’s Subramanian. However,the material decreased performanceby reducing the ability of electrons inthe channel to move around and

thereby increase current flow throughthe channel.

Researchers minimized this prob-lem by adding an intervening layerof silicon oxide. The materialreduced the effect of thermal cur-rents between the transistor channeland the dielectric, which inhibit elec-tron mobility

Gates. Transistor gates currentlyare made of layers of polysilicon—doped noncrystallized silicon—deposited onto the substrate.

High-k dielectrics can’t be usedwith conventional polysilicon gateelectrodes because the two materi-als don’t match well electromagnet-ically. This keeps the current flowacross the transistor channel fromswitching as quickly as necessary.

To cope with this, AMD, IBM,and Intel have developed metal gateelectrodes, which match better elec-tromagnetically with the high-kmaterials.

IntelIntel has developed a prototype

45-nm static RAM chip. The company has also demon-

strated prototypes of 45-nm micro-processors, code-named Penryn, thatwill use the new technology. Intelplans to begin mass-producing andreleasing them later this year. Thesechips will be the next-generation

Low-resistance layerPolysilicon gate

Silicon dioxide gate dielectric

Newtransistor

Standardtransistor

Silicon substrate Silicon substrate

Low-resistance layerMetal gate

High-k gate dielectricDrainSource DrainSource

Source: Intel

Figure 1. A new chipmaking technique replaces the silicon dioxide in the transistor

gate dielectric, which is an insulating layer, with a high-k material.The material

increases charge transmission and reduces electrical leakage.This helps manufactur-

ers reduce transistor size—letting them pack more transistors onto processors—

without losing energy efficiency or having to use new chipmaking techniques that

would require expensive fabrication-plant changes.The transistor gates would use

metal, instead, of polysilicon, to work better with the high-k material.

20 Computer

T E C H N O L O G Y N E W S

AMD and IBM plan to build the new chips using immersion lithography.

AMD is not sure whether it willincorporate the new technology intoits 45-nm or 32-nm chips, said JonCarvil, the company’s technologycommunications director. It is notclear whether the benefits are com-pelling enough for use in 45-nmprocessors, he explained.

CHIPMAKING CHALLENGESEven though the new technique

uses current chipmaking processes,retooling existing fabrication plantswill still be expensive, noted VLSIResearch’s Puhakka.

Raj Jammy, director of the FrontEnd Processes Division at Sematech,a chip-industry research consortium,noted that for 30 years, the industryhas created gate dielectrics by sub-jecting parts of the chip substrate tooxygen exposed through a pho-tomask. This oxidization processyields the dielectric’s silicon oxide.

Chipmakers have not figured outhow to use this type of process with

IBM is adding the infrastructurenecessary to build the new chips intoits semiconductor-manufacturingline in East Fishkill, New York. Thecompany plans to introduce the newtechnology in 45-nm chips next yearbut has not disclosed the types ofcomputers or devices in which theprocessors will be used.

The company has been workingon the technology for nearly a decadeand had to overcome significantmanufacturing and materials chal-lenges to create a reliable, mass-pro-duced product, said IBM Researchsenior manager Mukesh Khare.

For example, identifying compat-ible high-k-dielectric and metal-gate-electrode materials was difficult, aswas identifying metals that couldendure the necessary high-tempera-ture manufacturing process, ex-plained Ghavam Shahidi, director ofsilicon technology at IBM’s ThomasJ. Watson Research Center.

He said the company’s high-kchips will reduce gate leakage by99.9 percent and improve perfor-mance by up to 20 percent.

high-k materials and instead have todeposit material directly onto the sub-strate. The deposition process entailsthe risk of material contamination.

Also, Jammy said, the AMD, IBM,and Intel chips will introduce twonew sets of materials and immersionlithography into the productionprocess. Such a big change couldprove to be complex and difficult.

For example, ensuring reliabilityand putting the new materials intothe process flow will be a challenge,noted Intel’s Bohr.

A ll new high-performance proces-sors will use the new materialswithin the next five years, pre-

dicted Jammy.However, said VLSI Research’s

Puhakka, the up-front capital invest-ment necessary to build new facili-ties or convert current ones toproduce the new processors won’tmake sense for manufacturers ofchips that don’t need high perfor-mance or that are likely to be pro-duced only in small quantities.

While the new gate and dielectricmaterials are important, McGregorsaid, advances in design and lithog-raphy techniques will have to occurto enable the ongoing manufacture ofhigher-performance processors usingcurrent chipmaking techniques.

And, said University of Texasassociate professor Steve Keckler,many real advances are likely tocome not from new materials butfrom the development of better mul-ticore chips—which improve per-formance by having multiple coresrun tasks in parallel rather than byincreasing clock speed—as well asfrom the optimization of applica-tions for these processors. ■

George Lawton is a freelance technol-ogy writer based in San Francisco. Con-tact him at [email protected].

Editor: Lee Garber, Computer,[email protected]

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