Thin ®lm transistors on polyimide substrates

Hamide Kavak a, Carl Gruber b, Howard Shanks c,*, Allen Landin c,Alan Constant c, Stanley Burns d

a Physics Department, Cukurova University, Adana, Turkeyb Electrical Engineering Department, Minnesota State University, Mankato, MN, USA

c Microelectronics Research Center, Iowa State University, Ames, IA, USAd Electrical and Computer Engineering Department, University of Minnesota, Duluth, MN, USA

Abstract

The properties of individual inverted gate, thin ®lm transistors (TFT) with a range of channel width to length from

2/2 to 4780/4 fabricated on 5 lm thick polyimide substrates have been investigated. In addition to the room temperature

properties, the e�ects of illumination, bias stress and temperature have been measured. The current as a function of

voltage of the TFTs scale linearly with transistor size and the threshold voltages are independent of size. Illumination of

the transistors increases the o� current and decreases the threshold voltage. Gate characteristics were determined for

transistors before and after a bias stress of VGS � 20 V for t � 10, 102, 103 and 104 s. The threshold voltage shifted to

larger voltages and the on/o� ratio decreased with application time. Gate and transfer characteristics of the TFTs were

measured every 25°C from 25°C to 125°C. The threshold voltages decreased with increasing temperature while ®eld

e�ect mobilities increased. Ó 2000 Elsevier Science B.V. All rights reserved.

1. Introduction

Polyimide ®lm or web is being used as a ¯exiblesubstrate material for amorphous silicon ultra thinelectronics in a developing technology [1]. A classof channel length (L) equal to 2±50 lm minimumfeature size inverted gate thin ®lm transistor (TFT)circuitry has been demonstrated, including indi-vidual devices and switches with channel width tolength ratio �W =L� from 1 to 1000, inverters,drivers and receivers, ring oscillators, logic circuitsand SRAM cells on 5 and 75 lm polyimide sub-strates [2±4]. The technology developed is com-patible with roll-to-roll processing and mass

production and demonstrates the feasibility ofTFT based circuits on polyimide comparable tothose on rigid substrates.

2. Experimental

For this work, individual, inverted gate, thin®lm transistors were fabricated on 5 lm thickpolyimide substrates using the process describedelsewhere [2]. Brie¯y, a procedure has been de-veloped which allows for all process steps to becarried out at or below 300°C. A standard in-verted gate structure was used for all devices. Achromium metal gate is followed by a PECVDdeposited SiO2±Si3N4 graded dielectric. Anintrinsic amorphous silicon channel was deposit-ed followed by n-type a-Si:H source and drain

Journal of Non-Crystalline Solids 266±269 (2000) 1325±1328

www.elsevier.com/locate/jnoncrysol

* Corresponding author. Fax: +1-515 294 9584.

E-mail address: shanks@iastate.edu (H. Shanks).

0022-3093/00/$ - see front matter Ó 2000 Elsevier Science B.V. All rights reserved.

PII: S 0 0 2 2 - 3 0 9 3 ( 9 9 ) 0 0 9 4 5 - X

contacts. Aluminum was used for the top contactsand interconnects.

Current as a function of voltage, C�V �, prop-erties were determined as a function of W =L ratio.In addition the e�ects of light, temperature andbias stress on the some properties of the deviceswere determined. The gate capacitance (Cm) with afully saturated channel was measured at 200 Hz byconnecting source and drain together andmeasuring capacitance to the gate. These mea-sured capacitances were used rather than calcu-lated capacitances in the determination of channelmobility because of the SiO2±Si3N4 graded di-electric used. The calculated capacitances wereabout 25% less than the measured capacitanceswhich would result in larger apparent ®eld e�ectmobilities.

3. Results

The C�V � were measured on TFT samples withW =L ratios of 2/2, 500/50 and 4780/4. The resultingcurves, shown in Fig. 1, indicate that C�V � scalelinearly with device size over a range of 1±1000.However, short channel e�ects as indicated by thereduced early voltages can be observed for 2 and4 lm channel lengths.

The threshold voltages were measured on anumber of samples (Table 1) and were nearly in-dependent of size. The Ion/Ioff ratios for the threesizes of transistor samples at a source-drain volt-age (VDS) of 10 V are also listed in Table 1. Sametransistor properties were measured as a functionof temperature from room temperature to 125°C.The threshold voltage decreased with increasingtemperature about as Tÿ1 as shown in Fig. 2.

The ®eld e�ect mobility (l) was obtained fromthe slope of a plot of the square root of draincurrent verses the source-gate voltage (VGS) mea-sured in the saturation region and the dielectriccapacitance (Cox). Coxs were obtained from mea-sured Cms with a fully saturated channel measuredat 200 Hz. The gate capacitance scaled appropri-ately with transistor channel area. A plot of Cm perunit area versus W =L ratio was used to extrapolateto 2/2 as the capacitance of these small devices wastoo small to measure directly. Under channelcuto� conditions the overlap capacitance was re-duced by the series capacitance of the intrinsic a-Si:H layer. The ®eld e�ect mobilities obtained wereindependent of device size (Table 1) and increasedas the temperature was increased (Fig. 2). Theslope of the mobility versus 1=T was independentof device size.

Gate properties were determined for the varioussize transistor samples both before and after ap-plication of a bias stress of VGS � 20 V for t � 10,

Fig. 1. The C�V �s for thin ®lm transistors on polyimide nor-

malized by dividing the current by the transistor W =L ratios.

Note the short channel e�ects for the smaller transistors. The

solid and dashed lines are drawn for illustrative purpose.

Table 1

Typical device properties of thin ®lm transistors at VDS � 10 V

W =L Vt (V) �2% ION/IOFF �4% Cm (10ÿ8 F/cm2) �5% Mobility (cm2/V s) �5%

4780/4 2.34 4:51� 107 4.83 0.22

500/50 2.98 0:76� 107 5.36 0.26

2/2 2.47 0:27� 107 5.63a 0.23

a Cm extrapolated for W =L � 2=2.

1326 H. Kavak et al. / Journal of Non-Crystalline Solids 266±269 (2000) 1325±1328

102, 103 and 104 s. The threshold voltages in-creased and the ION/IOFF ratios decreased as afunction of bias stress application time. Results fora typical transistor are shown in Table 2.

Individual transistor samples were measured inthe dark and under an illumination of approxi-mately 10 mW/cm2 of white light. Results for thevarious size devices are listed in Table 3. The lightincreased the o� current and decreased thethreshold voltages.

4. Discussion

Same properties of amorphous silicon thin ®lmtransistors fabricated on polyimide are similar tothose prepared on rigid substrates [5±8]. Goodrepeatability of some of the TFT properties wereobtained on the polyimide with less than 10%variability of, for example, the threshold voltages.The I�V � for TFT samples on polyimide scalelinearly with transistor size over a range from 2/2±500/50 to 4780/4. Short channel e�ects, i.e. reducedearly voltage, are noticeable at 2 and 4 lm channellengths. Threshold voltages are independent oftransistor size and decrease with temperature asTÿ1.

Gate capacitance scales appropriately withtransistor channel area. Under channel cuto�conditions with test frequencies 200 Hz, overlapcapacitance is reduced by the series capacitance ofthe a-Si layer. Field e�ect mobility is independentof transistor size and increases with temperature asTÿ1 in the range 25±125°C.

The gate bias stress instability appears to beapproximately independent of transistor size. Thethreshold voltage shift follows an approximatelylogarithmic time dependence for intermediate timescales. Illumination of the TFT channel (10 mw/cm2) generates additional electron±hole pairswhich increase the o�-current and decrease thethreshold voltage.

5. Conclusions

From this study, we conclude that TFT devicesand circuits can be fabricated at low temperatures(<300°C) on ¯exible polyimide substrates. DeviceC�V �s scale as expected with device size, althoughfor small devices the early voltage or short channele�ects are larger. Measured ®eld e�ect mobilities

Table 2

Typical e�ects of 20 V bias stress on device characteristics

W =L 500/50 Threshold voltage

(V) �2%

ION/IOFF

(VDS� 10) �4%

Before bias

stress

3.10 4:9� 106

After 10 s 4.91 4:0� 106

After 102 s 5.95 2:5� 106

After 103 s 6.93 0:4� 106

After 104 s 7.94 0:1� 106

Table 3

E�ect of illumination on the device characteristics for VDS � 10 V

W =L Vt (V) (dark) �2% Vt (V) (light) �2% ION/IOFF (dark) �4% ION/IOFF (light) �4%

4780/4 2.34 1.15 4:51� 107 0:62� 104

500/50 2.98 1.82 0:76� 107 0:79� 103

2/2 2.47 0.93 0:27� 106 0:10� 103

Fig. 2. The temperature dependence of the threshold voltage

and the ®eld e�ect mobility for a thin ®lm transistor on polyi-

mide with W =L � 500=50. Lines are drawn as guides for the eye.

H. Kavak et al. / Journal of Non-Crystalline Solids 266±269 (2000) 1325±1328 1327

and threshold voltages are independent of devicesize. Under illumination additional electron±holepairs are created in the devices which increases thecurrent leakage under device-o� conditions. Theinstability observed in the TFTs which increasesthe threshold voltage and decreases the current on/o� ratio under bias stress decreases after removalof the bias and with time returns these parametersto pre-stress values.

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