Tiva C Series TM4C123GH6ZRB Microcontroller Data Sheet ... 15.3.1 BitRateGeneration.....989 15.3.2 FIFOOperation.....989

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  • Tiva™ TM4C123GH6ZRB Microcontroller

    DATA SHEET

    Copyr ight © 2007-2014 Texas Instruments Incorporated

    DS-TM4C123GH6ZRB-15842.2741 SPMS378E

    TEXAS INSTRUMENTS-PRODUCTION DATA

  • Copyright Copyright © 2007-2014 Texas Instruments Incorporated. Tiva and TivaWare are trademarks of Texas Instruments Incorporated. ARM and Thumb are registered trademarks and Cortex is a trademark of ARM Limited. All other trademarks are the property of others.

    PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

    Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

    Texas Instruments Incorporated 108 Wild Basin, Suite 350 Austin, TX 78746 http://www.ti.com/tm4c http://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm

    June 12, 20142 Texas Instruments-Production Data

    http://www.ti.com/tm4c http://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm

  • Table of Contents Revision History ............................................................................................................................. 39 About This Document .................................................................................................................... 43 Audience .............................................................................................................................................. 43 About This Manual ................................................................................................................................ 43 Related Documents ............................................................................................................................... 43 Documentation Conventions .................................................................................................................. 44

    1 Architectural Overview .......................................................................................... 46 1.1 Tiva™ C Series Overview .............................................................................................. 46 1.2 TM4C123GH6ZRB Microcontroller Overview .................................................................. 47 1.3 TM4C123GH6ZRB Microcontroller Features ................................................................... 50 1.3.1 ARM Cortex-M4F Processor Core .................................................................................. 50 1.3.2 On-Chip Memory ........................................................................................................... 52 1.3.3 Serial Communications Peripherals ................................................................................ 54 1.3.4 System Integration ........................................................................................................ 58 1.3.5 Advanced Motion Control ............................................................................................... 64 1.3.6 Analog .......................................................................................................................... 66 1.3.7 JTAG and ARM Serial Wire Debug ................................................................................ 68 1.3.8 Packaging and Temperature .......................................................................................... 68 1.4 TM4C123GH6ZRB Microcontroller Hardware Details ....................................................... 69 1.5 Kits .............................................................................................................................. 69 1.6 Support Information ....................................................................................................... 69

    2 The Cortex-M4F Processor ................................................................................... 70 2.1 Block Diagram .............................................................................................................. 71 2.2 Overview ...................................................................................................................... 72 2.2.1 System-Level Interface .................................................................................................. 72 2.2.2 Integrated Configurable Debug ...................................................................................... 72 2.2.3 Trace Port Interface Unit (TPIU) ..................................................................................... 73 2.2.4 Cortex-M4F System Component Details ......................................................................... 73 2.3 Programming Model ...................................................................................................... 74 2.3.1 Processor Mode and Privilege Levels for Software Execution ........................................... 74 2.3.2 Stacks .......................................................................................................................... 75 2.3.3 Register Map ................................................................................................................ 75 2.3.4 Register Descriptions .................................................................................................... 77 2.3.5 Exceptions and Interrupts .............................................................................................. 93 2.3.6 Data Types ................................................................................................................... 93 2.4 Memory Model .............................................................................................................. 93 2.4.1 Memory Regions, Types and Attributes ........................................................................... 96 2.4.2 Memory System Ordering of Memory Accesses .............................................................. 96 2.4.3 Behavior of Memory Accesses ....................................................................................... 97 2.4.4 Software Ordering of Memory Accesses ......................................................................... 97 2.4.5 Bit-Banding ................................................................................................................... 98 2.4.6 Data Storage .............................................................................................................. 101 2.4.7 Synchronization Primitives ........................................................................................... 101 2.5 Exception Model ......................................................................................................... 102 2.5.1 Exception States ......................................................................................................... 103

    3June 12, 2014 Texas Instruments-Production Data

    Tiva™ TM4C123GH6ZRB Microcontroller

  • 2.5.2 Exception Types .......................................................................................................... 103 2.5.3 Exception Handlers ..................................................................................................... 108 2.5.4 Vector Table ................................................................................................................ 108 2.5.5 Exception Priorities ...................................................................................................... 109 2.5.6 Interrupt Priority Grouping ............................................................................................ 110 2.5.7 Exception Entry and Return ......................................................................................... 110 2.6 Fault Handling ............................................................................................................. 113 2.6.1 Fault Types ................................................................................................................. 114 2.6.2 Fault Escalation and Hard Faults .................................................................................. 114 2.6.3 Fault Status Registers and Fault Address Registers ...................................................... 115 2.6.4 Lockup ....................................................................................................................... 115 2.7 Power Management .................................................................................................... 116 2.7.1 Entering Sleep Modes ................................................................................................. 116 2.7.2 Wake Up from Sleep Mode .......................................................................................... 116 2.8 Instruction Set Summary .............................................................................................. 117

    3 Cortex-M4 Peripherals ......................................................................................... 124 3.1 Functional Description ................................................................................................. 124 3.1.1 System Timer (SysTick) ............................................................................................... 125 3.1.2 Nested Vectored Interrupt Controller (NVIC) .................................................................. 126 3.1.3 System Control Block (SCB) ........................................................................................ 127 3.1.4 Memory Protection Unit (MPU) ....................................