Tiva C Series TM4C123GH6ZRB Microcontroller Data … · DS-TM4C123GH6ZRB-15553.2700 SPMS378C ... 9.2.10 InterruptsandErrors ... 1340 21.4 InitializationandConfiguration

Tiva TM4C123GH6ZRB Microcontroller

DATA SHEET

Copyr ight 2007-2013Texas Instruments Incorporated

DS-TM4C123GH6ZRB-15553.2700SPMS378C

TEXAS INSTRUMENTS-PRODUCTION DATA

CopyrightCopyright 2007-2013 Texas Instruments Incorporated. Tiva and TivaWare are trademarks of Texas Instruments Incorporated. ARM and Thumb areregistered trademarks and Cortex is a trademark of ARM Limited. All other trademarks are the property of others.

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Texas Instruments Incorporated108 Wild Basin, Suite 350Austin, TX 78746http://www.ti.com/tm4chttp://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm

November 16, 20132Texas Instruments-Production Data

http://www.ti.com/tm4chttp://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm

Table of ContentsRevision History ............................................................................................................................. 39About This Document .................................................................................................................... 42Audience .............................................................................................................................................. 42About This Manual ................................................................................................................................ 42Related Documents ............................................................................................................................... 42Documentation Conventions .................................................................................................................. 43

1 Architectural Overview .......................................................................................... 451.1 Tiva C Series Overview .............................................................................................. 451.2 TM4C123GH6ZRB Microcontroller Overview .................................................................. 461.3 TM4C123GH6ZRB Microcontroller Features ................................................................... 491.3.1 ARM Cortex-M4F Processor Core .................................................................................. 491.3.2 On-Chip Memory ........................................................................................................... 511.3.3 Serial Communications Peripherals ................................................................................ 531.3.4 System Integration ........................................................................................................ 571.3.5 Advanced Motion Control ............................................................................................... 631.3.6 Analog .......................................................................................................................... 651.3.7 JTAG and ARM Serial Wire Debug ................................................................................ 671.3.8 Packaging and Temperature .......................................................................................... 671.4 TM4C123GH6ZRB Microcontroller Hardware Details ....................................................... 681.5 Kits .............................................................................................................................. 681.6 Support Information ....................................................................................................... 68

2 The Cortex-M4F Processor ................................................................................... 692.1 Block Diagram .............................................................................................................. 702.2 Overview ...................................................................................................................... 712.2.1 System-Level Interface .................................................................................................. 712.2.2 Integrated Configurable Debug ...................................................................................... 712.2.3 Trace Port Interface Unit (TPIU) ..................................................................................... 722.2.4 Cortex-M4F System Component Details ......................................................................... 722.3 Programming Model ...................................................................................................... 732.3.1 Processor Mode and Privilege Levels for Software Execution ........................................... 732.3.2 Stacks .......................................................................................................................... 742.3.3 Register Map ................................................................................................................ 742.3.4 Register Descriptions .................................................................................................... 762.3.5 Exceptions and Interrupts .............................................................................................. 922.3.6 Data Types ................................................................................................................... 922.4 Memory Model .............................................................................................................. 922.4.1 Memory Regions, Types and Attributes ........................................................................... 952.4.2 Memory System Ordering of Memory Accesses .............................................................. 952.4.3 Behavior of Memory Accesses ....................................................................................... 962.4.4 Software Ordering of Memory Accesses ......................................................................... 962.4.5 Bit-Banding ................................................................................................................... 972.4.6 Data Storage .............................................................................................................. 1002.4.7 Synchronization Primitives ........................................................................................... 1002.5 Exception Model ......................................................................................................... 1012.5.1 Exception States ......................................................................................................... 102

3November 16, 2013Texas Instruments-Production Data


2.5.2 Exception Types .......................................................................................................... 1022.5.3 Exception Handlers ..................................................................................................... 1072.5.4 Vector Table ................................................................................................................ 1072.5.5 Exception Priorities ...................................................................................................... 1082.5.6 Interrupt Priority Grouping ............................................................................................ 1092.5.7 Exception Entry and Return ......................................................................................... 1092.6 Fault Handling ............................................................................................................. 1122.6.1 Fault Types ................................................................................................................. 1132.6.2 Fault Escalation and Hard Faults .................................................................................. 1132.6.3 Fault Status Registers and Fault Address Registers ...................................................... 1142.6.4 Lockup ....................................................................................................................... 1142.7 Power Management .................................................................................................... 1152.7.1 Entering Sleep Modes ................................................................................................. 1152.7.2 Wake Up from Sleep Mode .......................................................................................... 1152.8 Instruction Set Summary .............................................................................................. 116

3 Cortex-M4 Peripherals ......................................................................................... 1233.1 Functional Description ................................................................................................. 1233.1.1 System Timer (SysTick) ............................................................................................... 1243.1.2 Nested Vectored Interrupt Controller (NVIC) .................................................................. 1253.1.3 System Control Block (SCB) ........................................................................................ 1263.1.4 Memory Protection Unit (MPU) ..................................................................................... 1263.1.5 Floating-Point Unit (FPU) ............................................................................................. 1313.2 Register Map .............................................................................................................. 1353.3 System Timer (SysTick) Register Descriptions .............................................................. 1383.4 NVIC Register Descriptions .......................................................................................... 1423.5 System Control Block (SCB) Register Descriptions ........................................................ 1573.6 Memory Protection Unit (MPU) Register Descriptions .................................................... 1863.7 Floating-Point Unit (FPU) Register Descriptions ............................................................ 195

4 JTAG Interface ...................................................................................................... 2014.1 Block Diagram ............................................................................................................ 2024.2 Signal Description ....................................................................................................... 2024.3 Functional Description ................................................................................................. 2034.3.1 JTAG Interface Pins ..................................................................................................... 2034.3.2 JTAG TAP Controller ................................................................................................... 2054.3.3 Shift Registers ............................................................................................................ 2054.3.4 Operational Considerations .......................................................................................... 2064.4 Initialization and Configuration ..................................................................................... 2084.5 Register Descriptions .................................................................................................. 2094.5.1 Instruction Register (IR) ............................................................................................... 2094.5.2 Data Registers ............................................................................................................ 211

5 System Control ..................................................................................................... 2135.1 Signal Description ....................................................................................................... 2135.2 Functional Description ................................................................................................. 2135.2.1 Device Identification .................................................................................................... 2135.2.2 Reset Control .............................................................................................................. 2145.2.3 Non-Maskable Interrupt ............................................................................................... 2195.2.4 Power Control ............................................................................................................. 2195.2.5 Clock Control .............................................................................................................. 220


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5.2.6 System Control ........................................................................................................... 2285.3 Initialization and Configuration ..................................................................................... 2325.4 Register Map .............................................................................................................. 2325.5 System Control Register Descriptions ........................................................................... 2385.6 System Control Legacy Register Descriptions ............................................................... 432

6 System Exception Module ................................................................................... 4986.1 Functional Description ................................................................................................. 4986.2 Register Map .............................................................................................................. 4986.3 Register Descriptions .................................................................................................. 498

7 Hibernation Module .............................................................................................. 5067.1 Block Diagram ............................................................................................................ 5077.2 Signal Description ....................................................................................................... 5077.3 Functional Description ................................................................................................. 5087.3.1 Register Access Timing ............................................................................................... 5087.3.2 Hibernation Clock Source ............................................................................................ 5097.3.3 System Implementation ............................................................................................... 5107.3.4 Battery Management ................................................................................................... 5117.3.5 Real-Time Clock .......................................................................................................... 5127.3.6 Battery-Backed Memory .............................................................................................. 5147.3.7 Power Control Using HIB ............................................................................................. 5147.3.8 Power Control Using VDD3ON Mode ........................................................................... 5157.3.9 Initiating Hibernate ...................................................................................................... 5157.3.10 Waking from Hibernate ................................................................................................ 5157.3.11 Arbitrary Power Removal ............................................................................................. 5157.3.12 Interrupts and Status ................................................................................................... 5167.4 Initialization and Configuration ..................................................................................... 5167.4.1 Initialization ................................................................................................................. 5167.4.2 RTC Match Functionality (No Hibernation) .................................................................... 5177.4.3 RTC Match/Wake-Up from Hibernation ......................................................................... 5187.4.4 External Wake-Up from Hibernation .............................................................................. 5187.4.5 RTC or External Wake-Up from Hibernation .................................................................. 5187.5 Register Map .............................................................................................................. 5187.6 Register Descriptions .................................................................................................. 519

8 Internal Memory ................................................................................................... 5378.1 Block Diagram ............................................................................................................ 5378.2 Functional Description ................................................................................................. 5388.2.1 SRAM ........................................................................................................................ 5388.2.2 ROM .......................................................................................................................... 5398.2.3 Flash Memory ............................................................................................................. 5418.2.4 EEPROM .................................................................................................................... 5478.3 Register Map .............................................................................................................. 5528.4 Flash Memory Register Descriptions (Flash Control Offset) ............................................ 5548.5 EEPROM Register Descriptions (EEPROM Offset) ........................................................ 5728.6 Memory Register Descriptions (System Control Offset) .................................................. 589

9 Micro Direct Memory Access (DMA) ................................................................ 5989.1 Block Diagram ............................................................................................................ 5999.2 Functional Description ................................................................................................. 599



9.2.1 Channel Assignments .................................................................................................. 6009.2.2 Priority ........................................................................................................................ 6019.2.3 Arbitration Size ............................................................................................................ 6019.2.4 Request Types ............................................................................................................ 6019.2.5 Channel Configuration ................................................................................................. 6029.2.6 Transfer Modes ........................................................................................................... 6049.2.7 Transfer Size and Increment ........................................................................................ 6129.2.8 Peripheral Interface ..................................................................................................... 6129.2.9 Software Request ........................................................................................................ 6129.2.10 Interrupts and Errors .................................................................................................... 6139.3 Initialization and Configuration ..................................................................................... 6139.3.1 Module Initialization ..................................................................................................... 6139.3.2 Configuring a Memory-to-Memory Transfer ................................................................... 6149.3.3 Configuring a Peripheral for Simple Transmit ................................................................ 6159.3.4 Configuring a Peripheral for Ping-Pong Receive ............................................................ 6179.3.5 Configuring Channel Assignments ................................................................................ 6199.4 Register Map .............................................................................................................. 6199.5 DMA Channel Control Structure ................................................................................. 6219.6 DMA Register Descriptions ........................................................................................ 628

10 General-Purpose Input/Outputs (GPIOs) ........................................................... 66210.1 Signal Description ....................................................................................................... 66210.2 Functional Description ................................................................................................. 66710.2.1 Data Control ............................................................................................................... 66810.2.2 Interrupt Control .......................................................................................................... 66910.2.3 Mode Control .............................................................................................................. 67110.2.4 Commit Control ........................................................................................................... 67110.2.5 Pad Control ................................................................................................................. 67110.2.6 Identification ............................................................................................................... 67110.3 Initialization and Configuration ..................................................................................... 67110.4 Register Map .............................................................................................................. 67310.5 Register Descriptions .................................................................................................. 676

11 General-Purpose Timers ...................................................................................... 72511.1 Block Diagram ............................................................................................................ 72611.2 Signal Description ....................................................................................................... 72711.3 Functional Description ................................................................................................. 72911.3.1 GPTM Reset Conditions .............................................................................................. 73011.3.2 Timer Modes ............................................................................................................... 73111.3.3 Wait-for-Trigger Mode .................................................................................................. 74011.3.4 Synchronizing GP Timer Blocks ................................................................................... 74111.3.5 DMA Operation ........................................................................................................... 74111.3.6 Accessing Concatenated 16/32-Bit GPTM Register Values ............................................ 74211.3.7 Accessing Concatenated 32/64-Bit Wide GPTM Register Values .................................... 74211.4 Initialization and Configuration ..................................................................................... 74411.4.1 One-Shot/Periodic Timer Mode .................................................................................... 74411.4.2 Real-Time Clock (RTC) Mode ...................................................................................... 74511.4.3 Input Edge-Count Mode ............................................................................................... 74511.4.4 Input Edge Timing Mode .............................................................................................. 74611.4.5 PWM Mode ................................................................................................................. 746


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11.5 Register Map .............................................................................................................. 74711.6 Register Descriptions .................................................................................................. 748

12 Watchdog Timers ................................................................................................. 79612.1 Block Diagram ............................................................................................................ 79712.2 Functional Description ................................................................................................. 79712.2.1 Register Access Timing ............................................................................................... 79812.3 Initialization and Configuration ..................................................................................... 79812.4 Register Map .............................................................................................................. 79812.5 Register Descriptions .................................................................................................. 799

13 Analog-to-Digital Converter (ADC) ..................................................................... 82113.1 Block Diagram ............................................................................................................ 82213.2 Signal Description ....................................................................................................... 82313.3 Functional Description ................................................................................................. 82413.3.1 Sample Sequencers .................................................................................................... 82513.3.2 Module Control ............................................................................................................ 82513.3.3 Hardware Sample Averaging Circuit ............................................................................. 82913.3.4 Analog-to-Digital Converter .......................................................................................... 83013.3.5 Differential Sampling ................................................................................................... 83213.3.6 Internal Temperature Sensor ........................................................................................ 83413.3.7 Digital Comparator Unit ............................................................................................... 83513.4 Initialization and Configuration ..................................................................................... 83913.4.1 Module Initialization ..................................................................................................... 83913.4.2 Sample Sequencer Configuration ................................................................................. 84013.5 Register Map .............................................................................................................. 84013.6 Register Descriptions .................................................................................................. 842

14 Universal Asynchronous Receivers/Transmitters (UARTs) ............................. 92014.1 Block Diagram ............................................................................................................ 92114.2 Signal Description ....................................................................................................... 92114.3 Functional Description ................................................................................................. 92214.3.1 Transmit/Receive Logic ............................................................................................... 92314.3.2 Baud-Rate Generation ................................................................................................. 92314.3.3 Data Transmission ...................................................................................................... 92414.3.4 Serial IR (SIR) ............................................................................................................. 92414.3.5 ISO 7816 Support ....................................................................................................... 92614.3.6 Modem Handshake Support ......................................................................................... 92614.3.7 9-Bit UART Mode ........................................................................................................ 92714.3.8 FIFO Operation ........................................................................................................... 92814.3.9 Interrupts .................................................................................................................... 92814.3.10 Loopback Operation .................................................................................................... 92914.3.11 DMA Operation ........................................................................................................... 92914.4 Initialization and Configuration ..................................................................................... 93014.5 Register Map .............................................................................................................. 93114.6 Register Descriptions .................................................................................................. 933

15 Synchronous Serial Interface (SSI) .................................................................... 98115.1 Block Diagram ............................................................................................................ 98215.2 Signal Description ....................................................................................................... 98215.3 Functional Description ................................................................................................. 983



15.3.1 Bit Rate Generation ..................................................................................................... 98415.3.2 FIFO Operation ........................................................................................................... 98415.3.3 Interrupts .................................................................................................................... 98415.3.4 Frame Formats ........................................................................................................... 98515.3.5 DMA Operation ........................................................................................................... 99315.4 Initialization and Configuration ..................................................................................... 99415.5 Register Map .............................................................................................................. 99515.6 Register Descriptions .................................................................................................. 996

16 Inter-Integrated Circuit (I2C) Interface .............................................................. 102516.1 Block Diagram ........................................................................................................... 102616.2 Signal Description ..................................................................................................... 102616.3 Functional Description ............................................................................................... 102716.3.1 I2C Bus Functional Overview ...................................................................................... 102716.3.2 Available Speed Modes ............................................................................................. 103216.3.3 Interrupts .................................................................................................................. 103416.3.4 Loopback Operation .................................................................................................. 103516.3.5 Command Sequence Flow Charts .............................................................................. 103516.4 Initialization and Configuration .................................................................................... 104316.4.1 Configure the I2C Module to Transmit a Single Byte as a Master .................................. 104316.4.2 Configure the I2C Master to High Speed Mode ............................................................ 104416.5 Register Map ............................................................................................................ 104516.6 Register Descriptions (I2C Master) .............................................................................. 104616.7 Register Descriptions (I2C Slave) ............................................................................... 106316.8 Register Descriptions (I2C Status and Control) ............................................................ 1073

17 Controller Area Network (CAN) Module ........................................................... 107617.1 Block Diagram ........................................................................................................... 107717.2 Signal Description ..................................................................................................... 107717.3 Functional Description ............................................................................................... 107817.3.1 Initialization ............................................................................................................... 107917.3.2 Operation .................................................................................................................. 108017.3.3 Transmitting Message Objects ................................................................................... 108117.3.4 Configuring a Transmit Message Object ...................................................................... 108117.3.5 Updating a Transmit Message Object ......................................................................... 108217.3.6 Accepting Received Message Objects ........................................................................ 108317.3.7 Receiving a Data Frame ............................................................................................ 108317.3.8 Receiving a Remote Frame ........................................................................................ 108317.3.9 Receive/Transmit Priority ........................................................................................... 108417.3.10 Configuring a Receive Message Object ...................................................................... 108417.3.11 Handling of Received Message Objects ...................................................................... 108517.3.12 Handling of Interrupts ................................................................................................ 108717.3.13 Test Mode ................................................................................................................. 108817.3.14 Bit Timing Configuration Error Considerations ............................................................. 109017.3.15 Bit Time and Bit Rate ................................................................................................. 109017.3.16 Calculating the Bit Timing Parameters ........................................................................ 109217.4 Register Map ............................................................................................................ 109517.5 CAN Register Descriptions ......................................................................................... 1096


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18 Universal Serial Bus (USB) Controller ............................................................. 112718.1 Block Diagram ........................................................................................................... 112818.2 Signal Description ..................................................................................................... 112818.3 Functional Description ............................................................................................... 112918.3.1 Operation as a Device ............................................................................................... 112918.3.2 Operation as a Host ................................................................................................... 113418.3.3 OTG Mode ................................................................................................................ 113818.3.4 DMA Operation ......................................................................................................... 114018.4 Initialization and Configuration .................................................................................... 114118.4.1 Pin Configuration ....................................................................................................... 114118.4.2 Endpoint Configuration .............................................................................................. 114218.5 Register Map ............................................................................................................ 114218.6 Register Descriptions ................................................................................................. 1148

19 Analog Comparators .......................................................................................... 124219.1 Block Diagram ........................................................................................................... 124319.2 Signal Description ..................................................................................................... 124319.3 Functional Description ............................................................................................... 124419.3.1 Internal Reference Programming ................................................................................ 124519.4 Initialization and Configuration .................................................................................... 124719.5 Register Map ............................................................................................................ 124819.6 Register Descriptions ................................................................................................. 1248

20 Pulse Width Modulator (PWM) .......................................................................... 125820.1 Block Diagram ........................................................................................................... 125920.2 Signal Description ..................................................................................................... 126120.3 Functional Description ............................................................................................... 126320.3.1 Clock Configuration ................................................................................................... 126320.3.2 PWM Timer ............................................................................................................... 126320.3.3 PWM Comparators .................................................................................................... 126320.3.4 PWM Signal Generator .............................................................................................. 126420.3.5 Dead-Band Generator ............................................................................................... 126520.3.6 Interrupt/ADC-Trigger Selector ................................................................................... 126520.3.7 Synchronization Methods .......................................................................................... 126620.3.8 Fault Conditions ........................................................................................................ 126720.3.9 Output Control Block .................................................................................................. 126820.4 Initialization and Configuration .................................................................................... 126820.5 Register Map ............................................................................................................ 126920.6 Register Descriptions ................................................................................................. 1272

21 Quadrature Encoder Interface (QEI) ................................................................. 133721.1 Block Diagram ........................................................................................................... 133721.2 Signal Description ..................................................................................................... 133921.3 Functional Description ............................................................................................... 134021.4 Initialization and Configuration .................................................................................... 134221.5 Register Map ............................................................................................................ 134321.6 Register Descriptions ................................................................................................. 1343

22 Pin Diagram ........................................................................................................ 136023 Signal Tables ...................................................................................................... 136123.1 Signals by Pin Number .............................................................................................. 1362



23.2 Signals by Signal Name ............................................................................................. 137823.3 Signals by Function, Except for GPIO ......................................................................... 139123.4 GPIO Pins and Alternate Functions ............................................................................ 140223.5 Possible Pin Assignments for Alternate Functions ....................................................... 140623.6 Connections for Unused Signals ................................................................................. 1410

24 Electrical Characteristics .................................................................................. 141224.1 Maximum Ratings ...................................................................................................... 141224.2 Operating Characteristics ........................................................................................... 141324.3 Recommended Operating Conditions ......................................................................... 141424.4 Load Conditions ........................................................................................................ 141624.5 JTAG and Boundary Scan .......................................................................................... 141724.6 Power and Brown-Out ............................................................................................... 141924.6.1 VDDA Levels ............................................................................................................ 141924.6.2 VDD Levels ............................................................................................................... 142024.6.3 VDDC Levels ............................................................................................................ 142124.6.4 VDD Glitches ............................................................................................................ 142224.6.5 VDD Droop Response ............................................................................................... 142224.7 Reset ........................................................................................................................ 142424.8 On-Chip Low Drop-Out (LDO) Regulator ..................................................................... 142624.9 Clocks ...................................................................................................................... 142724.9.1 PLL Specifications ..................................................................................................... 142724.9.2 PIOSC Specifications ................................................................................................ 142824.9.3 Low-Frequency Internal Oscillator (LFIOSC) Specifications .......................................... 142824.9.4 Hibernation Clock Source Specifications ..................................................................... 142824.9.5 Main Oscillator Specifications ..................................................................................... 142924.9.6 System Clock Specification with ADC Operation .......................................................... 143224.9.7 System Clock Specification with USB Operation .......................................................... 143324.10 Sleep Modes ............................................................................................................. 143424.11 Hibernation Module ................................................................................................... 143624.12 Flash Memory and EEPROM ..................................................................................... 143824.13 Input/Output Pin Characteristics ................................................................................. 143924.13.1 GPIO Module Characteristics ..................................................................................... 143924.13.2 Types of I/O Pins and ESD Protection ......................................................................... 143924.14 Analog-to-Digital Converter (ADC) .............................................................................. 144324.15 Synchronous Serial Interface (SSI) ............................................................................. 144724.16 Inter-Integrated Circuit (I2C) Interface ......................................................................... 145024.17 Universal Serial Bus (USB) Controller ......................................................................... 145124.18 Analog Comparator ................................................................................................... 145224.19 Current Consumption ................................................................................................. 1454

A Package Information .......................................................................................... 1457A.1 Orderable Devices ..................................................................................................... 1457A.2 Part Markings ............................................................................................................ 1458A.3 Packaging Diagram ................................................................................................... 1459A.4 Packaging Materials .................................................................................................. 1460


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List of FiguresFigure 1-1. Tiva TM4C123GH6ZRB Microcontroller High-Level Block Diagram ....................... 48Figure 2-1. CPU Block Diagram ............................................................................................. 71Figure 2-2. TPIU Block Diagram ............................................................................................ 72Figure 2-3. Cortex-M4F Register Set ...................................................................................... 75Figure 2-4. Bit-Band Mapping ................................................................................................ 99Figure 2-5. Data Storage ..................................................................................................... 100Figure 2-6. Vector Table ...................................................................................................... 108Figure 2-7. Exception Stack Frame ...................................................................................... 111Figure 3-1. SRD Use Example ............................................................................................. 129Figure 3-2. FPU Register Bank ............................................................................................ 132Figure 4-1. JTAG Module Block Diagram .............................................................................. 202Figure 4-2. Test Access Port State Machine ......................................................................... 205Figure 4-3. IDCODE Register Format ................................................................................... 211Figure 4-4. BYPASS Register Format ................................................................................... 211Figure 4-5. Boundary Scan Register Format ......................................................................... 212Figure 5-1. Basic RST Configuration .................................................................................... 216Figure 5-2. External Circuitry to Extend Power-On Reset ....................................................... 216Figure 5-3. Reset Circuit Controlled by Switch ...................................................................... 217Figure 5-4. Power Architecture ............................................................................................ 220Figure 5-5. Main Clock Tree ................................................................................................ 223Figure 5-6. Module Clock Selection ...................................................................................... 230Figure 7-1. Hibernation Module Block Diagram ..................................................................... 507Figure 7-2. Using a Crystal as the Hibernation Clock Source with a Single Battery Source ...... 510Figure 7-3. Using a Dedicated Oscillator as the Hibernation Clock Source with VDD3ON

Mode ................................................................................................................ 510Figure 7-4. Using a Regulator for Both VDD and VBAT ............................................................ 511Figure 7-5. Counter Behavior with a TRIM Value of 0x8002 ................................................... 514Figure 7-6. Counter Behavior with a TRIM Value of 0x7FFC .................................................. 514Figure 8-1. Internal Memory Block Diagram .......................................................................... 537Figure 8-2. EEPROM Block Diagram ................................................................................... 538Figure 9-1. DMA Block Diagram ......................................................................................... 599Figure 9-2. Example of Ping-Pong DMA Transaction ........................................................... 605Figure 9-3. Memory Scatter-Gather, Setup and Configuration ................................................ 607Figure 9-4. Memory Scatter-Gather, DMA Copy Sequence .................................................. 608Figure 9-5. Peripheral Scatter-Gather, Setup and Configuration ............................................. 610Figure 9-6. Peripheral Scatter-Gather, DMA Copy Sequence ............................................... 611Figure 10-1. Digital I/O Pads ................................................................................................. 667Figure 10-2. Analog/Digital I/O Pads ...................................................................................... 668Figure 10-3. GPIODATA Write Example ................................................................................. 669Figure 10-4. GPIODATA Read Example ................................................................................. 669Figure 11-1. GPTM Module Block Diagram ............................................................................ 726Figure 11-2. Reading the RTC Value ...................................................................................... 734Figure 11-3. Input Edge-Count Mode Example, Counting Down ............................................... 736Figure 11-4. 16-Bit Input Edge-Time Mode Example ............................................................... 737Figure 11-5. 16-Bit PWM Mode Example ................................................................................ 739Figure 11-6. CCP Output, GPTMTnMATCHR > GPTMTnILR ................................................... 739



Figure 11-7. CCP Output, GPTMTnMATCHR = GPTMTnILR ................................................... 740Figure 11-8. CCP Output, GPTMTnILR > GPTMTnMATCHR ................................................... 740Figure 11-9. Timer Daisy Chain ............................................................................................. 741Figure 12-1. WDT Module Block Diagram .............................................................................. 797Figure 13-1. Implementation of Two ADC Blocks .................................................................... 822Figure 13-2. ADC Module Block Diagram ............................................................................... 823Figure 13-3. ADC Sample Phases ......................................................................................... 827Figure 13-4. Doubling the ADC Sample Rate .......................................................................... 827Figure 13-5. Skewed Sampling .............................................................................................. 828Figure 13-6. Sample Averaging Example ............................................................................... 829Figure 13-7. ADC Input Equivalency Diagram ......................................................................... 830Figure 13-8. ADC Voltage Reference ..................................................................................... 831Figure 13-9. ADC Conversion Result ..................................................................................... 832Figure 13-10. Differential Voltage Representation ..................................................................... 834Figure 13-11. Internal Temperature Sensor Characteristic ......................................................... 835Figure 13-12. Low-Band Operation (CIC=0x0 and/or CTC=0x0) ................................................ 837Figure 13-13. Mid-Band Operation (CIC=0x1 and/or CTC=0x1) ................................................. 838Figure 13-14. High-Band Operation (CIC=0x3 and/or CTC=0x3) ................................................ 839Figure 14-1. UART Module Block Diagram ............................................................................. 921Figure 14-2. UART Character Frame ..................................................................................... 923Figure 14-3. IrDA Data Modulation ......................................................................................... 925Figure 15-1. SSI Module Block Diagram ................................................................................. 982Figure 15-2. TI Synchronous Serial Frame Format (Single Transfer) ........................................ 986Figure 15-3. TI Synchronous Serial Frame Format (Continuous Transfer) ................................ 987Figure 15-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................... 988Figure 15-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................. 988Figure 15-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ......................................... 989Figure 15-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............... 990Figure 15-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........ 990Figure 15-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ......................................... 991Figure 15-10. MICROWIRE Frame Format (Single Frame) ........................................................ 992Figure 15-11. MICROWIRE Frame Format (Continuous Transfer) ............................................. 993Figure 15-12. MICROWIRE Frame Format, SSInFss Input Setup and Hold Requirements .......... 993Figure 16-1. I2C Block Diagram ........................................................................................... 1026Figure 16-2. I2C Bus Configuration ....................................................................................... 1027Figure 16-3. START and STOP Conditions ........................................................................... 1028Figure 16-4. Complete Data Transfer with a 7-Bit Address ..................................................... 1028Figure 16-5. R/S Bit in First Byte .......................................................................................... 1029Figure 16-6. Data Validity During Bit Transfer on the I2C Bus ................................................. 1029Figure 16-7. High-Speed Data Format .................................................................................. 1034Figure 16-8. Master Single TRANSMIT ................................................................................ 1036Figure 16-9. Master Single RECEIVE ................................................................................... 1037Figure 16-10. Master TRANSMIT of Multiple Data Bytes ......................................................... 1038Figure 16-11. Master RECEIVE of Multiple Data Bytes ............................................................ 1039Figure 16-12. Master RECEIVE with Repeated START after Master TRANSMIT ....................... 1040Figure 16-13. Master TRANSMIT with Repeated START after Master RECEIVE ....................... 1041Figure 16-14. Standard High Speed Mode Master Transmit ..................................................... 1042Figure 16-15. Slave Command Sequence .............................................................................. 1043


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Figure 17-1. CAN Controller Block Diagram .......................................................................... 1077Figure 17-2. CAN Data/Remote Frame ................................................................................. 1079Figure 17-3. Message Objects in a FIFO Buffer .................................................................... 1087Figure 17-4. CAN Bit Time ................................................................................................... 1091Figure 18-1. USB Module Block Diagram ............................................................................. 1128Figure 19-1. Analog Comparator Module Block Diagram ....................................................... 1243Figure 19-2. Structure of Comparator Unit ............................................................................ 1244Figure 19-3. Comparator Internal Reference Structure .......................................................... 1245Figure 20-1. PWM Module Diagram ..................................................................................... 1260Figure 20-2. PWM Generator Block Diagram ........................................................................ 1260Figure 20-3. PWM Count-Down Mode .................................................................................. 1264Figure 20-4. PWM Count-Up/Down Mode ............................................................................. 1264Figure 20-5. PWM Generation Example In Count-Up/Down Mode .......................................... 1265Figure 20-6. PWM Dead-Band Generator ............................................................................. 1265Figure 21-1. QEI Block Diagram .......................................................................................... 1338Figure 21-2. QEI Input Signal Logic ...................................................................................... 1339Figure 21-3. Quadrature Encoder and Velocity Predivider Operation ...................................... 1341Figure 22-1. 157-Ball BGA Package Pin Diagram (Top View) ................................................. 1360Figure 24-1. Load Conditions ............................................................................................... 1416Figure 24-2. JTAG Test Clock Input Timing ........................................................................... 1417Figure 24-3. JTAG Test Access Port (TAP) Timing ................................................................ 1418Figure 24-4. Power Assertions versus VDDA Levels ............................................................. 1420Figure 24-5. Power and Brown-Out Assertions versus VDD Levels ........................................ 1421Figure 24-6. POK assertion vs VDDC ................................................................................... 1422Figure 24-7. POR-BOR0-BOR1 VDD Glitch Response .......................................................... 1422Figure 24-8. POR-BOR0-BOR1 VDD Droop Response ......................................................... 1423Figure 24-9. Digital Power-On Reset Timing ......................................................................... 1424Figure 24-10. Brown-Out Reset Timing .................................................................................. 1424Figure 24-11. External Reset Timing (RST) ............................................................................ 1425Figure 24-12. Software Reset Timing ..................................................................................... 1425Figure 24-13. Watchdog Reset Timing ................................................................................... 1425Figure 24-14. MOSC Failure Reset Timing ............................................................................. 1425Figure 24-15. Hibernation Module Timing ............................................................................... 1437Figure 24-16. ESD Protection on Fail-Safe Pins ...................................................................... 1440Figure 24-17. ESD Protection on Non-Fail-Safe Pins .............................................................. 1441Figure 24-18. ADC External Reference Filtering ..................................................................... 1445Figure 24-19. ADC Input Equivalency Diagram ....................................................................... 1446Figure 24-20. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing

Measurement .................................................................................................. 1448Figure 24-21. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............... 1448Figure 24-22. Master Mode SSI Timing for SPI Frame Format (FRF=00), with SPH=1 .............. 1449Figure 24-23. Slave Mode SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................ 1449Figure 24-24. I2C Timing ....................................................................................................... 1450Figure A-1. Key to Part Numbers ........................................................................................ 1457Figure A-2. TM4C123GH6ZRB 157-Ball BGA Package Dimensions ..................................... 1459Figure A-3. 157-Ball BGA ZRB Package Carrier Tape .......................................................... 1460Figure A-4. 157-Ball BGA ZRB Package Plastic Reel .......................................................... 1461Figure A-5. 157-Ball BGA ZRB Package Tape and Reel Box ................................................ 1462



List of TablesTable 1. Revision History .................................................................................................. 39Table 2. Documentation Conventions ................................................................................ 43Table 1-1. TM4C123GH6ZRB Microcontroller Features ......................................................... 46Table 2-1. Summary of Processor Mode, Privilege Level, and Stack Use ................................ 74Table 2-2. Processor Register Map ....................................................................................... 75Table 2-3. PSR Register Combinations ................................................................................. 81Table 2-4. Memory Map ....................................................................................................... 92Table 2-5. Memory Access Behavior ..................................................................................... 96Table 2-6. SRAM Memory Bit-Banding Regions .................................................................... 98Table 2-7. Peripheral Memory Bit-Banding Regions ............................................................... 98Table 2-8. Exception Types ................................................................................................ 104Table 2-9. Interrupts .......................................................................................................... 104Table 2-10. Exception Return Behavior ................................................................................. 112Table 2-11. Faults ............................................................................................................... 113Table 2-12. Fault Status and Fault Address Registers ............................................................ 114Table 2-13. Cortex-M4F Instruction Summary ....................................................................... 116Table 3-1. Core Peripheral Register Regions ....................................................................... 123Table 3-2. Memory Attributes Summary .............................................................................. 127Table 3-3. TEX, S, C, and B Bit Field Encoding ................................................................... 129Table 3-4. Cache Policy for Memory Attribute Encoding ....................................................... 130Table 3-5. AP Bit Field Encoding ........................................................................................ 130Table 3-6. Memory Region Attributes for Tiva C Series Microcontrollers ............................. 131Table 3-7. QNaN and SNaN Handling ................................................................................. 134Table 3-8. Peripherals Register Map ................................................................................... 135Table 3-9. Interrupt Priority Levels ...................................................................................... 165Table 3-10. Example SIZE Field Values ................................................................................ 193Table 4-1. JTAG_SWD_SWO Signals (157BGA) ................................................................. 202Table 4-2. JTAG Port Pins State after Power-On Reset or RST assertion .............................. 203Table 4-3. JTAG Instruction Register Commands ................................................................. 209Table 5-1. System Control & Clocks Signals (157BGA) ........................................................ 213Table 5-2. Reset Sources ................................................................................................... 214Table 5-3. Clock Source Options ........................................................................................ 221Table 5-4. Possible System Clock Frequencies Using the SYSDIV Field ............................... 224Table 5-5. Examples of Possible System Clock Frequencies Using the SYSDIV2 Field .......... 224Table 5-6. Examples of Possible System Clock Frequencies with DIV400=1 ......................... 225Table 5-7. System Control Register Map ............................................................................. 233Table 5-8. RCC2 Fields that Override RCC Fields ............................................................... 263Table 6-1. System Exception Register Map ......................................................................... 498Table 7-1. Hibernate Signals (157BGA) .............................................................................. 507Table 7-2. Hibernation Module Clock Operation ................................................................... 517Table 7-3. Hibernation Module Register Map ....................................................................... 519Table 8-1. Flash Memory Protection Policy Combinations .................................................... 542Table 8-2. User-Programmable Flash Memory Resident Registers ....................................... 546Table 8-3. Flash Register Map ............................................................................................ 552Table 9-1. DMA Channel Assignments .............................................................................. 600Table 9-2. Request Type Support ....................................................................................... 602


Table of Contents

Table 9-3. Control Structure Memory Map ........................................................................... 603Table 9-4. Channel Control Structure .................................................................................. 603Table 9-5. DMA Read Example: 8-Bit Peripheral ................................................................ 612Table 9-6. DMA Interrupt Assignments .............................................................................. 613Table 9-7. Channel Control Structure Offsets for Channel 30 ................................................ 614Table 9-8. Channel Control Word Configuration for Memory Transfer Example ...................... 614Table 9-9. Channel Control Structure Offsets for Channel 7 .................................................. 615Table 9-10. Channel Control Word Configuration for Peripheral Transmit Example .................. 616Table 9-11. Primary and Alternate Channel Control Structure Offsets for Channel 8 ................. 617Table 9-12. Channel Control Word Configuration for Peripheral Ping-Pong Receive

Example ............................................................................................................ 618Table 9-13. DMA Register Map .......................................................................................... 620Table 10-1. GPIO Pins With Non-Zero Reset Values .............................................................. 663Table 10-2. GPIO Pins and Alternate Functions (157BGA) ..................................................... 663Table 10-3. GPIO Pad Configuration Examples ..................................................................... 672Table 10-4. GPIO Interrupt Configuration Example ................................................................ 673Table 10-5. GPIO Pins With Non-Zero Reset Values .............................................................. 674Table 10-6. GPIO Register Map ........................................................................................... 675Table 10-7. GPIO Pins With Non-Zero Reset Values .............................................................. 689Table 10-8. GPIO Pins With Non-Zero Reset Values .............................................................. 696Table 10-9. GPIO Pins With Non-Zero Reset Values .............................................................. 698Table 10-10. GPIO Pins With Non-Zero Reset Values .............................................................. 701Table 10-11. GPIO Pins With Non-Zero Reset Values .............................................................. 708Table 11-1. Available CCP Pins ............................................................................................ 727Table 11-2. General-Purpose Timers Signals (157BGA) ......................................................... 727Table 11-3. General-Purpose Timer Capabilities .................................................................... 730Table 11-4. Counter Values When the Timer is Enabled in Periodic or One-Shot Modes .......... 731Table 11-5. 16-Bit Timer With Prescaler Configurations ......................................................... 733Table 11-6. 32-Bit Timer (configured in 32/64-bit mode) With Prescaler Configurations ............ 733Table 11-7. Counter Values When the Timer is Enabled in RTC Mode .................................... 733Table 11-8. Counter Values When the Timer is Enabled in Input Edge-Count Mode ................. 735Table 11-9. Counter Values When the Timer is Enabled in Input Event-Count Mode ................ 736Table 11-10. Counter Values When the Timer is Enabled in PWM Mode ................................... 738Table 11-11. Timeout Actions for GPTM Modes ...................................................................... 741Table 11-12. Timers Register Map .......................................................................................... 748Table 12-1. Watchdog Timers Register Map .......................................................................... 799Table 13-1. ADC Signals (157BGA) ...................................................................................... 823Table 13-2. Samples and FIFO Depth of Sequencers ............................................................ 825Table 13-3. Differential Sampling Pairs ................................................................................. 832Table 13-4. ADC Register Map ............................................................................................. 840Table 14-1. UART Signals (157BGA) .................................................................................... 922Table 14-2. Flow Control Mode ............................................................................................. 927Table 14-3. UART Register Map ........................................................................................... 932Table 15-1. SSI Signals (157BGA) ........................................................................................ 983Table 15-2. SSI Register Map .............................................................................................. 996Table 16-1. I2C Signals (157BGA) ...................................................................................... 1026Table 16-2. Examples of I2C Master Timer Period Versus Speed Mode ................................. 1032Table 16-3. Examples of I2C Master Timer Period in High-Speed Mode ................................ 1033



Table 16-4. Inter-Integrated Circuit (I2C) Interface Register Map ........................................... 1045Table 16-5. Write Field Decoding for I2CMCS[3:0] Field ....................................................... 1051Table 17-1. Controller Area Network Signals (157BGA) ........................................................ 1078Table 17-2. Message Object Configurations ........................................................................ 1084Table 17-3. CAN Protocol Ranges ...................................................................................... 1091Table 17-4. CANBIT Register Values .................................................................................. 1091Table 17-5. CAN Register Map ........................................................................................... 1095Table 18-1. USB Signals (157BGA) .................................................................................... 1129Table 18-2. Remainder (MAXLOAD/4) ................................................................................ 1140Table 18-3. Actual Bytes Read ........................................................................................... 1140Table 18-4. Packet Sizes That Clear RXRDY ...................................................................... 1141Table 18-5. Universal Serial Bus (USB) Controller Register Map ........................................... 1142Table 19-1. Analog Comparators Signals (157BGA) ............................................................. 1243Table 19-2. Internal Reference Voltage and ACREFCTL Field Values ................................... 1245Table 19-3. Analog Comparator Voltage Reference Characteristics, VDDA = 3.3V, EN= 1, and

RNG = 0 .......................................................................................................... 1246Table 19-4. Analog Comparator Voltage Reference Characteristics, VDDA = 3.3V, EN= 1, and

RNG = 1 .......................................................................................................... 1247Table 19-5. Analog Comparators Register Map ................................................................... 1248Table 20-1. PWM Signals (157BGA) ................................................................................... 1261Table 20-2. PWM Register Map .......................................................................................... 1269Table 21-1. QEI Signals (157BGA) ..................................................................................... 1339Table 21-2. QEI Register Map ............................................................................................ 1343Table 23-1. GPIO Pins With Default Alternate Functions ...................................................... 1361Table 23-2. Signals by Pin Number ..................................................................................... 1362Table 23-3. Signals by Signal Name ................................................................................... 1378Table 23-4. Signals by Function, Except for GPIO ............................................................... 1391Table 23-5. GPIO Pins and Alternate Functions ................................................................... 1402Table 23-6. Possible Pin Assignments for Alternate Functions .............................................. 1406Table 23-7. Connections for Unused Signals (157-Ball BGA) ............................................... 1411Table 24-1. Absolute Maximum Ratings .............................................................................. 1412Table 24-2. ESD Absolute Maximum Ratings ...................................................................... 1412Table 24-3. Temperature Characteristics ............................................................................. 1413Table 24-4. Thermal Characteristics ................................................................................... 1413Table 24-5. Recommended DC Operating Conditions .......................................................... 1414Table 24-6. Recommended GPIO Pad Operating Conditions ................................................ 1414Table 24-7. GPIO Current Restrictions ................................................................................ 1414Table 24-8. GPIO Package Side Assignments ..................................................................... 1415Table 24-9. JTAG Characteristics ....................................................................................... 1417Table 24-10. Power-On and Brown-Out Levels ...................................................................... 1419Table 24-11. Reset Characteristics ....................................................................................... 1424Table 24-12. LDO Regulator Characteristics ......................................................................... 1426Table 24-13. Phase Locked Loop (PLL) Characteristics ......................................................... 1427Table 24-14. Actual PLL Frequency ...................................................................................... 1427Table 24-15. PIOSC Clock Characteristics ............................................................................ 1428Table 24-16. Low-Frequency internal Oscillator Characteristics .............................................. 1428Table 24-17. Hibernation Oscillator Input Characteristics ........................................................ 1428Table 24-18. Main Oscillator Input Characteristics ................................................................. 1429


Table of Contents

Table 24-19. Crystal Parameters .......................................................................................... 1431Table 24-20. Supported MOSC Crystal Frequencies .............................................................. 1432Table 24-21. System Clock Characteristics with ADC Operation ............................................. 1432Table 24-22. System Clock Characteristics with USB Operation ............................................. 1433Table 24-23. Sleep Modes AC Characteristics ....................................................................... 1434Table 24-24. Time to Wake with Respect to Low-Power Modes .............................................. 1434Table 24-25. Hibernation Module Battery Characteristics ....................................................... 1436Table 24-26. Hibernation Module AC Characteristics ............................................................. 1436Table 24-27. Flash Memory Characteristics ........................................................................... 1438Table 24-28. EEPROM Characteristics ................................................................................. 1438Table 24-29. GPIO Module Characteristics ............................................................................ 1439Table 24-30. Pad Voltage/Current Characteristics for Fail-Safe Pins ....................................... 1440Table 24-31. Fail-Safe GPIOs that Require an External Pull-up .............................................. 1441Table 24-32. Non-Fail-Safe I/O Pad Voltage/Current Characteristics ....................................... 1441Table 24-33. ADC Electrical Characteristics .......................................................................... 1443Table 24-34. SSI Characteristics .......................................................................................... 1447Table 24-35. I2C Characteristics ........................................................................................... 1450Table 24-36. Analog Comparator Characteristics ................................................................... 1452Table 24-37. Analog Comparator Voltage Reference Characteristics ...................................... 1452Table 24-38. Analog Comparator Voltage Reference Characteristics, VDDA = 3.3V, EN= 1, and

RNG = 0 .......................................................................................................... 1452Table 24-39. Analog Comparator Voltage Reference Characteristics, VDDA = 3.3V, EN= 1, and

RNG = 1 .......................................................................................................... 1453Table 24-40. Current Consumption ....................................................................................... 1454Table A-1. Orderable Part Numbers .................................................................................. 1457



List of RegistersThe Cortex-M4F Processor ........................................................................................................... 69Register 1: Cortex General-Purpose Register 0 (R0) ........................................................................... 77Register 2: Cortex General-Purpose Register 1 (R1) ........................................................................... 77Register 3: Cortex General-Purpose Register 2 (R2) ........................................................................... 77Register 4: Cortex General-Purpose Register 3 (R3) ........................................................................... 77Register 5: Cortex General-Purpose Register 4 (R4) ........................................................................... 77Register 6: Cortex General-Purpose Register 5 (R5) ........................................................................... 77Register 7: Cortex General-Purpose Register 6 (R6) ........................................................................... 77Register 8: Cortex General-Purpose Register 7 (R7) ........................................................................... 77Register 9: Cortex General-Purpose Register 8 (R8) ........................................................................... 77Register 10: Cortex General-Purpose Register 9 (R9) ........................................................................... 77Register 11: Cortex General-Purpose Register 10 (R10) ....................................................................... 77Register 12: Cortex General-Purpose Register 11 (R11) ........................................................................ 77Register 13: Cortex General-Purpose Register 12 (R12) ....................................................................... 77Register 14: Stack Pointer (SP) ........................................................................................................... 78Register 15: Link Register (LR) ............................................................................................................ 79Register 16: Program Counter (PC) ..................................................................................................... 80Register 17: Program Status Register (PSR) ........................................................................................ 81Register 18: Priority Mask Register (PRIMASK) .................................................................................... 85Register 19: Fault Mask Register (FAULTMASK) .................................................................................. 86Register 20: Base Priority Mask Register (BASEPRI) ............................................................................ 87Register 21: Control Register (CONTROL) ........................................................................................... 88Register 22: Floating-Point Status Control (FPSC) ................................................................................ 90

Cortex-M4 Peripherals ................................................................................................................. 123Register 1: SysTick Control and Status Register (STCTRL), offset 0x010 ........................................... 139Register 2: SysTick Reload Value Register (STRELOAD), offset 0x014 ..........................................