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Tng quan v ngn ng lp trnh VHDL

1. Cng c pht trin VHDL

VHDL (VHSIC Hardware Description Language) l mt ngn ng c dng m t cc h thng in t s. N c chng trnh quc gia v cc mch tch hp tc rt cao VHSIC (Very Hight Speed Intergated Circuit) do chnh ph M khi xng vo u nhng nm 1980. Cc cng ty tham gia chng trnh VHSIC nhn thy rng h cn phi c mt cng c no thit k cc gin u vo cho cc IC chuyn dng c ln, v h xut vic lp ra mt ngn ng m t phn cng dng m t cu trc v chc nng ca cc mch tch hp (cn c gi l IC- Intergated Circuit).

1.1. Gii thiu v lc s cc tiu chun VHDL

1.1.1 Chun IEEE 1076. u nm 1980, mt nhm k s t ba cng ty IBM, Texas Instruments v Intermetrics tp hp li hon thin cc c im k thut ca mt ngn ng mi - phng php m t thit k c s. Phin bn c sn dng chung ca VHDL l 7.2, n c a ra nm 1982. Nm 1986, hip hi cc k s in v in t, vit tt l IEEE a ra xut chun ho ngn ng, n c thc hin nm 1987 sau ci tin v sa i thc hin bi mt nhm i din ca cc cng ty qung co chnh ph v cc trng i hc. Kt qu chun ho, IEEE 1076-1987, l c s cho hu ht mi m phng VHDL v sn phm tng hp ngy nay. S ci tin v cp nht phin bn ca ngn ng, IEEE 1076-1993, c pht hnh nm 1994, v cc nh cung cp cng c hng ng bng cch thm cc c trng ngn ng mi ny cho cc sn phm ca h.

1.1.2 Tiu chun IEEE 1164 Tiu chun IEEE 1076 ch r ngn ng VHDL hon thin, l mt b phn ca ngn ng m thc hin n kh khn cho vit m t thit k linh hot. Vn chnh t s vic m cc phn h tr ca VHDL l nhiu kiu d liu tru tng, nhng n khng ch ra cc trc trc n gin ca chui cc tn hiu phc tp hay cc iu kin m phng s dng ph bin, nh cc n s v tr khng cao.

Ngay sau khi tiu chun IEEE 1076-1987 c thng qua, cc nhm m phng bt u ci tin VHDL vi cc kiu tn hiu mi, cho php cc khch hng ca h m phng chnh xc cc mch in phc tp.

Nguyn do ca cc vn ny bi v cc m t thit k s dng nhp mt m phng trong nhiu trng hp khng tng thch vi cc iu kin m phng khc. VHDL nhanh chng khng c chun ho. tm ra hng gii quyt vn ca cc kiu d liu khng chun ha, cc chun khc, s 1164, c to ra hip hi IEEE . N nh r cc ng gi chun bao gom cc nh ngha cho mt chun kiu d liu nine-valued. Chun d liu ny c gi l std_logic, v ng gi IEEE 1164 c s dng thng xuyn nh ng gi logic chun, hay MVL9.

Chun IEEE 1076-1987 v IEEE 1164 trong dng chun ca VHDL c s dng rng ri ngy nay.

1.1.2.1 Tiu chun IEEE 1076.3 (tiu chun numeric)

Chun 1076.3 (thng c gi l chun Numeric hay chun Synthesis) ch r tiu chun ng gi v s th hin cho d liu chun VHDL ging nh cc chun lin quan ti cc phn cng c thc. Chun ny c dng thay th cc th tc ng gi m cc nh cung cp cng c tng hp to v phn phi cc sn phm ca h.

Tiu chun IEEE 1076.3 khng cho ngi s dng tng hp m chun IEEE 1164 cho ngi s dng m phng:

Tng thm kh nng ca chun IEEE 1076, trong khi thi gian bo m tng thch gia cc cng c ca cc nh cung cp sn phm khc nhau. Tiu chun 1076.3 bao gm nhng ni dung c thm:

Mt ti liu gii thch phn cng ca cc gi tr lin quan ti kiu bt v boolean c ch r bi tiu chun IEEE 1076, ging nh m t ca std_logic nh r bi tiu chun IEEE 1164.

Mt chc nng m cung cp dont care hay will card kim tra gi tr c s ca kiu std_logic. Tnh cht c bit ny s dng cho s tng hp, khi ny n rt c li cho biu din logic trong cc iu kin ca gi tr dont care.

nh r kiu d liu s hc c du v khng c du, cng vi kiu s hc, dch chuyn, v kiu qu trnh hot ng chuyn i ca cc kiu ny.

1.1.2.2 Tiu chun IEEE 1076.4 (VITAL).

S ch gii thng tin thi gian cho mt m hnh m phng l mt v tr quan trng ca s m phng s chnh xc. Chun IEEE 1076 m t s a dng ca cc c trng ngn ng m c th s dng m t thi gian, tuy nhin n khng m t mt phng php chun cho s biu din gi tr thi gian cho thi gian ca chnh m hnh .

Kh nng chia nh cc hot ng m t ca mt s m phng m hnh t thi gian nh l quan trng cho nhiu lp lun. Mt trong nhng chuyn ngnh mnh ca Verilog HDL l c s lp lun m n bao gm mt c trng nh r dng cho s ch gii thi gian.

Chun nh dng gi chm (SDF), cho php s la chn ng lc d liu biu din trong tabular form v bao gm trong m hnh thi gian Verilog trong thi gian m phng.

Tiu chun IEEE 1076.4, c cng b bi hip hi cc k s in t nm 1995, thm kh nng cho VHDL nh l mt chun ng gi. S thc y u tin sau tiu chun ny l s n lc c thc hin mt cch d dng cho cc nh cung cp ASIC v nhng nh cung cp cc sn phm khc to ra cc m hnh thi gian ng dng cho c VHDL v Verilog HDL. Vi l do ny, c s nh dng d liu ca chun IEEE 1076.4 v Verilogs SDF l hon ton nh nhau.

1. 2. Cc cu trc c bn ca ngn ng VHDL.

Cc thnh phn chnh xy dng trong ngn ng VHDL c chia ra thnh nm nhm c bn nh sau:

- Entity

- Architecture

- Package-

- Configuration- Library Entity: Trong mt h thng s, thng thng c thit k theo mt s xp chng cc modul, m mi modul ny tng ng vi mt thc th thit k (c gi l Entity) trong VHDL. Mi mt Entity bao gm hai phn :

- Khai bo thc th ( Entity).

- Thn kin trc ( Architecture Bodies )

Mt khai bo Entity c dng m t giao tip bn ngoi ca mt phn t (component), n bao gm cc khai bo cc cng u vo, cc cng u ra ca phn t . Phn thn ca kin trc c dng m t s thc hin bn trong ca thc th .

Packages: Cc ng gi ch ra thng tin dng chung, m cc thng tin ny c s dng bi mt vi Entity no .

Configuration: nh cu hnh, n cho php gn kt cc th hin ca phn t no cn dng ca mt thit k no c dng mt cu trc v a cc th hin ny vo trong cp Entity v Architecture.

N cho php ngi thit k c th th nghim thay i cc s thc thi khc nhau trong mt thit k. Mi mt thit k dng VHDL bao gm mt vi n v th vin, m mt trong cc th vin ny c dch sn v ct trong mt th vin thit k.

1.2.1 Khai bo Entity:

Nh trn cp, phn khai bo Entity ch a ra mt ci nhn pha bn ngoi cu mt phn t m khng cung cp thng tin v s thc hin ca phn t nh th no. C php khai bo ca mt Entity nh sau:

Entity entity_name is

[generic (generic_declaration);]

[port (port_declaration);]

{entity_declarative_item {constants, types, signals};}

end [entity_name];

[] : Du ngoc vung ch ra cc tham s c th la chn.

| : Du gch ng hin th mt s la chn trong s cc la chn khc.

{}: Khai bo mt hoc nhiu cc i tng, m cc i tng ny c th c nh ngha bi ngi dng.

a. Khai bo Generic dng khai bo cc hng m chng c th c dng iu khin cu trc v s hot ng ca Entity. C php ca khai bo ny nh sau:

generic ( constant_name : type [:=init_value];

{constant_name: type [:=init_value]});

y tn hng constant_name ch ra tn ca mt hng dng generic (hng dng chung).

Kiu (Type) c dng ch ra kiu d liu ca hng.

init_value : ch ra gi tr khi to cho hng.

b. Khai bo cng ( Port ): c dng khai bo cc cng vo, ra ca Entity. C php ca khai bo ny nh sau:

Port ( port_name : [mode] type [:= init_value]; { port_name: [mode] type [:=init_value]});

port_name c dng ch ra tn ca mt cng, mode ch ra hng vo ra ca tn hiu ti cng . Type ch ra kiu d liu ca mt cng v init_value ch ra gi tr khi to cho cng .

Ch ! VHDL khng phn bit ch hoa v ch thng, chng hn nh : xyz = xYz = XYZ.

* C bn mode c s dng trong khai bo cng :

- in : Ch c th c c, n ch c dng cho cc tn hiu u vo ( ch c php nm bn phi php gn )

- out : Ch c dng gn gi tr, n ch c dng cho cc cng u ra ( N ch c nm bn tri ca php gn ).

- inout : C th c dng c v gn gi tr. N c th c nhiu hn mt hng iu khin ( C th nm bn tri hoc bn phi php gn ).

- Buffer : C th c dng c v gn gi tr. ( C th nm bn tri hoc bn phi php gn ).

inout l mt cng hai hng, cn Buffer l mt cng khng c hng.

c. entity_declarative_item : c dng khai bo cc hng, kiu d liu, hoc tn hiu m n c th c s dng trong khi thc hin ca mt Entity.

d. V d :

* V d v khai bo cc cng vo ra:

entity xxx is

port ( A : in integer ;

B : in integer ;

C : out integer ;

D : inout integer ;

E : buffer integer) ;

end xxx;

architecture bhv of xxx isbegin

process (A,B)

begin

C