Tutorial on Design For Manufacturability for Physical Design · 2005. 11. 30. · Design For Manufacturability for Physical Design Andrzej J. Strojwas PDF Solutions Inc., San Jose,

Tutorial on Design For Manufacturability

for Physical DesignAndrzej J. Strojwas

PDF Solutions Inc., San Jose, CA& Carnegie Mellon University, Pittsburgh, PA

2005 ISPD, San Francisco, CAApril 5, 2005

Overview of Presentation

Yield Loss Mechanism Evolution

Classification of DFM Approaches

True DFM: Defining Proactive DFM

Necessary Conditions for Proactive DFM

Process Characterization

Design Flows that Provide Proactive DFM

DFM Results

Looking into the Future: Extreme Layout Regularity

Yield, Performance, Profitability

The Evolution of Product Yields

Random defects are no longer the dominant yield loss mechanism• Yields are limited by design features, systematic and parametric effects

Yield Limiters by Technology Node

40%

50%

60%

70%

80%

90%

100%

0.8um

0.5um

0.35u

m0.2

5um

0.18u

m0.1

3um

90nm

Technology

Yiel

d

Random Defect Limited YieldDesign Feature Limited YieldTotal Yield


Random Yield Loss Mechanisms – Al Interconnect

Contact and via opens due to formation defectivity

Active, poly and metal shorts and opens due to particle defects

Random

Yield Loss MechanismsType

Material opens

Material shorts


Systematic Yield Loss Mechanisms - Cu Interconnect

Misalignment, line-ends/borders

Contact/via opens due to local neighborhood effects (e.g. pitch/hole size)

Leakage from STI related stress

Impact of micro/macro loading design rule marginalitiesSystematicYield Loss MechanismsType

Failure Rate

020406080

100120140160

0.4 1.8 4.2 9

Pitch (um)

Via

Fai

lure

Rat

e (fp

b)

Sparse neighborhood


Systematic Yield Loss: Printability – Nanometer Era

Material opens

Poor contact coverage due to misalignment and defocus/pull backSystematicYield Loss MechanismsType

Poly/Metal shorts


Parametric Yield Loss Mechanisms – Nanometer Era

Non-physical corner modelingDevice mismatchDummy fill parasitic effects

Performance variation from lithography effectse.g., contact/via coverage, active/poly flaring, CD variation

Parametric

Yield Loss MechanismsType

ACLV / CD VariationEnvironment dependent poly CD variation

-10.50-10.00-9.50-9.00-8.50-8.00-7.50-7.00-6.50-6.00

300.00 400.00 500.00 600.00 700.00 800.00Idrive

Ioff

Env I Env II Env III


Technology Challenges: Implications for Manufacturability

65nmLitho:

OPC/PSM integration

issues w/photo window

(DOF)

Front-end/Transistor

Layout dependent

performance

Product ramp issues

Parametric variations -

> yield loss

65nmLitho:

OPC/PSM integration

issues w/photo window

(DOF)

Front-end/Transistor

Layout dependent

performance

Product ramp issues

Parametric variations -

> yield loss

45nmLitho:

Layout pattern

dependence, Scanner NA,

Immersion litho, OPC/PSM

integration, issues w/photo

window (DOF)

Front end/Transistor

New transistor

architectures (UTB, DG SOI)

Product ramp issues

Reliability assurance

45nmLitho:

Layout pattern

dependence, Scanner NA,

Immersion litho, OPC/PSM

integration, issues w/photo

window (DOF)

Front end/Transistor

New transistor

architectures (UTB, DG SOI)

Product ramp issues

Reliability assurance

90nmBack-end integration

issues

Low k: stress and

reliability

CMP - multi-layer

topography issues

Product ramp issues

Variability

Yield-performance

tradeoffs

90nmBack-end integration

issues

Low k: stress and

reliability

CMP - multi-layer

topography issues

Product ramp issues

Variability

Yield-performance

tradeoffs


DFM is a Business Opportunity"Seamless" DFM Can Contribute 5% More Good Die

What's 5% more good die worth?

$50M over the life of a cell phone

$80M over the life of a game chip

$100M per year per fab at 90nm


A Brief History of DFM

Design rules guarantee yield!…well, not really……then recommended rules …and opportunistic design data base post-processing to enforce them

Functional Yield means Rules

The corners represent the process…The corners don’t represent the process but they are conservative…Within chip variations are important so..

• Restrict transistor layouts?• Statistical timing simulation?

Performance Yield is Covered by CornersIdsat Distribution

-500

-450

-400

-350

-300

-250

-200600 650 700 750 800 850 900 950 1000 1050

NIdsatPI

dsat

ASIC Corners

Realistic Corners


Post-GDS Yield Opt.

OPC/ RET

DesignDesign ManufacturingManufacturingMDP and

Mask Making

Yield Ramp

IP lib. Design

pre-MDP

Timing and SI

AnalysesPhysical

Verification

Physical SP&R

Verification and Yield Opt.Verification and Yield Opt.Dummy Fill

and Cheesing

Volume Production

Post-GDS Yield Opt.

OPC/ RET

DesignDesign ManufacturingManufacturingMDP and

Mask Making

Yield Ramp

IP lib. Design

pre-MDP

Timing and SI

AnalysesPhysical

Verification

Physical SP&R

Verification and Yield Opt.Verification and Yield Opt.

Dummy Fill and

CheesingVolume

Production

Process Characterization + Yield Modeling

DFM needs to be ProactiveOccurring early in the design flowUp-front accurate process characterizationYield modeling to characterize IP and drive EDA tools

Proactive DFMDesigner access to the process is limitedMost DFM today is Reactive

•Increase in design cycle time•Misaligned mask GDSII and design database

•Risky design feature changes


Necessary Conditions for Pro-Active DFM

Accurate characterization of design-interactions at target fab(s)

Effects modeled across the whole process window

Quantification of alternatives that allow EDA tools to make millions of DFM trade-offs

Integration early in the design flow where there are more degrees of freedom

• Floor planning• SP&R

Modifications made prior to verification


Yield Simulation is Core to Proactive DFM

A yield model for DFM:• Model of failure rate of a design element (e.g., transistor, contact, via)

as a function of the layout design• Example:

• What is the failure rate of a single via vs. double?• What is the probability of a short in two metal lines if there are lots of vias

underneath them

To do this, we need process characterization

Yield Simulation allows for better understanding of the DFM universe


Process Yield Loss Mechanisms

ActivePoly Poly

CC

M1V1

M1V1

M2M2V2V2

Mx

Yield Loss MechanismsYield Loss Mechanisms•Layer defect densities•Attribute dependent failure rates•Lithography / CMP driven interactions•…

Yield Loss Mechanisms (Yield Loss Mechanisms (YLM’sYLM’s))• Root causes of process related yield loss• Each YLM must be characterized in the process with a specific test

structure – Characterization Vehicle (CV)


Typical Die Yield Estimation

Model implies that for a given die size, yield is based only upon process maturity – this is not correct

• Yield is different for different IP content• Process defectivity is different for each module

)(cm area dieA

)(1/cm defects meanDyielddieY

whereeY

2

20

AD

=

=

=

= −

,

0Die Yield Model

0%

20%

40%

60%

80%

100%

0 0.5 1 1.5 2Mean Defectivity (1/cm^2)

Die

Yie

ld

Area = 2 cm^2Area = 1.5 cm^2Area = 1 cm^2Area = 0.5 cm^2


Process-Design Interaction

Chip Yield is a strong function of design content• Physical design features interact with specific module weakness

Memory

Logic

Memory

Logic

Ratio << 1.0Ratio << 1.0 Ratio >> 1.0Ratio >> 1.0

LOGICMEMORYYYY =

Die Content Impact on Yield (~40mm^2 Die Size)

5%

15%

25%

35%

45%

55%

0.0 1.0 2.0 3.0 4.0Memory/Logic Ratio

Yiel

d

Total Yield (130nm)Total Yield (90nm)


Accurate Process Characterization

Defect Size Distribution by Process Module

Defect Size [um]D

efec

t Den

sity

[D

efec

ts/c

m^2

]

ondistributitsize/coundefectDSD(x) =

Metal Opens/Shorts Metal Opens/Shorts Characterization VehicleCharacterization Vehicle

Poly and Active Opens/Shorts Poly and Active Opens/Shorts Characterization VehicleCharacterization Vehicle


Product Design Attributes

SRAM

ASIC Logic

ROM

Analog

I/O

Custom Logic

Design Attributes:Design Attributes:• Physical design properties that interact with specific module marginalities• Each attribute can be extracted from physical layout• Design attribute extraction (DAE) enables quantification of design content specific

YLM models

Design AttributesDesign Attributes• Widths, lengths and spacing• Counts• Densities• Overlaps/enclosures• …


Design Attribute Extraction

Contact/Via Count Design Attribute Extraction

Contacts and Vias

Cou

nt

Critical Area Shorts Design Attribute Extraction

Defect Diameter [um]

Crit

ical

Are

a [u

m^2

]

Contacts/Via Counts•N/P Active•Poly•V1-Vx

Critical Area Shorts Sensitivities•AA•Poly•M1-Mx

xtoty sensitiviattributedesign(x)AC =Yield, Performance, Profitability

Accurate Process Characterization

Process Margin

0

0.2

0.4

0.6

0.8

1

1.2

0

0.02

0.04

0.06

0.08 0.

1

0.12

0.14

0.16

0.18 0.

2

Spacing

Yiel

d

0

0.05

0.1

0.15

0.2

0.25

0.3

p(sp

acin

g)

Layo

utMe

tric

Misalignment

Mask Error

DOE on litho parameters RSM of layout metric

INPUT: Characterization of litho process statistics

Defocus

Exposure

Yield Loss

Defocus

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

Misalignment

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

−3.0 σ

−2.5 σ

−2.0 σ

−1.5 σ

−1.0 σ

−0.5 σ

0.0 σ

0.5 σ

1.0 σ

1.5 σ

2.0 σ

2.5 σ

3.0 σExposure

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7


PSD: condition 1

PSD: condition2

PSD Analysis

Process Margin data from CV

Implicit YLM model: process window effects


Yield Simulation Results: Yield Impact Matrix

SRAM

ASIC Logic

ROM

Analog

I/O

Custom Logic

Physical design properties that interact with specific module defectivitiesEach attribute can be extracted from GDSIIDesign attribute extraction (DAE) enables quantification of die content specific yield models

Design AttributesDesign Attributes• Widths, lengths and spacing• Counts• Densities• Overlaps/enclosures• …

YIMP Matrix

Active Random 98% 99% 99%Pattern Dependent 99% 99% 100%

Total 97% 98% 99%Poly Random 97% 98% 99%

Pattern dependent 94% 95% 99%Total 91% 95% 96%

Metal Random 97% 98% 99%Pattern dependent 97% 98% 99%

Total 94% 95% 99%Holes 97% 98% 99%

Total 81% 82% 99%

Metal Islands 87% 89% 90%Pattern Density 91% 93% 94%Narrow Space Wide Neighbor 97% 99% 100%Via induced Metal Shorts 77% 78% 79%

Total 62% 64% 64%

Ran

dom

Def

ects

Sys

tem

atic

LOGIC

Limited Yield

Failure Mode Full Chip SRAM


Yield Simulation Accuracy

Yield modeling accuracy is excellent when you characterize right• Error represents unidentified yield loss mechanisms

or lack of yield model

Accuracy of Yield Prediction

0%

20%

40%

60%

80%

100%

A B C D E FProduct

Yiel

d

-10%

-8%

-6%

-4%

-2%

0%

2%

4%

Abs

olut

e Er

ror

PredictedActualAbs. Error


Overview of Layout Design for Manufacturability

Critical Area Based Wire Spreading • Most useful in Al interconnect era (random metal shorts – dominant

yield loss mechanism)

Contact/via Doubling• Effective in reduction yield losses due to random hole opens (Al & Cu)

Systematic Yield Model Based Local and Global P&R Layout Modifications

• Essential for 3-D topography effects due to Cu CMP and low-k interconnect

Printability and Performance Variability Driven Layout Generation

• Absolute must in the Nanometer Era• Pro-active (not afterthought in RET)


Limited Yield Optimization

Product yields must be optimized by improving LY’s• LYGAIN ratio of improvement for any specific optimization

Prioritizing which LY’s to improve requires an understanding of the specific Design Manufacturability ObjectivesDesign Manufacturability Objectives

LY(SRAM)

LY(ASIC)

LY(ROM)

LY(Analog)

LY(I/O)

LY(Custom)

( )( )

variant originalvvariant optimizedv

Parametric c, SystematiRandomjwhere

Y

YLY

2

1

j vj

vjGAIN

==

=

= ∏

,,

2

1


0

10

20

30

40

50

60

40% 60% 80% 100%Yield

# of

lots

Design Manufacturability Objectives

Best Yield Variability

Best Average

Yield

Tailored specifically for a process and product

Custom

MicroprocessorsPerformance Variability

Networking, Graphics, DSP

Yield Variability

DVD, STB, Cell Phone, Digital Cameras

Average Yield

ProductsObjectives

Customization of DFM objectives• High volume parts in mature process• Lower volume parts during ramp


Enabling Proactive DFM For DesignersDesign Flow

RTL Design

Hierarchical Floorplan

Physical Synthesis

Chip Assembly

Sign-off

VERI

FICA

TION Yield Models

Yield View (.pdfm)

DFM Optimized

LibraryModule

Standard IP Platform

DFM Software

Yield Simulation

and optimization

Three components to enable Proactive DFM• DFM library module• Layout attribute dependent yield models (DFM library view)• Yield simulation and optimization software


DFM Variant Generation Flow

Cell LayoutsCell Layouts

Manufacturability Hot Spot LocalizationManufacturability

Hot Spot LocalizationConstraint generation

Constraint generation

Layout Design

DFMLibraryDFM

Library

Hot Spots Minimized?Hot Spots

Minimized?No Yes

MFG Characterization

MFG Characterization

PruningPruning

DFM Architecture SpecificationsDFM Architecture Specifications

Average Yield

Average Yield

Yield Variability

Yield Variability

Performance Variability

Performance Variability

NetlistNetlist


Yield Variants ExampleHigh Density Random/Systematic Yield Variant

Litho hot spots

M1 shorts

M1 opens

Yield/Speed Consistency Variant

+20% area

-50% FR (ppb)

+40% area

-50% FR (ppb)

-85% YV (std.dev)


Standard Cell Optimization Flow

Litho Environment

Hot Spot Analysis

Litho Simulated Layout

0.14u

Optimized Layout

0.18u

Synthesized Layout

0.16u

Optimized Layout

0.2u

MOS1 d g s b nmos L=0.13u W=1uMOS2 d g s b pmos L=0.13u W=0.8uMOS3 d g s b nmos L=0.13u W=0.7uMOS4 d g s b pmos L=0.13u W=1.2uMOS5 d g s b nmos L=0.13u W=1.3uMOS6 d g s b pmos L=0.13u W=1u

Original Netlist

Contact redundancy definitionSpacing rules definitionTransitions rules definitionMetal islands definitionTaps…

Cell Architecture

DFM Library View for EDA

.pdfm view.pdfm view includes relevant data to enable EDA tools to make yield tradeoffs

• Process Defectivities• Design Attributes• Yield and Manufacturability

Models

.pdfm data also enables BEOL routing optimzation

Characteristic Library View

Layout GDSII

Schematic SPICE Netlist

Logic Function Verilog

Manufacturability .pdfm

Performance .lib

P&R Footprint LEF

DFM Library Module

Core Libraries

Process Characterization

Design Attribute Extractions

Defectivities

Compiler

DFM Library View

“pDfx enabled” P&R

Include yield in the cost functionTake advantage of design slacksTiming convergence properties unchanged

Global/ Detailed

Routing

Logic/Physical Synthesis

Clock routing

Timing Sign-off

Post-Routing

Optimization

.PDFMSTD.CELL YLM models

STD.CELL YLM models

BEOL YLM models

BEOL YLM models

Stat. Gate Models

CMP/Litho Models

And the Silicon Says…

Silicon shows up to 12% GDPW improvement by applying our Silicon shows up to 12% GDPW improvement by applying our Proactive DFM methodologyProactive DFM methodology

0%2%4%6%8%

10%12%

GD

PW

Impr

ovem

ent (

%)

A (0.15um)

B (0.13um)

C (0.13um)

D (0.13um)

E (0.13um)

Chip / Technology

Percentage GDPW Improvement• Fabless• Graphics chip• Early process

lifecycle

• IDM• Controller chip• Mid-process lifecycle

• IDM• Cell phone chip• Mid process lifecycle

• IDM• Set top box• Mid-process lifecycle

• IDM• Graphics• Mature process


Looking Into the Future: Extreme Layout Regularity

RETs are time-consuming and difficult to optimize for large process windows• Defocus, Illumination conditions, Pattern neighborhood

Conventional design rules are becoming insufficient to guaranteedesign’s adherence to RETs• Increasing need for more geometry regularity by design

Sensitive to growdue to defocus

Sensitive to shrinkdue to defocus

Sensitive to exposure variation

Sensitive to resist effects

Regular Logic Bricks

Arrays offer advantages for silicon characterization and even inventory, but at a high area penaltyRegular Logic Bricks can offer more efficient use of area, and still provide the required regularity

Map a simple set of logic primitives onto regular fabric patterns to form logic bricks

Macro Regularity

Optical proximity:

r ≈ 1um

2-3 INVs on boundaries of

logic bricks

Regular fabric ensures that logic bricks share geometry regularity with all other bricks and registers Fabric “rules” co-optimized for memories, IPs, and bricksCompatible RETs and geometries at brick boundaries

On-gridgeometries

On-gridgeometries

On-gridgeometries

On-gridgeometries r

r

Region of influence

Some Experimental Results

Little area benefit for using more than 10 unique bricks

• Few unique bricks allows for macro regularity and silicon validation analogous to CLBsand bit cells

Trade-off between number of geometry patterns and area/performanceIdeally, regular fabric synthesis tool would determine this for each design in an application-specific manner

Firewire Controller

0

5000

10000

15000

20000

25000

3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

Number of Bricks

Are

a Es

timat

e

0

1

2

3

4

5

6

7

8

9

10

Avg

. no.

of V

ias

per B

rick

AreaNo. of vias

Koggstone

0

5000

10000

15000

20000

25000

30000

35000

40000

3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

Number of Bricks

Are

a Es

timat

e

0

1

2

3

4

5

6

Avg

. no.

of V

ias

per B

rick

AreaNo. of vias

Exploiting RegularityLogic regularity provides opportunities for new predictable methodologies

1. Small library of primitives2. Mapping into a set of configurable

pre-defined bricks

Factors f & f’ from FG1 & G2 are positive & negative cofactors with respect to function f

Ultimate Goal

From synthesis we define the set of regular logic bricks that cover the extracted logic modulesFrom the fabrics level, perform shapes-level physical-synthesis to construct configurable bricks• Nano-scale constraints allow us to

simplify this shapes-level physical synthesis problem

• Can be optimized with simulation-based printability modeling

Automated layout

Further ConsiderationsGlobal effects and system-level issues

• Memory and logic compatibility • Regular BEOL – structured routing• Analog components

Cu thickness distribution

WLAN WCDMA GPS

Documents

Tutorial on Design For Manufacturability for Physical Design · 2005. 11. 30. · Design For Manufacturability for Physical Design Andrzej J. Strojwas PDF Solutions Inc., San Jose,