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© Bharati Vidyapeeth’s Institute of Computer Applications and Management, New Delhi-63., by Deepali Kamthania U1. 1 UNIT-II BASIC COMPUTER ORGANIZATION AND DESIGN


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UNIT-II BASIC COMPUTER ORGANIZATION AND DESIGN. LEARNING OBJECTIVES. • System Bus Instruction Codes • Computer Registers • Computer Instructions • Timing and Control • Instruction Cycle • Memory Reference Instructions • Input-Output and Interrupt • Complete Computer Description - PowerPoint PPT Presentation



  • System Bus Instruction Codes

    Computer Registers

    Computer Instructions

    Timing and Control

    Instruction Cycle

    Memory Reference Instructions

    Input-Output and Interrupt

    Complete Computer Description

    Design of Basic Computer

    Design of Accumulator Logic



  • The major computer system components (processor, main memory, I/O modules) need to be interconnected in order to exchange data and control signalsA bus is a communication pathway connecting two or more devicesA bus that connects major computer components (processor, memory, I/O) is called a system bus. Bus = a shared transmission medium. Only one device at a time Can successfully transmit. shared system bus consisting of multiple linesa hierarchy of buses to improve performance. Key design elements for buses include: Arbitration, Timing, widthSYSTEM BUSES


  • In general, the more devices attached to the bus, the greater the bus length and hence the greater the propagation delay.The bus may become a bottleneck as the aggregate data transfer demand approaches the capacity of the bus.


  • Synchronous buses include a clock line between the control lines, line that is controlled by a clock quartz oscillator, usually between 5 - 133 MHz All the transfers on the system bus has a fixed protocol related to the clock signal, and it is developed along an integer number of cycles, called bus cycles.The advantages of a synchronous bus are a high speed of transfer, the very simple implied logicThe disadvantage comes from transfers that can be shorter than the time corresponding to the integer number of bus cycles.SYNCHRONOUS BUSES

  • INTRODUCTIONEvery different processor type has its own design (different registers, buses, microoperations, machine instructions, etc)Modern processor is a very complex deviceIt containsMany registersMultiple arithmetic units, for both integer and floating point calculationsThe ability to pipeline several consecutive instructions to speed execution etc.

  • INTRODUCTIONHowever, to understand how processors work, we will start with a simplified processor modelThis is similar to what real processors were like ~25 years agoM. Morris Mano introduces a simple processor model he calls the Basic ComputerWe will use this to introduce processor organization and the relationship of the RTL model to the higher level computer processor

  • BASIC COMPUTERThe Basic Computer has two components, a processor and memoryThe memory has 4096 words in it4096 = 212, so it takes 12 bits to select a word in memoryEach word is 16 bits longCPURAM04095015

  • INSTRUCTIONSInstruction codesProgramA sequence of (machine) instructions (Machine) InstructionA group of bits that tell the computer to perform a specific operation (a sequence of micro-operation) The instructions of a program, along with any needed data are stored in memoryThe CPU reads the next instruction from memoryIt is placed in an Instruction Register (IR)Control circuitry in control unit then translates the instruction into the sequence of microoperations necessary to implement it

  • INSTRUCTION FORMATInstruction codesA computer instruction is often divided into two partsAn opcode (Operation Code) that specifies the operation for that instructionAn address that specifies the registers and/or locations in memory to use for that operationIn the Basic Computer, since the memory contains 4096 (= 212) words, we needs 12 bit to specify which memory address this instruction will use

  • INSTRUCTION FORMATInstruction codesIn the Basic Computer, bit 15 of the instruction specifies the addressing mode (0: direct addressing, 1: indirect addressing)Since the memory words, and hence the instructions, are 16 bits long, that leaves 3 bits for the instructions opcode

  • ADDRESSING MODESInstruction codesThe address field of an instruction can represent eitherDirect address: the address in memory of the data to use (the address of the operand), orIndirect address: the address in memory of the address in memory of the data to use

    Effective Address (EA)The address, that can be directly used without modification to access an operand for a computation-type instruction, or as the target address for a branch-type instruction

  • PROCESSOR REGISTERSInstruction codesA processor has many registers to hold instructions, addresses, data, etcThe processor has a register, the Program Counter (PC) that holds the memory address of the next instruction to getSince the memory in the Basic Computer only has 4096 locations, the PC only needs 12 bitsIn a direct or indirect addressing, the processor needs to keep track of what locations in memory it is addressing: The Address Register (AR) is used for thisThe AR is a 12 bit register in the Basic ComputerWhen an operand is found, using either direct or indirect addressing, it is placed in the Data Register (DR). The processor then uses this value as data for its operationThe Basic Computer has a single general purpose register the Accumulator (AC)

  • PROCESSOR REGISTERSInstruction codesThe significance of a general purpose register is that it can be referred to in instructionse.g. load AC with the contents of a specific memory location; store the contents of AC into a specified memory locationOften a processor will need a scratch register to store intermediate results or other temporary data; in the Basic Computer this is the Temporary Register (TR)The Basic Computer uses a very simple model of input/output (I/O) operationsInput devices are considered to send 8 bits of character data to the processorThe processor can send 8 bits of character data to output devices

  • PROCESSOR REGISTERSThe Input Register (INPR) holds an 8 bit character gotten from an input deviceThe Output Register (OUTR) holds an 8 bit character to be send to an output device

  • BASIC COMPUTER REGISTERSList of BC RegistersDR 16 Data Register Holds memory operandAR 12 Address Register Holds address for memoryAC 16 Accumulator Processor registerIR 16 Instruction Register Holds instruction codePC 12 Program Counter Holds address of instructionTR 16 Temporary Register Holds temporary dataINPR 8 Input Register Holds input characterOUTR 8 Output Register Holds output characterRegistersRegisters in the Basic Computer110PC150IR150TR70OUTR150DR150AC110ARINPR07Memory

    4096 x 16CPU

  • COMMON BUS SYSTEMRegistersThe registers in the Basic Computer are connected using a busThis gives a savings in circuitry over complete connections between registers



  • COMMON BUS SYSTEMRegistersThree control lines, S2, S1, and S0 control which register the bus selects as its input

    Either one of the registers will have its load signal activated, or the memory will have its read signal activatedWill determine where the data from the bus gets loadedThe 12-bit registers, AR and PC, have 0s loaded onto the bus in the high order 4 bit positionsWhen the 8-bit register OUTR is loaded from the bus, the data comes from the low order 8 bits on the bus0 0 0x0 0 1AR0 1 0PC0 1 1DR1 0 0AC1 0 1IR1 1 0TR1 1 1MemoryS2 S1 S0 Register

  • BASIC COMPUTER INSTRUCTIONS Basic Computer Instruction Format15 1412 110IOpcodeAddressMemory-Reference Instructions (OP-code = 000 ~ 110)

    Register-Reference Instructions (OP-code = 111, I = 0)

    Input-Output Instructions(OP-code =111, I = 1)

  • BASIC COMPUTER INSTRUCTIONS Hex CodeSymbol I = 0 I = 1 DescriptionAND 0xxx 8xxx AND memory word to ACADD 1xxx 9xxx Add memory word to ACLDA 2xxx Axxx Load AC from memorySTA 3xxx Bxxx Store content of AC into memoryBUN 4xxx Cxxx Branch unconditionallyBSA 5xxx Dxxx Branch and save return addressISZ 6xxx Exxx Increment and skip if zero

    CLA 7800 Clear ACCLE 7400 Clear ECMA 7200 Complement ACCME 7100 Complement ECIR 7080 Circulate right AC and ECIL 7040 Circulate left AC and EINC 7020 Increment ACSPA 7010 Skip next instr. if AC is positiveSNA 7008 Skip next instr. if AC is negativeSZA 7004 Skip next instr. if AC is zeroSZE 7002 Skip next instr. if E is zeroHLT 7001 Halt computer

    INP F800 Input character to ACOUT F400 Output character from ACSKI F200 Skip on input flagSKO F100 Skip on output flagION F080 Interrupt onIOF F040 Interrupt off

  • INSTRUCTION SET COMPLETENESS Instruction TypesA computer should have a set of instructions so that the user can construct machine language programs to evaluate any function that is known to be computable. Functional Instructions - Arithmetic, logic, and shift instructions - ADD, CMA, INC, CIR, CIL, AND, CLATransfer Instructions - Data transfers between the main memory and the processor registers - LDA, STAControl Instructions - Program sequencing and control - BUN, BSA, ISZInput/Output Instructions - Input and output - INP, OUT

  • CONTROL UNITControl unit (CU) of a processor translates from machine instructions to the control signals for the microoperations that implement themControl units are implemented in one of two waysHardwired ControlCU is made up of sequential and combinational circuits to generate the control signalsMicroprogrammed ControlA control memory on the processor contains microprograms that activate the necessary control signals

    We will consider a hardwired implementation of the control unit for the Basic Computer


  • TIMING AND CONTROLControl unit of Basic ComputerInstruction register (IR)1514 13 1211 - 03 x 8

    decoder 7 6 5 4 3 2 1 0ID015 14 . . . . 2 1 04 x 16




    (SC)Increment (INR)Clear (CLR)ClockOther inputsControlsignals


  • TIMING SIGNALS- Generated by 4-bit sequence counter and 416 decoder- The SC can be incremented or cleared.

    - Example: T0, T1, T2, T3, T4, T0, T1, . . . Assume: At time T4, SC is cleared to 0 if decoder output D3 is active.D3T4: SC 0Timing and control

  • INSTRUCTION CYCLEIn Basic Computer, a machine instruction is executed in the following cycle:Fetch an instruction from memoryDecode the instructionRead the effective address from memory if the instruction has an indirect addressExecute the instruction

    After an instruction is executed, the cycle starts again at step 1, for the next instructionNote: Every different processor has its own (different) instruction cycle

  • FETCH and DECODE Fetch and DecodeT0: AR PC (S0S1S2=010, T0=1)T1: IR M [AR], PC PC + 1 (S0S1S2=111, T1=1)T2: D0, . . . , D7 Decode IR(12-14), AR IR(0-11), I IR(15)S2S1S0Bus7Memory

    unitAddressReadARLDPCINRIRLDClock125Common busT1T0Instruction Cycle

  • DETERMINE THE TYPE OF INSTRUCTIOND'7IT3:AR M[AR]D'7I'T3:NothingD7I'T3:Execute a register-reference instr.D7IT3:Execute an input-output instr.Instruction Cycle

  • REGISTER REFERENCE INSTRUCTIONSr = D7 IT3 => Register Reference InstructionBi = IR(i) , i=0,1,2,...,11- D7 = 1, I = 0- Register Ref. Instr. is specified in b0 ~ b11 of IR- Execution starts with timing signal T3

    Instruction CycleRegister Reference Instructions are identified whenr:SC 0CLArB11:AC 0CLErB10:E 0CMArB9:AC ACCMErB8:E ECIRrB7:AC shr AC, AC(15) E, E AC(0)CILrB6:AC shl AC, AC(0) E, E AC(15)INCrB5:AC AC + 1SPArB4:if (AC(15) = 0) then (PC PC+1)SNArB3:if (AC(15) = 1) then (PC PC+1)SZArB2:if (AC = 0) then (PC PC+1)SZErB1:if (E = 0) then (PC PC+1)HLTrB0:S 0 (S is a start-stop flip-flop)

  • MEMORY REFERENCE INSTRUCTIONSAND to ACD0T4:DR M[AR]Read operandD0T5:AC AC DR, SC 0AND with ACADD to ACD1T4:DR M[AR]Read operandD1T5:AC AC + DR, E Cout, SC 0Add to AC and store carry in E

    - The effective address of the instruction is in AR and was placed there during timing signal T2 when I = 0, or during timing signal T3 when I = 1- Memory cycle is assumed to be short enough to complete in a CPU cycle- The execution of MR instruction starts with T4MR InstructionsSymbolOperationDecoderSymbolic DescriptionAND D0 AC AC M[AR]ADD D1 AC AC + M[AR], E CoutLDA D2 AC M[AR]STA D3 M[AR] ACBUN D4 PC ARBSA D5 M[AR] PC, PC AR + 1ISZ D6 M[AR] M[AR] + 1, if M[AR] + 1 = 0 then PC PC+1

  • MEMORY REFERENCE INSTRUCTIONS Memory, PC after execution210BSA135Next instructionSubroutine20PC = 21AR = 1351361BUN135 Memory, PC, AR at time T40BSA135Next instructionSubroutine2021135PC = 1361BUN135MemoryMemoryLDA: Load to ACD2T4:DR M[AR]D2T5:AC DR, SC 0STA: Store ACD3T4:M[AR] AC, SC 0BUN: Branch UnconditionallyD4T4:PC AR, SC 0BSA: Branch and Save Return AddressM[AR] PC, PC AR + 1


    ISZ: Increment and Skip-if-ZeroD6T4:DR M[AR]D6T5:DR DR + 1D6T4:M[AR] DR, if (DR = 0) then (PC PC + 1), SC 0



    SC 0AC AC + DR

    E Cout

    SC 0AC DR

    SC 0D T04D T14D T24D T34D T05D T15D T25PC AR

    SC 0M[AR] PC


    SC 0M[AR] DR

    If (DR = 0)

    then (PC PC + 1)

    SC 0D T66

  • INPUT-OUTPUT AND INTERRUPT Input-Output ConfigurationINPRInput register - 8 bitsOUTROutput register - 8 bitsFGIInput flag - 1 bitFGOOutput flag - 1 bitIENInterrupt enable - 1 bitA Terminal with a keyboard and a PrinterInput-output



    interfaceComputerregisters andflip-flops



    interfaceFGOOUTRACINPRFGISerial Communications PathParallel Communications Path

  • INPUT-OUTPUT AND INTERRUPT- The terminal sends and receives serial information - The serial info. from the keyboard is shifted into INPR The serial info. for the printer is stored in the OUTR

    - INPR and OUTR communicate with the terminal serially and with the AC in parallel.

    - The flags are needed to synchronize the timing difference between I/O device and the computer

  • PROGRAM CONTROLLED DATA TRANSFERloop: If FGI = 1 goto loop INPR new data, FGI 1

    loop: If FGO = 1 goto loop consume OUTR, FGO 1-- CPU -- -- I/O Device --/* Input */ /* Initially FGI = 0 */ loop: If FGI = 0 goto loop AC INPR, FGI 0

    /* Output */ /* Initially FGO = 1 */ loop: If FGO = 0 goto loop OUTR AC, FGO 0

    I/O and InterruptStart InputFGI 0FGI=0AC INPRMoreCharacterENDStart OutputFGO 0FGO=0MoreCharacterENDOUTR ACAC DatayesnoyesnoFGI=0FGO=1yesyesnono


    D7IT3 = pIR(i) = Bi, i = 6, , 11p:SC 0Clear SCINPpB11:AC(0-7) INPR, FGI 0Input char. to AC OUTpB10:OUTR AC(0-7), FGO 0Output char. from AC SKIpB9:if(FGI = 1) then (PC PC + 1)Skip on input flag SKOpB8:if(FGO = 1) then (PC PC + 1) Skip on output flagIONpB7:IEN 1Interrupt enable onIOFpB6:IEN 0Interrupt enable off

  • PROGRAM-CONTROLLED INPUT/OUTPUT Program-controlled I/O- Continuous CPU involvement I/O takes valuable CPU time- CPU slowed down to I/O speed- Simple- Least hardwareI/O and InterruptInput




  • INTERRUPT INITIATED INPUT/OUTPUT- Open communication only when some data has to be passed --> interrupt.

    - The I/O interface, instead of the CPU, monitors the I/O device.

    - When the interface founds that the I/O device is ready for data transfer, it generates an interrupt request to the CPU

    - Upon detecting an interrupt, the CPU stops momentarily the task it is doing, branches to the service routine to process the data transfer, and then returns to the task it was performing.

    * IEN (Interrupt-enable flip-flop)- can be set and cleared by instructions- when cleared, the computer cannot be interrupted


    I/O and InterruptStore return address

    R=1=0in location 0

    M[0] PCBranch to location 1

    PC 1IEN 0 R 0

    Interrupt cycleInstruction cycleFetch and decode


    instructionsR 1=1=1=1=0=0=0

  • INTERRUPT CYCLE- The interrupt cycle is a HW implementation of a branch and save return address operation.- At the beginning of the next instruction cycle, the instruction that is read from memory is in address 1.At memory address 1, the programmer must store a branch instruction that sends the control to an interrupt service routine- The instruction that returns the control to the original program is "indirect BUN 0"

    I/O and Interrupt

  • REGISTER TRANSFER OPERATIONS IN INTERRUPT CYCLE Register Transfer Statements for Interrupt Cycle- R F/F 1 if IEN (FGI + FGO)T0T1T2 T0T1T2 (IEN)(FGI + FGO): R 1

    - The fetch and decode phases of the instruction cycle must be modified Replace T0, T1, T2 with R'T0, R'T1, R'T2- The interrupt cycle :RT0:AR 0, TR PCRT1:M[AR] TR, PC 0RT2:PC PC + 1, IEN 0, R 0, SC 0 After interrupt cycle0BUN112001PC = 2562551BUN0 Before interruptMain


    Program0BUN11200PC = 1 2562551BUN0MemoryMain



  • FURTHER QUESTIONS ON INTERRUPTHow can the CPU recognize the device requesting an interrupt ?

    Since different devices are likely to require different interrupt service routines, how can the CPU obtain the starting address of the appropriate routine in each case ?

    Should any device be allowed to interrupt the CPU while another interrupt is being serviced ?

    How can the situation be handled when two or more interrupt requests occur simultaneously ?

    I/O and Interrupt

  • COMPLETE COMPUTER DESCRIPTIONFlowchart of OperationsDescription=1 (I/O) =0 (Register) =1(Indir) =0(Dir)startSC 0, IEN 0, R 0RAR PCRT0IR M[AR], PC PC + 1RT1AR IR(0~11), I IR(15)D0...D7 Decode IR(12 ~ 14)RT2AR 0, TR PCRT0M[AR] TR, PC 0RT1PC PC + 1, IEN 0R 0, SC 0RT2D7IIExecuteI/OInstructionExecuteRRInstructionAR



    Memory-Reference AND





    RT0: RT1:RT2:



    D0T4:D0T5:D1T4:D1T5:D2T4:D2T5:D3T4:D4T4:D5T4:D5T5:D6T4:D6T5:D6T6:AR PCIR M[AR], PC PC + 1D0, ..., D7 Decode IR(12 ~ 14), AR IR(0 ~ 11), I IR(15)AR M[AR]

    R 1AR 0, TR PCM[AR] TR, PC 0PC PC + 1, IEN 0, R 0, SC 0

    DR M[AR]AC AC DR, SC 0DR M[AR]AC AC + DR, E Cout, SC 0DR M[AR]AC DR, SC 0M[AR] AC, SC 0PC AR, SC 0M[AR] PC, AR AR + 1PC AR, SC 0DR M[AR]DR DR + 1M[AR] DR, if(DR=0) then (PC PC + 1), SC 0T0T1T2(IEN)(FGI + FGO):

  • Register-Reference




    D7IT3 = rIR(i) = Bi r: rB11: rB10: rB9: rB8: rB7: rB6: rB5: rB4: rB3: rB2: rB1: rB0:

    D7IT3 = p IR(i) = Bi p: pB11: pB10: pB9: pB8: pB7: pB6:

    (Common to all register-reference instr)(i = 0,1,2, ..., 11)SC 0AC 0E 0AC ACE EAC shr AC, AC(15) E, E AC(0)AC shl AC, AC(0) E, E AC(15)AC AC + 1If(AC(15) =0) then (PC PC + 1)If(AC(15) =1) then (PC PC + 1)If(AC = 0) then (PC PC + 1)If(E=0) then (PC PC + 1)S 0

    (Common to all input-output instructions)(i = 6,7,8,9,10,11)SC 0AC(0-7) INPR, FGI 0OUTR AC(0-7), FGO 0If(FGI=1) then (PC PC + 1)If(FGO=1) then (PC PC + 1)IEN 1IEN 0


  • DESIGN OF BASIC COMPUTER(BC)Hardware Components of BC A memory unit: 4096 x 16.Registers: AR, PC, DR, AC, IR, TR, OUTR, INPR, and SCFlip-Flops(Status): I, S, E, R, IEN, FGI, and FGODecoders: a 3x8 Opcode decoder a 4x16 timing decoderCommon bus: 16 bitsControl logic gates:Adder and Logic circuit: Connected to ACControl Logic Gates- Input Controls of the nine registers- Read and Write Controls of memory- Set, Clear, or Complement Controls of the flip-flops- S2, S1, S0 Controls to select a register for the bus- AC, and Adder and Logic circuit

  • CONTROL OF REGISTERS AND MEMORYScan all of the register transfer statements that change the content of AR:LD(AR) = R'T0 + R'T2 + D'7IT3CLR(AR) = RT0INR(AR) = D5T4Address Register; ARRT0: AR PC LD(AR)RT2: AR IR(0-11) LD(AR)D7IT3: AR M[AR] LD(AR)RT0: AR 0 CLR(AR)D5T4: AR AR + 1 INR(AR)Design of Basic Computer

  • CONTROL OF FLAGSpB7: IEN 1 (I/O Instruction)pB6: IEN 0 (I/O Instruction)RT2: IEN 0 (Interrupt)

    p = D7IT3 (Input/Output Instruction)IEN: Interrupt Enable FlagDesign of Basic Computer

  • CONTROL OF COMMON BUSFor ARD4T4: PC ARD5T5: PC AR x1 = D4T4 + D5T5Design of Basic Computerx1 x2 x3 x4 x5 x6 x7S2 S1 S0


    0 0 0 0 0 0 0 0 0 0 none1 0 0 0 0 0 0 0 0 1 AR0 1 0 0 0 0 0 0 1 0 PC0 0 1 0 0 0 0 0 1 1 DR0 0 0 1 0 0 0 1 0 0 AC0 0 0 0 1 0 0 1 0 1 IR0 0 0 0 0 1 0 1 1 0 TR0 0 0 0 0 0 1 1 1 1 Memory

  • DESIGN OF ACCUMULATOR LOGICCircuits associated with ACAll the statements that change the content of ACD0T5:AC AC DR AND with DRD1T5:AC AC + DR Add with DRD2T5:AC DR Transfer from DRpB11:AC(0-7) INPR Transfer from INPRrB9:AC AC ComplementrB7 :AC shr AC, AC(15) E Shift rightrB6 :AC shl AC, AC(0) E Shift leftrB11 :AC 0 ClearrB5 :AC AC + 1 Increment

  • CONTROL OF AC REGISTERGate structures for controlling the LD, INR, and CLR of AC

  • ALU (ADDER AND LOGIC CIRCUIT)One stage of Adder and Logic circuit

  • CONCLUSIONSDesigning of the instructions format Types of Computer cyclesDesign of Control Logic

  • SUMMARYComputers structure indicates its internal connectionsFunctional structure identifies functional block and relationship between these blocksPhysical structure identifies the physical modules and interconnection between them.Computer function indicates the behavior. At overall level its function is program execution.Relation between computer organization and architecture.Design of ALUDesign of bus, its interconnection and control logic


  • Microprogammed Control UnitControl Unit DesignIntroduction to PipeliningLEARNING OBJECTIVES


    Sequencing Microinstructions

    Microprogram Example

    Design of Control Unit

    Microinstruction Format

    Nanostorage and Nanoprogram

  • COMPARISON OF CONTROL UNIT IMPLEMENTATIONSControl Unit ImplementationCombinational Logic Circuits (Hard-wired)MicroprogramI RStatus F/FsControl DataCombinational

    Logic CircuitsControl

    PointsCPUMemoryTiming StateIns. Cycle StateControl Unit's StateStatus F/FsControl DataNext Address








    memory)MemoryI RC






  • TERMINOLOGYMicroprogram

    - Program stored in memory that generates all the control signals required to execute the instruction set correctly - Consists of microinstructions


    - Contains a control word and a sequencing word Control Word - All the control information required for one clock cycleSequencing Word - Information needed to decide the next microinstruction address - Vocabulary to write a microprogram

  • Cont.Control Memory(Control Storage: CS)

    - Storage in the microprogrammed control unit to store the microprogram

    Writeable Control Memory(Writeable Control Storage:WCS)

    - CS whose contents can be modified -> Allows the microprogram can be changed -> Instruction set can be changed or modified

    Dynamic Microprogramming

    - Computer system whose control unit is implemented with a microprogram in WCS - Microprogram can be changed by a systems programmer or a user

  • ContSequencer (Microprogram Sequencer) A Microprogram Control Unit that determines the Microinstruction Address to be executed in the next clock cycle

    - In-line Sequencing - Branch - Conditional Branch - Subroutine - Loop - Instruction OP-code mapping


  • MICROINSTRUCTION SEQUENCINGSequencing Capabilities Required in a Control Storage- Incrementing of the control address register- Unconditional and conditional branches- A mapping process from the bits of the machine instruction to an address for control memory- A facility for subroutine call and return

  • CONDITIONAL BRANCHUnconditional Branch Fixing the value of one status bit at the input of the multiplexer to 1SequencingConditional Branch

    If Condition is true, then Branch (address from the next address field of the current microinstruction) else Fall Through Conditions to Test: O(overflow), N(negative), Z(zero), C(carry), etc.Control address registerControl memoryMUXLoad addressIncrementStatus(condition)bitsMicro-operationsCondition selectNext address...

  • MAPPING OF INSTRUCTIONSSequencingADD RoutineAND RoutineLDA RoutineSTA RoutineBUN RoutineControlStorage00000001001000110100OP-codes of Instructions ADD AND LDA STA BUN00000001001000110100...Direct MappingAddress10 0000 010

    10 0001 01010 0010 01010 0011 01010 0100 010MappingBits10 xxxx 010ADD Routine

    AddressAND RoutineLDA RoutineSTA RoutineBUN Routine

  • MAPPING OF INSTRUCTIONS TO MICROROUTINESMapping function implemented by ROM or PLAOP-codeMapping memory

    (ROM or PLA)Control address registerControl Memory Mapping from the OP-code of an instruction to the address of the Microinstruction which is the starting microinstruction of its execution microprogram1 0 1 1 Address OP-codeMapping bits Microinstruction address 0 x x x x 0 0

    0 1 0 1 1 0 0 MachineInstruction

  • MICROPROGRAM EXAMPLEMicroprogram Computer ConfigurationMUXAR100PC100AddressMemory

    2048 x 16MUXDR150Arithmeticlogic andshift unit

    AC150SBR60CAR60Control memory

    128 x 20Control unit

  • MACHINE INSTRUCTION FORMATMicroinstruction FormatEA is the effective addressSymbol OP-code DescriptionADD 0000AC AC + M[EA]BRANCH 0001 if (AC < 0) then (PC EA)STORE 0010M[EA] ACEXCHANGE 0011AC M[EA], M[EA] AC

    Machine instruction formatIOpcode15141110Address0Sample machine instructionsF1F2F3CDBRAD333227F1, F2, F3: Microoperation fields

    CD: Condition for branching

    BR: Branch field

    AD: Address field



  • SYMBOLIC MICROINSTRUCTIONS Symbols are used in microinstructions as in assembly language A symbolic microprogram can be translated into its binary equivalent by a microprogram assembler.Sample Format five fields: label; micro-ops; CD; BR; AD

    Label: may be empty or may specify a symbolic address terminated with a colon Micro-ops: consists of one, two, or three symbols separated by commas

    CD: one of {U, I, S, Z}, whereU: Unconditional Branch I: Indirect address bit S: Sign of AC Z: Zero value in AC

    BR: one of {JMP, CALL, RET, MAP} AD: one of {Symbolic address, NEXT, empty}Microprogram

  • SYMBOLIC MICROPROGRAM - FETCH ROUTINE -AR PCDR M[AR], PC PC + 1AR DR(0-10), CAR(2-5) DR(11-14), CAR(0,1,6) 0Symbolic microprogram for the fetch cycle:ORG 64PCTAR U JMP NEXT READ, INCPC U JMP NEXT DRTAR U MAP

    FETCH:Binary equivalents translated by an assembler1000000 110 000 000 00 00 10000011000001 000 100 101 00 00 10000101000010 101 000 000 00 11 0000000Binaryaddress F1 F2 F3 CD BR ADDuring FETCH, Read an instruction from memoryand decode the instruction and update PCSequence of microoperations in the fetch cycle:

  • SYMBOLIC MICROPROGRAM Control Storage: 128 20-bit words The first 64 words: Routines for the 16 machine instructions The last 64 words: Used for other purpose (e.g., fetch routine and other subroutines) Mapping: OP-code XXXX into 0XXXX00, the first address for the 16 routines are 0(0 0000 00), 4(0 0001 00), 8, 12, 16, 20, ..., 60ORG 0NOPREADADD






    SU IU





















    INDRCT:Label Microops CD BR ADPartial Symbolic Microprogram

  • This microprogram can be implemented using ROM Microprogram Address Binary MicroinstructionMicro Routine Decimal Binary F1 F2 F3 CD BR ADADD0 0000000000000 000 01 01 1000011 1 0000001 000 100 000 00 00 0000010 2 0000010 001 000 000 00 00 1000000 3 0000011 000 000 000 00 00 1000000 BRANCH 4 0000100 000 000 000 10 00 0000110 5 0000101 000 000 000 00 00 1000000 6 0000110 000 000 000 01 01 1000011 7 0000111 000 000 110 00 00 1000000 STORE 8 0001000 000 000 000 01 01 1000011 9 0001001 000 101 000 00 00 0001010 10 0001010 111 000 000 00 00 1000000 11 0001011 000 000 000 00 00 1000000 EXCHANGE 12 0001100 000 000 000 01 01 1000011 13 0001101 001 000 000 00 00 0001110 14 0001110 100 101 000 00 00 0001111 15 0001111 111 000 000 00 00 1000000

    FETCH 64 1000000 110 000 000 00 00 1000001 65 1000001 000 100 101 00 00 1000010 66 1000010 101 000 000 00 11 0000000INDRCT 67 1000011 000 100 000 00 00 1000100 68 1000100 101 000 000 00 10 0000000 BINARY MICROPROGRAM

  • DESIGN OF CONTROL UNIT - DECODING ALU CONTROL INFORMATION - microoperation fields3 x 8 decoder76543210F13 x 8 decoder76543210F23 x 8 decoder76543210F3Arithmetic

    logic and

    shift unitANDADDDRTACACLoadFrom




  • MICROPROGRAM SEQUENCER - NEXT MICROINSTRUCTION ADDRESS LOGIC -Subroutine CALL MUX-1 selects an address from one of four sources and routes it into a CAR

    - In-Line Sequencing CAR + 1 - Branch, Subroutine Call CS(AD) - Return from Subroutine Output of SBR - New Machine instruction MAP3210SS10MUX1External

    (MAP)SBRLIncrementerCARClockAddress source selectionIn-LineRETURN form SubroutineBranch, CALL AddressControl StorageS1S0 Address Source 00 CAR + 1, In-Line 01 SBR RETURN 10 CS(AD), Branch or CALL 11 MAP


    logicI0I1TMUX2Select1ISZTestCD Field of CSFrom CPUBR fieldof CSL(load SBR with PC) for subroutine CallS0S1for next addressselection I0I1T Meaning Source of Address S1S0 L

    000 In-Line CAR+1 00 0 001 JMP CS(AD) 10 0 010 In-Line CAR+1 00 0 011 CALL CS(AD) and SBR



    logicI0TMUX2Select1ISZTestClockControl memoryMicroopsCDBRADLI1S0. . .. . .

  • MICROINSTRUCTION FORMATInformation in a Microinstruction - Control Information - Sequencing Information - Constant Information which is useful when feeding into the system

    These information needs to be organized in some way for - Efficient use of the microinstruction bits - Fast decoding

    Field Encoding

    - Encoding the microinstruction bits - Encoding slows down the execution speed due to the decoding delay - Encoding also reduces the flexibility due to the decoding hardware

  • HORIZONTAL AND VERTICAL MICROINSTRUCTION FORMATHorizontal Microinstructions Each bit directly controls each micro-operation or each control point Horizontal implies a long microinstruction word Advantages: Can control a variety of components operating in parallel. --> Advantage of efficient hardware utilization Disadvantages: Control word bits are not fully utilized --> CS becomes large --> CostlyVertical Microinstructions A microinstruction format that is not horizontal Vertical implies a short microinstruction word Encoded Microinstruction fields --> Needs decoding circuits for one or two levels of decoding One-level decodingField A

    2 bits2 x 4

    Decoder3 x 8

    DecoderField B

    3 bits1 of 41 of 8Two-level decodingField A

    2 bits2 x 4

    Decoder6 x 64

    DecoderField B

    6 bitsDecoder and

    selection logic

  • NANOSTORAGE AND NANOINSTRUCTIONThe decoder circuits in a vertical microprogram storage organization can be replaced by a ROM=> Two levels of control storage First level - Control Storage Second level - Nano Storage

    Two-level microprogram

    First level -Vertical format Microprogram Second level -Horizontal format Nanoprogram - Interprets the microinstruction fields, thus converts a vertical microinstruction format into a horizontal nanoinstruction format.

    Usually, the microprogram consists of a large number of short microinstructions, while the nanoprogram contains fewer words with longer nanoinstructions.

    Control Storage Hierarchy

  • TWO-LEVEL MICROPROGRAMMING EXAMPLE* Microprogram: 2048 microinstructions of 200 bits each* With 1-Level Control Storage: 2048 x 200 = 409,600 bits* Assumption: 256 distinct microinstructions among 2048* With 2-Level Control Storage: Nano Storage: 256 x 200 bits to store 256 distinct nanoinstructions Control storage: 2048 x 8 bits To address 256 nano storage locations 8 bits are needed* Total 1-Level control storage: 409,600 bits Total 2-Level control storage: 67,584 bits (256 x 200 + 2048 x 8)Control Storage Hierarchy Control address register11 bitsControl memory

    2048 x 8Microinstruction (8 bits)

    Nanomemory addressNanomemory

    256 x 200Nanoinstructions (200 bits)

  • CONCLUSIONSMicro programmed control organizationAddress SequencingMapping of instruction Design of micro instructionsSymbolic/Binary Micro programDesign of control unit


    General Register Organization

    Stack Organization

    Instruction Formats

    Addressing Modes

    Data Transfer and Manipulation

    Program Control

    Reduced Instruction Set Computer

  • MAJOR COMPONENTS OF CPUIntroduction Storage Components Registers Flags

    Execution (Processing) Components Arithmetic Logic Unit(ALU) Arithmetic calculations, Logical computations, Shifts/Rotates

    Transfer Components Bus

    Control Components Control Unit

  • REGISTERSIn Basic Computer, there is only one general purpose register, the Accumulator (AC)In modern CPUs, there are many general purpose registersIt is advantageous to have many registersTransfer between registers within the processor are relatively fastGoing off the processor to access memory is much slower

    How many registers will be the best ?


  • OPERATION OF CONTROL UNITThe control unit Directs the information flow through ALU by - Selecting various Components in the system - Selecting the Function of ALUExample: R1 R2 + R3[1] MUX A selector (SELA): BUS A R2[2] MUX B selector (SELB): BUS B R3[3] ALU operation selector (OPR): ALU to ADD[4] Decoder destination selector (SELD): R1 Out BusControl WordEncoding of register selection fieldsBinaryCodeSELASELBSELD000InputInputNone001 R1 R1 R1010 R2 R2 R2011 R3 R3 R3100 R4 R4 R4101 R5 R5 R5110 R6 R6 R6 R7 R7 R7

  • ALU CONTROLEncoding of ALU operations OPRSelect OperationSymbol

    00000 TransferATSFA00001 Increment AINCA00010 ADD A + BADD00101 Subtract A - BSUB00110 Decrement ADECA01000 AND A and BAND01010 OR A and BOR01100 XOR A and BXOR01110 Complement ACOMA10000 Shift right ASHRA11000 Shift left ASHLAControl

  • ALU CONTROLExamples of ALU Microoperations Symbolic DesignationMicrooperation SELASELBSELDOPR Control WordControl

    R1 R2 R3 R2 R3 R1 SUB 010 011 001 00101R4 R4 R5 R4 R5 R4 OR 100 101 100 01010R6 R6 + 1R6- R6 INCA 110 000 110 00001R7 R1 R1- R7 TSFA 001 000 111 00000Output R2 R2- None TSFA 010 000 000 00000Output Input Input- None TSFA 000 000 000 00000R4 shl R4R4- R4 SHLA 100 000 100 11000R5 0 R5R5 R5 XOR 101 101 101 01100

  • REGISTER STACK ORGANIZATION Register StackPush, Pop operations/* Initially, SP = 0, EMPTY = 1, FULL = 0 */PUSHPOPStack OrganizationSP SP + 1 DR M[SP]M[SP] DR SP SP 1If (SP = 0) then (FULL 1) If (SP = 0) then (EMPTY 1)EMPTY 0 FULL 0Stack - Very useful feature for nested subroutines, nested interrupt services - Also efficient for arithmetic expression evaluation - Storage which can be accessed in LIFO - Pointer: SP - Only PUSH and POP operations are applicableABC0123463AddressFULLEMPTYSPDRFlagsStack pointerstack6 bits

  • MEMORY STACK ORGANIZATION - A portion of memory is used as a stack with a processor register as a stack pointer

    - PUSH:SP SP - 1 M[SP] DR - POP:DR M[SP] SP SP + 1

    Memory with Program, Data, and Stack Segments400140003999399839973000Data


    (instructions)1000PCARSPstackStack growsIn this direction

    - Most computers do not provide hardware to check stack overflow (full stack) or underflow (empty stack) must be done in software

  • REVERSE POLISH NOTATIONA + BInfix notation+ A BPrefix or Polish notationA B +Postfix or reverse Polish notation - The reverse Polish notation is very suitable for stack manipulation

    Evaluation of Arithmetic Expressions Any arithmetic expression can be expressed in parenthesis-free Polish notation, including reverse Polish notation(3 * 4) + (5 * 6) 3 4 * 5 6 * +Stack Organization Arithmetic Expressions: A + B33121212124245563034*56*+

  • PROCESSOR ORGANIZATIONIn general, most processors are organized in one of 3 waysSingle register (Accumulator) organizationBasic Computer is a good exampleAccumulator is the only general purpose registerGeneral register organizationUsed by most modern computer processorsAny of the registers can be used as the source or destination for computer operationsStack organizationAll operations are done using the hardware stackFor example, an OR instruction will pop the two top elements from the stack, do a logical OR on them, and push the result on the stack

  • INSTRUCTION FORMATOP-code field - specifies the operation to be performedAddress field - designates memory address(es) or a processor register(s)Mode field - determines how the address field is to be interpreted (to get effective address or the operand) The number of address fields in the instruction format depends on the internal organization of CPU

    The three most common CPU organizations:Single accumulator organization:ADDX /* AC AC + M[X] */General register organization:ADDR1, R2, R3 /* R1 R2 + R3 */ ADDR1, R2 /* R1 R1 + R2 */MOVR1, R2 /* R1 R2 */ ADDR1, X /* R1 R1 + M[X] */Stack organization:PUSHX /* TOS M[X] */ ADD Instruction Fields

  • Three-Address Instructions

    Program to evaluate X = (A + B) * (C + D) :ADDR1, A, B /* R1 M[A] + M[B]*/ ADDR2, C, D /* R2 M[C] + M[D]*/ MULX, R1, R2 /* M[X] R1 * R2*/

    - Results in short programs - Instruction becomes long (many bits)

    Two-Address Instructions

    Program to evaluate X = (A + B) * (C + D) :

    MOV R1, A /* R1 M[A] */ADD R1, B /* R1 R1 + M[A] */MOV R2, C /* R2 M[C] */ADD R2, D /* R2 R2 + M[D] */MUL R1, R2 /* R1 R1 * R2 */MOV X, R1 /* M[X] R1 */


  • ONE AND ZERO-ADDRESS INSTRUCTIONS One-Address Instructions- Use an implied AC register for all data manipulation- Program to evaluate X = (A + B) * (C + D) :Instruction Format LOAD A /* AC M[A] */ADD B /* AC AC + M[B] */STORE T /* M[T] AC */LOAD C /* AC M[C] */ADD D /* AC AC + M[D]*/MUL T /* AC AC * M[T]*/STORE X /* M[X] AC */ Zero-Address Instructions- Can be found in a stack-organized computer- Program to evaluate X = (A + B) * (C + D) :PUSHA/* TOS A*/PUSHB/* TOS B*/ADD/* TOS (A + B)*/PUSHC/* TOS C*/PUSHD/* TOS D*/ADD/* TOS (C + D)*/MUL/* TOS (C + D) * (A + B) */ POPX/* M[X] TOS*/

  • ADDRESSING MODES Addressing Modes

    * Specifies a rule for interpreting or modifying the address field of the instruction (before the operand is actually referenced) * Variety of addressing modes

    - to give programming flexibility to the user - to use the bits in the address field of the instruction efficiently

  • TYPES OF ADDRESSING MODES Implied ModeAddress of the operands are specified implicitly in the definition of the instruction - No need to specify address in the instruction - EA = AC, or EA = Stack [SP] - Examples from Basic ComputerCLA, CME, INP

    Immediate Mode Instead of specifying the address of the operand, operand itself is specified - No need to specify address in the instruction - However, operand itself needs to be specified - Sometimes, require more bits than the address - Fast to acquire an operand

  • TYPES OF ADDRESSING MODES Register Mode Address specified in the instruction is the register address - Designated operand need to be in a register - Shorter address than the memory address - Saving address field in the instruction - Faster to acquire an operand than the memory addressing - EA = IR(R) (IR(R): Register field of IR)

    Register Indirect ModeInstruction specifies a register which contains the memory address of the operand - Saving instruction bits since register address is shorter than the memory address - Slower to acquire an operand than both the register addressing or memory addressing - EA = [IR(R)] ([x]: Content of x)

    Autoincrement or Autodecrement Mode - When the address in the register is used to access memory, the value in the register is incremented or decremented by 1 automatically

  • TYPES OF ADDRESSING MODES Direct Address Mode Instruction specifies the memory address which can be used directly to access the memory - Faster than the other memory addressing modes - Too many bits are needed to specify the address for a large physical memory space - EA = IR(addr) (IR(addr): address field of IR)

    Indirect Addressing ModeThe address field of an instruction specifies the address of a memory location that contains the address of the operand - When the abbreviated address is used large physical memory can be addressed with a relatively small number of bits - Slow to acquire an operand because of an additional memory access - EA = M[IR(address)]


    Relative Addressing Modes The Address fields of an instruction specifies the part of the address (abbreviated address) which can be used along with a designated register to calculate the address of the operand - Address field of the instruction is short - Large physical memory can be accessed with a small number of address bits - EA = f(IR(address), R), R is sometimes implied 3 different Relative Addressing Modes depending on R; * PC Relative Addressing Mode (R = PC) - EA = PC + IR(address) * Indexed Addressing Mode (R = IX, where IX: Index Register) - EA = IX + IR(address) * Base Register Addressing Mode(R = BAR, where BAR: Base Address Register) - EA = BAR + IR(address)

  • ADDRESSING MODES - EXAMPLES -AddressingModeEffectiveAddressContentof ACDirect address500/* AC (500) */ 800Immediate operand -/* AC 500 */ 500Indirect address800/* AC ((500)) */ 300Relative address702/* AC (PC+500) */ 325Indexed address600/* AC (RX+500) */ 900Register -/* AC R1 */ 400Register indirect400 /* AC (R1) */ 700Autoincrement400 /* AC (R1)+ */ 700Autodecrement399 /* AC -(R) */ 450

    Load to AC ModeAddress = 500Next instruction200201202399400450700500800600900702325800300MemoryAddressPC = 200R1 = 400XR = 100AC

  • DATA TRANSFER INSTRUCTIONSLoad LDStore STMove MOVExchange XCHInput INOutput OUTPush PUSHPop POPName Mnemonic Typical Data Transfer InstructionsDirect addressLD ADRAC M[ADR]Indirect addressLD @ADRAC M[M[ADR]]Relative addressLD $ADRAC M[PC + ADR]Immediate operandLD #NBRAC NBRIndex addressingLD ADR(X)AC M[ADR + XR]RegisterLD R1AC R1Register indirectLD (R1)AC M[R1]AutoincrementLD (R1)+AC M[R1], R1 R1 + 1Autodecrement LD -(R1) R1 R1 - 1, AC M[R1]ModeAssemblyConventionRegister Transfer Data Transfer Instructions with Different Addressing Modes

  • DATA MANIPULATION INSTRUCTIONS Three Basic Types:Arithmetic instructionsLogical and bit manipulation instructionsShift instructions Arithmetic InstructionsName MnemonicClearCLRComplementCOMANDANDORORExclusive-ORXORClear carryCLRCSet carrySETCComplement carryCOMCEnable interruptEIDisable interruptDIName MnemonicLogical shift rightSHRLogical shift leftSHLArithmetic shift rightSHRAArithmetic shift leftSHLARotate rightRORRotate leftROLRotate right thru carryRORCRotate left thru carryROLCName Mnemonic Logical and Bit Manipulation Instructions Shift InstructionsIncrement INCDecrement DECAdd ADDSubtract SUBMultiply MULDivide DIVAdd with Carry ADDCSubtract with Borrow SUBBNegate(2s Complement) NEG

  • FLAG, PROCESSOR STATUS WORDIn Basic Computer, the processor had several (status) flags 1 bit value that indicated various information about the processors state E, FGI, FGO, I, IEN, RIn some processors, flags like these are often combined into a register the processor status register (PSR); sometimes called a processor status word (PSW)Common flags in PSW areC (Carry): Set to 1 if the carry out of the ALU is 1S (Sign): The MSB bit of the ALUs outputZ (Zero): Set to 1 if the ALUs output is all 0sV (Overflow): Set to 1 if there is an overflowStatus Flag Circuit

  • PROGRAM CONTROL INSTRUCTIONSPC+1In-Line Sequencing (Next instruction is fetched from the next adjacent location in the memory)

    Address from other source; Current Instruction, Stack, etc; Branch, Conditional Branch, Subroutine, etc Program Control Instructions Name MnemonicBranch BRJump JMPSkip SKPCall CALLReturn RTNCompare(by ) CMPTest(by AND) TSTCMP and TST instructions do not retain their results of operations ( and AND, respectively).They only set or clear certain Flags.

  • CONDITIONAL BRANCH INSTRUCTIONSBZBranch if zeroZ = 1BNZBranch if not zeroZ = 0BCBranch if carryC = 1BNCBranch if no carryC = 0BPBranch if plusS = 0BMBranch if minusS = 1BVBranch if overflowV = 1BNVBranch if no overflowV = 0BHIBranch if higherA > BBHEBranch if higher or equalA BBLOBranch if lowerA < BBLOEBranch if lower or equalA BBEBranch if equalA = BBNEBranch if not equalA BBGTBranch if greater thanA > BBGEBranch if greater or equalA BBLTBranch if less thanA < BBLEBranch if less or equalA BBEBranch if equalA = BBNEBranch if not equalA BUnsigned compare conditions (A - B)Signed compare conditions (A - B)Mnemonic Branch condition Tested conditionProgram Control

  • SUBROUTINE CALL AND RETURNCall subroutineJump to subroutineBranch to subroutineBranch and save return address Fixed Location in the subroutine (Memory) Fixed Location in memory In a processor Register In memory stack - most efficient wayProgram Control Subroutine Call Two Most Important Operations are Implied;

    * Branch to the beginning of the Subroutine - Same as the Branch or Conditional Branch

    * Save the Return Address to get the address of the location in the Calling Program upon exit from the Subroutine

    Locations for storing Return Address CALL SP SP - 1 M[SP] PC PC EA

    RTN PC M[SP] SP SP + 1

  • PROGRAM INTERRUPT Types of InterruptsExternal interrupts External Interrupts initiated from the outside of CPU and Memory - I/O Device Data transfer request or Data transfer complete - Timing Device Timeout - Power Failure - Operator

    Internal interrupts (traps) Internal Interrupts are caused by the currently running program - Register, Stack Overflow - Divide by zero - OP-code Violation - Protection Violation

    Software Interrupts Both External and Internal Interrupts are initiated by the computer HW. Software Interrupts are initiated by the executing an instruction. - Supervisor Call Switching from a user mode to the supervisor mode Allows to execute a certain class of operationswhich are not allowed in the user modeProgram Control`

  • INTERRUPT PROCEDUREThe interrupt is usually initiated by an internal or an external signal rather than from the execution of an instruction (except for the software interrupt)The address of the interrupt service program is determined by the hardware rather than from the address field of an instructionAn interrupt procedure usually stores all the information necessary to define the state of CPU rather than storing only the PC.The state of the CPU is determined from; Content of the PCContent of all processor registersContent of status bitsMany ways of saving the CPU state depending on the CPU architectures

    Program ControlInterrupt Procedure and Subroutine Call

  • RISC: HISTORICAL BACKGROUNDIBM System/360, 1964The real beginning of modern computer architectureDistinction between Architecture and ImplementationArchitecture: The abstract structure of a computer seen by an assembly-language programmer

    Continuing growth in semiconductor memory and microprogramming A much richer and complicated instruction setsCISC(Complex Instruction Set Computer)

  • ARGUMENTS ADVANCED AT THAT TIMERicher instruction sets would simplify compilersRicher instruction sets would alleviate the software crisis move as much functions to the hardware as possibleRicher instruction sets would improve architecture quality

  • ARCHITECTURE DESIGN PRINCIPLES - IN 70s -RISC Large microprograms would add little or nothing to the cost of the machine Rapid growth of memory technology Large General Purpose Instruction Set

    Microprogram is much faster than the machine instructions Microprogram memory is much faster than main memory Moving the software functions into microprogram for the high performance machines

    Execution speed is proportional to the program size Architectural techniques that led to small program High performance instruction set

    Number of registers in CPU has limitations Very costly Difficult to utilize them efficiently

  • COMPARISONS OF EXECUTION MODELSA B + C Data: 32-bit RISCLoadrBBLoadrCCAddrAStorerAArBrCLoadBAddCStoreAAddBCA Register-to-register Memory-to-register Memory-to-memoryI = 104b; D = 96b; M = 200bI = 72b; D = 96b; M = 168bI = 56b; D = 96b; M = 152b84168168161616

  • RISCFOUR MODERN ARCHITECTURES IN 70sYear# of instrs.Control mem. sizeInstr. size (bits)TechnologyExecution modelCache size1973208420 Kb16-48ECL MSIreg-mem


    reg-reg64 Kb1978303480 Kb16-456TTL MSIreg-mem


    reg-reg64 Kb1978270136 Kb8-24ECL MSIstack64 Kb1982222420 Kb6-321NMOS VLSIstack


    64 KbIBM 370/168VAX-11/780DoradoiAPX-432DECXeroxIntel

  • COMPLEX INSTRUCTION SET COMPUTER These computers with many instructions and addressing modes came to be known as Complex Instruction Set Computers (CISC)

    One goal for CISC machines was to have a machine language instruction to match each high-level language statement type

  • VARIABLE LENGTH INSTRUCTIONS The large number of instructions and addressing modes led CISC machines to have variable length instruction formatsThe large number of instructions means a greater number of bits to specify themIn order to manage this large number of opcodes efficiently, they were encoded with different lengths:More frequently used instructions were encoded using short opcodes.Less frequently used ones were assigned longer opcodes.Also, multiple operand instructions could specify different addressing modes for each operandFor example, Operand 1 could be a directly addressed register,Operand 2 could be an indirectly addressed memory location,Operand 3 (the destination) could be an indirectly addressed register.All of this led to the need to have different length instructions in different situations, depending on the opcode and operands used

  • For example, an instruction that only specifies register operands may only be two bytes in lengthOne byte to specify the instruction and addressing modeOne byte to specify the source and destination registers.

    An instruction that specifies memory addresses for operands may need five bytesOne byte to specify the instruction and addressing modeTwo bytes to specify each memory addressMaybe more if theres a large amount of memory.

    Variable length instructions greatly complicate the fetch and decode problem for a processor The circuitry to recognize the various instructions and to properly fetch the required number of bytes for operands is very complex


  • COMPLEX INSTRUCTION SET COMPUTER Another characteristic of CISC computers is that they have instructions that act directly on memory addressesFor example, ADD L1, L2, L3 that takes the contents of M[L1] adds it to the contents of M[L2] and stores the result in location M[L3]An instruction like this takes three memory access cycles to executeThat makes for a potentially very long instruction execution cycle

    The problems with CISC computers are The complexity of the design may slow down the processor,The complexity of the design may result in costly errors in the processor design and implementation,Many of the instructions and addressing modes are used rarely, if ever

  • SUMMARY: CRITICISMS ON CISCHigh Performance General Purpose Instructions

    - Complex Instruction Format, Length, Addressing Modes Complicated instruction cycle control due to the complex decoding HW and decoding process

    - Multiple memory cycle instructions Operations on memory data Multiple memory accesses/instruction

    - Microprogrammed control is necessity Microprogram control storage takes substantial portion of CPU chip area Semantic Gap is large between machine instruction and microinstruction

    - General purpose instruction set includes all the features required by individually different applications When any one application is running, all the features required by the other applications are extra burden to the application

  • In the late 70s and early 80s there was a reaction to the shortcomings of the CISC style of processorsReduced Instruction Set Computers (RISC) were proposed as an alternativeThe underlying idea behind RISC processors is to simplify the instruction set and reduce instruction execution time

    RISC processors often feature: Few instructionsFew addressing modesOnly load and store instructions access memoryAll other operations are done using on-processor registersFixed length instructionsSingle cycle execution of instructionsThe control unit is hardwired, not microprogrammed.REDUCED INSTRUCTION SET COMPUTERS

  • Since all but the load and store instructions use only registers for operands, only a few addressing modes are neededBy having all instructions the same length, reading them in is easy and fastThe fetch and decode stages are simple, looking much more like Manos Basic Computer than a CISC machineThe instruction and address formats are designed to be easy to decodeUnlike the variable length CISC instructions, the opcode and register fields of RISC instructions can be decoded simultaneouslyThe control logic of a RISC processor is designed to be simple and fastThe control logic is simple because of the small number of instructions and the simple addressing modesThe control logic is hardwired, rather than microprogrammed, because hardwired control is faster


  • ARCHITECTURAL METRICA B + CB A + CD D - B RISC Register-to-register (Reuse of operands) Register-to-register (Compiler allocates operands in registers) Memory-to-memoryI = 228b D = 192b M = 420bI = 60b D = 0b M = 60bI = 168b D = 288b M = 456bLoadrBBLoadrCCAddrAStorerAArBrC8416AddrBrArCStorerBBLoadrDDSubrDrDrBStorerDDAddrArBrCAddrBrArCSubrDrDrB8444AddBCA8161616AddACBSubBDD

  • CHARACTERISTICS OF INITIAL RISC MACHINES IBM 801 RISC I MIPSYear 1980 1982 1983Number of instructions 120 39 55Control memory size 0 0 0Instruction size (bits) 32 32 32Technology ECL MSI NMOS VLSI NMOS VLSIExecution model reg-reg reg-reg reg-reg


  • REGISTERS By simplifying the instructions and addressing modes, there is space available on the chip or board of a RISC CPU for more circuits than with a CISC processorThis extra capacity is used toPipeline instruction execution to speed up instruction executionAdd a large number of registers to the CPU

  • PIPELINING A very important feature of many RISC processors is the ability to execute an instruction each clock cycleThis may seem nonsensical, since it takes at least once clock cycle each to fetch, decode and execute an instruction. It is however possible, because of a technique known as pipeliningWell study this in detail laterPipelining is the use of the processor to work on different phases of multiple instructions in parallel

  • For instance, at one time, a pipelined processor may beExecuting instruction itDecoding instruction it+1Fetching instruction it+2 from memory So, if were running three instructions at once, and it takes an average instruction three cycles to run, the CPU is executing an average of an instruction a clock cycle

    As well see when we cover it in depth, there are complicationsFor example, what happens to the pipeline when the processor branches However, pipelined execution is an integral part of all modern processors, and plays an important roleCont

  • REGISTERS By having a large number of general purpose registers, a processor can minimize the number of times it needs to access memory to load or store a valueThis results in a significant speed up, since memory accesses are much slower than register accessesRegister accesses are fast, since they just use the bus on the CPU itself, and any transfer can be done in one clock cycleTo go off-processor to memory requires using the much slower memory (or system) busIt may take many clock cycles to read or write to memory across the memory busThe memory bus hardware is usually slower than the processorThere may even be competition for access to the memory bus by other devices in the computer (e.g. disk drives)So, for this reason alone, a RISC processor may have an advantage over a comparable CISC processor, since it only needs to access memory for its instructions, and occasionally to load or store a memory value


    The procedure (function) call/return is the most time-consuming operations in typical HLL programsPascalCPascalCPascalCDynamicOccurrenceMachine-InstructionWeightedMemoryReferenceWeightedASSIGN 45 38 13 13 14 15LOOP 5 3 42 32 33 26CALL 15 12 31 33 44 45IF 29 43 11 21 7 13GOTO 3Other 6 1 3 1 2 1

  • RISCCALL-RETURN BEHAVIOR Call-return behavior as a function of nesting depth and time

  • ObservationsWeighted Dynamic Frequency of HLL Operations Procedure call/return is the most time consuming operationsLocality of Procedure Nesting The depth of procedure activation fluctuates within a relatively narrow rangeA typical procedure employs only a few passed parameters and local variables SolutionUse multiple small sets of registers (windows), each assigned to a different procedureA procedure call automatically switches the CPU to use a different window of registers, rather than saving registers in memoryWindows for adjacent procedures are overlapped to allow parameter passingRISCREGISTER WINDOW APPROACH

  • OVERLAPPED REGISTER WINDOWSRISCR15R10R15R10R25R16Common to D and ALocal to DCommon to C and DLocal to CCommon to B and CLocal to BCommon to A and BLocal to ACommon to A and DProc DProc CProc BProc AR9R0Common to all



  • OVERLAPPED REGISTER WINDOWS There are three classes of registers:Global RegistersAvailable to all functionsWindow local registersVariables local to the functionWindow shared registersPermit data to be shared without actually needing to copy itOnly one register window is active at a timeThe active register window is indicated by a pointerWhen a function is called, a new register window is activatedThis is done by incrementing the pointerWhen a function calls a new function, the high numbered registers of the calling function window are shared with the called function as the low numbered registers in its register windowThis way the callers high and the called functions low registers overlap and can be used to pass parameters and results

  • In addition to the overlapped register windows, the processor has some number of registers, G, that are global registersThis is, all functions can access the global registers.The advantage of overlapped register windows is that the processor does not have to push registers on a stack to save values and to pass parameters when there is a function callConversely, pop the stack on a function returnThis saves Accesses to memory to access the stack.The cost of copying the register contents at allAnd, since function calls and returns are so common, this results in a significant savings relative to a stack-based approachCont

  • BERKELEY RISC I- 32-bit integrated circuit CPU- 32-bit address, 8-, 16-, 32-bit data- 32-bit instruction format- total 31 instructions- three addressing modes: register; immediate; PC relative addressing- 138 registers 10 global registers 8 windows of 32 registers eachBerkeley RISC I Instruction FormatsRISCOpcodeRsRd0Not usedS23124 2319 1814 1312540855185OpcodeRsRd1S23124 2319 1814 13120855113OpcodeCONDY3124 2319 1808519Regsiter mode: (S2 specifies a register)Register-immediate mode (S2 specifies an operand)PC relative mode

  • Register 0 was hard-wired to a value of 0.There are eight memory access instructionsFive load-from-memory instructionsThree store-to-memory instructions.

    The load instructions: LDLload long LDSUload short unsigned LDSSload short signed LDBUload byte unsigned LDBSload byte signedWhere long is 32 bits, short is 16 bits and a byte is 8 bitsThe store instructions: STLstore long STSstore short STBstore byteCont

  • LDLRd M[(Rs) + S2]load long LDSURd M[(Rs) + S2]load short unsigned LDSSRd M[(Rs) + S2]load short signed LDBURd M[(Rs) + S2]load byte unsigned LDBSRd M[(Rs) + S2]load byte signed STLM[(Rs) + S2] Rd store long STSM[(Rs) + S2] Rd store short STBM[(Rs) + S2] Rd store byteHere the difference between the lengths is A long is simply loaded, since it is the same size as the register (32 bits).A short or a byte can be loaded into a register Unsigned - in which case the upper bits of the register are loaded with 0s.Signed - in which case the upper bits of the register are loaded with the sign bit of the short/byte loaded.Cont

  • INSTRUCTION SET OF BERKELEY RISC IData manipulation instructionsADD Rs,S2,RdRd Rs + S2Integer addADDC Rs,S2,RdRd Rs + S2 + carryAdd with carrySUB Rs,S2,RdRd Rs - S2Integer subtractSUBC Rs,S2,RdRd Rs - S2 - carrySubtract with carrySUBR Rs,S2,RdRd S2 - RsSubtract reverseSUBCR Rs,S2,RdRd S2 - Rs - carrySubtract with carryAND Rs,S2,RdRd Rs S2ANDOR Rs,S2,RdRd Rs S2ORXOR Rs,S2,RdRd Rs S2Exclusive-ORSLL Rs,S2,RdRd Rs shifted by S2Shift-leftSRL Rs,S2,RdRd Rs shifted by S2Shift-right logicalSRA Rs,S2,RdRd Rs shifted by S2Shift-right arithmetic

    Opcode Operands Register Transfer Description

  • Data transfer instructionsLDL (Rs)S2,RdRd M[Rs + S2]Load longLDSU (Rs)S2,RdRd M[Rs + S2]Load short unsignedLDSS (Rs)S2,RdRd M[Rs + S2]Load short signedLDBU (Rs)S2,RdRd M[Rs + S2]Load byte unsignedLDBS (Rs)S2,RdRd M[Rs + S2]Load byte signedLDHI Rd, YRd YLoad immediate highSTL Rd,(Rs)S2M[Rs + S2] RdStore longSTS Rd,(Rs)S2M[Rs + S2] RdStore shortSTB Rd,(Rs)S2M[Rs + S2] RdStore byteGETPSWRdRd PSWLoad status wordPUTPSWRdPSW RdSet status wordRISC Opcode Operands Register Transfer DescriptionCont

  • Program control instructionsJMP COND,S2(Rs)PC Rs + S2Conditional jumpJMPR COND,YPC PC + YJump relativeCALL Rd,S2(Rs)Rd PC, PC Rs + S2Call subroutine& CWP CWP - 1 Change windowCALLR Rd,YRd PC, PC PC + YCall relative and CWP CWP - 1 change windowRET Rd,S2PC Rd + S2 Return and CWP CWP + 1 change windowCALLINT RdRd PC,CWP CWP - 1 Call an interrupt pr.RETINT Rd,S2PC Rd + S2Return from CWP CWP + 1 interrupt pr.GTLPC RdRd PCGet last PCINSTRUCTION SET OF BERKELEY RISC I Opcode Operands Register Transfer Description

  • CHARACTERISTICS OF RISC RISC Characteristics Advantages of RISC- VLSI Realization- Computing Speed- Design Costs and Reliability- High Level Language SupportRISC- Relatively few instructions- Relatively few addressing modes- Memory access limited to load and store instructions- All operations done within the registers of the CPU- Fixed-length, easily decoded instruction format- Single-cycle instruction format- Hardwired rather than microprogrammed control

  • ADVANTAGES OF RISC Computing Speed- Simpler, smaller control unit faster- Simpler instruction set; addressing modes; instruction format faster decoding- Register operation faster than memory operation- Register window enhances the overall speed of execution- Identical instruction length, One cycle instruction execution suitable for pipelining fasterRISC VLSI RealizationControl area is considerably reduced

    Example:RISC I: 6%RISC II: 10%MC68020: 68%general CISCs: ~50% RISC chips allow a large number of registers on the chip - Enhancement of performance and HLL support - Higher regularization factor and lower VLSI design costThe GaAs VLSI chip realization is possible

  • ADVANTAGES OF RISC Design Costs and Reliability- Shorter time to design reduction in the overall design cost and reduces the problem that the end product will be obsolete by the time the design is completed

    - Simpler, smaller control unit higher reliability

    - Simple instruction format (of fixed length) ease of virtual memory management High Level Language Support- A single choice of instruction shorter, simpler compiler

    - A large number of CPU registers more efficient code

    - Register window Direct support of HLL

    - Reduced burden on compiler writerRISC

  • CONCLUSIONSCPU OrganizationsAddressing ModesAddress InstructionsClassification of computer instructionsRISC/CISC

  • OBJECTIVE QUESTIONSA CPUs microinstruction format has five separate control fields. The number of micro operations in each fields are as follows F1=4, F2 = 4, F3 = 3, F4 = 12, F5 = 21What is the total length of microinstrcution needed to accommodate the five control fieldsIf pure horizontal microprogramming is followed without encoding, what will be the length of microinstruction? Pick out the incorrect RTL statement and indicate the problemsPC:= MAR, PC:= PC+12. MR:=1, Pc:=PC+1NOOP instruction requires nothing (no action) to be performed for the instruction. This is true for macro operation level but false for the microoperation level. The control unit must perform one microoperation which is necessary for any instruction. Identify the essential micro operation which is performed for NOOP instruction.Is nano and micro programming same?The address of stack is stored in _____________In ___________________addressing mode the content of PC is added to address part of the instruction in order to obtain the effective address

  • 7. Control word specifies ________________Memory unit that stores the control word is ___________________ is program which convert symbolic language into machine code.________ is also called nexr address generator.The instructions which copy information from one location to another either in the processors internal register set or in the external main memory are called a. Data transfer instructions. b. Program control instructions.c. Input-output instructions.d.Logical instructions.12. If the value V(x) of the target operand is contained in the address field itself, the addressing mode isa.immediate.b. direct.c.indirect.d.implied.13. A microprogram sequencera.generates the address of next micro instruction to be executed.b.generates the control signals to execute a microinstruction.csequentially averages all microinstructions in the control memory.d.enables the efficient handling of a micro program subroutine.Cont

  • During what CPU cycle is an instruction moved from primary storage to the control unit? a. fetch b. execution c. access d. refresh What type of processor does not directly implement instructions that combine data movement and manipulation? a. CISC b. RISC c. microprocessor d. PSW When the control unit fetches an instruction from memory, it stores it in the ____. a. instruction pointer b. program status word c. op code d. instruction register Cont

  • Which of the following is a storage location that holds inputs and outputs for the ALU? a. Control unit b. ALU c. I/O device d. Register The ____ tests the bit values in the source location and places copies of those values in the destination location. a. LOAD b. MOVE c. STORE d. ADD


  • SHORT QUESTIONSThe instruction length and operand address field is 36 bits and 14 bits respectively. If two operand instructions of 240 numbers are used, then how many one operand instructions are possible?The stack based CPU dont have registers for storing the operands. Can we conclude that the stack based CPU has less hardware circuit and cheaper than register based CPU? The instruction format of a CPU is designed for the two types (a) op-code and three fields for register address; (b) op-code and one field for memory address. Identify different formats for instructions.Difference between horizontal and vertical instruction format.What is firmware? How it is different from software and hardware?A register based CPU can be viewed as multiple accumulators based CPU. Justify this statementA micro programmed CPU has 1K words in the control memory. Each instruction needs 8 microinstructions. Assuming that the op-code in the macro instruction is of 5 bits length, propose a mapping scheme to generate control memory address for the op-code.

  • Name some functions of control unit.What is the difference between internal and software interrupts?A computer has 32 bit instructions and 12 bit addresses. If there are 250 two address instruction, how many one address instruction can be formulated?What is the Fetch routine in Micro programmed control unitThe instructions are classified on the basis of following factorsOp-code: ______________Data:_________________,__________________, etcOperand location: __________,______________Operand addressing: ______________________Instruction length:_______,_________,_____No. of address field____________,________,_______


  • LONG QUESTIONSWrite an assembly language program to derive the expression X=(A+B)-(C+D) for an accumulator, register and stack based CPUWhat is addressing mode? Discuss different types of addressing modes with its advantages and disadvantages.A program has three jump instructions in three consecutive words (locations) in memory: 0111, 1000and 1001.The corresponding jump addresses are 1001, 0111, 0111 respectively. Suppose we load 0111.Initially in PC and start the CPU, how many times will the instruction in location be fetched and executed?A 32-bit CPU has 16-bit instruction and 12-bit memory address. Its memory is organized as 4K of 32-bits each. Each memory word stores two instructions. The instruction format has 4-bits for op-code. The CPUs instruction register can accommodate two instructions. Suggest a design strategy for the instruction cycle sequence.What is the basic difference between a branch instruction, a call subroutine instruction, and a program interrupt? Explain various types of interrupts and give examples of each.

  • A processor has following hardware configuration a. No. of registers=8b. ALU operations: arithmetic 8,logic 8c. Shifter : 4 operationsd. Bus: single busDesign the microinstruction format for this CPU7. A digital computer has a common bus system for 12 registers of 9 bits each. The bus is constructed with multiplexers.a. How many selection inputs are there in each multiplexer? b. What size of multiplexers are needed? c. How many multiplexers are there in the bus? d. Draw a diagram of the bus system using three-state buffers and a decoder instead of multiplexers? 8.The system uses a control memory of 1024 words of 32 bits each. The microinstruction has three fields for micro-operations. select a status bit and Brach address field. The micro-operation field has 16 bits.a. How many bits are there in the branch address field and select field?b. If there are 16 status bits in the system, how many bits of the branch logic are used to select a status bit?c. How many bits are left to select the input to the multiplexers?Cont..

  • Cont..9. Write micro operation for BSA and ISZ 10. A computer has following registers PC(12 bits), MAR(16), MBR(12), I(1),OPR(3), E(1), AC(16) and six timing signal t0 to t5 and one flip-flop F for cycle control. Fetch cycle is performed when F=0 and execute cycle when F=1. List the micro-operations and control functions for the computer(i) When F=0(ii) For Executing XOR, SWAP (AC and memory Word) ADD (M M+AC)11. A digital system has 16 registers, each with 32-bits.It is necessary to provide parallel data transfer from each register to every other register a. How many lines are needed for direct parallel transfer?b. If we need to link these register to a common bus c. How many Multiplexer will be required?d. How many input lines are required for each multiplexer 12.In a seven register bus organization of CPU the propagation delays are given, 30s for multiplexer, 60 ns to perform the add operation in the ALU and 20 ns in the destination decoder, and 10 ns to clock the data into destination register. What is the minimum cycle time that can be used for the clock

  • RESEARCH PROBLEMWhat are the differences between CISC and RISC architectures? Which types of applications are properly suited for each of these categories of architecture?Compare and contrast CISC architecture and RISC architecture. Make sure to include the strengths and weaknesses of each as well as applications to which they would be most suited.You may also compare/contrast them with any architecture that may be considered as future replacements for either or both of these two.

  • REFERENCESHayes P. John, Computer Architecture and Organisation, McGraw Hill Comp., 1988.Mano M., Computer System Architecture, Prentice-Hall Inc. 1993.Patterson, D., Hennessy, J., Computer Architecture - AQuantitative Approach, second edition, Morgan KaufmannPublishers, Inc. 1996;Stallings, William, Computer Organization and Architecture, 5th edition, Prentice Hall International, Inc., 2000.Tanenbaum, A., Structured Computer Organization, 4th ed., Prentice- Hall Inc. 1999.Hamacher, Vranesic, Zaky, Computer Organization, 4th ed., McGraw Hill Comp., 1996.