UNLOCKING THE POWER OF BOUNDARY-SCAN

JTAGT e c h n o l o g i e s Inc..

1 © Copyright 2001 JTAG Technologies October 2001 JTAG Overview Presentation

UNLOCKING THE UNLOCKING THE POWER OF POWER OF

BOUNDARY-BOUNDARY-SCANSCAN



3Com

ABB

August

Systems

AGFEO

Alcatel

AscomTelecom.

Atlas Copco

Barco Graphics

Blaupunkt

Bofors

Celestica

Compaq

Datex

ECI

EKB

Ericsson

Ericsson Intracom

Force Computer

Fujitsu Microelectronics

Fujitsu Telecom

GEC Alsthom

Harris

Hewlett-Packard

Hirschmann

Hitachi Consumer

Hitachi Microsystems

Honeywell Regels.

Italtel Research Centre

Japanese Radio Corp.

Kontron

MarPoss

Matra

Matra Communications

Matra-Ericsson T.

Matsushita

MET

Mitsubishi Electric

Motorola

NEC Technologies

Nokia Mobile Comm.

NORTEL

NTT

Parsytec

Philips BCS

Philips CE

Philips CFT

Philips

MedicalSystems

Pioneer

Polytechnico di T.

Rolls Royce

Siemens Medical

Siemens Nixdorf

Sogitec

Solectron

Sony

Sun Microsystems

Telefunken

Thomson

Tokyo MITC

Toshiba

World Wide Users World Wide Users



Value– Uniform tools across multiple departments– Rapid development cycles, shorter time-to-market– High-speed production rates– Low initial investment and low cost of ownership– Comprehensive supporting services



IEEE 1149.1 Boundary-Scan Standard• Adopted in 1990 by the IEEE as Standard 1149.1

– Prepared by the Joint Test Action Group (JTAG) – Originally for testing boards and devices

• Provides a serial 4-wire (5th is optional) interface, regardless of device complexity

• Semi-conductor manufacturer responsible for:– Designing device for compatibility– Providing BSDL file

• Many of today’s key components contain Boundary-Scan– Microprocessors, CPLDs, ASICs, FPGAs, DSPs, etc.– Flash isn’t directly compatible, but programmable



Drivers• Lack of access for testing via

conventional methods

• Desire to program devices after board assembly

• Need for commonality of platforms

• Requirement for system-level testing

Boundary-Scan Market Drivers

1970s

1980s

2000s

Pin

coun

t

DIP

PLCC

uBGA

Complexity



Boundary-Boundary-Scan at the Scan at the Chip LevelChip Level

Internal Core Logic

Instruction Reg.

ID Register

TAPcontroller

TMS

TCK

TDI TDOBypass

• Implemented in the ICs• Adds logic to the chips, allowing data from an external source to be loaded into ... … and read from the device pins• Accesses a large number of previously unavailable test points• Many of ICs today contain boundary-scan

BR

BR

BR

BR

BR

BR

BR BR BRBR BR



Applied to the PCBApplied to the PCBBoard Testing• Scan Infrastructure--verifies the

test system and the scan chain

• Interconnection -- paths between scan devices

• Clusters -- non-scan portions of

the board such as edge connectors and other logic

• Memory -- address, data, and control lines to memory arrays

In-System Programming• CPLDs--all of the major brands

• Flash--all types, at high speed

CPLDFlash

Test

Acc

ess

Port



FAST FlashFAST Flash ProgrammingProgrammingProgramming times of Intel 28F016 16 Mb Flash memory

via scan chains at various shift frequencies using AutoWriteTM

0.0

10.0

20.0

30.0

40.0

50.0

60.0

70.0

80.0

90.0

100.0

110.0

120.0

130.0

140.0

0.0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0

Scan chain consisting of 165 boundary-scan cells @ 12 Volt Vpp

Scan chain consisting of 165 boundary-scan cells @ 5 Volt Vpp

Scan chain consisting of 251 boundary-scan cells

Intrinsic programming time @ Vpp=12 Volt

Intrinsic programming time @ Vpp=5 Volt

(Close to theoretical speeds, 1-3 seconds per megabit, depending on board design)

Prog

ram

min

g Ti

me

(sec

onds

)

TCK Frequency (MHz)



Product LineupProduct LineupTest: Basic

StandardFullProfessional

Flash Programming: StandardProfessional

PLD Programming: StandardFull

Production PackagesStand-AloneServer Integration Packages

•Netlist•BSDLs•Cluster Descriptions

Boundary- Scan

Controller

Application Files

Application Development

Packages

UUT



BOUNDARY-SCAN TEST BOUNDARY-SCAN TEST CHARACTERISTICSCHARACTERISTICS

• Achievable Fault-coverage- Infrastructure Test: 100%

- Interconnect Test: 100%

- Memory Interconnection Test: 100%

- Clusters: a) Use PCB SIM (TSSI) w/Active Test

b) Use Active Test w/ golden PCB

Diagnostics – Automatic – To the Pin on the Part at fault!

• Test Preparation Time: Much Faster

(5-7 days for most complex designs)

• Size of Capital Investments, < ICT

Opens

Shorts

Stuck 0/1

Wrong/Missing

Components

Pin-Level

Shorted Nets

Components



The Power of Boundary-Scan The Power of Boundary-Scan TestingTesting

• Overcomes the Access Problem– Simple TAP interface vs. parallel test points

• Detects Structural PCB Defects– Shorts, Opens, Missing Components, Stuck 0/1– Connector, cluster, memory interconnection testing possible

• Automated Test Pattern Generation and Diagnostics

• Coverage Can be High, Depending on Scannable Parts



Summary of BenefitsSummary of Benefits

• Can provide significant savings• Allows test access to complex SMT boards• Integrates development, manufacturing, test, and programming• Simplifies inventory management, reduces device handling• Optimizes use of expensive ATE equipment• Less complex ATE and/or test fixtures• Rapid test and programming development

Documents

UNLOCKING THE POWER OF BOUNDARY-SCAN