VCS Commands Tutorial

VCS

© Seer Akademi Pvt. Ltd., 2011

Verilog Design Code


Verilog Test bench


File Directory


Analyzing the file

vlogan decoder.v tb.v


File Directory after analyze


Elaborating the designvcs –debug_all decoder_2to4 Test_decoder_2to4


File Directory after elaborate


Simulating in batch mode

./simv


File Directory after simulation


Generation of Log File

File Directory structure

vcs –debug_all decoder_2to4 Test_decoder_2to4 -l logfile.log


Suppressing the copyright

vcs –nc decoder_2to4 Test_decoder_2to4


Elaborating in quit mode

vcs –q decoder_2to4 Test_decoder_2to4


Elaborating in Verbose modevcs –v decoder_2to4 Test_decoder_2to4


Compile and simulate in a single command

vcs –R decoder_2to4 Test_decoder_2to4


Generating a VCD File

• Add

• $dumpfile(“File.vcd”);

• $dumpvars ;

• system task in the test bench


vcs –debug_all decoder_2to4 Test_decoder_2to4

./simv



File Directory Structure


Open the DVE


DVE Window


Opening the vcd file


Dve when loaded


Viewing the waveforms


waveforms


Interactive mode


vcs –debug_all decoder_2to4 Test_decoder_2to4

./simv -gui


dve


Simulation time insertion


Adding to waves


See schematic in dve


schematic


See path schematic


Path schematic


Generation of VPD file

• Add

• $vcdplusfile(“hahaFile.vpd”);

• $vcdpluson;

• system task in the test bench


vcs –debug_pp decoder_2to4 Test_decoder_2to4

./simv

dve&

Load the vpd file




Steps to generate coverage reportsvlogan decoder.v tb.vvcs –debug_all decoder_2to4 Test_decoder_2to4 -Mupdate -cm line+tgl+fsm+cond+branch./simv -cm line+tgl+fsm+cond+branchdve -cov


Coverage reports


Coverage reports


Coverage reports


Coverage reports


THANK YOU


Documents

VCS Commands Tutorial