Vedic Multiplier design

Testable fault detecting Vedic Multiplier coreSaranya B 1BG08EC087 Priti Saigal 1BG08EC074 Sahana R 1BG08EC086 Batch B10-2012 Project Seminar Project Guides Dr Veena S Chakravarthi (Internal) Mr.Chandramohan Umapathy (External) Professor ECE, BNMIT Cofounder of Pool Systems Department of Electronics Communication Engineering 1 BNM Institute of Technology 08-05-12 www.bnmit.org Sharan J M 1BG08EC093

BNMIT DEPT OF ECE-2012

Introduction

Literature survey Application scenario Functional Specification

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Testable fault detecting vedic multiplier core

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Data Pre-processor

RTL CODE

TEST BENCH

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Squarer using Duplex Sutra..Input number32

Hardware implementation of duplex sutra

(ab) = a + 2ab + b16

16

16

16

MAS8 8 8 8 8 8 8

MAS

MAS

X = 14 a = 1, b = 4 a = 1 b = 16. 2ab = 2 * 1 * 2 = 8. Find the sum X = 1968

Squarer-8 bit LUT

Squarer-8 bit LUT

Squarer-8 bit LUT

Squarer-8 bit LUT

RTL CODEDuplex adder_832

3332

Duplex adder_8

Duplex adder_1664

MAS-Multiply and shift

FUNCTIONAL VERIFICATION

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Squarer using YVDN Sutra

Hardware implementation of YVDN sutra

RTL CODE


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Multiplier using Nikhilam and Anurupye..

Multiplier

RTL CODE

FUNCTIONAL VERIFICATION6

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Multiplier using Duplex Sutra and Babylonian Mathematics=


RTL CODE


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Multiplier using Urdhva Tiryagbyham Sutra..INPUTS A32 8 8 8 8 8 8 8

B32 8

A7A6 A5A4 A3A2 A1A0 A1A0 B1B0 P1 A7A6 A5A4 B7B6 B5B4 P14 + P15 A3A2 A1A0 B3B2 B1B0 P2 + P3 A7A6 RTL CODE B7B6 P16 FUNCTIONAL VERIFICATIONP16 P14+P15

B7B6 B5B4 B3B2 B1B0 A7A6 A5A4 A3A2 A1A0 B7B6 B5B4 B3B2 B1B0 P7 + P8 + P9 + P10 A7A6 A5A4 A3A2

A5A4 A3A2 A1A0 B5B4 B3B2 B1B0 P4 + P5 + P6

B7B6 B5B4 B3B2P11 + P12 + P13 A1A0 B1B0P1

A7A6 A5A4 A3A2 B7B6 B5B4 B3B2P11+P12 P7+P8+ P4+P5 P2+P3 +P13 P9+P10 +P6

PRODUCT08-05-12 Testable fault detecting vedic multiplier core 64 8

OUTPUT


Cuber

(ab) = a + 3ab + 3ab + b

RTL CODE

FUNCTIONAL VERIFICATION9

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Fault Detector

RTL CODE


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Performance Analysis using Cadence32 bit Conventional Multiplier 13,160 20,242ps 15,77,624nW 32 bit Quarter Squarer Multiplier 14,528 15,520ps 4,00,386nW 32 bit Urdhva Multiplier 4,748 12,777ps 3,96,192nW 32 bit YVDN Multiplier 13,710 12,974ps 18,19,291nW 32 bit YVDN Squarer 9060 11,756ps 7,86,076nW Improvement

Performance Parameter Cell Area Timing Power Performance Parameter Cell Area Timing Power

63.92% 36.87% 74.88% Improvement 60.74% 81.25% 78.24% Improvement

32 bit Conventional Squarer 10,044 12,747ps 6,86,743nW

32 bit Duplex Squarer 3943 2390ps 1,49,404nW

Performance ParameterCell Area Timing Power08-05-12

32 bit Conventional Cuber34,780 36,558ps 48,98,269nW

32 bit Vedic Cuber48,039 30,386ps 39,64,048

16.88% 19.07%11



Chipscope

Chipscope is a set of tools made by Xilinx that allows you to easily probe the internal signals of your design inside an FPGA. It has two main parts: Embeddable IP cores that capture and store values of signals within the FPGA. Software tool that allows one to read the captured data and visualize it on a host computer. The Xilinx Chipscope tools package has several modules that are added to Verilog design. They are: ICON (Integrated controller) VIO (Virtual Input/Output) ILA (Integrated Logic Analyser)


Chipscope

Incorporating ChipScope Modules into Your Design 1. Generate the ChipScope modules, using the ChipScope Core Generator. 2. Incorporate and instantiate the ChipScope modules into the top-level module in your design. 3. Connect the ChipScope modules to your design. 4. Synthesize, implement, and run the design on the FPGA.


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Generating the ICON, VIO and UCF files

ICON-1 ICON-2 ICON-3 1. Double-click on ICON. (a) Component Name: Assign your ICON a name (this is arbitrary). (b) Select the correct Number of Control Ports. 2. Your ICON will have been created in the directory you specified to store your project. VIO-1 VIO-2 VIO-3

1. Double-click on VIO. (a) Component Name: Assign your VIO a name (this is arbitrary). (b) Enter the bit width for any 2 of the 4 signals: asynchronous inputs, synchronous inputs, asynchronous outputs and synchronous outputs. 2. Your VIO will have been created in the directory you specified to store your project. UCF You will also need a UCF file in the same directory to specify that the designs timing should be meet a clock constraint, and that the system clock is located at a specific pin on the board.Testable fault detecting vedic multiplier core 14

Generating Top Module and Starting Chipscope Pro analyzer


Instantiate ICON and VIO in top module. TOP MODULE After generating the top module, implement the process by clicking on analyze design using chipscope. After the entire process is successful, the main window of Chipscope Pro opens. Make sure that FPGA board is connected to PC. Click on Initialize JTAG Chain icon located at the top right corner of the window. Now select the FPGA device from the JTAG chain, right click and then select Configure to specify the configuration bit stream file. CHIPSCOPE PRO

The required input and output signals are obtained in VIO Console. Result for Quarter Squarer multiplier is displayed.

SNAPSHOT


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Functional Validation with UART Core

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UART Functional Specification

UART Data Transmission UART data transmit and receive UART Tx byte register UART Rx byte register Clock frequency = 66MHz Baud rate of UART core = 19200 bits/sec Frame format

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References

High speed squarer by Chandra Mohan Umapathy. http://www.magicalmethods.com/FREE/applications_in_sw/Camera_high_speed_paper.pdf Vedic Mathematics based 32 Bit High Speed Squarer Circuit using McCMOS Technique for Low Power VLSI Applications by Arindam Chakraborty ,Hamim Zafar, Jubin Hazra . High speed vedic multiplier for digital signal processor by Ramesh pushpangadam, Vineet Sukumaran, Rino Innocent, Dinesh Sasikumar, Vaisak Sundar. Analysis, Verification and FPGA Implementation of Vedic Multiplier with BIST Capability by Vinay Kumar . www.vedicmaths.org www.vedicganita.orgTestable fault detecting vedic multiplier core 18

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Cadence Design Contest 2012

Greetings from Cadence! Congratulations! Your submission below has been shortlisted for the next stage of the Cadence Design Contest 2012. Title of abstract: Testable fault detecting Vedic Multiplier Core Category: Bachelor's Institute: BNM Institute of Technology Please submit your project report by *Friday, July 20, 2012*. Late submissions will not be accepted. Format of Paper Your final submission must be in the following format (IEEE Standard). On Front Cover: Project Name Project Submitters Details (name, email address, semester) Guides Details (name, email address) if applicable

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Thank you !!!

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Literature survey..

Vedic Mathematics was Rediscovered in the early twentieth century by Swami Sri Bharati Krishna Tirthaji Maharaja. The sutras were contained in the Atharva Veda a branch of mathematics and engineering. It comprises of 16 sutras like Urdhva Tiryagbyham, Nikhilam Navatascaramama Dasatah and sub sutras derived from the main sutras like duplex sutra. Reduces cumbersome looking calculations to very simple ones resulting in a more efficient method in terms of speed and implementation

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Application scenario..CONVOLUTION

C I A F

MAC FFT CMUL FIR

ALUMICROPROCESSOR

DSP OPERATIONS

RSA CIRCUITRY ENCRYPTION

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Functional specification..

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Functional verification Duplex squarer..



Functional verification YVDN squarer..

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Functional verification Quarter square BNMIT DEPT OF ECE-2012 multiplier..

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Functional verification Urdhva multiplier..

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Functional verification multiplier using Nikhilam BNMIT DEPT OF ECE-2012 and Anurupye..

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Functional verification Cuber

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ICON-1

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ICON-2

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ICON-3

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VIO-1

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VIO-2

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VIO-3

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UCF

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Top Module

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Quarter Squarer multiplier result

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Documents

Vedic Multiplier design