VHDL Basic Language

VHDL-Basic Language Elements

VHDL - Lesson Two

Objective

© Ali Elkateeb, 2000 Programmable Logic Course Basic Language Elements 2

• To Learn:– The basic elements of the VHDL language

• data objects• literals• operators• object declarations (how to associate types with

objects)

Identifiers


– Two kinds of identifiers in VHDL:– basic identifiers and– extended identifiers

– Basic identifiers: composed of a sequence of one or more characters

– legal character: – upper-case (A ……Z)– lower-case (a….z)– digit (0…..9)– underscore ( _ )

– first character must be a letter– last character may not be an underscore

Identifiers


– two underscore characters cannot appear consecutively– lower-case and upper-case letters are considered to be

identical when used in basic identifier:example: COUNT, Count, coUNT are all refer to the

same basic identifier

– Extended Identifier: sequence of characters written between two backslashes

– any of the allowable characters can be used, including characters like !, ., @, and $.

– Lower-case and upper-case are distinct.Examples: \Test\ , \-25\ , \2FOR$\ , \.~$*****\ , \--\\--\

Identifiers


– Comments: must be preceded by two consecutive hyphens (--)

– can be appear anywhere within a descriptionExamples:

-- this is a comment; it ends at the end of the line-- always continue your comment on the second lineentity xxxx is end; -- can be after declaration

– Reserved words: listed at the end of every book on VHDL

– cannot be used as basic identifiers

Data Objects


– A data object holds a value of a specified type– object declaration:

variable COUNT: INTERGER;-- data object called COUNT, which can hold integer -- value

– Every data object belongs to one of the following four classes1. Constant2. Variable3. Signal (can be regarded as wires in a circuit)4. File

Data Objects


– constant declarations:examples:constant rise_time:TIME :=10ns; --object rise_time, which

-- can hold a value of type TIME, and the value of 10ns-- assigned to the object at the start of the simulation

constant bus_width: Integer:=8;

constant no_of_inputs: INTEGER;-- constant has not specified-- such a constant is called a deferred constant

Data Objects


– Variable declarations:Examples:

variable CTRL_Status: BIT_VECTOR (10 downto 0);variable SUM:INTERGER range 0 to 100:=10;variable found,done:BOOLEAN;

– Signal declarations:Examples:

signal clock:BIT;signal data_bus:BIT_VECTOR(0 to7);signal gate_delay:TIME :=10ns;signal init_P: STD_LOGIC_VECTOR(7 downto 0):=

(0 => ‘1’, others => ‘U’);

Data Objects


– File declarations:file file-names: file-type-name [[open mode] is string-expression];

– string expression: interpreted by the host environment as the physical name of a file

– mode specifies whether the files is to be used as read-only or write-only, or in the append mode

Examples:file STIMULUS:TEXT open READ_MODE

is “/usr/home/jb/add.sti”;file VECTOR: BIT_FILE is “/usr/home/james/add.vec”;

--default is READ_MODE

Data Types


– Every data object in VHDL can hold a value that belongs to a set of values by using the type declaration

– Certain types, and operations that can be performed on objects, are predefined in the language

– The declarations for the predefined types of the language are contained in package STANDARD

– The language also provides the facility to define new types by using type declarations

– Also a set of operations can be defined on these new types– It is possible to derive subtypes from predefined or user-

defined types

Data Types


Subtypes: – A subtype is a type with a constraint– The constraint specifies the subset of values for the subtype– The type is called the base type of the subtype– Subtypes are useful for range checking and for imposing

additional constraint on typesExamples:subtype MY_INTEGER is INTEGER range 48 to 80;-- MY_INTEGER is a subtype of the INTEGER base type-- and has a range constraint

type DIGIT is (‘0’, ‘1’, ‘2’, ‘3’, ‘4’, ‘5’, ‘6’, ‘7’, ‘8’, ‘9’);

subtype MIDDLE is DIGIT range ‘3’ to ‘7’;-- DIGIT is a user-defined enumeration type. MIDDLE is subtype

Data Types


– Subtype could not impose a constraintExample:subtype NUMBER is DIGIT --NUMBER is a subtype with no constraint-- the subtype simply gives another name to an already existing type

– Types in VHDL language can be categorized into four major categories:

– Scalar types– Composite types– Access types– File types

Data Types


1. Scalar Types– There are four different kinds of scalar types:

– Enumeration– Integer– Physical (not supported by synthesis tools)– Floating point (not supported by synthesis tools)

– Integer, floating point, and physical types are classified as numeric types

– Enumeration and Integer types are called discrete types

Data Types - Scalar Types


Enumeration Types: A set of user-defined values consisting of identifiers and character literals

Syntax: type enum_type_name is (enum_value {,enum_vlaue});

whereenum_type_name is the identifier name of the

enumerated data type

enum_value is an identifier or character literal



Enumeration Types:

Examples:type MVL is (‘U’, ‘0’, ‘1’, ‘Z’);type MICRO_OP is (LOAD, STORE, ADD, SUB, MUL);subtype ARITH_OP is MICR_OP range ADD to MUL;

Examples: of objects defined for these types

signal CONTROL_A: MVL;signal CLOCK: MVL range ‘0’ to ‘1’; --CLOCK restricted to ‘0’ or ‘1’

--range constraint can be specified in an object declaration



Enumeration Types:- The order in which values appear in an enumeration type

declaration defines their orderExample:

type Micro_op is (Load, Store, Add, Sub, Mul, Div); The binary numbers assigned to the above examples would be:Load = 000, Store = 001, Add =010, Sub = 011,Mul = 100, Div = 101

- These assigned numbers enable relational operators to be used on enumerated typesexample: if (load < store) then



Enumeration Types:- The values of an enumeration type are called enumeration

literalsexample:

type car_state is (stop, slow, medium, fast);-- enumeration literals are stop, slow, medium and fast-- the object of car_state may be assigned only these values



Enumeration Types:- If the same literal is used in two different enumeration type

declarations, the literal is said to be overloadedexample:

type MVL is (‘U’, ‘0’, ‘1’, ‘Z’);type TWO_STATE is (‘0’, ‘1’);-- ‘0’ and ‘1’ are two literals that are overloaded since they-- appear in both MVL and TWO_STATE types.



Enumeration Types:- The predefined enumeration types of the language are:1. Character: includes 191 characters of the ISO eight-bit

coded character set.- Values belonging to the type character are called

Character literals and are always written between two single quotes (‘ ‘).

Examples:‘A’‘_’‘’’‘3’



Enumeration Types:2. BIT: has the literals ‘0’ and ‘1’3. BOOLEAN: has the literals FALSE and TRUE4. SEVERITY_LEVEL: has the values NOTE, WARNING,

ERROR, and FAILURE5. FILE_OPEN_KIND: has the values READ_MODE,

WRITE_MODE, and APPEND_MODE

6. FILE_OPEN_STATUS: has the values OPEN_OK,STATUS_ERROR, MODE_ERROR, NAME ERROR,and MODE_ERROR



Enumeration Types:- STD_ULOGIC is an enumeration type (defined in

STD_LOGIC_1164)type STD_ULOGIC is ( -- is used for single bit data type

‘U’, --Uninitialized‘X’, --Forcing unknown‘0’, -- forcing 0‘1’, -- forcing 1‘Z’, -- high impedance‘W’, -- Weak unknown‘L’, -- weak 0‘H’, -- weak 1‘-’ -- Don’t care);



Integer Types: - defines a range of integer numbersSyntax:type type_name_identifier is range integer_range;where: type_name_identifier is the identifier name of the

data typeinteger_range is the defined subrange of integers

examples:type CountValue is range 0 to 15;type WORD_LENGTH is range 31 downto 0;

Note: there is no difference between using to or downto when declaring integer range



Integer Types: - Values belonging to an integer type are called integer

literalsExamples:

- 56623- 6E2- 98_71_28 -- underscore has no impact on the

-- value of the literal, I.e., 98_71_28 is -- same as 987128

- Integer is the only predefined integer type in VHDL- Integer type is implementation-dependent

- must be at least cover the range from -(2^31 -1) to +(2^31 -1)



Composite Types: - Represents a collection of values (elements) which

together constitute an array or record- individual elements of an array must belong to the

same type while record elements may be of a different type

- Composite array data type: useful for modeling linear structure such as RAMs and ROMs.type address_word is array (0 to 63) of BIT;type data_word is array (7 downto 0) of STD_ULOGIC;type ROM is array (0 to 125) of data_word;- It is possible to specify arrays to any dimension (synthesis

tools support one or two dimensions)



Composite Types: - Composite record data type: useful for modeling data

packetstype PIN_TYPE is range 0 to 10;type MODULE is

recordSIZE :INTEGER range 20 to 200;CRITICAL_DLY :TIME;NO_INPUTS :PIN_TYPE;

end record;



Other scalar types:- The physical and floating point types will be discussed

briefly later on

- Both physical and floating point data types are notsupported by synthesis tools

Other Categories of data types:- The Access and File types will be discussed briefly

later on- Both access and file types are not supported by

synthesis tools

Expressions, Operators


- An expression comprises of operands and operatorsexample: Y <= A -Z

where: (-) is operatorA, Z are operands

- We covered in details many operandsOperators:

- classified into six categories:1. Logical operators2. Relational operators3. Shift operators4. Adding operators5. Multiplying operators6. Miscellaneous operators

Operators


1. Logical Operators:- and, or, nand, nor, xor, xnor, not- These operators are defined for

- the predefined types BIT and BOOLEAN- one-dimensional array of BIT and BOOLEAN

- The operators nand and nor are not associativeexample: A nand B nand C -- is illegal

- Parentheses can be used to avoid this problem

Operators


2. Relational operators:= /= < <= > >=- The result type is always the predefined type BOOLEAN- The = (equality) and /= (inequality) are predefined on any

type except file types- The operators <, <=, >, >= are all predefined on any

scalar type, e.g., integer or enumerated types or discrete array type (i.e., array in which element values belong to discrete type)

example: BIT_VECTOR’(‘0’, ‘1’, ‘1’) < BIT_VECTOR’(‘1’, ‘0’, ‘1’)is true since comparison is performed one element at a time from left to right

Operators


3. Shift Operators:sll srl sla sra rol ror- each operator takes an array of BIT or BOOLEAN as the left operand and an integer values as the right operand and performs the specified operationexample: “1001010” sll 2 is “0101000”

“1001010” rol 2 is “0101010”“ 1001010” rol -1 is “0100101”

-- with negative number, the opposite action is performed

Operators


4. Adding operators+ - &- For (+) and (-) operators must be of the same numeric type- For & (concatenation) operator can be either a one-

dimensional array type or an element typeexamples:

‘0’ & ‘1’ results of “01”- & useful for separate signals are to be grouped into one bus

signal Dbus: std_logic_vector(0 to 7);signal Ctrl:std_logic_vector (5 downto 0);signal enable, RW:std_logic;Dbus <= Ctrl & enable & RW;

Operators


5. Multiplying operators* / mod rem- * is for multiplication- / is for division- mod is for modulus- rem is for remainder- * and / are predefined for both operands being of the same

integer or floating point, the result is also of the same type- the rem and mod operators operate on operands of integer

types, and the result is also of the same type

Operators


6. Miscellaneous operatorsabs (absolute)** (exponentiation)

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VHDL Basic Language