Filename=”AET_ch3.doc”

VHDL & VHDL-AMS Object Classes and Data Types

In VHDL, a data object holds a value of some specified type and can be classified into one of the following six classes: constants, variables, signals, file, quantity, terminal. The declaration syntax is:

OBJECT_CLASS identifier [,identifier ...] :TYPE [:=value];

1.1 Constant Class

An object of class constant holds a single value of of a given type. It must be assigned a value upon declaration, and the value can’t be changed subsequently. The declaration syntax is:

CONSTANT identifier [,identifier ...]:TYPE:=value;

Example:

CONSTANT a1:REAL :=1.2;CONSTANT word_size:INTEGER:= 16;

1.2 Variable Class

An object of class variable holds a single value of a given type. It can be assigned new value any number of times during program executions. It needs not be initialized upon declaration. The declaration syntax is:

VARIABLE identifier [,identifier ...]:TYPE [:=value];

Example:

VARIABLE counter: BIT_VECTOR(3 DOWNTO 0) := “0000”;VARIABLE sum: REAL;

Variables are changed by executing an assignment operator. For example,

counter := “0001”;sum := 0.0;

The variable assignments have no time dimension associated with them. That is, the assignments take their effect immediately. Thus variable has no direct analogue in hardware. Variable can only be used within sequential areas, within a PROCESS, in subprograms (functions and procedures) and not within ARCHITECTURE BODY.

PROCESS(a,b)VARIABLE val1:STD_LOGIC:=’0’;

BEGINval1 := a; --variable val1 is assigned the value of signal a.b <= val1; --signal b is assigned the value of variable val1.

END;

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1.3 Signal Class

An object of class signal can hold or pass logic values, while variables cannot. A signal is a pathway along which information passes from one component in a VHDL description to another. It is analogous to a wire in hardware. It needs not be initalized upon declaration.

SIGNAL identifier [,identifier ...] :TYPE [:=value];

Example:

SIGNAL sigA, sigB: BIT;

Signals are objects whose values may be changed and have a time dimension. Signal values are changed by signal assignment operator (<=).

Example:

a <= b AFTER 10 ns;c<= d OR e;

The AFTER 10 ns clause in the first example means that signal a will be assigned signal b 10 ns later. In the second example there is no AFTER clause; this is equivalent to AFTER delta. That is, signal assignments are used to represent real circuit phenomena, so if there is no AFTER clause, it is assumed that the signal takes on its new value delta time later. Delta is an arbitrary small time greater than zero.

1.3.1 Signals and Variables

Whenever the code assigns a value to a variable, the simulator simply updates the current value of that variable, as you would expect in any programming language.

But when the code assigns a value to a signal, that assignment is treated differently. The signal has a current value, which is used whenever the signal appears in an expression, and a list of “next values,” each of which consists of a pair of data items: a value for the signal, and the number of simulation cycles after which the signal is actually given that value. So, a signal assignment does not affect the current value of the signal but only the value for a future simulation cycle. At the end of each simulation cycle, the simulator scans through all the signals, and updates each one from its “next values” list for the next cycle that is to occur.

1 LIBRARY IEEE; 2 USE IEEE.STD_LOGIC_1164.ALL; 3 4 ENTITY and_or IS 5 PORT(a,b,c : IN BIT; 6 q: OUT BIT); 7 END and_or; 8 ARCHITECTURE archand_or OF and_or IS9 SIGNAL temp : BIT;10 BEGIN11 temp <= a AND b;12 q <= temp OR c;13 END archand_or

2

TIME cba temp q0 001 0 0t 011 0 0t + 011 1 0t + 2 011 1 1

The current value of temp is calculated based on the previous values of a and b. The current value of q is calculated based on the previous values of c and temp.

1.3.2 When to use Variables

Signals assigned to in a process are updated at the end of the process. The signal driver is filled with the new value when the assignment statement is executed. Then, as the last step before the process is suspended, that driver is passed to the signal.

Variables, on the other hand, are updated as soon as the variable assignment is executed.

The following process based code implementation of the and_or circuit can’t be implemented.

1 LIBRARY IEEE; 2 USE IEEE.STD_LOGIC_1164.ALL; 3 4 ENTITY and_or IS 5 PORT(a,b,c : IN BIT; 6 q: OUT BIT); 7 END and_or; 8 ARCHITECTURE archand_or OF and_or IS 9 SIGNAL temp : BIT;10 BEGIN11 PROCESS(a,b,c)12 BEGIN13 temp <= a AND b;14 q <= temp OR c;15 END PROCESS;16 END archand_or

3

TIME cba temp q0 001 0 0t 011 0 0t + 011 1 0

Since temp is not in the sensitivity, the event in temp does not cause the activation of q in line 14. In addition, because temp is not in the sensitivity list, this implies that its value must be stored, hence the flip-flop. The problem then is to determine the clock for the flip-flop. Because the process is triggered by any event on a, b, or c, the flip-flop must be active to both a rising and a falling edge for any or all three of the signals. Because very few libraries have flip-flops that are active to edges of a clock, a new function must be built. The edge detector would have to create an active edge for the flip-flop whenever an input signal changes, but this cannot be synthesized. Modify the process sensitivity list to include temp, as follows:

PROCESS(a,b,c,temp);

That is, for a process based description to be synthesized as a combinatorial network, any signal that appears on both the right-hand-side (RHS) and the left-hand-side (LHS) of assignment statements must be included in the process sensitivity definition. To more efficiently describe intermediate results of operations that are not needed outside of a process you can use variables.

1 LIBRARY IEEE; 2 USE IEEE.STD_LOGIC_1164.ALL; 3 4 ENTITY and_or IS 5 PORT(a,b,c : IN BIT; 6 q: OUT BIT); 7 END and_or; 8 ARCHITECTURE archand_or OF and_or IS 9 BEGIN11 PROCESS(a,b,c)12 VARIABLE temp : BIT;12 BEGIN13 temp := a AND b;14 q <= temp OR c;15 END PROCESS;16 END archand_or

TIME cba temp q0 001 0 0t 011 1 0t + 011 1 1

1.4 Quantity Class1

New Object in VHDL 1076.1 Represents an unknown in the set of Differential Algebraic Equations (DAEs) implied by the text

of a model Continuous-time waveform Scalar sub-elements must be of a floating-point type Default initial value for scalar sub-elements is 0.0

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Declaration Syntax:

QUANTITY identifier [,identifier ...] :TYPE [:=value];

Example:QUANTITY qc : charge; --coulomb in ELECTRICAL_SYSTEMS packageQUANTITY vt : voltage; --volt in ELECTRICAL_SYSTEMS packageQUANTITY v: velocity; --m/s in MECHANICAL_SYSTEMS packageQUANTITY s: displacement --m in MECHANICAL_SYSTEMS packageQUANTITY vout1: REAL :=12.0;QUANTITY vd ACROSS id THROUGH anode TO cathode;

--defining vd as ACROSS quantity and id as THROUGH quantity flowing from --anode to cathode

1.5 Terminal Class

New object in VHDL 1076.1

Basic support for structural composition with conservative semantics

Belong to a nature

Declaration Syntax:

TERMINAL identifier [,identifier ...] :NATURE ;

Example:

TERMINAL anode, cathode: ELECTRICAL;

Nature ELECTRICAL is defined in IEEE.ELECTRICAL_SYSTEMS package

1.6 Nature

Represents a physical discipline or energy domain: electrical, fluidic, mechanical, radiant, thermal

Has two aspects related to physical effects Across: effort like effects (voltage, velocity, temperature, etc.) Through: flow like effects (current, force, heat flow rate, etc.)

A nature defines the types of the across and through quantities incident to a terminal of the nature

A scalar nature additionally defines the reference terminal for all terminals whose scalar sub-elements belong to the scalar nature

A nature can be composite: array or record All scalar sub-elements must have the same scalar nature

1.7 Signal Attributes

Specific values associated with signals.

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Format: signal_name' attribute_designator

Example: clock'ACTIVE

1.7.1 Signal Attributes Which Define Another Signals

1. S'DELAYED(T) is a signal which echoes the value of the prefix signal, delayed by the specified time factor. If T=0, the value is equal to S after a delta delay (i.e. in the next simulation cycle).

2. S'QUIET(T) is a boolean signal whose value is TRUE if S has not had a transaction (i.e. not active) for the length of time T. If T=0,FALSE during simulation cycle in which S was assigned to and then will return to TRUE.

3. S'STABLE(T) is a boolean signal whose value is TRUE if S has not had an event (i.e. not changed value) for the length of time T. If T=0, the value will be FALSE during the simulation cycle in which S changed and then will return to TRUE.

4. S'TRANSACTION is a bit signal whose value toggles each time a transaction occurs on S (i.e. S is active).

1.7.2 Signal Attributes Which Provide Information About Signals

1. S'EVENT is TRUE if an event has occured on S during the current simulation cycle (i.e. if S has changed value during the cycle).

2. S'ACTIVE is TRUE if a transaction has occured on S during the current simulation cycle.

3. S'LAST_EVENT returns the amount of time which has elapsed since the last event on S (i.e. since S last changed value).

4. S'LAST_ACTIVE returns the amount of time which has elapsed since the last transaction on S (i.e. since S was last active).

5. S'LAST_VALUE returns the value of S before the last event on S.

6. S’DRIVING is false if the current driver of signal S is a null transaction.

7. S’DRIVING_VALUE returns the current driving value of signal S.

Signal Attribute Supported Attribute for synthesis

‘active No‘delayed[(t)] No‘event Yes‘last_active No‘last_event No‘last_value Yes‘quiet[(t)] No‘stable Yes‘transaction Yes

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1.7.3 Signal Attribute Relationships

An activity is any change on the signal value. A change from `1' to `X' is an example of an activity, and a change from `1' to `1' is an activity. The only criteria is that something happened. However an event requires a change in value of the signal. A change from `1' to `X' is an event, but a change from `1' to `1' is not an event. All events represent activities, but not all activities represent events.

IF S'STABLE is given without a time expression, the expression defaults to 0 ns which means that the check is for stability of the signal at this exact instance in time. This is equivalent to S'EVENT.

S'EVENT is more efficient than S'STABLE. Simulator will take more work to evaluate S'STABLE.

1.7.4 Examples

Example 1: Delayed Signal

CLK

clk1

ped := 1mdel := 0periodical := 1

sdelay

sdelay1

clk1.val

t [s]

1.2

-0.2

0.2

0.6

0 3m0.5m 1m 1.5m 2m 2.5m

sdelay1.sout

t [s]

1.2

-0.2

0.20.40.60.8

0 3m0.5m 1m 1.5m 2m 2.5m

ENTITY sdelay ISGENERIC (T: TIME:=1ms ); --Simplorer does not allow changes to TIME parPORT (SIGNAL sin: IN BIT;

SIGNAL sout: OUT BIT);END ENTITY sdelay;

ARCHITECTURE behav OF sdelay IS

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BEGINsout <= sin'DELAYED(T);

END ARCHITECTURE behav;

To change the delay parameter T requires re-compilation of the model.

ENTITY sdelay ISGENERIC (T: TIME:=2ms );PORT (SIGNAL sin: IN BIT;

SIGNAL sout: OUT BIT);END ENTITY sdelay;

ARCHITECTURE behav OF sdelay ISBEGIN

sout <= sin'DELAYED(T);END ARCHITECTURE behav;

sdelay1.sout

t [s]

1.2

-0.2

0.20.40.60.8

0 3m0.5m 1m 1.5m 2m 2.5m

Example 2: Phase-shifted Clock generationtwo_ph_clk1.phase0

t [s]

1.2

-0.2

0.2

0.6

0 0.1u10n 20n 30n 40n 50n 60n 70n 80n 90n

two_ph_clk1.phase1

t [s]

1.2

-0.2

0.20.40.60.8

0 0.1u10n 20n 30n 40n 50n 60n 70n 80n 90n

ENTITY two_ph_clk IS GENERIC(Cycle_Time: TIME:=25 ns); PORT(Phase0,Phase1:OUT BIT);END ENTITY two_ph_clk;

ARCHITECTURE behav OF two_ph_clk ISSIGNAL ControlSignal:BIT:='0';

BEGIN ControlSignal <= NOT ControlSignal AFTER Cycle_Time; Phase0 <= ControlSignal; Phase1 <= ControlSignal'DELAYED(Cycle_Time/2);END ARCHITECTURE behav;

Example 3: Detecting Rising Clock Edge:

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clock'EVENT AND clock='1; (or) NOT clock'STABLE AND clock='1'; (or) NOT clock'QUIET AND clock='1'; (Not supported by Autologic II) (or) clock’LAST_VALUE=’0’ AND clock=’1’; (Preferred Method)

Example 4: Detecting Falling Clock Edge:

clock'EVENT AND clock='0'; (or) NOT clock'STABLE AND clock='0'; (or) clock'LAST_VALUE='1' AND clock='0'; (Preferred Method )

Example 5: Checking Setup and Hold Time of D Flip Flop:

ENTITY DFF IS GENERIC(Setup,Hold,Delay:TIME:=0 ns); PORT(D,clock:IN BIT:='0';Q:OUT BIT:='0';QB:OUT BIT:='1'); BEGIN -- passive process (no signal assignment) only for checking -- generic constraints. Check_Setup_and_Hold_Times: PROCESS(D,clock) BEGIN -- Check for setup time IF NOT clock'STABLE AND clock='0' THEN ASSERT D'STABLE(Setup) REPORT "D changed within setup interval" SEVERITY Warning; END IF; -- Check for hold time IF NOT D'STABLE AND clock='0' THEN ASSERT clock'STABLE(Hold) REPORT "D changed within hold interval" SEVERITY Warning; END IF;

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--Check for Delay TimeASSERT (Delay>=Hold)

REPORT “Delay>=Hold Violation”SEVERITY Warning;

END PROCESS; END DFF;

ARCHITECTURE one OF DFF IS SIGNAL value: BIT; BEGIN PROCESS(D,clock) BEGIN IF((NOT clock'LAST_VALUE) AND (clock = `0')) THEN value <= D; END IF; END PROCESS; Q <= TRANSPORT value AFTER Delay; QB <= TRANSPORT NOT value AFTER Delay; END one;

-- Setup Test Bench ENTITY tb IS -- no IO END tb;

ARCHITECTURE setup_one OF tb IS COMPONENT FF GENERIC(Setup,Hold,Delay:TIME); PORT(D,clock: IN BIT;Q,QB:OUT BIT); END COMPONENT; FOR u1:FF USE ENTITY WORK.DFF(one); SIGNAL s1,s2,s3,s4:BIT; BEGIN FF_1: FF GENERIC MAP(2 ns, 1 ns, 5 ns) PORT MAP(s1,s2,s3,s4);

s1 <= `1' AFTER 13 ns; --must , not ;[only the last one is ;] `0' AFTER 17 ns; `1' AFTER 27 ns; `0' AFTER 35 ns;

s2 <= `1' AFTER 5 ns; `0' AFTER 15 ns; `1' AFTER 25 ns; `0' AFTER 30 ns; `1' AFTER 35 ns; `0' AFTER 40 ns; END setup_one;

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1.8 Implicit Quantities

Q’Dot: The derivative of quantity Q with respect to time

Q’Integ :The integral of quantity Q over time from zero to current time

Q’Slew(max_rising_slope, max_falling_slope): Follow Q, but its derivative w.r.t. time is limited by the specified slopes. Default for max_falling_slope is max_rising_slope, default for max_rising_slope is infinity

Q’Delayed(T): Quantity Q delayed by T (ideal delay, T>=0)

Q’Ltf(num, den): Laplace transfer function whose input is Q

Q’ZOH(T, initial_delay): A sampled version of quantity Q (zero-order hold)

Q’Ztf(num, den, T, initial_delay): Z-domain transfer function whose input is S’Ramp(tr, tf): A quantity that follows signal S, but with specified rise and fall times. Default for

tf is tr, default for tr is 0.0

S’Slew(max_rising_slope, max_falling_slope): A quantity that follows signal S, but its derivative w.r.t. time is limited by the specified slopes. Default for max_falling_slope is max_rising_slope, default for max_rising_slope is infinity

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Vsine

vsine1

Electrical2Sfg

electrical2sfg1

ampl := 1.0freq := 1k

deriv

deriv1

vsine1.v

t [s]

1

-1

0

-0.5

0.5

0 2m0.2m 0.6m 1m 1.4m

deriv1.qout

t [s]

8k

-8k

0

-4k

4k

0 2m0.2m 0.6m 1m1.2m 1.6m

LIBRARY IEEE;USE IEEE.ELECTRICAL_SYSTEMS.ALL;USE IEEE.MATH_REAL.ALL;ENTITY Vsine IS

GENERIC ( ampl, freq : REAL);PORT (TERMINAL p, m : ELECTRICAL);

END ENTITY Vsine;

ARCHITECTURE Sine OF Vsine ISQUANTITY v ACROSS i THROUGH p TO m;

BEGINv == ampl * sin (math_2_pi*freq*NOW);

END ARCHITECTURE Sine;

ENTITY deriv ISPORT (QUANTITY qin: IN REAL;

QUANTITY qout: OUT REAL);END ENTITY deriv;

ARCHITECTURE behav OF deriv ISBEGIN

qout == qin'DOT;END ARCHITECTURE behav;

NOTE: Terminals and quantities cannot be connected directly, conversion models are needed.

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ELECTRICAL TO QUANTITY CONVERSION MODEL

LIBRARY IEEE;USE IEEE.ELECTRICAL_SYSTEMS.ALL;ENTITY Electrical2Sfg IS

PORT (TERMINAL p, m : ELECTRICAL; QUANTITY output: OUT REAL);

END ENTITY Electrical2Sfg;

ARCHITECTURE Across2Sfg OF electrical2sfg ISQUANTITY v ACROSS p TO m;

BEGINoutput == v;

END ARCHITECTURE Across2Sfg;

QUANTITY TO ELECTRICAL CONVERSION MODEL

LIBRARY IEEE;USE IEEE.ELECTRICAL_SYSTEMS.ALL;ENTITY SfgElectrical IS

PORT (TERMINAL p, m:ELECTRICAL; QUANTITY input: IN REAL);

END ENTITY SfgElectrical;

ARCHITECTURE Across2Electrical OF sfgelectrical ISQUANTITY v ACROSS i THROUGH p TO m;

BEGINv == input;

END ARCHITECTURE Across2Electrical;

Vsine

vsine1

Electrical2Sfg

electrical2sfg1

ampl := 1.0freq := 1k

integ

integ1

vsine1.v

t [s]

1

-1

0

-0.5

0.5

0 2m0.2m 0.6m 1m 1.4m

13

integ1.qout

t [s]

0.35m

-50u50u

0.15m

0.25m

0 2m0.2m 0.6m 1m 1.4m

ENTITY integ ISPORT (QUANTITY qin: IN REAL;

QUANTITY qout: OUT REAL:=0.0);END ENTITY integ;

ARCHITECTURE behav OF integ ISBEGIN

qout==qin'INTEG;END ARCHITECTURE behav;

Vsine

vsine1

Electrical2Sfg

electrical2sfg1

ampl := 1.0freq := 1k

qslew

qslew1

tr := 5.0ktf := -5.0k

vsine1.v

t [s]

1

-1

0

-0.5

0.5

0 2m0.2m 0.6m 1m1.2m 1.6m

qslew1.qout

t [s]

1

-1

0

-0.5

0.5

0 2.1m0.25m 0.75m1m 1.3m1.5m1.8m

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ENTITY qslew ISGENERIC (tr : REAL:=0.0; tf:REAL:=0.0); --NOTE: tr>=0 & tf<=0PORT (QUANTITY qin: IN REAL;

QUANTITY qout: OUT REAL);END ENTITY qslew;

ARCHITECTURE behav OF qslew ISBEGIN

qout==qin'slew(tr, tf);END ARCHITECTURE behav;

Vsine

vsine1

Electrical2Sfg

electrical2sfg1

zoh

zoh1

ts := 0.1m

ampl := 1.0freq := 1k

vsine1.v zoh1.q

t [s]

1

-1

0

-0.5-0.25

0.250.5

0 1m0.1m 0.3m 0.5m 0.7m

ENTITY zoh ISGENERIC(ts : REAL:= 0.0); --ts must be type REAL, not TIMEPORT( QUANTITY din : IN REAL;

QUANTITY q: OUT REAL);END ENTITY zoh;

ARCHITECTURE behav OF zoh ISBEGIN

q==din'ZOH(ts);END ARCHITECTURE behav;

15

B=>R

bit_real1CLK

clk1ramp

ramp1

tr := 0.1mtf := 0.2m

ped := 1mdel := 0periodical := 1

clk1.val ramp1.q

t [s]

1.2

-0.2

0.20.40.60.8

0 3.5m0.5m 1m 1.5m 2m 2.5m

B=>R is signal to signal data type conversion from bit to real. It is located in Tools library:

(Tools)Omnicasters>Signal-Signal>Bit-Real

ENTITY ramp ISGENERIC (tr : REAL:=0.0; tf:REAL:=0.0); --tr,tf must be type REAL, not TIMEPORT (SIGNAL s: IN REAL;

QUANTITY q: OUT REAL);END ENTITY ramp;

ARCHITECTURE behav OF ramp ISBEGIN

q==s'RAMP(tr, tf); --signal s must be of type REALEND ARCHITECTURE behav;

delay

delay1

Vsine

vsine2 Electrical2Sfg

electrical2sfg2

ampl := 1.0freq := 1.0k

t := 0.5m

vsine2.v

t [s]

1

-1

0

-0.5

0.5

0 3.5m0.5m 1m 1.5m 2m 2.5m

16

delay1.qout

t [s]

1

-1

0

-0.5

0.5

0 3.7m0.5m 1m 1.5m 2m 2.5m 3m

ENTITY delay ISGENERIC (T: REAL:=0.0);PORT (QUANTITY qin: IN REAL;

QUANTITY qout: OUT REAL);END ENTITY delay;

ARCHITECTURE behav OF delay ISBEGIN

qout == qin'DELAYED(T);END ARCHITECTURE behav;

CLK

clk1

B=>R

bit_real1sslew

sslew1

tr := 5.0ktf := 5.0k

ped := 1mdel := 0periodical := 1

clk1.val

t [s]

1.2

-0.2

0.2

0.6

0 2m0.2m 0.6m 1m1.2m 1.6m

sslew1.qout

t [s]

1.2

-0.2

0.20.40.60.8

0 2m0.2m 0.6m 1m1.2m 1.6m

ENTITY sslew ISGENERIC (tr : REAL:=0.0; tf:REAL:=0.0); --NOTE tr , tf are of type REAL and both positive, unlike qslew.PORT (SIGNAL sin: IN REAL;

QUANTITY qout: OUT REAL);END ENTITY sslew;

ARCHITECTURE behav OF sslew ISBEGIN

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qout==sin'SLEW(tr, tf);END ARCHITECTURE behav;

1.9 Implicit Signal

Q’Above(E): A Boolean signal that is TRUE when quantity Q is above threshold E Q must be a scalar quantity, E must be an expression of the same type as Q A event occurs on signal Q’Above(E) at the exact time of the threshold crossing A process can be sensitive to Q’Above(E), since it is a signal

Comparator

comparator1

Vsine

vsine1

ampl := 1.0

freq := 1k

vthresh := 0.0

vsine1.v

t [s]

1

-1

0

-0.5

0.5

0 3m0.5m 1m 1.5m 2m 2.5m

comparator1.dout

t [s]

1.2

-0.2

0.20.40.60.8

0 3m0.5m 1m 1.5m 2m 2.5m

LIBRARY IEEE;USE IEEE.ELECTRICAL_SYSTEMS.ALL;ENTITY Comparator IS

GENERIC(vthresh: REAL); --thresholdPORT(TERMINAL ain, ref: ELECTRICAL;

SIGNAL dout: OUT BOOLEAN);END ENTITY Comparator;

ARCHITECTURE Ideal OF comparator ISQUANTITY vin ACROSS ain TO ref;

BEGINdout<=vin'Above(vthresh);

END ARCHITECTURE Ideal;

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1.10 Literal

Integer literals may be expressed in any base from 2 to 16. Any two adjacent digits may be separated by a single underscore (_).

Examples: 12343 --base 10 integer literal 2#10011110# --base 2 (binary) integer literal 8#720# --base 8 (octal) integer literal 16#FFFF0ABC# --base 16 (hex) integer literal 16#FFFF_0ABC# --using (_) for readability

Floating point literals differs from an integer literal in that it contains a dot(.).

Examples: 65971.333333 65_971.333_333 8#43.6#

A character literal consists of a single character and can be any character, which can be entered. Identifiers are names and must follow the VHDL rules for creating names. To distinguish the difference, character literals must be entered in single quote marks. That is, a is an identifier, while `a' is a character.

Character literals are case sensitive. When they appear within the model,they must appear in single quotes and they must be the same case.

Identifiers are not case sensitive and can include letters, numbers and the underscore character (_). It must start with a letter and it cannot end with an underscore.

1.11 Typing

Object's TYPE determine values it may assume and operations which may be performed on it. Aids in design verification: Data Paths .Object Values Type Classifications:

Scalar Composite File Access (Pointer)

The type of an object indentifies the values the object may assume. When a value is assigned to a signal, the value is checked to be sure that it is within the allowable set of values. If it is not, an error message is issued. This is particularly useful for values assigned from a arithmetic computation.

1.11.1 Scalar Types

Scalar types (no structure) include all numeric, enumeration, and physical object types. Types which are made up of real numbers, integer, quantities with associated physical units such as times, and object which are made up of character literals or identifiers are all scalar types.

1.11.1.1 Integer Types

Integers are the unbounded set of positive and negative whole numbers.

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32 bit limitation restricts range. Upper and lower range constraints must be integer range. Declaration format: TYPE type_name IS RANGE int_range_constraint; Predefined integer type: TYPE integer IS RANGE –2147483648=[ -2 (32-1) ] TO 2147483647 = [2 (32-1) -1];

RANGE

Identifies subset of values. May be used with type declarations or object declarations Format: RANGE begin direction end Direction may be: Ascending - TO Descending - DOWNTO Examples:

TYPE day IS RANGE 1 TO 31; TYPE voltage IS RANGE 12 DOWNTO -12; SIGNAL in_volts:voltage RANGE 5 DOWNTO 0; -- object declaration

with range a subset of the full range of voltage.

When the range clause does not appear in an object declaration, the object assumes the full range of the type which appears in them declaration.

Example :

SIGNAL output : voltage means that output ranges from 12 to -12.

1.11.1.2 Floating Point Types

Floating Points are the unbounded set of positive and negative numbers which contain a decimal point. 32 bit limitation restricts range. Upper and lower range constraints must contain a decimal point. Declaration format: TYPE type_name IS RANGE range_constraint; Predefined floating point type: TYPE REAL IS RANGE -1.79769E308 TO 1.79769E308; --CADENCE TYPE REAL IS RANGE –9.9e99 TO 9.9e99; --Simplorer

1.11.1.3 Enumeration Types

Lists of identifiers or character literals. Identifiers follow standard naming rules Character literals are all upper and lower case alpha characters numbers, and special characters. Declaration Format: TYPE type_name IS (enumeration_ident_list); Predefined enumeration types: TYPE BIT IS (`0','1'); TYPE BOOLEAN IS (false,true); TYPE SEVERITY_LEVEL IS (note,warning,error,failure); TYPE CHARACTER IS (character_set_used_by_the_system); TYPE DOMAIN_TYPE IS (quiescent_domain, time_domain, frequency_domain);

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Examples:

TYPE Two_level_logic IS (`0','1'); TYPE Three_level_logic IS (`0','1','Z'); TYPE Four_level_logic IS (`X','0','1','Z'); TYPE Opcode IS (Add,Add_with_carry,Sub,Sub_with_carry,Complement); TYPE qsim_state IS (`0','1','X','Z');

1.11.1.4 Physical Types

Describes objects in terms of a base unit, multiples of base unit, and a specified range. Declaration format: TYPE type_name IS RANGE range_constraints UNITS base_unit; [ -- multiples;] END UNITS; Predefined physical type: TYPE time IS RANGE –2147483648 TO 2147483647 ; --CADENCE TYPE time IS RANGE –9.9e99 TO 9.99e99 ; --Simplorer

UNITS fs; --femtosecond =10-15 sec ps = 1000 fs; --picosecond =10-12 sec ns = 1000 ps; --nanosecond =10-9 sec us = 1000 ns; --microsecond =10-6 sec ms = 1000 us; --millisecond =10-3 sec sec =1000 ms; --second min =60 sec; --minute hr =60 min; --hour END UNITS;

Example:

TYPE Resistance IS RANGE 1 TO 10E9 UNITS ohm; --the base unit. kohm=1000 ohm; --secondary unit, multiple of base unit. END UNITS;

1.11.1.5 Scalar Subtypes

Subsets of specified types Do not define new types Range constraints must be within defining type's range. Declaration format: SUBTYPE name IS type_name RANGE constraints; Predefined scalar subtypes: SUBTYPE natural IS integer RANGE 0 TO 2147483647; SUBTYPE positive IS integer RANGE 1 TO 2147483647; A subtype declares a contiguous subset of values of a specified type.

1.12 Composite Types

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There are two kinds of composite types: arrays and records.

1.12.1 Array Types

Multiple values of same type under single identifier. One or more dimensions. (Autologic only support 2D). Values referenced by indices. Indice's type must be integer or enumeration. Declaration format: TYPE array_type_name IS ARRAY (range_constraints) OF type; Predefined array types: TYPE string IS ARRAY (positive RANGE <>) OF character; TYPE bit_vector IS ARRAY (natural RANGE <>) OF bit; Example:

TYPE Column IS RANGE 1 TO 80; TYPE Row IS RANGE 1 TO 24; TYPE Matrix IS ARRAY (Row,Column) OF boolean;

Array Range: Constrained or unconstrained.

Boundaries of constrained array are stated: TYPE array_1 IS ARRAY (integer RANGE -10 TO 25) OF bit; TYPE array_1_too IS ARRAY (-10 TO 25) OF bit; (NOTE: integer is optional) Boundaries of unconstrained array are left open: TYPE array_2 IS ARRAY (integer RANGE <>) OF bit; Boundaries can be enumerated types: TYPE pet IS (dog,cat,bird,horse,kid); TYPE pet_it IS ARRAY (pet RANGE dog TO cat) OF bit; TYPE pet_too IS ARRAY (pet RANGE <>) OF bit;

Array Subtypes:

Subsets of specified array types.Do not define a new array type.TYPE that SUBTYPE is based on must be an unconstrained array.Declaration format: SUBTYPE name IS (array_name RANGE range_constraint);

Example:

TYPE data IS ARRAY (natural RANGE <>) OF bit; SUBTYPE low_range IS (data RANGE 0 TO 7); SUBTYPE high_range IS (data RANGE 8 TO 15);

There are several advantages of subtypes. The primary advantage is to clarify what is being done in the model. They make it easier to visualize what is being stored and why by breaking large groupings of values into smaller groupings. Each "smaller grouping" can have a name which more descriptively tells what values it represents.

Array Slices:

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Consecutive positions of one-dimensional arrays. Created by by appending a parenthesized discrete range to the name of the one-dimensional array.

Example:

TYPE Byte IS ARRAY (7 DOWNTO 0) OF bit; TYPE Memory IS ARRAY (0 TO 2**16-1) OF Byte;

SIGNAL S_byte: Byte; SIGNAL S_memory:Memory;

S_byte(0) -- refers to element 0 S_byte(3 DOWNTO 1) -- slice of three elements S_memory(2**15-1 TO 2**16-1) -- slice of 2**15 elements S_byte - refers to the entire array.

Example of using slice names:

PROCESS TYPE ref_array IS ARRAY(positive RANGE<>)OF Integer; VARIABLE array_a:ref_array(1 TO 12); VARIABLE array_b:ref_array(1 TO 4); BEGIN FOR i IN 1 TO 12 LOOP array_a(i):=i+10; END LOOP; array_b:=array_a(6 TO 9) END PROCESS;

Array Example:

TYPE bit_nibble IS ARRAY(3 DOWNTO 0) OF BIT;TYPE bit_byte IS ARRAY(7 DOWNTO 0) OF BIT;SIGNAL sq4: bit_nibble;SIGNAL sq8: bit_byte;

sq4 <= sq8(2)&sq8(3)&sq8(4)&sq(5); -- reversing sq8 into sq4sq8 <= sq(0)&sq8(7 DOWNTO 1) -- rotate right sq8 by 1sq8 <= sq8(6 DOWNTO 0)&sq8(7) -- rotate left sq8 by 1

Array Initialization:

1. Initial values for a one-dimensional array type signal must be placed in a set of parenthesis and should follow the := symbol in the signal declarations. The initial values of individual array elementsshould be separatedby commas.

SIGNAL sq4: bit_nibble :=(`1','0','1','1');

2. Nested sets of parentheses as should be used for multi-dimensional arrays. In this case, the top level set of parentheses corresponds to the left-most range of the array.

TYPE bit_4by8 IS ARRAY(3 DOWNTO 0, 0 TO 7) OF BIT;SIGNAL sq_4_8: bit_4by8 :=

((`0','0','0','0','1','1','1','1'),(`0','0','0','1','1','1','1','1')

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(`0','0','1','1','1','1','1','1')(`0','1','1','1','1','1','1','1')

);

Computer Memory Example:

TYPE memory IS ARRAY(0 TO 11) OF std_logic_vector(0 TO 7);SIGNAL M: memory :=

("00000001", "00000010", "11001100", "00000011", "00001001","00000100", "00001010", "00000101", "00001011", "11101110", "00000000", "00000010");

1.12.2 Predefined Array Attributes

A’LEFT – leftmost subscript of array A A’RIGHT – rightmost subscript of array A A’HIGH – highest subscript of array A A’LOW – lowest subscript of array A A’RANGE – range A’LEFT TO A’RIGHT or A’LEFT DOWNTO A’RIGHT A’REVERSE_RANGE – range of array A with TO and DOWNTO reversed A’LENGTH – integer value of the number of elements in array A A’ASCENDING –boolean TRUE if range of array A is defined with TO, FALSE otherwise

Example:

SIGNAL ray:BIT_VECTOR(0 TO 7);

ray'LEFT - returns 0 ray'RIGHT - returns 7 ray'HIGH - returns 7 ray'LOW - returns 0 ray'RANGE - returns 0 TO 7 ray'REVERSE_RANGE - returns 7 DOWNTO 0 ray'LENGTH - returns 8 ray’ASCENDING -returns TRUE

`RIGHT and `HIGH return the same value when the range is declared as "value TO value". In this case the highest index value appears on the right side ofrange declaration. However, if the range is declared as "value DOWNTO value", the highest appears on the left side of the declaration. In this case `RIGHT and `HIGH would return different values. The same explanation applies to `LEFT and `LOW.

Example:

TYPE array2 IS ARRAY(Integer RANGE <>,Integer RANGE <>) OF Integer; VARIABLE matrix:Array2(1 TO 3, 9 DOWNTO 6) matrix'high(1) -- returns 3 matrix'high(2) -- returns 9 matrix'left(1) -- returns 1 matrix'left(2) -- returns 9

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Array Attribute Supported for synthesis‘high[(n)] Yes‘left[(n)] Yes‘length[(n)] Yes‘low[(n)] Yes‘range[(n)] Yes‘reverse_range[(n)] Yes‘right[(n)] Yes

1.12.3Record Types

Records are heterogeneous composite types; that is, the elements of a record can be of various types. A record type definition specifies one or more elements, each element having a different name and

possibly a different type. Declaration format: RECORD element_declaration {element_declaration} END RECORD;

Example:

TYPE Opcode IS (Add,Add_with_carry,Sub,Sub_with_carry,Complement); TYPE Address IS RANGE 16#0000# TO 16#FFFF#; TYPE Instruction IS RECORD Op_field :Opcode; Operand_1 :Address; Operand_2 :Address; END RECORD;

1.12.4 Referencing Elements of Composites

An object of a composite type may be referenced in its entirety or by element. A simple name of an array or record is a reference to the entire array or record. An Indexed name is used to reference an element of an array. An indexed name consists of the name

of the object, followed by a parenthesized list of index expressions, one index expression for each dimension of the array.

Example:

TYPE Column IS RANGE 1 TO 80; TYPE Row IS RANGE 1 TO 24; TYPE Matrix IS ARRAY (Row,Column) OF boolean; SIGNAL S: Matrix;

S(1,1) --reference element (1,1) S(3,14) --reference element (3,14)

A selected name is a reference to an element of a record. A selected name consists of the name of the object, followed by a dot (.), followed by the field name of the record.

Example:

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TYPE Fraction IS RECORD Numerator: Integer; Denominator: Integer; END RECORD;

SIGNAL S: Fraction;

S.Numerator --reference numerator field of S. S.Denominator --reference denominator field of S.

REFERENCES

1. “Analog and Mixed-Signal Modeling Using the VHDL-AMS Language”, E.C. Beaverton et.al., 36th Design Automation Conference, New Orleans, June 21-25, 1999.

2. “Simulation System SIMPLORER VHDL-AMS Tutorial,” English Edition, © 2003 Ansoft Corporation.

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