VHDL – Fundamental concepts

8/8/2019 VHDL Fundamental concepts

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VHDL Fundamental concepts

Dept. of E&C, NITKS August 2006

Basic language organisation

a

b

cin

sum

cout

fa


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fulladder.vhdentity FullAdder is

port (a, b, cin : in bit; sum, cout : out bit);

end FullAdder;

architecture FullAdder_eqns ofFullAdder is

begin

sum


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entityentity entity_name is

port (signal_name : mode signal_type;

..

);

end entity_name;

mode - signal direction in out buffer inout

port

identifier , reserved words -not case sensitive

signal_type - built in or user defined


architecture body

architecture fa_eqns offa is

begin

sum


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Concurrent signal assignment statements

Output changes value whenever any of thesignals on the right change value

Textual order has no effect on order ofexecution

int1


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architecture As a set of concurrent assignment statements

dataflow

As a set of interconnected components

Structure

As a set of sequential statements

behaviour


Language organisation

Types

Objects

Expressions

Statements

DU

Lib Design units are conceptually stored inlibraries

Statements are contained in design units

Statements describe functionality

Expressions combine operations withobjects to yield new values

Objects hold values of defined data types

Predefined or user defined data types


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Design units Primary design units

Entity declaration

Package declaration

Configuration declaration

Secondary design units

Architecture body

Package body


Structural model of a 4 bit adder


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Structural model of a 4 bit adderentityAdder4 isport (A, B: in bit_vector(3 downto 0); Ci: in bit; -- Inputs

S: out bit_vector(3 downto 0); Co: out bit); -- OutputsendAdder4;

architecture Structure ofAdder4 iscomponent FullAdderport (X,Y, Cin: in bit;

Sum, Cout: out bit);end component;signal C: bit_vector(3 downto 1);begin --instantiate four copies of the FullAdder

FA0: FullAdder port map (A(0), B(0), Ci, S(0), C(1));FA1: FullAdder port map (A(1), B(1), C(1), S(1), C(2));FA2: FullAdder port map (A(2), B(2), C(2), S(2), C(3));FA3: FullAdder port map (A(3), B(3), C(3), S(3), Co);

end Structure;


signal named wire in logic diagram Read or written to within architecture

component declaration ports declared as in entity virtual design entities

component instantiation creates an instance of the component port map defines interconnections

Positional association FA0: FullAdder port map (A(0), B(0), Ci, C(1), S(0));

Named association FA0: FullAdder port map (X => A(0), Y => B(0), Sum

=>S(0), Cin => Ci, Cout => C(1));


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Behavioral model of adderlibrary IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_arith.all;

entity vadd isport (A, B: in unsigned (3 downto 0); -- Inputs

S: out unsigned (4 downto 0);); -- Outputsend vadd;architecture behav ofvadd isbegin

add: process (A,B)

S


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Mixed Example - multiplier

shift_reg

reg

shift_adder

control_section

multiplier multiplicand

product


entity multiplier is

port ( clk, reset : in bit;multiplicand, multiplier : in integer;

product : out integer );end entity multiplier;

architecture mixed of mulitplier is

signal partial_product, full_product : integer;signal arith_control, result_en, mult_bit, mult_load : bit;

begin

arith_unit : entity work.shift_adder(behavior)port map ( addend => multiplicand, augend => full_product,

sum => partial_product,

add_control => arith_control );

result : entity work.reg(behavior)port map ( d => partial_product, q => full_product,

en => result_en, reset => reset );

...


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multiplier_sr : entity work.shift_reg(behavior)port map ( d => multiplier, q => mult_bit,

load => mult_load, clk => clk );

product


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Basic Design MethodologyRequirements

SimulateRTL Model

Gate-level

Model

Synthesize

Simulate Test Bench

ASIC or FPGA Place & Route

Timing

ModelSimulate


Analysis

Check for syntax and semantic errors

syntax: grammar of the language

semantics: the meaning of the model

Analyze each design unitseparately

entity declaration

architecture body

best if each design unit is in a separate file

Analyzed design units are placed in a library

in an implementation dependent internal form

current library is called work


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Elaboration

Flattening the design hierarchy

create ports

create signals and processes within architecture body

for each component instance, copy instantiated entity andarchitecture body

repeat recursively

bottom out at purely behavioral architecture bodies

Final result of elaboration

flat collection of signal nets and processes


Elaboration Example

int_clk

d0

d1

d2

d3

en

clk

q0

q1

q2

q3

bit0

d_latch

d

clk

q

bit1

d_latch

d

clk

q

bit2

d_latch

d

clk

q

bit3

d_latch

d

clk

q

gate

and2

a

b

y

reg4(struct)


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Elaboration Example

int_clk

d0

d1

d2

d3

en

clk

q0

q1

q2

q3

bit0

bit1

bit2

bit3

gate

reg4(struct)d_latch(basic)

d

clk

q

d_latch(basic)

d

clk

q

d_latch(basic)

d

clk

q

d_latch(basic)

d

clk

q

and2(basic)

a

b

y

process with variables

and statements


Simulation

Execution of the processes in the elaborated model

Discrete event simulation

time advances in discrete steps

when signal values changeevents

A processes is sensitive to events on input signals

specified in wait statements

resumes and schedules new values on output signals schedules transactions

event on a signal if new value different from old value


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Simulation Algorithm

Initialization phase

each signal is given its initial value

simulation time set to 0

for each process

activate

execute until a wait statement, then suspend

execution usually involves scheduling transactions on

signals for later times


Simulation Algorithm

Simulation cycle

advance simulation time to time of next transaction

for each transaction at this time

update signal value

event if new value is different from old value

for each process sensitive to any of these events, or whosewait for time-out has expired

resume

execute until a wait statement, then suspend

Simulation finishes when there are no furtherscheduled transactions


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Synthesis

Translates register-transfer-level (RTL) designinto gate-level netlist

Restrictions on coding style for RTL model

Tool dependent

Documents

VHDL – Fundamental concepts