Vignan BTech Syllabus.pdf

CONTENT

Page No

1 Academic calendar 2

2 Pulse & Digital Circuits 3

3 Switching Theory & Logic Design 54

4 Electronic Circuit Analysis 102

5 Electromagnetic Theory & Transmission Lines 149

6 Principles Of Electrical Engineering 195

7 Pulse & Digital Circuits Laboratory 250

8 Electronic Circuit Analysis Laboratory 252

9 Electrical Engineering Laboratory 255

ACADEMIC CALENDAR

Note: class review meeting for II and III year students and faculty on every Thursday at 1:00 pm onwards Cc: principal All staff members HOD,ECE

VIGNAN INSTITUTE OF TECHNOLOGY AND SCIENCE

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

DEPARTMENT ACADEMIC CALENDAR

B. Tech Academic Year 2013 - 2014 - II - Semester

S.No Event Date

1. Submission of abstracts of main project by IVth

years 16-12-13

2. Faculty orientation program 28-11-13 to 05-12-13

3. Commencement of Class work 09-12-13

4. Spell for UNIT I Instructions 09-12-13 to 21-12-13

5. Freshers day 14-12-13

6. Spell for UNIT II Instructions 23-12-13 to 04-01-14

7. Alumni meet 29-12-13

8. VIGNAN TARANG 02-01-14 to 04-01-14

9. Spell for Unit-III Instructions 06-01-14 to 25-01-14

10. Assignment -1/ Unit test-1 on Ist

& IInd

Units 06-01-14 to 10-01-14

11. Submission of results & week students list to Dept 20-01-14

12. Spell for Unit-IV Instructions 27-01-14 to 07-02-14

13. University I-Mid-Exam- II & IV Year 10-02-14 to 12-02-14

14. University I-Mid-Exam- IIIrd

Year 13-02-14 to 15-02-14

15. Spell for UNIT V Instructions for II &IV years 13-02-14 to 25-02-14

16. Spell for UNIT V Instructions for IIIrd

year 17-02-14 to 27-02-14

17. LAB INTERNAL-1 17-02-14 to 22-02-14

18. Commencement of Special classes for Slow learners 24-02-14

19. Spell for UNIT VI Instructions for II &IV years 26-02-14 to 10-03-14

20. Spell for UNIT VI Instructions for IIIrd

year 01-03-14 to 12-03-14

21. Submission of Mini project title along with guide for IIIrd

year 04-03-13

22. Spell for Unit VII Instructions for II &IV years 11-03-14 to 24-03-14

23. Spell for UNIT VII Instructions for III year 13-03-14 to 27-03-14

24. Assignment-II / Unit test on Vth & VIth Units 17-03-14 to 21-03-14

25. Submission of results & week students list to Dept 19-03-14 to 22-03-14

26. Spell for Unit- VIII Instructions for II & IV year 25-03-14 to 05-04-14

27. Spell for Unit- VIII Instructions for III year 28-03-14 to 09-04-14

28. Thanks giving party 01-04-14

29. Farewell to final years from staff and pre final years and student memoir distribution

03-04-14

30. LAB INTERNAL-2 24-03-14 to 29-03-14

31. University II-Mid-Exam- II & IV Year 07-4-14 to 09-4-14

32. University II-Mid-Exam- III Year 10-4-14 to 12-4-14

33. Practical Examinations for II Year 10-04-14to 14-04-14

34. Final Project demo and draft copy submission 28-03-14

35. Practical Examinations for III Year 15-04-14 to 17-04-14

36. EXTERNAL PROJECT VIVA (IV years) 15-04-14

37. End Semester Examination 21-04-14 to 03-05-14

38. Commencement of next semester 16-06-14

PULSE &DIGITAL CIRCUITS

MS. VijayALAXMI

Associate. Professor &

Mrs.P.Padmaja Assistant Professor

COURSEFILE

Department of

ELECTRONICS AND COMMUNICATION ENGINEERING

VIGNAN INSTITUTE OF TECHNOLOGY AND SCIENCE VIGNAN HILLS, DESHMUKHI VILLAGE, POCHAMPALLY (MANDAL)

NALGONDA (DISTRICT) - 508284

Sponsored by

Lavu Educational Society (Approved by AICTE and Affiliated to JNT University, Hyderabad)

COURSE OBJECTIVE

Pulse and Digital Circuits Course Objective

Vignan Institute of Technology & Science II Year B.Tech. 2nd Semester Page 5

COURSE OBJECTIVE

1. To understand the concepts of wave shaping and to design various circuits for any application.

2. Understand the principles of digital electronics and abstractions on which the design of digital

systems is based. These include TTL and CMOS digital systems.

3. Use these engineering abstractions to analyze and design simple digital circuits.

4. Build digital logic gates and take measurements of such parameters as propagation delay, noise

margins, fan-out. Compare the measurements with the behavior predicted by mathematic models

and explain the discrepancies.

5. Understand the relationship between the mathematical representation of circuit behavior and

corresponding real-life effects.

6. Obtain V-I characteristics of TTL and CMOS inverters and determine their noise margins.

7. Understand the operation of various memory units.

8. Implement multivibrators/timing circuits of specified duty cycles.

9. Understand the principle and operation of BiCMOS and GaAs circuits.

10. Learn VLSI fabrication techniques.

11. Appreciate the practical significance of the systems developed in the course.

12. Understand the, transistor switch, and logic families of TTL and CMOS.

13. Understand how to use and implement ADC and DAC, and how to design the timing circuits.

14. To provide the student with an understanding of the transistor level design of the most

commonly used BJT and MOSFET logic families. Emphasis is placed on design and analysis of

the logic gate hardware rather than logic design via inter-connection of standard gates. Dynamic

response of the logic gates and other specialized pulse and switching circuits is a key topic

including transmission line effects for high frequency circuits.

Syllabus

Pulse and Digital Circuits Syllabus


SYLLABUS

UNIT I:LINEAR WAVESHAPING:

High pass, low pass RC circuits, their response for sinusoidal, step, pulse, square and ramp

inputs. RC network as differentiator and integrator, attenuators, its applications in CRO probe, RL

and RLC circuits and their response for step input, Ringing circuit

UNIT II: NON-LINEAR WAVE SHAPING :

Diode clippers, Transistor clippers, clipping at two independent levels, Transfer characteristics of

clippers, Emitter coupled clipper, Comparators, applications of voltage comparators, clamping

operation, clamping circuits using diode with different inputs, Clamping circuit theorem, practical

clamping circuits, effect of diode characteristics on clamping voltage, Transfer characteristics

of clampers.

UNIT III: SWITCHING CHARACTERISTICS OF DEVICES:

Diode as a switch, piecewise linear diode characteristics, Transistor as a switch, Break down voltage

consideration of transistor, saturation parameters of Transistor and their variation with temperature,

Design of transistor switch, transistor-switching times.

UNIT IV: MULTIVIBRATORS :

Analysis and Design of Bistable, Monostable, Astable Multivibrators and Schmitt trigger using

transistors

UNIT V: TIME BASE GENERATORS :

General features of a time base signal, methods of generating time base waveform, Miller and

Bootstrap time base generators basic principles, Transistor miller time base generator,

Transistor Bootstrap time base generator, Current time base generators.

UNIT VI: SYNCHRONIZATION AND FREQUENCY DIVISION :

Principles of Synchronization, Frequency division in sweep circuit, Astable relaxation circuits, Monostable

relaxation circuits, Synchronization of a sweep circuit with symmetrical signals, Sine wave frequency

division with a sweep circuit.

UNIT- VII: SAMPLING GATES:

Basic operating principles of sampling gates, Unidirectional and Bi-directional sampling gates,

Reduction of pedestal in gate circuits, Applications of sampling gates.

UNIT-VIII: REALIZATION OF LOGIC GATES USING DIODES & TRANSISTORS:

AND, OR gates using Diodes, Resistor, Transistor Logic, Diode Transistor Logic.

Pulse and Digital Circuits Syllabus


TEXT BOOKS

1. Pulse, Digital and Switching Waveforms - J. Millman and H. Taub, McGraw-Hill, 1991.

2. Solid State Pulse circuits - David A. Bell, PHI, 4th Edn., 2002 .

REFERENCE BOOKS

1. Pulse and Digital Circuits A. Anand Kumar, PHI, 2005.

2. Wave Generation and Shaping - L. Strauss.

3. Pulse, Digital Circuits and Computer Fundamentals - R.Venkataraman.

WEBSITES

1. http://www.onsemi.com/

2. http://www.kpsec.freeuk.com/symbol.htm

3. http://buildinggadgets.com/index_circuitlinks.htm

4. http://www.guidecircuit.com/

JOURNALS

1. IEEE Transaction on Electronic Devices (ISSN: 0018-9383)

2. Journal of Active and Passive Electronic Devices (ISSN: 1555-0281)

3. International Journal of Micro and Nano Electronics, Circuits and Systems (ISSN: 0975-4768)

4. Active and Passive Electronic Components (ISSN: 0882-7516)

5. Journal of Electronic Testing (ISSN: 0923-8174)

STUDENT'S SEMINAR TOPICS

Pulse and Digital Circuits Seminar Topics


STUDENTS SEMINAR TOPICS

1. High pass filter response for square-wave input

2. Ringing circuits

3. Zener slicer working

4. Diode Switching times

5. Triggering methods of bistable multivibrator

6. UJT relaxation oscillator

7. Principles of Synchronization

8. Working principle and VI characteristics of UJT

9. Miller time base generators basic principles

10. Bootstrap time base generators basic principles

LECTURE PLAN

Pulse and Digital Circuits Lecture Plan

Vignan Institute of Technology & Science II B.Tech 1st Semester Page 12

LECTURE PLAN

S.No NAME OF THE TOPIC

Proposed Date

No of

Periods

Method of Teaching

Actual Date of Completion Remarks

UNIT I:LINEAR WAVESHAPING

1. Introduction 1 ---

2. Introduction to PDC 1 Black board and Chalk ---

3. LINEAR WAVESHAPING: Introduction 1 Black board and Chalk

4. Different types of inputs 1 Black board, Chalk and LCD Projector

5. Response of high pass and low pass circuits for: Sine input 1 Black board and Chalk

6. Step and Pulse input 1 Black board and Chalk

7. Square input 1 Black board and Chalk

8. Ramp input 1 Black board and Chalk

9. Attenuators 1 Black board and Chalk

10. Applications of attenuators in CRO probe 1 Black board and Chalk

11. Response of RL circuits for step input 1 Black board, Chalk and LCD Projector

12. Response of RLC circuit for step input 1 Black board and Chalk

13. Ringing circuits 1 Black board and Chalk

UNIT II: NON-LINEAR WAVE SHAPING

14. NON LINEAR WAVE SHAPING: Introduction 1 Black board and Chalk

15. Diode clippers 1 Black board and Chalk

16. Clipping circuits 1 Black board and Chalk


Vignan Institute of Technology & Science II B.Tech2 ndSemester Page 13

17. Transistor clipper 1 Black board and Chalk

18. Analysis of waveforms 1 Black board and Chalk

19. Clipping at two independent levels 1 Black board and Chalk

20. Transfer characteristics of clippers 1 Black board and Chalk

21. Emitter coupled clipper 1 Black board and Chalk

22. Comparators 1 Black board and Chalk

23. Applications of voltage comparators 1 Black board and Chalk

24. Clamping operation 1 Black board and Chalk

25. Clamping circuits using diode with different inputs 1 Black board and Chalk

26. Practical clamping circuits 1 Black board, Chalk and LCD Projector

27. Effect of diode characteristics on clamping voltage 1

UNIT III: SWITCHING CHARACTERISTICS OF DEVICES

28. Diode as a switch, piecewise linear diode characteristics 1 Black board, Chalk and LCD projector

29. Transistor as a switch 1 Black board, Chalk and LCD Projector

30. Breakdown voltage consideration of transistor 1 Black board, Chalk and LCD Projector

31. Saturation parameter of transistor and their variation with temperature 1 Black board, Chalk and LCD Projector

32. Design of transistor switch 1 Black board, Chalk and LCD Projector

33. Transistor switching times 1 Black board, Chalk and LCD Projector

UNIT IV: MULTIVIBRATORS

34. Multivibrators 1 Black board and Chalk

35. Analysis of Bistable multivibrators. 1 Black board and Chalk



36. Design of Bistable Multivibrators 1 Black board and Chalk

37. Analysis monostable Multivibrators 1 Black board and Chalk

38. Design monostable Multivibrators 1 Black board and Chalk

39. Analysis astable Multivibrators 1 Black board and Chalk

40. Design astable Multivibrators 1 Black board and Chalk

41. Schmitt trigger using transistors 1 Black board and Chalk

UNIT V: TIME BASE GENERATORS

42. General features of a time base signal 1 Black board and Chalk

43. Methods of generation of time base waveform 1 Black board and Chalk

44. Miller time base generator. 1 Black board and Chalk

45. Bootstrap time base generator 1 Black board and Chalk

46. Transistor miller time base generator 1 Black board and Chalk

47. Transistor bootstrap time base generator 1 Black board and Chalk

48. Current time base generator 1 Black board and Chalk

UNIT VI: SYNCHRONIZATION AND FREQUENCY DIVISION

49. Principles of Synchronization, frequency division 1 Black board and Chalk

50. Frequency division in sweep circuit 1 Black board, Chalk and LCD Projector

51. Synchronization in astable relaxation circuits 1 Black board and Chalk

52. Synchronization in monostable relaxation 1 Black board and Chalk

53. Frequency division in monostable relaxation circuits 1 Black board, Chalk and LCD Projector

54. Frequency division in astable relaxation circuits 1 Black board and Chalk



55. Synchronization of a sweep circuit with symmetrical signals 1 Black board and Chalk

56. Sine wave frequency division with a sweep circuit 1 Black board and Chalk

UNIT- VII: SAMPLING GATES

57. Basic operation principles of sampling gates 1 Black board and Chalk

58. Unidirectional sampling gates 1 Black board and Chalk

59. Bi- directional sampling gates using diode 1 Black board and Chalk

60. Reduction of pedestal in gate circuits 1 Black board and Chalk

61. Bi- directional sampling gates using transistor 1 Black board and Chalk

62. Four diode and six diode sampling gate 1 Black board and Chalk

63. Application of sampling gates. 1 Black board and Chalk

UNIT-VIII: REALIZATION OF LOGIC GATES USING DIODES & TRANSISTORS

64. Introduction to logic gates 1 Black board and Chalk

65. OR, AND & NOT gate using diodes and transistors. 1 Black board and Chalk

66. Transistor logic 1 Black board and Chalk

67. Diode transistor logic 1 Black board, Chalk and

LCD Projector

68. Totempole nand gate 1 Black board, Chalk and

LCD Projector

69. Comparision of all logical families, Problems 1 Black board and Chalk

70. Revision on I and II Units 1 Black board and Chalk

71. Revision on III and IV Units 1 Black board and Chalk

72. Revision on V and VI Units 1 Black board and Chalk

73. Revision on VII and VIII Units 1 Black board and Chalk

LEARNING OBJECTIVES

Pulse and Digital Circuits Learning Objective

Vignan Institute of Technology & Science II B.Tech2 nd Semester Page 17

LEARNING OBJECTIVES

UNIT I: LINEAR WAVE SHAPING At the conclusion of this unit student will

1. Define linear wave shaping.

2. Explain low pass RC circuit

3. Explain high pass RC circuit.

4. Explain different types of inputs signals.

5. Explain RC network as differentiator.

6. Explain RC network as integrator.

7. Define attenuators.

8. Explain RL and RLC circuits.

9. Define ringing circuit.

UNIT II: NON LINEAR WAVE SHAPING At the conclusion of this unit student will

1. Explain diode clippers.

2. Explain clipping at two independent levels using diode.

3. Explain positive clipper.

4. Explain negative clipper.

5. Explain single ended clipping circuits.

6. Explain transistors clippers.

7. Define comparator.

8. Explain voltage comparator circuits.

9. Define clamping.

10. Explain clamping circuit theorem

11. Explain positive clamping.

12. Explain negative clamping.

13. Explain transfer characteristics of clamper.

14. Explain the function of rectifier

UNIT III: SWITHING CHARACTERISTICS OF DEVICES At the conclusion of this unit student will

1. Name the devices that can be used as switches.

2.Explain how a diode acts as a switch.

3.Define forward recovery time.



4.Define reverse recovery time.

5.Define storage time of a diode.

6.Define transition time of a diode.

7.Explain avalanche break down.

8.Explain zener break down.

9.Justify the transistor acts as a switchList out the applications of BJT

10.Explain the three region of operation of a transistor.

11.When does the transistor acts as a closed switch and an open switch.

12.Define rise time.

13.Define storage time.

14.Define fall time.

15.Explain diode switching time.

16.Explain transistor switching time.

UNIT IV: MULTIVIBRATORS At the conclusion of this unit student will

1.Define multivibrator.

2.Discuss the types of multivibrator.

3.Define dc coupling.

4.Discuss the application of bistable multivibrator.

5.Explain the stable state of a binary.

6.Define loop gain.

7.Explain collector catching diodes.

8.Write a short note communicating capacitor.

9.Define resolving time.

10.Define settling time.

11.Define resolution time.

12.Define transition time.

13.Define triggering.

14.Explain symmetrical triggering.

15.Explain unsymmetrical triggering.

16.Explain Schmitt trigger.

17.Define the term upper triggering point.

18.Define the term lower triggering point.

19.Define ac coupling.

20.Define quasi stable state.

21.Explain monosatable multivibrator.



22.Explain astable multivibrator.

Unit V: TIME BASE GENERATORS

At the conclusion of this unit student will

1.Why time circuits are called sweep circuits.

2.List the application of time base generators.

3.Define sweep time.

4.Define restoration time.

5.Define slope error.

6.Define displacement error.

7.Define transmission error.

8.Drive the relation between different types of errors.

9.Explain the methods of generating a time base waveform.

10.Explain the principle of miller ad boot strap time base generators.

11.Explain the working of transistor current time base generators.



1.Explain the principles of synchronization.

2.Explain synchronization on one to one basis.

3.Explain synchronization with frequency division.

4.Explain relaxation circuit. Give some example of it.

5.Name some negative resistance used in relaxation oscillators.

6.Explain synchronization of sweep generator with pulse signals.

7.Explain how the synch signal affects the frequency of operation of the sweep generator.

8.Explain frequency division with respect to a sweep circuit.

9.Explain frequency division by an astable blocking oscillator.

10.Explain frequency division by an astable mutlivibrator.

11.Explain synchronization of a sweep circuit with symmetrical signals.

12.Compare sine wave synchronization with pulse synchronization.

UNIT- VII: SAMPLING GATES


1.Explain sampling gates.



2.Why sampling gates are called as linear gates.

3.Differentiate sampling gate and logic gates.

4.Explain unidirectional sampling gate.

5.Explain bidirectional sampling gate.

6.Define gate signal.

7.Define pedestal.

8.Explain the working of bidirectional gates using transistor.

9.Explain the working of four diode gate.

10.Explain the working of six diode gate.

UNIT-VIII: LOGIC GATES


1.Draw the OR logic using diodes.

2.Draw the AND logic using diodes.

3.Draw the NOT logic using transistor.

4.Explain the transistor logic.

5.Explain diode transistor logic.

II Year B.Tech. 1st Semester

OBJECTIVE TYPE

QUESTIONS

Pulse and digital circuits Objectives Questions


OBJECTIVE TYPE QUESTIONS

UNIT I: LINEAR WAVE SHAPING

1. The response of a high pass RC circuit to a step input of amplitude V is a) V(1-e

-t/RC ) b) Ve

-t/RC ) c) V d)None [ ]

2. The response of a differentiator circuit to a pulse input is a) ramp b) spikes c) square d) none [ ]

3. A High pass RC circuit acts like a differentiator for the condition ( RC = Time constant of the circuit & T= Time period of the input signal ) [ ]

a) RC = T b)RC>>T c) RC 1 b) k < 1 c) k = 1 d) None [ ]

11. The response of a RLC circuit to a step input for damping constant k = 1, corresponds to [ ]

a)over damping b) critical damping c) under damping d) none

12. The response of a series RL circuit to a pulse input for smaller time constant is a) ramp b) exponential c)spikes d) None [ ]

13. Attenuator is used to [ ] a)Reduce the amplitude of a signal b) increase the amplitude of a signal

c) change the frequency of the signal d) none



14) The time constant of a series RL circuit is [ ]

a) LR b) L/R c) R/L d) None

15 The expression for transmission error (et), when ramp input is applied to a High pass

RC circuit for the condition RC >> T is [ ]

a) T/RC b)T/4RC c) T / 8RC d) T / 2RC

16. The expression for transmission error (et ), when ramp input is applied to a Low pass

RC circuit for the condition RC



a) Round shaped edges of input waveform b) No transmission of signal

c) Transmits same signal d) Doubles amplitude of input waveform

11.the negative clamper is also called [ ]

a) Positive peak clamper b) Negative peak clamper c) Positive peak clipper d) Negative peak

clipper

ANSWERS:

1 (d) 2 (b) 3 (c) 4 (b) 5 (b) 6 (d) 7 (c) 8 (d) 9 (d) 10 (a) 11 (a)

UNIT III: SWITHING CHARACTERISTICS OF DEVICES

1.if the transistor is indeed in saturation ,the following condition must be satisfied [ ]

a) ic=iB/hfe(min) b) iB>iC/hfe(min) C) iB=iC+Vce d) iB=iC

2.The reverse saturation current increases approximately for every ------- rise in temperature [ ]

a) 30 c b) 50 c c) 70 c d) 10 c

3. Turn off time of the transistor is =------- [ ]

a) toff =tf +ts b) toff =tf +ton c) toff =tfd +ts d) toff =ton +t.s

4T The reverse saturation current increases approximately for every ------- rise in temperature [ ]

a) 30 c b) 50 c c) 70 c d) 10 c

5) The Vce of the n-p-n transistor is [ ]

a)-0.1v b)0.1v c) 0.7 v d)0 v

6.the capacitance which appears across a reverse biased function of a diode is called [ ]

a) Diffusion capacitance b) Fixed capacitance c) Transition capacitance d) Valuable capacitance

7. common base configurations is little used because [ ]

a) High voltage gain b) High current gain c) It has low input impedance d) High input impedance

8. the Vce (sat) of Si n-p-n transistor at 27 c is [ ]

a) 0.7 v b) 0.3 v c) 0.8 v d) 0.1 v

9. smallest times between two successive triggers is ----------- [ ]

a) Restoring time b) Storage time c) Delay time d) Rise time

10.zener diode has ---------- temperature coefficient [ ]

a) some times positive and sometimes negative b) Only NEGITIVE

c) Both positive and negative d) Only positive

11) Turn off time of the transistor is =------- [ ]

a) toff =tf +ts b) toff =tf +ton c) toff =tfd +ts d) toff =ton +ts

12.when does the transistor act as a closed switch

a) both junctions are forward biased [ ]

b) input junction is reverse biased and output junction is forward biased



c) input junction is forward biased and output junction is reverse biased

d) both junctions are reverse biased

13.when does the transistor act as open swit [ ]

a) input junction is reverse biased and output junction is forward biased

b) both junctions are forward biased c) both junctions are reverse biased

d) input junction is forward biased and output junction is reverse biased

14.transiton capacitance of diode is given as [ ]

a) n/(VB)3 b) /(VB)n c) n/VB d) (VB)n

/

15.the base width in a junction transistor is deliberately chosen small so that [ ]

a) the concentration of injected carrier is small b) the majority carriers easily reachs the collector

c) the electric field s large d) to reduce the recombination of injected minority carriers

16.which of the following is the fastest switching device [ ]

a) MOSFET b) DIODE c) JFET d)BJT

17.in a transistor leakage current mainly depends on [ ]

a) temperature b) minority carriers c)concentration of majority carriers d) none of the above

18.for an ideal p-n junction diode the current I=Io (eV/Vt

-1) than what is the value for Ge [ ]

a)5 b) 15 c) 1 d) 10

19. at constant base and collector current forward B-E voltage has typical temperature sensitivity in the

range of [ ]

a) -7.5 m V /c to -8.0 m V /c b) -1.5 V /c to -2. m V /c c) 1.5m V /c to -2 m V /c d) -7.5 m V /c to 8.0

m V /c

20the maximum reverse biasing voltage which may be applied before breakdown between collector

and base terminals is [ ]

a) BVCEO b) VCE c) VCB d) BVCBO

21.a large signal approximation which often leads to a sufficient accurate solution is the ------------

representation [ ]

a) Ebers model b) Hybrid model c) Pi model d) Piecewise linear

22.in the diode the time required for minority charge carriers to move into the other side of the PN

junction and become majority charge carrier is called [ ]

a) Delay time b) Transition time c) Reverse recovery time d) Storage time

23. the collector to emitter breakdown voltage with base not open ckt is BVCER is given by [ ]

BVCBOn (1-ICORB/V) b) BVCEO (1-ICORB/V) c) BVCBO (1-ICORB/V) d) BVCEO

n (1-ICORB/V)

24. if the VCB of n-p-n transistor in CE configuration is negative when the transistor is in [ ]

a) Active region b) Cut off region c) Saturation region d) Inverted

ANSWERS:



1 (b) 2 (d) 3 (d) 4 (a) 5 (b) 6 (c) 7 (c) 8 (b) 9 (a) 10 (b) 11 (a) 12 (a) 13 (c) 14 (b) 15(d) 16(d)

17 (a) 18 (c) 19 (b) 20 (d) 21 (d) 22(d) 23(a) 24(c)

UNIT IV:MULTIVIBRATORS

1.in a design of fixed bias binary VCC =VBB =12v ,hfe(min)=20, ic sat=4 mA,assume n-p-n(Si) transistor

then Rc is = [ ]

a) 2.925 k b) 200 c) 0.5 k d) 100

2) The duration of quasi stable state of a mono shot is----- [ ]

a) Fall gate b) Gate time c) Storage time d) Recovery time

3. the capacitor which assists the binary in making abrupt transition between states are called [ ]

a)delay b) Storage c) commutating d) translation

4. monostable vibrators generates [ ]

a) Pulse wave form b) Ramp signal c) Sine wave d) Square wave

5. -------- Are basically regenerative circuits comprising of two cross coupled active devices [ ]

a)filters b) Multivibrators c) Attenuators d) Clampers

6.Which one of the following circuits converts any arbitrary waveform into a square wave

a. Monostable Multivibrator b. Bistable Multivibrator [ ]

c. Astable Multivibrator d. Schmitt Trigger

7.The Schmitt Trigger is also called as [ ]

a. emitter coupled binary b. collector coupled binary

c. any of the two d. none

8.The Astable Multivibrator has one of the following applications [ ]

a. voltage to frequency converter b. gating circuit

c. comparator d. none

9. The Monostable Multivibrator has one of the following applications [ ]

a. Schmitt trigger b. gating circuit c. square wave generator d. none

11. The time period of the quasi stable state in a Monostable Multivibrator is given by

a. T=0.69RC b. T=0.63RC c. T=1.38RC d.T=RC [ ]

12.the pulse width or gate width of monoshot is [ ]

a) RC b) 2 RC c) 0.69 RC d)none

13. if VTP=5.12 and LTP =3.312 then the value of hysterisis in schimmit trigger is [ ]

a) 1.81 V b) 5.4 V c) 4.8 V d) 3.2V

14.the commutating capacitor are also called [ ]

a) speed up capacitor b) varicap c) tuning capacitor d) delay capacitor



15. a stable state of binary is one in which the current and voltages satisfy kirrchofs laws and are

constant and the condition satisfied that loop gain is [ ]

a) =1 b) >1 d) >1

16. the schmit trigger can be used as a [ ]

a) filter b) attenuator c) comparator d) clamper

17. a ckt which can indefinitely exist in either of two stable state and which can be induced to make

abrupt transition from one state to other by means of external excitation [ ]

a) monoshot b) oscillator c) binary d) attenuator

18. which of the following is the advantage of emitter coupled over collector coupled multivibrator

a) inherently self starting b) low power dissipation c) less noisy d) only one trigger signal is enough

19.no of triggers required for monostable multi to change from stable state to quasi stable state and vice

versa [ ]

a) 1 b) 2 c) 3 d) 4

20. monostable multi vibrators generates [ ]

a) Square b) Pulse c) Sine d) Ramp

21. find the value of collector resistor in a collector coupled stable multi for the following [ ]

specifications f=10 KHZ ,Vcc=9 V, ic(max) =2 mA,hfe=20

a) 1 b) 4.35 K c) 3 K d) 2K

22.the binary is sometimes referred to as [ ]

a) Nortons ckt b) Eccless Jordon ckt c) Thevinins ckt d) Millimans ckt

ANSWERS:

1 (a) 2 (b) 3 (c) 4 (b) 5 (b) 6 (d) 7 (a) 8 (a) 9 (b) 10 (a) 11 (a) 12 (c) 13 (a) 14 (a) 15 (b) 16 (c) 17 (c) 18 (c) 19 (a) 20 (b) 21 (b) 22(b)


1. The input impedance of bootstrap integrator Is [ ]

(a) low (b) high (c) moderate (d) Too high

2. A set of coil is called as [ ]

(a) magnetic coil (b) LOT (c) yoke (d) sweep coil

3. Sweep speed error is defined as [ ]

(a) initial ramp speed/final ramp speed (b) initial ramp speed-final ramp speed/ initial ramp speed

(c) initial ramp speed +final ramp speed/initial ramp speed (d) final ramp speed/ initial ramp speed

4. Waveform can have either positive slope or negative slope [ ]

(a) Ramp (b) square (c) Trapizoidal (d) Rectangular



5. The variations in phase delay occur due to variations in factors like and [ ]

(a) Q point only (b) current gain & voltage gain (c) Q-point, supply voltage and gain

(d) loop gain, suply voltage and transistor parametres

6. The phenomenon of charging and discharging of a capacitor in a pulse digital circuit is called as

(a) Relaxation circuit (b) Timing circuit (c) Stable circuit (d) unstable circuit [ ]

7. The duration during which the voltage level decreases to the initial level is Known as [ ]

(a) Trace (b) Retrace interval (c) sweep interval (d) Signal reconstruction

8. Difference between the input and output divided by the input is called as [ ]

(a) transistor error (b) et (c) translational error (d) translational & transmission error

9. Current time base generators are used in [ ]

(a) In Radar screen scanning (b) Tv scanning

(c) Sonar application (d) where large raster area is to be scanned

10. In integrator neither terminals of the capacitor are connedcted to ground [ ]

(a) Emitter follower (b) Source follower (c) Bootstrap (d) Miller Integrator

11. The three different stages of ramp waveforms are [ ]

(a) Recycling ,Non-return to zero (b) Rise or fall, recycling arrangement, return to original;

(c) Rise or fall, recycling (d) Recycling only

12. Slope error is given by [ ]

(a) final slope/initial slope (b) initial slope+final slope/final slope

(c) initial slope-final slope/initial slope (d) Initial slope/final slope

13. The biggest disadvantage of Bootstrap using Darlington circuit is [ ]

(a) gain greater than unity (b) gain of the composite amplifier is smaller than each stage

(c) gain less than unity (d) gain of comosite amplifier is too large

14. Millers sweep circuit produces type of waveform [ ]

(a) negative going ramp (b) Sinusodalwave (c) positive going ramp (d) squarewave

15. Millers Integrator generates a ramp voltage [ ]

(a) sinusoidal (b) non-linear (c) linear (d) Cosinusoidal

16. The error arising due to transmission through a linear network is known as .transmisssion error

(a) Transmission error (b) True (c) Sweep error (d) False

17. Current time base generators are used in [ ]

(a) In Radar screen scanning (b) Tv scanning

(c) Sonar application (d) where large raster area is to be scanned

18. For a basic Bootstrap integrator the transistor is connected as [ ]

(a) common base (b) common emitter (c) Common collector configuration (d) emitter follower

19. The maximum deviation in rate of change of sweep voltage with time is called differential linearity



(a) False (b) Sweep voltage (c) Sweep error (d) True

20. The Sweep speed error in a current time base generator is given by [ ]

(a) IL[RL + Rcesat]/Vcc (b) (VCC/RL)IL (c) (RL/VCC) (d) [RL + RCE]/Vcc

ANSWERS:

l (b) 2 (c) 3 (b) 4 (a) 5 (d) 6 (a) 7 (b) 8 (b) 9 (b) 10 (d) 11 (b) 12 (c) 13 (b) 14 (a) 15 (c) 16 (c) 17 (b) 18 (b) 19 (a) 20 (a)


1. If synchronisation is achieved with different frequencies , ie., one Frequency being twice the other

then it is termed as [ ]

(a) No synchronization occurs (b) frequency matching

(c) synchronization (d) synchronisation with frequency division

2. The variations in phase delay are called as [ ]

(a) Sampling gates (b) phase jitters (c) phase shifters (d) Blocking jitters

3. When two generators with equal frequencies run in synchronism the Synchronisation is said to be on

(a) one-to many (b) multiplexing (c) one-to-one basis (d) many to one [ ]

4. When two generators produce waveforms at different frequencies, it is Essential for proper

synchronization that the frequency of one generator is an of that of the other generator. [ ]

(a) odd multiples (b) secondary harmonies (c) even multiples (d) integral multiple

5. If synchronization is achieved with different frequencies , ie., one Frequency being twice the other


(a) frequency matching (b) No synchronization occurs

(c) synchronization (d) synchronization with frequency division

6. When two generators with equal frequencies run in synchronism the Synchronization is said to be on

(a) many to one (b) one-to-one basis (c) one-to many (d) multiplexing

7. The biggest advantage of Triggered sweep circuit is [ ]

(a) slow wave operation (b) Free running operation

(c) Complex operation (d) Fast running operators



(a) No synchronization occurs (b) synchronization (c) frequency matching (d) synchronization

with frequency division

9. A sampling gate is also termed as [ ]



(a) linear gate (b) time-selection gate (c) time selection & linear gates (d) non-linear gate

10. Synchronization of sweep circuit can be obtained by [ ]

(a) Non identical phase signals (b) identical phase signals

(c) Symmetrical signals (d) unsymmetrical signals

11. Monostable relaxation circuit is used as a [ ]

(a) time division (b) both time and frequency

(c) frequency division (d) only frequency multiplexing

12. By making , a divider circuit with a division factor n can be built [ ]

(a) TO < nTp (b) TO > nTp (c) TO = 2nTp (d) TO = nTp

13. Sampling gate for which input voltage is [ ]

(a) dc only (b) Sampling of acsignal (c) ac only (d) Either dc or ac

14. When two generators with equal frequencies run in synchronism the Synchronisation is said to be

on a [ ]

(a) many to one (b) multiplexing (c) one-to many (d) one-to-one basis

15. stray signals are [ ]

(a) Introducing distortion (b) affects synchronization severely

(c) doesnt affect synchronization (d) unwanted noisy signals

16. In a Sinusoidal synchronization signal UJT is used as a switch beause [ ]

(a) negative resistance voltage controlled device(b) negative resistance current controlled device

(c) voltage divider (d) Current divider

17. Synchronization of sweep circuit can be obtained by [ ]

(a) Non identical phase signals (b) Symmetrical signals

(c) identical phase signals (d) unsymmetrical signals

18. Monostable relaxation circuit is used as a [ ]

(a) both time and frequency (b) time division

(c) only frequency multiplexing (d) frequency division


then it is termed n as [ ]

(a) frequency matching (b) No synchronization occurs

(c) synchronization (d) synchronization with frequency division

20. The biggest disadvantage of sampling gate is [ ]

(a) fast rise of control voltage (b) the slow rise of control current

(c) the slow rise of control voltage (d) Risetime fall time

ANSWERS:



1(d) 2 (d) 3 (c) 4 (d) 5 (d) 6 (b) 7 (b) 8 (d) 9 (c) 10 (c) 11 (c) 12 (b) 13 (d) 14 (d) 15 (b) l6 (b) 17 (d) 18 (d) 19 (d) 20 (c)

UNIT- VII :SAMPLING GATES 1. The biggest disadvantage of sampling gate is [ ]

(a) the slow rise of control voltage (b) the slow rise of control current

(c) Rise time fall time (d) fast rise of control voltage

2. The parameters of a Non-ideal switch are [ ]

(a) Digital and analog control (b) Digital switch control

(c) Analog & Digital (d) Analog channel & digital control line control parameters

3. Sampling gate for which input voltage is [ ]

(a) ac only (b) Sampling of acsignal (c) dc only (d) Either dc or ac

4. Advantages of Diode sampling gate over the transistor Sampling gate are [ ]

(a) Linearity only (b) Non-linearity of operation and elimination of pedestal

(c) Linearity of operation and elimination of pedestal (d) stable operating point achievement

5. Chopper amplifier is also known as [ ]

(a) modulator (b) signal generator

(c) Non-linear wave form generator (d) Waveform generator

6. The interval of time is selected by means of an externally applied signal is Termed as [ ]

(a) ramp (b) square wave (c) sync pulse (d) gating signal

7. The time interval for transmission is selected by means of an externally applied signal Called as

(a) Gating signal (b) control signal (c) Logic signal (d) Threshold signal [ ]

8. A Sampling gate which can handled the input signal excursion of both polarities is termed as

[ ]

(a) multidirectional gate (b) n-directional gate (c) Bi-directional gate (d) unidirectional gate

9. The parametres of a Non-ideal switch are [ ]

(a) Analog channel & digital control line control parameters (b) Analog & Digital

(c) Digital and analog control (d) Digital switch control

10. Chopper amplifier is also known as [ ]

(a) Waveform generator (b) modulator

(c) signal generator (d) Non-linear wave form generator

11. A is basically a transmission circuit which allows input signal to pass through it during selected

interval and blocks its passage outside this this time interval. [ ]

(a) XOR gate (b) Sampling gate (c) OR gate (d) nor gate



ANSWERS:

l (a) 2 (d) 3 (d) 4 (c) 5 (a) 6 (d) 7 (a) 8 (c) 9 (a) 10 (b) 11(b)


1. Complementary output is available in which of the following logic families [ ]

(a) RTL (b) TTL (c) ECL (d) DTL

2. The noise - margin of ECL family is given by [ ]

(a) 200 milli watt (b) 10 milli watt (c) 250 milli watt (d) 110 milli watt

3. The IC74147 which acts like [ ]

(a) AND gate (b) adder (c) multiplexer (d) encoder

4. Which of the following logic family is called TRISTATE gate [ ]

(a) TTL (b) RTL (c) ECL (d) DTL

5. Differential signals are used in the following logic family [ ]

(a) .RTL (b) DTL (c) TTL (d) ECL

6. Two basic technologies for digital ICs are bipolar and MOS Bipolar technology is preferred for

(a) LSI & MSI (b) LSI only (c) LSI, MSI & SSI (d) MSI and SSI [ ]

7. Complementary output is available in which of the following logic families [ ]

(a) TTL (b) DTL (c) ECL (d) RTL

8. Which of the following flip-flops is used as latch [ ]

(a) ECL (b) TTL (c) ISL (d) CMOS

9. An AND gate is a [ ]

(a) Multiplexing circuit (b) sequential circuit (c) combinational circuit (d) Memory circuit

10. The programmable logic device (PLD) having a programmable AND-array at the Input

and]programmable OR array at the output is called [ ]

(a) programmable gate array(PGA) (b) programmable array logic (PAL)

(c) programmable logic Array (PLA) (d) ASIC

11. Two similar RTL gates are wire-ANDed. What will be the fan-out of the Combined gate if each has

fan-out of 5? [ ]

(a) five (b) two (c) eight (d) ten

12. The cost of Schottky clamped TTL is [ ]

(a) low (b) average (c) very high (d) moderate

13. An IC that is a 4-bit latch is [ ]

(a) 7400 (b) 7446 (c) 7410 (d) 7475

14. The ECL can be used to switch frequencies as high as [ ]



(a) 100MHz (b) 1MHz (c) 1GHz (d) 500MHz

15. Which of the following logic has the fan-out more than 90 [ ]

(a) TTL (b) 8ns ECL (c) 4nsECL (d) CMOS

16. NOR operation is [ ]

(a) X + Y (b) X . Y (c) ( X + Y ) ( X + Y ) (d) XY

17. Power dissipation of logic family is defined as the supply power required for the gate to operate

with duty cycle at a certain specified frequency [ ]

(a) 50% (b) 25% (c) 100% (d) 75%

18. Fan-in for a TTL gate is given by [ ]

(a) 5 (b) 8 (c) 6 (d) 7

19. A NAND circuit with positive logic will operate as [ ]

(a) NOR with negative logic (b) AND with negative logic

(c) AND with positive logic (d) OR with negative logic

20. The programmable logic device (PLD) having a programmable AND-array at the Input and

programmable OR array at the output is called [ ]

(a) programmable gate array(PGA) (b) programmable array logic (PAL)

(c) programmable logic Array (PLA) (d) ASIC

21. Name the logic family which can always be Wire-Ored [ ]

(a) DTL (b) TTL (c) RTL and DTL (d) IIL

22. The cost of Schottky clamped TTL is - [ ]

(a) very high (b) moderate (c) low (d) average

23. In Boolean algebra , A+A+A+ +A is same as [ ]

(a) An (b) nA (c) Zero (d) A

ANSWERS:

1 (c) 2 (c) 3 (d) 4 (a) 5 (c) 6 (a) 7 (c) 8 (a) 9 (c) 10 (c) 11 (d) 12 (b) 13 (d) 14 (d) 15 (b ) 16 (b) 17 (a) 18 (b) 19 (a) 20 (c) 21 (c) 22(d) 23(d)

II Year B.Tech. 1st Semester

ESSAY TYPE QUESTIONS

Pulse and Digital Circuits Essay Type Questions


ESSAY TYPE QUESTIONS

1 a) A symmetrical square wave whose peak-to-peak amplitude is 2V and whose average value is

zero as applied to on RC integrating circuit. The time constant is equals to half -period of the

square wave. Find the peak to peak value of the output amplitude. Also sketch the output

waveform.

b) Derive the expression for percentage tilt for a square wave output of RC high pass circuit.

2. (a) A pulse of amplitude 5 V and duration 20 sec is applied to High pass RS circuit having

R= 10 k and C = 1000 pf. Calculate the output V0 (t) Sketch the output waveform. Calculate the

tilt and undershoot.

(b) What is meant by an attenuator and explain the application of an attenuator in a CRO probe.

3. a) The output of a high pass RC circuit for a symmetrical square wave input is shown in

figure.1. Derive the expression for percentage tilt in the output.

Figure.1

b) Explain about RLC Ringing Circuit.

4. a) Explain the response of RC low pass circuit for exponential input signal.

b) Derive the expression for percentage tilt for a square wave output of RC high pass circuit.

5.What is an attenuator? Draw the circuit of compensated attenuator. While sketching the

response of compensated attenuator for perfect compensation, over compensation and under

compensation, show that the condition for perfect compensation is R1C

1 = R

2C

2.

6. a) Draw the series RLC circuit and derive expression for its transfer function.

b) A ramp input, shown in Figure.1 is applied to a high-pass RC circuit. Draw to scale the

output waveform for the following cases:

i) T = 0.2 RC ii) T = 10 RC [7+8]

Figure.1

7.a) Prove that an RC circuit behaves as a reasonably good integrator if RC > 15T, Where T is

the period of an input Em

sin t.



b) What is the ratio of the rise time of the three sections in cascade to the rise-time of

Single section of low pass RC circuit?

8. a) Explain RC double differentiator circuit.

b) An oscilloscope displays a 5Hz square wave with 6% tilt. The signal input has no tilt and is

coupled to the oscilloscope via a 4.7F capacitor. Calculate the input resistance of

oscilloscope.

c) Draw the basic ringing circuit. Explain how it provides undamped oscillations.

9.a)The output of a high pass RC circuit for a symmetrical square wave input is shown in

Figure.1. Derive the expression for percentage tilt in the output.

Figure.1

b) An oscilloscope displays a 5Hz square wave with 6% tilt. The signal input has no tilt

and is coupled to the oscilloscope via a 4.7F capacitor. Calculate the input resistance of

the oscilloscope.

10.a) Prove that an RC circuit behaves as a reasonably good integrator if RC > 15T, Where T is

the period of an input Em

sin t.

b) What is the ratio of the rise time of the three sections in cascade to the rise-time of

Single section of low pass RC circuit?

UNIT II: NON LINEAR WAVE SHAPING

1.a) Draw the diode differentiator comparator circuit and explain its operation when a ramp input

signal is applied.

b) For a shunt diode clipper circuit Vi = 20 sin t, V

R = 10V is obtained from a potential divider

circuit using 100V supply and 10K potentiometer

i) Draw the circuit diagram.

ii) If Rf = 50, R

r = and V

= 0, sketch the transfer characteristic, output waveform for the given

Vi

2.a) A square wave input as shown in figure.2 is applied to a negative clamper circuit. Sketch the

steady-state output waveform and derive the necessary expressions.



Figure.2

b) Explain negative peak clipper with and without reference voltage.

3.a) Draw the basic circuit diagram of a DC restorer circuit and explain its operation.

b) For the circuit shown in Figure.1, a sine wave input of 100V peak is applied. Sketch the

output voltage VO

to the same time scale & transfer characteristic. Assume ideal diodes.

Figure.1

4.a) State and prove clamping circuit theorem.

b) Determine Vo for the network shown in Figure.1 for the given 16V P-P sine wave input. Also

sketch the transfer characteristics. (Assume ideal diodes).

Figure.1

5. a) A square wave input of period T=1000 sec, Vpeak = 10V and Duty cycle = 0.2 is applied

to the circuit shown in figure.1. Given, RS

= 100, C = 1F, R = 10K & Diode forward

resistance, Rf = 100.

i. Sketch the output waveform with voltage levels at steady state.

ii. Forward and reverse direction tilt

iii. Af / A

r

Figure.1

b) Write a short note on voltage comparators.

6. a) Draw the basic circuit diagram of negative peak clamper and explain its operation.

b) For the circuit shown in figure.2, an input voltage Vi linearly varies from 0 to 150V is applied.

Sketch the output voltage VO

and transfer characteristics. Assume ideal diodes.



Figure.2

7.a) State and prove clamping circuit theorem

b) In the diode circuit shown in figure.1b, the diode has Rf = 100, R

r = 10K, V=0. Sketch the

steady state output voltage indicating all voltages and time constants, for the given square

wave input with T1 = 2sec and T2 = 1sec, shown in figure.1a.

Figure.1a Figure.1b

a) Input signal b) Diode circuit

8. a) Explain negative peak clipper with and without reference voltage.

b) Draw the circuit diagram of an Emitter-Coupled clipping circuit. Explain its operation with its

transfer characteristic and necessary expressions.

9. a) Draw the diode differentiator comparator circuit and explain its operation when a ramp

input signal is applied.

b) For a shunt diode clipper circuit Vi = 20 sin t, V

R = 10V is obtained from a potential divider

circuit using 100V supply and 10K potentiometer

i) Draw the circuit diagram.

ii) If Rf = 50, R

r = and V

= 0, sketch the transfer characteristic, output waveform for the given

Vi.

10.

a) A square wave input of period T=1000 sec, Vpeak = 10V and Duty cycle = 0.2 is applied to

the circuit shown in figure.1. Given, RS

= 100, C = 1F, R = 10K & Diode forward

resistance, Rf = 100.

i. Sketch the output waveform with voltage levels at steady state.

ii. Forward and reverse direction tilt

iii. Af / A

r



Figure.1

b) Write a short note on voltage comparators.


1. a) Write about diode switching times.

b) Explain Zener & Avalanche breakdown mechanisms in diodes.

2. a) Explain the terms pertaining to transistor switching characteristics.

i. Rise time. ii. Delay time. iii. Turn-ON time.

iv. Storage time. v. Fall time. vi. Turn-OFF time.

b) Calculate the maximum operating frequency of a diode with storage time of 1ns and transition

time of 8ns.

3.a) The circuit shown in figure. 2 uses a silicon transistor with hFE

= 100 and VBE

= 0.7V. Find

the value of Rb

which saturates the transistor, when input voltage is +5V. Given RC

= 1K

& VCC

= +5V.

Figure.2

b) Write about diode switching times.

4. a) Explain the switching characteristics of a bipolar junction transistor.

b) A germanium transistor is operated at room temperature in the CE configuration. The supply

voltage is 6 V, the collector-circuit resistance is 200 and the base current is 20 percent higher

than the minimum value required to drive the transistor into saturation. Assume the following

transistor parameters: Ico

= -5A, IEO

= -2A, hFE

= 100, and rbb'

= 250. Find VBE

(Sat) and

VCE

(Sat).

5. a) Explain how transistor can be used as a switch in the circuit, under what condition a

transistor is said to be OFF and ON respectively.

b) A germanium transistor is operated at room temperature in the CE configuration. The supply

voltage is 6 V, the collector-circuit resistance is 200 and the base current is 20 percent



higher than the minimum value required to drive the transistor into saturation. Assume the

following transistor parameters:

Ico

= -5A, IEO

= -2A, hFE

= 100, and rbb'

= 250. Find VBE

(Sat) and VCE

(Sat).

6. a) With neat sketches and necessary equations, explain in detail about transistor switching

times.

b) Explain Zener & Avalanche breakdown

mechanisms in diodes.

7. a) Explain the phenomenon of latching

in a transistor switch.

b) For the CE transistor circuit shown in

Figure.2, VCC

= 15V and RC

= 1.5K.

Calculate the power dissipation in the transistor, when it is in

i) cut-off ii) saturation.

Figure.2

8. a) Explain the transistor switch in saturation region.

b) Explain the diode switching characteristics.

9. (a) Explain the terms pertaining to transistor switching characteristics.

i. Rise time. ii. Delay time. iii. Turn-on time. iv. Storage time. v. Fall time. vi. Turn-off time.

(b) Give the expression for risetime and falltime in terms of transistor parameters and operating

currents.

10.(a) Diode switching times

(b) Switching characteristics of transistors

(c) FET as a switch


1.Draw and explain the circuit of Astable Multivibrator with necessary waveforms and also derive

the expression for its frequency of oscillations.

2.a) Explain different triggering methods of binary circuits.

b) What are transpose capacitors? Explain how the commutating capacitors will increase the

speed of a fixed-bias binary

3. Draw the circuit diagram for Schmitt trigger and explain its operation. What are the

applications of the above circuit? Derive the expressions for UTP and LTP.

4.In the monostable circuit shown in figure.2, the resistor R is connected to an auxiliary supply

V1 instead of VYY

. If Q2 is in saturation or clamp and if Q1 is OFF in the stable state, verify that



the gate time T is given by equation, T = ln (VYY

+I1R

Y V

) / (V

YY V

) with V

YY replaced by

V1.

5. a) With reference to multivibrators, explain:

i) stable-state ii) loop-gain iii) quasi stable-state

b) Design a collector coupled astable multivibrator for the following specifications with silicon

transistor. IC

(sat) = 10mA; hfe

(min) = 20; VCC

=10V; pulse width=10sec; duty cycle=40%.

6. a. Design the Astable Multivibrator to generate 5 KHz square wave. The supply voltag

VCC=10V, IC(sat)=10mA hFE=50 and assume Si transistors.

b. Explain the operation of Schmitt trigger wit h circuit diagram and and waveforms. Define UTP

and LTP.

7.a. Explain the operation of Astable Multivibrator and derive the expression for time-period of

output square wave.

b. Design collector coupled fixed-bias Bistable Multivibrator to operate from 6Vsupply.Given

IC(sat)= 1mA, hFE=35. Assume Si transistor.

8. a. Explain the operation of Fixed-Bias Bistable multivibrator with circuit diagram and

wavefoms.

b. Design collector coupled monostable multivibrator for the following specificatios. VCC=10V,

VBB= -5V, IC(sat)= 10mA, hFE=20 ,VBE(off)= -0.5V, Output pulse width tp= 200S. (assume

Si transistors)

9. a. Design the Astable Multivibrator to generate 1 KHz square wave. The supply voltag

VCC=10V, IC(sat)=10mA hFE=50 and assume Si transistors.

b. Explain the operation of Monostable Multivibrator wit h circuit diagram and derive the

expression for output pulse width.

10. (a) Draw the circuit diagram of a Schmitt trigger circuit and explain its operation. Derive the

Expressions for its UTP and LTP.

(b) Explain how an Schmitt trigger circuit acts as a comparator.


1.a) With the help of a circuit diagram and waveforms, explain frequency division of an astable

multivibrator with pulse signals.

b) With a neat sketch, explain the frequency division by a factor of 2 in sweep generators.

2. Define sweep speed error, transmission error and displacement error pertaining to sweep

circuits. Also derive the expressions for the same with respect to an exponential sweep circuit.

3. 1.(a) How are linearly varying current waveforms generated?

(b) In the boot strap circuit shown in figure5 Vcc = 25 V, VEE = -15 V, R = 10 K ohms, RB =

150 K ohms, C = 0.05 F. The gating waveform has a duration of 300

s. The transistor parameters are hie = 1.1Kohms, hre = 2.5 x 104 K ohms hfe =50 hoe =

1/40K ohms.

i. Draw the waveform of IC1 and Vo , labeling all current and voltage levels,

ii. What is the slope error of the sweep?

iii. What is the sweep speed and the maximum value of the sweep voltage?

iv. What is the retrace time Tr for C to discharge completely?

v. Calculate the recovery time T1 for C1 to recharge completely.

4 .(a) What is a Linear time base generator? Give its Applications



(b) Write the differences between the voltage and current time base generators?

(c) Why the time base generators are called sweep circuits?

5. (a) What is a linear time base generator?

(b) Write the applications of time base generators.

(c) Define the sweep speed error, displacement error and transmission error of voltage time

base waveform

6. (a) If the amplifier gain is different from unity in a bootstrap circuit, what is the effect on the

sweep voltage? What is the effect of amplifier bandwidth on the sweep output?

(b) In UJT sweep circuit VBB = 20 V, VY Y = 50V, R = 5k , RB1 = RB2 = 0 and C= 0.01 F.

the UJT fires when Vc = 10.6V and goes to OFF state when Vc = 2.8V. Find the

i. the amplitude of sweep signal

ii. the slope and displacement error

iii. the duration of the sweep, and

iv. the recovery time

7. (a) Draw the circuit diagram of fixed amplitude sweep circuit and explain its operation.

(b) Draw the circuit diagram of transistor Miller time base generator and explain its working.

8. (a) With the help of neat diagram explain the working of transistor Bootstrap time base

generator.

(b) Draw a simple current sweep circuit and explain its working with the help of diagrams.

9.(a) Draw and clearly indicate the restoration time and flyback time on the typical waveform of a

time base voltage.

(b) Derive the relation between the slope, transmission and displacement errors

(c) Explain how UJT is used for sweep circuit?

10. (a). Explain the basic principles of Miller and Bootstrap time base generators.

(b). Define the terms slope error, displacement error and transmission error of time-base signal


1. a) With the help of a circuit diagram and waveforms, explain frequency division of an astable


b) Describe synchronization with 2:1 frequency division with neat waveforms

2. (a) Explain the method of synchronization of a sinusoidal oscillator with pulses.

(b) Describe frequency division employing a transistor monostbale multivibrator.

3. (a) Describe the sine wave frequency division with a sweep circuit.

(b) Compare sine wave synchronzation with pulse synchronization.

(c) What is Synchronization on one-to-one basis?

4. (a) With the help of a circuit diagram and waveforms, explain frequency division of an astable


(b) The relaxation oscillator, when running freely, generates an output signal of peak - to - peak

amplitude 100V and frequency 1 kHz. Synchronizing pulsesare applied of such amplitude

that at each pulse the breakdown voltage is lowered by 20V. Over what frequency range

may the sync pulse frequency bevaried if 1 : 1 synchronization is to result? If 5 : 1

synchronization is to beobtained (fP /fS = 5), over what range of frequency may the pulse

source be varied?



5. (a) What is relaxation oscillator? Name some negative resistance devices used as relaxation

oscillators and give its applications.

(b) With the help of a circuit diagram and waveforms, explain the frequency division by an

astable multivibrator?

6. (a) What do you mean by synchronization ?

(b) What is the condition to be met for pulse synchronization?

(c) Compare sine wave synchronization with pulse synchronization?

7. (a) Explain the factors which influence the stability of a relaxation divider with the help of a

neat waveforms.

(b) A UJT sweep operates with Vv = 3V, Vp=16V and =0.5. A sinusoidal synchronizing

voltage of 2V peak is applied between bases and the natural frequency of the sweep is 1kHz,

over what range of sync signal frequency will the sweep remain in 1:1 synchronism with the

sync signal?

8.a) What is relaxation oscillator? Name some negative resistance devices used as relaxation

oscillators and give its applications.

(b) With the help of a circuit diagram and waveforms, explain the frequency division by an

astable multivibrator?

9. (a) Explain how monostable multivibrator is used as frequency divider?

(b) Draw and explain the block diagram of frequency divider without phase jitter.

10.a) Draw the circuit diagram of an astable multivibrator to obtain frequency division by 6.

Explain its working with waveforms.

(b) Explain the terms phase delay and phase jitter.

UNIT- VII :SAMPLING GATES

1.a) Explain the operation of a six - diode gate.

b) Briefly describe the operation of chopper amplifier.

2. a) Draw the circuit of FOUR-DIODE sampling gate. Derive expressions for its gain (A) and

Vmin

.

b) Explain the application of sampling gate in a sampling scope.

3. a) Illustrate the principle of sampling gates with series and parallel switches and compare them.

b) Explain with circuit diagram the operation of a two input sampling gate which does not have

any loading effect on control signal.

4. a) Draw the circuit of two-diode bi-directional sampling gate. Explain its operation & derive

expressions for gain and minimum control voltage in the circuit.

b) Illustrate the principle of sampling gates with series and parallel switches and compare them.

5. a) Illustrate with neat circuit diagram, the operation of unidirectional sampling gate for multiple

inputs.

b) Derive expressions for gain and minimum control voltages of a bi-directional two- diode

sampling gate.

6. a) Explain the operation of a six - diode gate.

b) Briefly describe the operation of chopper amplifier.

7. a) Draw the circuit of FOUR-DIODE sampling gate. Derive expressions for its gain (A) and

Vmin

.

b) Explain the application of sampling gate in a sampling scope.

8.(a) Why are sampling gates called linear gates?



(b) What are the other names of a gate signal?

(c) Compare the unidirectional and bi-directional sampling gates.

9.(a) Explain the effect of circuit capacitances on the operation of a bi-directional diode gate.

(b) In the circuit of figure 2 consider that RL=RC=100K ohms and that R2=2 K ohms, Rf=50

ohms for Vs=25V, compute A, Vnmin, and Vcmin.

10.(a) Explain the basic principles of sampling gates using series switch and also give the

applications of sampling gates.

(b) Explain the effect of control voltage on gate output of unidirectional sampling gate using

diode with some example.


1.a) Define positive and negative logic system

b) Define fan-in and fan-out

c) Draw and explain the circuit diagram of a diode OR gate for positive logic.

2. a) Realize two-input AND & OR gates using diodes and explain their operation with the help of

truth-tables.

b) Realize a three-input NOR gate using Resistor Transistor Logic and explain its operation

with the help of truth-table

3. a) Realize NAND & NOR gates using CMOS Logic and explain their operation with the help

of truth-tables.

b) Draw the circuit diagram of Resistor-transistor logic NOR gate and explain its operation.

4. a) Explain about DTL NAND gate.

b) Give some applications of logic gates.

c) Define positive and negative logic systems.

5. a) With reference to logic families, define:

i) Positive & negative logic system ii) Fan-in & fan-out

b) Draw and explain the circuit diagram of a diode OR gate for positive logic.

6. a) Realize two-input AND & OR gates using diodes and explain their operation with the help of

truth-tables.

b) Realize a three-input NOR gate using Resistor Transistor Logic and explain its operation

with the help of truth-table.

7. a) Explain about DTL NAND gate.

b) Give some applications of logic gates.

c) Define positive and negative logic systems.

8. a) With reference to logic families, define:

i) Positive & negative logic system



ii) Fan-in & fan-out

b) Draw and explain the circuit diagram of a diode OR gate for positive logic.

9 (a) Why totem pole is used in DTL? Draw the circuit diagram and explain a DTL gate with this.

(b) Verify the truth table of RTL NOR gate with the circuit diagram of two inputs.

10.(a) Draw and explain the circuit diagram of integrated positive DTL NAND gate

(b) Consider a two input positive logic diode OR and AND gates. Sketch the output waveform.

Shown in figure

ASSIGNMENt

QUESTIONS

Pulse and Digital Circuits Assignment Questions


ASSIGNMENT QUESTIONS

Unit I: LINEAR WAVE SHAPING 1. A pulse generator with an output resistance R s = 500 is connected to an

oscilloscope with an input capacitance of Ci=30 pf. Determine the fastest rise time

that can be displayed.

2. A 10V step is switched on to a 50k resistor in series with a 500pf capacitor. Calculate the rise time of the capacitor voltage, the time for the capacitor to charge to

63.2% of its maximum voltage, the time for the capacitor to be completely charged.

3. An ideal 1s pulse is fed to an amplifier. Calculate and plot the output waveform under the following conditions: The upper 3-db frequency is i) 10MHz ii) 0.1MHz.

4. The periodic waveform shown in figure 1.1 is applied to an RC integrating network

whose time constant is 10s. Sketch the output waveform. Calculate the maximum

and minimum values of the output voltage with respect to ground under steady state

conditions. Also calculate and plot the output for the first two cycles.

fig ure1.1

UNIT II: NON LINEAR WAVE SHAPING

1. Draw the transfer characteristics for the circuit shown in figure 2.1. Also draw the output

Waveform for a sinusoidal input of amplitude of 20V.

Figure 2.1

2. The input voltage vi to the two level clipper show in figure 2.2 varies linearly from 0 to

150V. Sketch the output voltage vo to the same time scale as the input voltage. Assume ideal

diodes.



figure 2.2

3.(a) Draw the diode comparator circuit and explain the operation of it when ramp

input signal is applied.

(b) Explain the operation of two level slicer.

4.(a) For the circuit shown in figure 2a , Vi is a sinusoidal voltage of peak 100

volts. Assume ideal diodes. Sketch one cycle of output voltage. Determine

the maximum diode Current.

(b) Explain positive peak clipping with reference voltage.

5. (a) Draw the basic circuit diagram of negative peak clamper circuit and explain

its operation.

(b) What is meant by comparator and explain diode differentiator comparator

operation with the help of ramp input signal is applied

6. (a) Determine Vo for the network shown in figure 1 for the given waveform. As-

sume ideal Diodes.



7. a. Draw the shunt clipper that clips the sine wave signal above +5V and explain its

Working with waveforms.

b. Draw the circuit of combinational clipper and explain with its transfer

Characteristics

8. a. Explain the operation of positive clamper circuit using diode.

b. State and prove clamping circuit theorem with relevant circuit and waveforms

9. a. Explain the operation of negative clamper circuit using diode.

b. State and prove clamping circuit theorem with relevant circuit and waveforms.

10 a. Draw the diode shunt clipper that clips the sine wave signal above +5V and below -5V.

Explain its Working with transfer characteristics.

b. Explain the working of an Emitter coupled clipper with circuit diagram.


1. A common- emitter circuit (figure 3.1) has Vcc = 20V and a collector resistor which can

be either 20k or 2k . Calculate the minimum level of base current to achieve saturation in

case.

figure 3.1

2. For CE transistor with Vcc = 15 V, Rc= 1.5K , Calculate the transistor power dissipation a)

At cut off and at saturation.figure3.2



figure3.2


1. The fixed bias binary shown in figure 4.1 uses n p n silicon transistors with Vce(sat)

=0.5V, Vbe(sat) = 1V, Icbo = 10nA at 25 deg C and zero base to emitter voltage at cut off.the

circuit parameters are Vcc = Vbb = 6V, Rc = 1.2k , R1= 4.7k ,R2 = 27k .

Find a) hfe(min) and stable state voltages and currents.b)if the reverse saturation current

doubles for every 10 deg C rise in temp,what is the maximum temperature at which the

circuit can operate properly with one device remaining OFF?

Documents

Vignan BTech Syllabus.pdf