Voltage Regulator Optimization Using Multiwinding Coupled Inductors and Extended Duty Ratio Mechanisms

1494 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 24, NO. 6, JUNE 2009

Voltage Regulator Optimization Using MultiwindingCoupled Inductors and Extended Duty Ratio

MechanismsBradley S. Oraw and Rajapandian Ayyanar, Senior Member, IEEE

Abstract—This paper examines design optimization of voltageregulators (VRs) for microprocessor applications. Optimality ofcompeting VR topologies, such as conventional (Conv) buck, cou-pled inductor, and extended duty ratio converters, is examinedusing efficiency norms and a new cost-per-watt metric to comparethe amount of output capacitance (which is strongly correlated tothe VR cost) to the efficiency. Coupled inductors provide a highersteady-state inductance than transient inductance. Lower transientinductance allows for smaller output capacitance. However, loweroutput capacitance requires a higher switching frequency and thusyields greater switching losses and lower efficiency. Extended dutyratio mechanisms reduce the switching voltage, and hence, reduceswitching losses and increase efficiency. Experimental data are pro-vided that the coupled inductor extended duty ratio converter hasthe same average efficiency, has higher light-load efficiency, anduses one-third of the output capacitance as the Conv multiphasebuck converter. Hence, the combination of multiwinding coupledinductors and extended duty ratio mechanisms is shown to be theoptimal VR configuration. The optimality concepts contributed inthis paper resolve the ambiguity between VR cost and efficiency,and are essential for selecting the best solution among several com-peting VR designs.

Index Terms—Coupled inductors, dc–dc converters, extendedduty ratio mechanism, optimization methods, voltage regulators.

I. INTRODUCTION

TRADITIONAL voltage regulator (VR) design approacheshave focused on transient performance. Transient perfor-

mance is a very important quality of VRs for microprocessorapplications [1]–[8]. However, it should not be the only consid-eration. VR designs that fail to satisfy the transient requirementsare not feasible and should not be considered. As such, transientperformance is really just a pass-or-fail test. It is argued in thispaper that the focus of VR design should be on optimization,and, in particular, the design should address the tradeoff thatexists between converter cost and efficiency. Transient require-ments are added to the optimization problem as constraints, suchthat only feasible designs are identified.

Manuscript received July 9, 2008; revised October 26, 2008. Current versionpublished June 3, 2009. Recommended for publication by Associate EditorK. Ngo.

B. S. Oraw was with the Department of Electrical Engineering, Arizona StateUniversity, Tempe, AZ 85287 USA. He is now with Nth Degree Technologies,Tempe, AZ 85284 USA (e-mail: [email protected]).

R. Ayyanar is with the Department of Electrical Engineering, Arizona StateUniversity, Tempe, AZ 85287 USA (e-mail: [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TPEL.2009.2013223

TABLE INORMALIZED COST AND SIZE OF A TYPICAL CONVENTIONAL FOUR-PHASE

BUCK VR

This paper proposes that future VR design methodologiesshould focus on the tradeoff between cost and power loss. Toquantify this tradeoff, a new concept, “cost-per-watt,” is pro-posed. VRs are cost-constrained in both monetary cost andphysical size. It is competitively advantageous to reduce bothcost and size (e.g., area or volume), but not necessarily if powerlosses increase as well. It can be shown that cost reduction andpower loss improvement are inversely related. Cost-per-watt isa metric that measures the cost and power loss tradeoff and canbe used as an objective function in a VR design optimizationproblem.

The output capacitance Co contributes a significant portionof the converter cost and size. Many VR designs have usedlarge can-type electrolytic bulk capacitors, which are expensive(approximately 10% of the total cost) and consume valuableboard area (31% of the total area). Note that VR designs arenot standardized. There is considerable freedom in capacitor,inductor, and switch selection. The author offers an example ofa valid VR design in Table I. The table contains the normalizedcost and size of a typical multiphase buck converter, which uses5.2 mF of output capacitance.

When a low switching frequency, fsw , is used, the transientrequirements necessitate a large bulk capacitance to support theoutput voltage during large load current disturbances. It canbe shown that capacitance is inversely related to the switchingfrequency and hence switching losses. All-ceramic-output ca-pacitor designs are attractive in low-cost VR applications. Thechallenge is preserving the same efficiency when the bulk isremoved.

Power loss is best described using efficiency as the met-ric, since efficiency is a unitless quantity. Efficiency η variesinversely with switching frequency, so there is a penalty for

0885-8993/$25.00 © 2009 IEEE

ORAW AND AYYANAR: VR OPTIMIZATION USING MULTIWINDING COUPLED INDUCTORS AND EXTENDED DUTY RATIO MECHANISMS 1495

Fig. 1. Qualitative relationship between small- and large-output-capacitancedesigns.

reducing capacitance. Switching losses increase with switchingfrequency. Efficiency is not strictly specified; however, there arecertain expectations. Most VR solutions achieve 80%–90% ef-ficiency at thermal current, which describes the typical averageoperating current of the converter. New solutions are expectedto fall in this range.

It can be shown from the transient requirements and neglect-ing parasitic resistance and inductance that the output induc-tance Lo is proportional to the output capacitance [4], [7], [8].It is well understood that smaller inductor slew current faster,which is important for load current disturbance response. Ifsmaller inductance is used, the capacitance can be reduced,which would require increasing the switching frequency andthe respective losses. Additionally, the inductor rms currentsare inversely proportional to inductance and directly (squared)related to conduction losses. Since switching and conductionlosses are higher, lower inductance designs are significantly lessefficient.

Qualitatively, the impact of reducing capacitance is shown inFig. 1. A low-capacitance design not only is low-cost but alsohas low efficiency. Alternatively, using more capacitance yieldsa higher cost but more efficient design. The task of the VRdesigner is to choose the appropriate tradeoff between cost andefficiency. This paper proposes the cost-per-watt framework tosystematically balance cost and efficiency.

Input voltage division and output current division are advan-tageous circuit techniques for use in low-voltage, high-current,microprocessor VR architectures. A multiphase output filter di-vides the output current, distributing the losses among severalinductors and switches. The maximum output current can be inexcess of 150 A, so for cooling purposes, it is advantageous tospread the conduction losses to avoid hot spots. Interleaving,or phase-shifting the inductor currents, in a multiphase outputfilter also is advantageous for reducing the current ripple in theoutput capacitors and, in turn, reducing the ripple in the out-put voltage. Coupled inductor (CI) output filters in VRs haverecently received attention for better transient performance andefficiency [9]–[12]. Extended duty ratio (ExtD) mechanisms are

very efficient input voltage dividers [12]–[15]. In many VRs, theinput voltage is at least 12 V, while the output voltage is of theorder of 1.2 V. This large step-down is indicative of significanthard switching losses. The ExtD converter efficiently reducesthe switching voltage and associated losses.

The conceptual diagram of voltage and current divider VRarchitecture is illustrated in Fig. 2.

The voltage divider network comprises switches and capaci-tors. Note that the voltage divider circuit in Fig. 2 is a conceptualillustration and not a valid steady-state circuit. Valid steady-statevoltage dividers, such as the ExtD buck, are described in thispaper. The current divider network is a combination of eitheruncoupled or coupled inductors. This paper claims that the CInetwork paired with the voltage divider network (i.e., the CIExtD buck) is the most optimal VR topology. It yields the lowercost solution with higher efficiency than a conventional (Conv)buck.

A. Transient Requirements

VR requirements for Intel microprocessors are specified in thevoltage-regulator-down (VRD) design guidelines [1]. Even froma brief examination of these specifications, it is clear that loadcurrent disturbances are the most significant dynamic events.Output voltage response to a load disturbance is determinedby the closed-loop output impendence of the converter. The dcoutput resistance, also known as the dc load line, has been theprimary focus in most VR designs. However, some attention hasbeen given to output-impedance-based VR designs [4]–[8], alsoknown as dynamic load line regulation.

Dynamic load line regulation is achieved by bounding theclosed-loop output impedance by the dc resistance (DCR) overthe controllable bandwidth, for instance, up to the Nyquist fre-quency [(1/2)fsw ]. It is not possible to shape the closed-loopoutput impedance beyond the feasible bandwidth; hence, theoutput impedance at high frequency is dominated by the open-loop properties of both VR and the power delivery networkthat interfaces to the load. From the perspective of VR con-troller design, only the low-frequency impedance is important.High-frequency impedance is determined by the decoupling ca-pacitors used along the power delivery path.

Simple analysis of the low-frequency output impedance re-veals that the required minimum output capacitance Comin andthe maximum output inductance Lomax are interdependent andrelated to the maximum load disturbance magnitude ∆io max ,the dc load line resistance RLL , the loop bandwidth fc , and theswitching frequency fsw . The loop bandwidth is upper boundedby the switching frequency in order to preserve linearity of thesampling nature of pulsewidth modulated (PWM) converters. Itcan be shown that all feasible VR designs that meet transientrequirements have output filters and a switching frequency thatsatisfy

Co ≥ Co min

Lo ≤ Lo max

fsw ≥ fsw min (1)


Fig. 2. Voltage and current divider VR architecture.

where the minimum and maximum values have been shownin [4]–[8] to be

Co min =2

πRLL

1fsw min

Lo max =min ((Vin − Vo) , Vo)

∆io max

1fsw min

fc =14fsw min

fsw min =fsw

αf

αf ≥ 1. (2)

The relationship between capacitance and inductance is basedon a critical inductance design suggested in [4] and [6]. Thebandwidth limitation has been discussed in [5] and [6]. Both ofthese topics have been reconsidered in [7] and [8].

It should be noted that the Comin calculation and the band-width limitations might be overly conservative. The Nyquist fre-quency is half the switching frequency, and typically, for goodlinearity and minimal sampling lag, the bandwidth is limited toa factor of 1/5 to 1/10. However, interleaving of multiphase con-verters reduces the sampling lag and increases linearity, sincethe effective switching frequency from the perspective of thecontroller is N times the actual operating frequency [5]–[8]. Inthis case, N is the number of phases in the converter. Load cur-rent feedforward and nonlinear control techniques have beendescribed in [5] and [7], which could also relax bandwidthlimitations. However, it is argued here that the given optimalcontrol response to the worst-case load transient is satisfied bya linear controller given by the conditions in (2). The optimalcontrol response to worst-case load disturbance is to saturatethe control. After the control saturates, the converter dynamicsare open-loop and are determined by the output inductance andcapacitance. Nonlinear control might be able to reach saturationfaster than linear control and preserve stability margins. How-ever, the rate at which the control can saturate is still boundedby Nyquist frequency. For linear control, a bandwidth equal toone-fourth of the minimum switching frequency is reasonablefor a multiphase converter.

The optimal frequency scaling factor αf describes how muchlarger the applied switching frequency is than the minimum. For

control purposes, there is no penalty for increasing the switchingfrequency. Actually, the linearity and sampling lag are betterwhen the operating frequency is higher. However, the efficiencyof the converter is greatly dependent on the switching frequency.It is possible, such as in designs with large output capacitance,that the efficiency of the converter could be higher at a frequencylarger than the minimum due to the tradeoff between switchingand conduction losses that both depend on frequency. The factorαf determines the scaling of the applied frequency from theminimum suggested by transient requirements.

B. Efficiency

In the multiphase buck converter, switching losses dominatethe light-load efficiency, while conduction losses drive heavy-load efficiency. Switching losses are dominated by hard switch-ing losses that occur during turn-ON and turn-OFF transitions.Bridges do not commutate in zero time; therefore, during thetransition, both the switch current and voltage will be highbriefly, resulting in power loss. The switching losses are de-scribed in this paper by the transition charge. This transitioncharge includes the charging of the switches’ output capac-itances, the reverse recovery of the antiparallel diodes, andhard switching losses. Gate drive, parasitic output capacitancecharge, and reverse recovery charge of the power switches (e.g.,MOSFETs) are also included in the total switching losses. Con-duction losses result from ON-state voltage drops of switchesand diodes and from parasitic resistances of other circuit com-ponents. Typically, the losses of the switches and diodes dom-inate the total converter losses. I2R of inductor DCR can alsobe significant. Resonances of switch transitions can result inconsiderable loss but are often difficult to quantify, since theydepend on the parasitics of a physical layout and componentpackaging, which are often uncertain.

Efficiency is a complicated function of many variables. It isvery sensitive to the operating conditions (input/output volt-ages/currents and switching frequency). Often, efficiency isplotted as function of the load current. It should be understoodthat one efficiency curve fails to completely characterize a con-verter. If the regulated output voltage, the input voltage, or theswitching frequency changes, the efficiency will change signif-icantly. Output voltage, input voltage, and switching frequencyare the primary factors, but the efficiency will also change with


temperature and any variation in component parameters. Hence,it is difficult to characterize efficiency with simple terms.

The efficiency η is defined as the output power Po dividedby the input power Pin . The input power is the sum of theoutput power and the total losses Ploss . A detailed treatment ofsynchronous buck converter losses can be found in [15]–[18].The total losses is the sum of the switch losses PSU and PSL in theupper and lower switches, respectively, the inductor conductionand core losses PL , and conduction losses in the input and outputcapacitors PC in and PC o . The calculation also accommodatesthe ExtD topology [11]–[14] losses in its storage capacitorsPC E and additional conduction losses in the lower switches.The parasitic resistance of printed circuit board (PCB) tracescan be embedded with the series resistances of the switches,inductors, and capacitors

η =Po

Pin

Pin = Po + Ploss

Ploss = PSU + PSL + PL + PC in + PC o + PC E . (3)

The individual loss component are found to be

PSU = NI2SU ,rmsRSU + N

(Qtran,SU

Vsw + Qg,SUVg,SU

)fsw

PSL ≈ N I2SL ,rmsRSL +

N

M(M − 1)

(I2SU ,rmsRSL

)× N

(Qtran,SL

Vsw +Qg,SLVg,SL

+tDTIAVGVdio, SL

)fsw

PL = N I2L,rmsRL, PC o = I2

C o,rmsRC o

PC in = I2C in,rmsRC in , PC E = (M − 1) I2

C E ,rmsRC E . (4)

For the upper switch SU , the conduction losses depend onthe rms current ISU ,rms and the parasitic ON-state resistanceRSU . The hard switching losses of the upper switch depend onthe transition charge Qtran,SU

and the drain–source switchingvoltage Vsw . The gate drive loss is a function of the gate chargeQg ,SU

and the applied gate voltage Vg ,SU.

The lower switch SL loss calculation is approximate since theconduction loss terms (terms with I2

SL ,rms and I2SU ,rms) do not

exactly add. The actual rms current through each lower switchcan be calculated from the current waveform, but it is sufficientto approximate the losses by adding the two rms terms. Theparasitic ON-state resistance is denoted by RSL . The gate driveloss is a function of the gate charge Qg ,SL

and the applied gatevoltage Vg ,SL

. During each switching cycle, the lower switchalso consumes a transition charge Qtran,SL

, which is equal to thecharge applied to the parasitic output capacitance of the switchand the reverse recovery charge of the parallel diode. This diodefacilitates soft switching of the lower switch and must carry theinductor current when the lower switch stops conducting andbefore the upper switch starts. Again see [15]–[18] for a moredetailed discussion of these losses. During the dead time tDTwhen the diode is conducting, the power loss is proportional tothe diode forward voltage Vdio,SL

. The ExtD mechanism alsohas an additional loss when the lower switch of an outer phaseconducts the upper switch current of an inner phase. There are(M – 1) of these losses for an M -phase ExtD converter.

For the inductors (L), the ac resistance (ACR) of a winding isa function of frequency and hence varies with the switching fre-quency. The DCR typically dominates the total resistance (RL ),so ACR can usually be neglected. The magnetic core lossesPcore are difficult to quantify, since magnetic material proper-ties are usually not well defined for a particular component.Again, DCR conduction is most significant, so core losses canbe neglected.

The capacitors (input, Cin ; output, Co ; and the ExtD stor-age, CE ) all dissipate power across their equivalent series re-sistances. The power loss is proportional to the square of therms current through the capacitors. The rms current through thecapacitors depends on the buck topology, interleaving pattern,and operating conditions.

C. Efficiency Norms

Efficiency is a rather ambiguous quantity and is very sensi-tive to operating conditions. The efficiency changes significantlywith the load current and the switching frequency. Often, effi-ciency is a concave function with respect to switching frequency.Such concavity implies the existence of an optimal switchingfrequency that maximizes efficiency. The optimal frequency is afunction of the load current, which motivates variable-frequencyoperation. For simplicity, this paper considers only constant-frequency operation, but the proposed methodologies could beextended to variable-frequency operation.

Rather than reporting efficiency as function of many variables,it is useful to form efficiency norms that describe the magnitudeof efficiency relative to a particular set of parameters. A normmeasures the size of vectors in a vector space. Form a real vectorof load currents with length a

�Io = �a×1 . (5)

The elements of this vector span a discrete range betweenminimum and maximum load currents (Iomin and Iomax )

Io (i) = Io min +Io max − Io min

a − 1(i − 1) ∋ i ∈ {1, . . . , a} .

(6)In general, an efficiency norm ‖ · ‖ is stated as a function

f (·) of the efficiency and is evaluated in the discrete vectorspace

‖η‖ = f(η(�Io)). (7)

1) Average Efficiency: The average efficiency can be definedby ‖ · ‖1 , scaled by the length of the load current vector a

η̄ = ‖η‖AVG =1a‖η‖1 =

1a

a∑i=1

η (Io (i)). (8)

The average efficiency assumes that all load currents areweighted equally. This may be inaccurate in some applications.The efficiency at some load values may be more important thanothers. For instance, a usage model could be identified thatdefines the probability that the converter is operating at a partic-ular load level. The usage model is an example of a weightingfunction.


A weighted average efficiency norm can be defined as

η̄W = ‖η · W‖AVG =1a‖η · W‖1

=1a

a∑i=1

[η (Io (i)) · W (Io (i))]. (9)

The weighting function W defines the significance of eachload level.

2) Peak Efficiency: The peak efficiency ηP is a commonlyreported quantity. The peak is simply the ‖ · ‖∞ of the efficiencyvector

ηP = ‖η‖∞ = maxi

η (Io (i)) . (10)

This norm is equivalent to the weighted average norm suchthat the weight function has a unity weighting for the loadcurrent that results in the highest efficiency and zero weightingfor all other load values. This is an ambiguous measure since thepeak efficiency load may not correspond to a high-probabilityoperating point. Optimization using the peak efficiency normmay result in poor efficiency at other load levels.

3) Thermal Design Efficiency: The efficiency at the ther-mal design current (ITD ) is also a useful quantity. Essentially,thermal design current is the load current at which the ther-mal management is designed. It is roughly the average currentof the load. The average current drives the average losses andhence average temperature of the system. The thermal designcurrent of a microprocessor load could also be defined as thethermal design power (TDP) [19] divided by the output voltage.The cooling devices such as heat sinks and fans are designedassuming that the converter is operating at ITD . The thermaltime constants are slow relative to the dynamics of the powerconverter and the load. The thermal design efficiency ηTD isevaluated at the thermal design current

ηTD = η (ITD)

ITD =TDPVo

. (11)

It could be argued that TDP and not ITD drives the ther-mal solution. But since they are proportional to each other bythe output voltage, they are equivalent in terms of optimality.Moreover, the VR solution can only be optimized at a particularoutput voltage. Thus, it is reasonable to consider the thermalcurrent in a design optimization.

4) Light-Load and Heavy-Load Efficiencies: Light-load ef-ficiency has recently received a lot of attention. In many appli-cations, usage models predict that the load current is low duringnormal operating conditions; therefore, light-load efficiency isof great concern. Define the light-load efficiency ηL as the effi-ciency at the minimum load current Imin

ηL = η (Imin) . (12)

Alternatively, the heavy-load efficiency ηH is defined at themaximum load current Imax

ηH = η (Imax) . (13)

Like peak and thermal design efficiencies, the light- andheavy-load efficiency norms are special cases of the weightedaverage norm. The weighting functions are selected to isolateparticular load values.

II. OPTIMAL CONVERTER DESIGN

This paper focuses on the output capacitances as the primarycontributor to the VR cost. Other circuit components like in-ductors and switches could be considered as well, but these aresecondary factors. As a first-order optimization, output capac-itance will be considered solely. The optimization problem isposed such that the amount of capacitance is minimized whilemaximizing the efficiency. There are two constraints in prob-lem: the design must satisfy the transient requirements and theefficiency must be greater than some minimum value. The tran-sient requirements are satisfied if the output capacitance is equalto or greater than the minimum determined by the transient re-quirements. The capacitance is also upper bounded by somemaximum value, which is determined by expectations of theconverter cost or size. Finally, as stated in the previous section,the converter is operated with a constant switching frequency.

In the analysis of the transient requirements, it was foundthat there are only two degrees of freedom in a VR design:the applied switching frequency fsw and the optimal frequencyscaling factor αf . The optimization problem is posed such thatthe objective function [J(Co , η)] is minimized. Define the 2-Doptimal VR design problem as

minx

J [Co (x) , |η (x)|]

s.t. Co max ≥ Co ≥ Co min

|η| ≥ |η|min

x = [ fsw αf ] (14)

where x is the 2-D argument containing the switching frequencyand the optimal scaling factor. The minimum efficiency con-straint is bounded by |η|min . The maximum capacitance for costand size constraints is Comax . And Comin is the constraint fortransient requirements.

Convexity of the objective function J(·) is important for theexistence of a global optimal solution. It is well known thatquadratic objective functions are convex. As such, a quadraticobjective function of capacitance and efficiency could be se-lected

J [Co (x) , |η (x)|] = [WcCo (x)]2 + |η (x)|2 (15)

where Wc is weighting function that relates per unit of capaci-tance to per unit of efficiency. The difficulty of such an objectivefunction is selecting the weighting functions (e.g., Wc ). Obvi-ously, cost and efficiency have different units and scales, soweighting functions must be defined for a quadratic objective.It will be shown that the cost-per-watt function does not requirean explicit weighting function. The function weights reducingcapacitance and increasing efficiency equally, which is similarto Wc = 1 in (15).


Fig. 3. Efficiency and cost-per-watt versus capacitance.

A. Cost-Per-Watt

Cost-per-watt is a function that describes the relative magni-tude of a converter’s “cost” to some notion of the converter’spower rating. The “cost” could be monetary cost of the convertersuch as the total bill of materials (BOM) cost or a particular cir-cuit component like the output capacitance (Co ). “Cost” alsocould be a measure of the converter’s physical size (e.g., area orvolume). Both monetary cost and physical size are significant ina VR design. The output capacitance, for example, contributessignificantly to both aspects of cost; therefore, there is muchinterest in reducing the amount of capacitance.

The general form of the cost-per-watt function χ is the ratio ofthe arbitrary cost K and the power P . The actual cost and powermeasured depend on the application. The function provides ameans to compare two competing parameters

χ (K,P ) =K

P. (16)

The output capacitance is a considerable portion of the con-verter’s cost, and the power can be simply the efficiency (η) ofthe converter.

It is desirable for the converter to use low capacitance andbe highly efficient. However, capacitance reduction is inverselyrelated to efficiency improvement. The cost-per-watt functionχ(Co , |η|) can be used to measure this tradeoff, where efficiencyis measured via a norm (|η|)

χ (Co, |η|) =Co

|η| . (17)

Both capacitance and efficiency are functions of the switchingfrequency. A maximum amount of capacitance (Comax ) couldbe defined for a given application based on converter size or costconstraints. The efficiency may also be bounded such that theconverter is at least as efficient as some minimum value (|η|min ).

The efficiency and the cost-per-watt decrease with capaci-tance, which is shown qualitatively in Fig. 3.

The optimal VR design, with respect to the lowest cost-per-watt, is the design that has least capacitance such that the con-verter is at least as efficient as the minimum efficiency

J (Co, |η|) = χ (Co, |η|) . (18)

The cost-per-watt increases monotonically with capacitance.Such a relationship occurs when the rate at which efficiencyincreases is less than the rate at which the capacitance increases.

The optimal solution can be found by tracing the cost-per-watt curve toward the point at which the efficiency |η| is equalto the minimum constraint |η|min . The optimal capacitance C∗

o

is the capacitance at this point and that satisfies the transientrequirements

Co = C∗o |η| = |η|min . (19)

At first glance, this result seems anticlimactic, but its simplic-ity is attractive and quite intuitive. By specifying the minimumefficiency, the efficiency of the optimal design is set, while theoutput capacitance is determined by transient requirements. Us-ing cost-per-watt as the objective function, the solution to theoptimal VR design problem is trivial.

III. CI EXTD CONVERTER

The advantages of both CIs and ExtD mechanisms can beobtained simultaneously when both mechanisms are used in asingle multiphase buck solution. It has been shown [11]–[15]that the primary advantage of an ExtD converter is a reducedswitching voltage and hence a reduction of the respective losses.The advantage of CIs has also been shown to be a larger steady-state inductance than transient inductance [8]–[11].

This paper has proposed that reducing capacitance decreasesconverter cost but also decreases efficiency. For transient spec-ifications, the output inductance is proportional to the capaci-tance. If the output capacitance is reduced, then the transientinductance must decrease as well. Using CIs to reduce outputcapacitance can actually result in lower efficiency. However,the ExtD mechanism can be used to compensate for the higherswitching loss of CIs. Thus, the most advantageous VR topol-ogy is the CI ExtD buck. It is less expensive and more efficientthan a Conv multiphase buck.

The CI ExtD topology is described by three parameters: N ,M , and P . The number of phases N equals the number ofupper/lower switch pairs. The duty ratio extension factor M isthe ratio of the input voltage to the switching voltage. P is thenumber of windings in each CI structure. All values are integers.Both M and P are factors of N , but M does not have to equalP

M ≤ N

P ≤ N. (20)

The notation {N , M , P} is used to describe the configura-tion of the converter. For example, a {2,2,2} converter has twophases: an M = 2 extension factor, and two-winding CIs. Otherconfigurations are illustrated in the following sections.

A. {4,1,1}-Conv Buck

The Conv multiphase buck converter is the traditional VRsolution. Several inductors are used in the output filter to divide


Fig. 4. Conventional four-phase buck converter.

the output current, but the switches must block the entire in-put voltage. The advantage of the Conv buck is its simplicity.VR solutions using isolated topologies have been proposed, butsuch added complexity and cost is difficult to justify in cost-constrained VR applications. A four-phase Conv buck (i.e., a{4,1,1} converter) is shown in Fig. 4.

1) {4,1,4}-CI Buck: Recently, interest in CIs for buck con-verters has grown. Two-winding CI solutions have receivedmost of the attention. However, multiwinding configurationshave some distinct advantages. Coupling coefficients for multi-winding devices are much lower than a two-winding couplingcoefficient, while they achieve similar equivalent inductance.The disadvantage of coupling more windings is the inflexibilityof PCB layout. It has been a common practice in microprocessorVR layout to place inductors on several sides of the CPU forbetter power delivery performance. This layout technique is notpossible for multiwinding CIs. A four-winding CI buck (i.e., a{4,1,4} converter) is shown in Fig. 5.

2) {4,2,1}-ExtD Buck: The ExtD topology is an efficient in-put voltage divider mechanism for multiphase buck converters.The high input voltage and low output voltage of micropro-cessor VR applications often yield low efficiency. The storagecapacitors CE are switched capacitors that efficiently divide theinput voltage. This mechanism reduces both the voltage stressacross switches and the voltage during switching transitions,and hence, the switching losses. The ExtD mechanism is a veryattractive addition to the multiphase buck converter. A divide by2, four-phase ExtD buck (i.e., a {4,2,1} converter) is shown inFig. 6.

3) {4,2,4}-CI ExtD Buck: The CI and ExtD mechanism canbe combined into a superior multiphase buck configuration. TheExtD mechanism is used to efficiently divide the input voltageand reduce switching losses. The CIs provide better transient andsteady-state inductance and necessitate much less capacitance

Fig. 5. Coupled inductor buck converter.

Fig. 6. Extended duty ratio buck converter.

than a Conv converter. The divide by 2, four-winding CI ExtDbuck (i.e., a {4,2,4} converter) is shown in Fig. 7.

4) General {N ,M ,P} Converter: The ripple currents,equivalent inductances, and power losses can be generalized foran {N ,M ,P} converter. Recall that N is the number of phases,and hence, the number of inductors in the output filter. The dutyratio extension factor M is the ratio of the input voltage Vin tothe switching voltage Vsw , which is the maximum voltage that


Fig. 7. Coupled inductor extended duty ratio buck converter.

appears across the bottom switches SL . And P is the number ofcoupled windings in each multiwinding part.

For valid steady-state operation of the ExtD mechanism, thephases in each M -phase block must be interleaved by 360◦/M .A common duty ratio should also be used and limited to 1/M .The duty ratio of the switching port Dsw is the ratio of the outputvoltage Vo to the switching voltage Vsw

0 ≤ Dsw =Vo

Vsw≤ 1

M. (21)

The conversion ratio Dc is the ratio of the output voltage tothe input voltage. Hence, the duty ratio at the switching port Dswis related to the conversion ratio Dc by the duty ratio extensionfactor M

Dsw = MDc

Dc =Vo

Vin. (22)

The maximum possible conversion ratio for an ExtD converteris

Dc max =1

M 2 . (23)

The steady-state inductor current ripple is a function of theequivalent steady-state inductance LSS of the CI network. Theripple current equation has the same form as the Conv buckconverter

∆IL CI-extD =Vo (1 − MDc)

fswLSS. (24)

The expression for LSS can be quite complicated for mul-tiwinding CIs. The equivalent inductance expression can begreatly simplified if the CIs are symmetric. For simplicity, as-sume that Ls is the self-inductance of all windings. And allpairs of windings have coupling coefficients equal to k. It canbe shown [20] that the coupling coefficient k varies inversely

with the number of coupled windings (P )

k =(LTR/Ls) − 1

P − 1. (25)

Typical coupling coefficients for 50 nH transient inductancewith a 470 nH self-inductance are −90% for two-winding CIs,−45% for three-winding CIs, and −30% for four-winding CIs.The advantage of multiwinding CIs (more than windings) isthat lower coupling is required, which, in most cases, is easierto fabricate.

LSS is actually a function of the duty ratio, and distinct ex-pressions exist for each discrete range of duty ratios

LSS = LSS(r) ∋r − 1

P≤ Dsw = MDc ≤ r

P

r = {1, . . . , P} . (26)

Again, for simplicity, constrain the duty ratio to the first dis-crete duty ratio range. For symmetric CIs, and with the duty ratioconstraint, the steady-state inductance [20] for the P -windinginductors is

LSS =(1 + (P − 1) k) (1 − k)

1 + (P − 2 + MDc/1 − MDc) kLs

∋ 0 ≤ MDc ≤ 1P

. (27)

The steady-state inductance depends on the extension factorM and the number of coupled windings P . The expression isvalid for duty ratios less than 1/P . Similar expressions could beformulated for larger duty ratios but are omitted for brevity.

The ripple current in the output capacitance is important indetermining the steady-state ripple in the output voltage. Inter-leaved multiphase buck converter demonstrates partial cancella-tion of the inductor current ripple when the inductor currents aresummed at the output node. In some cases, the ExtD mechanismcan further reduce the ripple in the output capacitance. Further,the equivalent transient inductance LTR of the CIs determinesthe capacitor ripple current. For the CI ExtD converter, the out-put capacitor ripple is simplest to calculate if the duty ratio isconstrained (Dsw < 1/ N ). In such a case, the ripple is

∆IC o CI-extD =NVo

fswLTR·(

1N

− MDc

)∋ 0 ≤ MDc ≤ 1

N.

(28)It should be understood that the output capacitor ripple current

is periodic about 1/N , so this expression sufficiently describesthe ripple in each discrete duty ratio range, as mentioned in (25).The transient inductance LTR for the P -winding inductor [20]is

LTR = [1 + (P − 1) k] Ls. (29)

It is also interesting to examine the steady-state inductance inrelation to the transient inductance. It can be shown by dividingthe expressions that LSS is proportional to LTR . The propor-tionality can be quantified by the factor αL . This factor speaksto how much larger the steady-state inductance is relative to thetransient inductance. A large separation between LSS and LTR


is desirable for high-speed and high-efficiency buck-type VRs

LSS = αLLTR

αL =(1 − k)

1 + (P − 2 + MDc/1 − MDc) k. (30)

Consider a critical inductance design that assumes the min-imum bandwidth as a function of the output capacitance. Theamount of output capacitance is the only variable in this design.The other parameters (e.g., RLL , Vo , etc.) are constants, with theexceptions of the scaling factor αf for the switching frequency.The switching frequency scaling factor provides additional effi-ciency optimization for high-capacitance designs since the op-timal switching frequency in such cases can be larger than theminimum required for transient performance

VR = {Lct , Co, fc,min , fsw}

Lo = Lct = γCo, γ =πRLLVo

2∆Io

fc =1

2πRLLCofsw = αf 4fc , αf ≥ 1. (31)

The equivalent inductance of the output filter Lo is parallelcombination of all the per-phase transient inductances LTR . Inthis design, we assume that the CIs are balanced such that allphases have the same equivalent transient inductance

Lo =LTR

N. (32)

To calculate the efficiency of this VR, an expression for theinductor current ripple must be determined. Substituting thesteady inductance in (26) and switching frequency from (30)into the ripple expression (24), we find that

∆IL =1

αLαf

∆Io (1 − Dsw )N

, αL ≥ 1, αf ≥ 1

fsw = αf2

πRLLCo. (33)

Substituting the ∆IL and fsw expressions in (4), the powerlosses are found to be

PSU = NI2SU ,rmsRSU

+ N (Qtran,SU Vsw + Qg ,SU Vg ,SU )2αf

πRLLCo

PSL ≈ NI2SL ,rmsRSL +

N

M(M − 1)

(I2SU ,rmsRSL

)+ N(Qtran,SL Vsw + Qg,SL Vg ,SL

+ tDTIAVGVdio,SL )2αf

πRLLCo

PL = NI2L,rmsRL, PC o = IC o,rms2 RC o

PC in = I2C in,rmsRC in , PC E = (M − 1) I2

C E ,rmsRC E (34)

where the currents of the CI ExtD buck converter are given by

IAVG =Io

NIin =

N

MDswIAVG

∆IL =1

αLαf

∆Io (1 − Dsw )N

, Dsw = MVo

Vin

ISU ,rms =

√Dsw

(I2

AVG +∆I2

L

12

)

ISL ,rms =

√(1 − Dsw )

(I2

AVG +∆I2

L

12

)

IL,rms =

√(I2

AVG +∆I2

L

12

)IC o,rms =

∆IL

2√

3

IC E ,rms =

√2Dsw

(I2

AVG +∆I2

L

12

)

IC in,rms

=

√N

M

(Dsw

3(I2

C in1 +IC in1IC in2 +I2C in2)+

(M

N−Dsw

)I2in

4

).

IC in1 =(

1 − N

M

Dsw

2

)IAVG − ∆IL

2

IC in2 =(

1 − N

M

Dsw

2

)IAVG +

∆IL

2. (35)

B. VR Optimization Using CI and ExtD

The optimal VR solution as stated in (19) is not an explicitsolution. To find the optimal capacitance C∗

o , the efficiency normmust be evaluated. And recall that efficiency varies with the loadcurrent, so the solution should be found using one of the normssuggested in this paper. For example, the thermal design normis a useful benchmark, and it is much easier to evaluate thanthe average or peak norms. Further, by evaluating efficiency atone current (e.g., thermal current), maximizing the efficiency isequivalent to minimizing the losses at this load current. As such,the optimal solution occurs when

Co = C∗o Ploss (ITD , Co , αf ) = Ploss max . (36)

The Ploss terms in (33) and the currents in (34) can be evalu-ated at ITD . The optimization searches over Co and αf to findthe solution when the losses equal the maximum constraint.Finding the optimal solution using the losses rather than theefficiency is slightly easier. A general symbolic solution to theoptimal VR problem is rather complicated. The general solu-tion is not given here. Rather, a comparison is made between aConv buck VR and CI and ExtD VRs. The optimality of thesedifferent topologies is examined. The efficiency norms and thecost-per-watt analysis are used to demonstrate the advantagesof CI and ExtD over a Conv buck VR.

It has been shown in this paper that reducing capacitanceyields a low-efficiency converter. Thus, using CIs in a buck VRto reduce output capacitance is a less efficient converter than aConv buck. It is possible to design CIs with the same transientinductance and higher steady-state inductance than a Conv buck.In this case, the CI buck would be more efficient, but the amount


TABLE IIPARAMETERS OF CI AND EXTD BUCK VR CONFIGURATIONS: NOMINAL DUTY

RATIO AND EQUIVALENT INDUCTANCES

of output capacitance would be the same. Therefore, it shouldbe clear that CIs alone cannot simultaneously reduce outputcapacitance and improve efficiency as compared to uncoupledinductors with the same steady-state inductance.

The ExtD mechanism improves efficiency by reducingswitching losses. Moreover, the ExtD mechanism has no nega-tive impact on transient performance. Thus, the best VR designapproach is to use the CIs to reduce the capacitance and the ExtDmechanism to recover the losses created by the higher switchingfrequency. A CI ExtD VR design uses less output capacitanceand has same or higher efficiency than a Conv buck.

The advantages of the CI ExtD converter are best understoodby comparing with a Conv buck, a CI buck, and an ExtD buck.The combination of CI ExtD is better than using each mech-anism separately. Table II lists the parameters of an examplecomparison between four different VR configurations.

In this example, the Conv, CI, and ExtD converters all have200 nH steady-state inductances. The CI ExtD has 360 nH,since the ExtD mechanism increases the duty ratio and LSS ofthe CI mechanism is larger when the duty ratio is higher. Bothconverters with CI have 50 nH transient inductance, which isfixed by the physical design of the CI part.

Less capacitance is needed for the designs with lower LTR .However, the designs with less capacitance require a higherswitching frequency. The CI ExtD design achieves both lowcapacitance and high efficiency. The performances of the fourVR configurations are given in Table III.

In these examples, it was found that the CI ExtD converter hadits highest efficiency when operated at 689 kHz, which is higherthan all other configurations. Even at this higher switching fre-quency, the CI ExtD is higher light-load and average efficiencyand only slightly lower thermal current (60 A) efficiency thanthe Conv converter. But the CI ExtD uses much less capacitancethan the conv.

It should be noted that the frequency scaling factor αf ishigher for the topologies with uncoupled inductors. This occurssince the minimum switching frequency for VRs with large Co ismuch lower than the optimal frequency. The critical inductancedesign approach was used to size the inductance relative to thecapacitance. The minimum closed-loop bandwidth and hencethe minimum switching frequency are determined by the amountof capacitance. For fixed transient specifications and using thesame switches and inductors, the designs with more capacitanceare less constrained in regard to the switching frequency. In the

large Co designs, the inductor current ripple can become large ifthe minimum switching frequency is used; hence, these designshave higher αf .

Hardware prototypes were constructed for the four topolo-gies. The operating conditions were 12 Vdc input and 1.2 Vdcoutput. As expected, the CI case has the lowest efficiency ofthe four topologies, whereas the ExtD converter has the highestefficiency. Measured efficiency data of the four configurationsare plotted in Fig. 8.

The efficiency data show that the ExtD configuration is themost efficient, whereas the CI configuration is the least efficient.The CI ExtD and the Conv converters have similar efficiency.The CI ExtD is slightly more efficient at lighter loads than theConv converter.

The cases with CIs have significantly lower capacitance thanthe uncoupled designs. Therefore, it is expected that the cost-per-watt (i.e., capacitance/efficiency) is lower for the CI config-urations. Second, the cases with ExtD have high efficiency, so itis expected that the cost-per-watt is lower. Thus, it is reasonableto expect that the combination of CI and ExtD yield the lowestcost-per-watt. The experimental data confirm this hypothesis;the CI ExtD converter uses one-third of the capacitance as theConv converter, has similar average and thermal design efficien-cies, and is 4% more efficient at light-load. Thus, the CI ExtDconverter has the lowest cost-per-watt. The cost-per-watt datafor the four configurations is shown in Fig. 9.

For all three efficiency norms (1, average; 2, light load; and3, thermal), the cost-per-watt from highest to lowest is ordered:conv, ExtD, CI, and CI ExtD. Hence, the data confirm that thecombination of CI and ExtD is the most optimal VR config-uration. A CI VR also has low cost-per-watt, but it has verylow efficiency compared to the other configurations. Recall thatthe VR optimization problem posed in this paper is constrainedsuch that the VR design is at least as efficient as some mini-mum value. The CI configuration is about 5% less efficient thanthe Conv converter, which is likely too low for this exampleapplication.

In terms of an all-ceramic-output capacitor design, the Convconverter requires one hundred twenty-three 22-µF ceramic ca-pacitors to create 2.7 mF. Using 123 components is not an at-tractive design. Such a solution would be expensive, and thepower delivery performance could be poor. It would consumeconsiderable board area, and the impedance between individ-ual components of the ceramic capacitor network could yieldpoor combined impedance for the power delivery path. As such,most Conv VR designs use large bulk electrolytic capacitorsfor most of the output capacitance. The bulk capacitors are lessexpensive per unit capacitance, but have larger equivalent seriesresistance (ESR) than ceramics. Therefore, ceramics are alsoused for high-frequency decoupling.

The CI ExtD converter requires only 41 ceramic capacitors.This is a very reasonable all-ceramic solution. No bulk capaci-tors are required. The CI ExtD converter is much less expensive(using one-third of the capacitance) and just as efficient as aConv converter (4% higher efficiency at light load and only1% lower efficient at thermal load). Thus, CI ExtD is the mostoptimal topology for VR applications.


TABLE IIIPERFORMANCE OF CI AND EXTD BUCK VR CONFIGURATIONS: CAPACITANCE AND EFFICIENCY NORMS

Fig. 8. Measured efficiency versus load current for Conv, ExtD, CI, and CIExtD VRs.

Fig. 9. Measured cost-per-watt data for Conv, ExtD, CI, and CI ExtD VRs.

IV. CONCLUSION

This paper has discussed the VR design requirements for ap-plications like microprocessor point-of-load converters. It wasargued that transient performance is a pass-or-fail test. All fea-sible VR designs will meet these minimum specifications, and

there is no competitive advantage for improving the performancebeyond the minimum if the cost of the converter increases or theefficiency decreases. Therefore, it is suggested that VR designoptimization focus on the tradeoff between cost and efficiency.A VR optimization problem was posed using a new metric,cost-per-watt, with constraints of the transient performance andminimum efficiency requirements. The optimal solution wasfound to be trivial, using the cost-per-watt metric to measure thetradeoff between the amount of output capacitance and the effi-ciency. The relationship between capacitance and cost-per-wattis almost linear, so the optimal solution is the feasible VR withefficiency equal to the constraint that has the minimum amountof capacitance. CI and ExtD mechanisms were discussed. CIsallow for less output capacitance but at the cost of lower effi-ciency. The ExtD mechanism reduces the switching losses andcan compensate for the lower efficiency using CIs. Thus, it wasshown that the CI ExtD converter is the most optimal VR con-figuration. It uses one-third of the output capacitance and is 4%more efficient at light load than the Conv buck VR.

REFERENCES

[1] Intel Corporation. (2006). Voltage regulator-down (VRD) 11.0[Online]. Available: ftp://download.intel.com/design/processor/applnots/31321402.pdf

[2] X. Zhou, P.-L. Wong, P. Xu, F. C. Lee, and A. Q. Huang, “Investigationof candidate VRM topologies for future microprocessors,” IEEE Trans.Power Electron., vol. 15, no. 6, pp. 1172–1182, Nov. 2000.

[3] Y. Panov and M. M. Jovanovic, “Design considerations for 12-V/1.5-V,50-A voltage regulator modules,” IEEE Trans. Power Electron., vol. 16,no. 6, pp. 776–783, Nov. 2001.

[4] K. Yao, M. Xu, Y. Meng, and F. C. Lee, “Design considerations for VRMtransient response based on the output impedance,” IEEE Trans. PowerElectron., vol. 18, no. 6, pp. 1270–1277, Nov. 2003.

[5] Y. Qiu, K. Yao, Y. Meng, M. Xu, F. C. Lee, and M. Ye, “Control-loopbandwidth limitations for multiphase interleaving buck converters,” inProc. IEEE APEC 2004, pp. 1322–1328.

[6] Y. Ren, K. Yao, M. Xu, and F. C. Lee, “Analysis of the power delivery pathfrom the 12-V VR to the microprocessor,” IEEE Trans. Power Electron.,vol. 19, no. 6, pp. 1507–1514, Nov. 2004.

[7] A. V. Peterchev and S. R. Sanders, “Load-line regulation with estimatedload-current feedforward: Application to microprocessor voltage regula-tors,” IEEE Trans. Power Electron., vol. 21, no. 6, pp. 1704–1717, Nov.2006.

[8] B. Oraw and R. Ayyanar, “Multivariable analysis of VR controllers withload line regulation and phase current balancing,” in Proc. IEEE APEC2008, Feb., pp. 1728–1734.

[9] P.-L. Wong, P. Xu, P. Yang, and F. C. Lee, “Performance improvementsof interleaving VRMs with coupling inductors,” IEEE Trans. PowerElectron., vol. 16, no. 4, pp. 499–507, Jul. 2001.

[10] J. Li, A. Stratakos, A. Schultz, and C. R. Sullivan, “Using coupled induc-tors to enhance transient performance of multi-phase buck converters,” inProc. APEC 2004, pp. 1289–1293.


[11] P. Xu, J. Wei, and F. C. Lee, “Multiphase coupled-buck converter—Anovel high efficient 12 V voltage regulator module,” IEEE Trans. PowerElectron., vol. 18, no. 1, pp. 74–82, Jan. 2003.

[12] Y. Dong, F. C. Lee, and M. Xu, “Evaluation of coupled inductor voltageregulators,” in Proc. IEEE APEC 2008, Feb., 2009, pp. 831–837.

[13] Y. Jang, M. M. Jovanovic, and Y. Panov, “Multiphase buck converterswith extended duty cycle,” in Proc. IEEE APEC 2006, Mar., pp. 38–44.

[14] B. Oraw and R. Ayyanar, “Small signal modeling and control designfor new extended duty ratio, interleaved multiphase synchronous buckconverter,” in Proc. INTELEC 2006, Feb., pp. 1–8.

[15] K. Abe, K. Nishijima, K. Harada, T. Nakano, T. Nabeshima, and T. Sato,“A novel multi-phase buck converter for lap-top PC,” in Proc. PCC-NAGOYA 2007, Apr., pp. 885–891.

[16] X. Zhou, T. Wang, and F. Lee, “Optimizing design for low-voltage DC-DCconverters,” in Proc. IEEE APEC 1997, Feb., pp. 612–616.

[17] Y. Ren, M. Xu, J. Zhou, and F. C. Lee, “Analytical loss model of powerMOSFET,” IEEE Trans. Power Electron., vol. 21, no. 2, pp. 310–319,Mar. 2004.

[18] J. A. A. Qahouq, O. Abdel-Rahman, L. Huang, and I. Batarseh, “On loadadaptive control of voltage regulators for power managed loads: Controlschemes to improve converter efficiency and performance,” IEEE Trans.Electron., vol. 22, no. 5, pp. 1806–1819, Sep. 2007.

[19] Z. Zhang, W. Eberle, Z. Yang, Y. F. Liu, and P. C. Sen, “Optimal designof resonant gate driver for buck converter based on a new analytical lossmodel,” IEEE Trans. Power Electron., vol. 23, no. 2, pp. 653–666, Mar.2008.

[20] J. Torresola, C. P. Chiu, G. Chrysler, D. Grannes, R. Mahajan, R. Prasher,and A. Watwe, “Density factor approach to representing impact of diepower maps on thermal management,” IEEE Trans. Adv. Packag., vol. 28,no. 4, pp. 659–664, Nov. 2005.

[21] B. Oraw and R. Ayyanar, “Stability of multi-winding coupled inductorsin buck converters,” in Proc. INTELEC 2008, Sep., pp. 1–6.

Bradley S. Oraw received the Ph.D. degree fromArizona State University, Tempe, in 2008.

He is currently an Electrical Engineer for NthDegree Technologies, Tempe, where he leads newproduct development focusing on power suppliesand magnetic components for lighting and con-sumer products. His current research interests in-clude topologies and controls for power electronicsystems, circuit theory, and magnetic design. He hasfour patents pending in the areas of switched capac-itor power converters and integrated power delivery

architectures.Dr. Oraw was the recipient of the 2006 Joseph J. Suozzi International

Telecommunications Energy Conference (INTELEC) Fellowship in powerelectronics.

Rajapandian Ayyanar (S’97–M’00–SM’06) re-ceived the M.S. degree from the Indian Institute ofScience, Bangaluru, India, and the Ph.D. degree fromthe University of Minnesota, Minneapolis.

He is currently an Associate Professor at ArizonaState University, Tempe. His current research in-terests include topologies and control methods forswitch-mode power converters, fully modular powersystem architecture, new PWM techniques, design ofpower conversion systems and distribution systemsfor large-scale, distributed integration of renewable

energy resources—mainly solar photovoltaic (PV) and wind and power elec-tronics applications in enabling “smart grid.”

Dr. Ayyanar received an Office of Naval Research (ONR) Young InvestigatorAward in 2005. He is currently an Associate Editor for the IEEE TRANSACTIONS

ON POWER ELECTRONICS.

Documents

Voltage Regulator Optimization Using Multiwinding Coupled Inductors and Extended Duty Ratio Mechanisms