Volume 1, January 2013

HCTL Open International Journal of Technology Innovations and Research (IJTIR) is an international, open-access, peer-reviewed journal devoted to

various disciplines of Science and Technology published (bi-monthly) by HCTL Open Publishing, India.

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HCTL Open Publishing, India.

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Phone: +91 810 955 9626

HCTL Open International Journal of Technology Innovations and Research (IJTIR)

Volume 1, January 2013

Edited by: Raj Gaurav Mishra

For HCTL Open Publishing

HCTL Open International Journal

ofTechnology Innovations and Research (IJTIR)

An International, Open-Access, Peer-Reviewed, Online JournalDevoted to Various Disciplines of Science and Technology.

Volume 1, January 2013

Edited by

Raj Gaurav MishraEditor-in-chief

for HCTL Open International Journal of Technology Innovations and Research(IJTIR)

31 January 2013

HCTL Open Publishing

http://www.hctl.org/publishing.html

Volume 1

January 2013

HCTL Open International Journal of TechnologyInnovations and Research (IJTIR)

e-ISSN: 2321-1814ISBN (Print): 978-1-62776-012-6

Raj Gaurav Mishra

Publisher:

HCTL Open Int. J. of Technology Innovations and Research (IJTIR)Volume 1, January 2013

Title Information

HCTL Open International Journal of Technology Innovations and Research(IJTIR)Volume 1, January 2013Date of Online Publishing: 31-January-2013

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c© HCTL Open Publishing, India.This volume is an open-access document, distributed under the terms andconditions of the Creative Commons Attribution 3.0 Unported License(http://creativecommons.org/licenses/by/3.0/).

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Published by:HCTL Open Publishing,Bhopal, MP, IndiaEmail: [email protected]: http://www.hctl.org/IJTIR.html

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Editorial Board Members

Publication Heads

Nirmala MishraHybrid Computing Technology Labs, India

Raj Gaurav MishraHybrid Computing Technology Labs, India

Editor-in-Chief


Associate Editors

Charu AgrawalAssistant Prof., Galgotia University, Greator Noida, India

Manish Kumar JaiswalResearcher, City University of Hongkong, Hongkong

Sanchita SenguptaResearcher, Delft Institute of Technology, Delft, Netherlands

Surajit PaulResearcher, IUCAA, University of Pune, Pune, MH, India

Abhay VidhyarthiAssistant Prof., ITM-University, Gwalior, MP, India

Amit ShrivastavaAssistant Prof., NRI-ITM, Gwalior, MP, India

Anand SrivastavaResearcher, Indian Institute of Technology - Mandi, HP, India

Devendra BhavsarAssistant Prof., J.K. Lakshmipath University, Jaipur, Rajasthan,

India

Gajendra SharmaResearcher, Indian Institute of Information Technology -

Allahabad, UP, India

Gaurav MishraAssistant Prof., SRMS, Bareily, UP, India

Ismathullakhan ShafiqResearcher, City University of Hongkong, Hongkong

Jayant SupaleAssistant Prof., SKN SITS, Mumbai-Pune Express Highway, Lonavala,

MH, India

Krishnakant AgrawalResearcher, Indian Institute of Information Technology -


Manisha RajpootReader, Rungta College of Engineering & Technology, Bhillai, CG,

India


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Pawan MishraResearcher, King Abdulla University of Science & Technology,

Saudi Arabia

Pawan VermaResearcher, Motilal Nehru National Institute of Technology -


Preetam SumanResearcher, Indian Institute of Information Technology -


Ravi BhramarambaAssociate Prof., GITAM Institute of Technology, GITAM UNIVERSITY,

AP, India

Ravindra MeenaAssistant Prof., J.K. Lakshmipath University, Jaipur, Rajasthan,

India

Richa ChauhanResearcher, Hybrid Computing Technology Labs, India

Sandeep BhaskarAssistant Prof., Echelon Institute of Technology, Faridabad, UP,

India

Shaishav AgrawalResearcher, Indian Institute of Information Technology -


Shubhi ShrivastavaResearcher, Hybrid Computing Technology Labs, India

Vimal UpadhyayResearcher, Indian Institute of Information Technology -


Vipin PataitAssistant Prof., ICFAI University, Faculty of Science &

Technology, Dehradun, UK, India

Vishal SrivastavaAssistant Prof., Selaqui Institute of Engineering & Technology,

Dehradun, UK, India

Zahid UllahResearcher, City University of Hongkong, Hongkong

Technical Advisors

Amit BhargawaSr. Consultant (IT & Networking), HCL Technologies, Noida, UP,

India

Ankit SharmaSr. Consultant (IT & Networking), HCL Technologies, Noida, UP,

India

Arpit SethSr. Consultant, Capgemini, Mumbai, MH, India


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Chandra Shekhar BhadauriaSr. Consultant (IT Services), Impetus Technologies, Inc.,

Indore, MP, India

Naval GargSr. Consultant (IT Services), Tata Consultancy Services, USA

Rahul ShrivastavaSr. Consultant (Marketing and Sales), Hybrid Computing

Technology Labs, India

Ritika ChauhanSr. Consultant (IT & Marketing), Hybrid Computing Technology

Labs, India

Rohit TripathiSr. Consultant (Technical), Subros - India, Greater Noida, India

Rudransh SharmaSr. Consultant (IT Services), Tata Consultancy Services, Mumbai,

MH, India

Sagar AmbasthaSr. Consultant (IT Services), Amdocs, Pune, MH, India

Vinod Kumar SinghSr. Consultant (Technical), Reliance Industries Ltd., Mumbai,

MH, India

Authors/Contributors - Volume 1 (January 2013)


Amit ShrivastavaAssistant Prof., NRI-ITM, Gwalior, MP, India

Preetam SumanResearcher, Indian Institute of Information Technology -


Amrit SumanAssistant Prof., Laxmi Narayan College of Technology, Bhopal, MP,

India

Vimal UpadhyayResearcher, Indian Institute of Information Technology -


Krishnakant AgrawalResearcher, Indian Institute of Information Technology -


Mukesh ChandM.D.U. Rohtak, Haryana, India

Devesh MishraM.Tech. Student, Indian Institute of Information Technology -



Page 7




















Editorial and Forewords

We are very happy to publish the first volume of HCTL Open InternationalJournal of Technology Innovations and Research (IJTIR).

HCTL Open International Journal of Technology Innovations and Research(IJTIR) is an international, open-access, peer-reviewed journal devoted tovarious disciplines of Science and Technology published by HCTL OpenPublishing, India.

This issue contains three research articles. Achieving such a high quality ofpapers would have never been possible without the huge work that wasundertaken by the Journal’s Production and Promotion Team, Editorial BoardMembers, Technical Advisory Committee Members and External Reviewers.

The first research article Implementation of Custom Precision Floating

Point Arithmetic on FPGAs have presented an empirical result of theimplementation of custom-precision floating point numbers on an FPGAprocessor using the rules of IEEE standards defined for single and doubleprecision floating point numbers.

In the second research article An Enhanced TCP Corruption Control

Mechanism For Wireless Network, an improved mechanism for TransmissionControl Protocol (TCP) corruption control and the comparative study ofEnhanced TCP (ETCP) with other TCP variants is presented on variousparameters like mobility, size of network and the speed.

In the third research article Ultrasonic Sensors Supervision of

Petrochemical and Nuclear Plant, a method of NDT (Non DestructiveTesting) for measurement of flow accelerated corrosion or thicknessdegradation in the pipelines used in oil and nuclear plants by using ultrasonicsensors is presented.

We take this opportunity to thank everyone (including Authors of thisvolume) for their great support and cooperation and we wish for their similarkind of support in future.

Raj Gaurav Mishra,Founder and Managing Director for HCTL Open Publishing, India

Editor of Volume 1, January 2013 - HCTL Open IJTIR


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Contents

S. No. Title of the Research Article Page No.

1. Cover Pages 1 - 3

2. Bibliographic Information 4

3. Editorial Board Members 5 - 7

4. Editorial and Forewords 8

5. Implementation of Custom Precision Floating Point Arith-metic on FPGAs.

10 - 26

6. An Enhanced TCP Corruption Control Mechanism ForWireless Network.

27 - 40

7. Ultrasonic Sensors Supervision of Petrochemical and Nu-clear Plant.

41 - 49


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HCTL Open Int. J. of Technology Innovations and ResearchHCTL Open IJTIR, Volume 1, January 2013e-ISSN: 2321-1814ISBN (Print): 978-1-62776-012-6

Implementation ofCustom PrecisionFloating PointArithmetic on FPGAsRaj Gaurav Mishra and Amit Kumar [email protected] and [email protected]

Abstract

Floating point arithmetic is a common requirement in signalprocessing, image processing and real time data acquisition &processing algorithms. Implementation of such algorithms on

FPGA requires an efficient implementation of floating point arith-metic core as an initial process. We have presented an empiricalresult of the implementation of custom-precision floating point num-bers on an FPGA processor using the rules of IEEE standards de-fined for single and double precision floating point numbers. Float-ing point operations are difficult to implement on FPGAs becauseof their complexity in calculations and their hardware utilization forsuch calculations. In this paper, we have described and evaluated theperformance of custom-precision, pipelined, floating point arithmeticcore for the conversion to and from signed binary numbers. Then,we have assessed the practical implications of using these algorithmson the Xilinx Spartan 3E FPGA boards.

Raj Gaurav Mishra and Amit Kumar ShrivastavaImplementation of Custom Precision Floating Point Arithmetic on FPGAs.

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Keywords

Field Programmable Gate Array (FPGA), floating point arithmetic, custom-precision floating point, floating point conversion.

Introduction

With the advent of sensor technology, it is now possible to measure and monitora large number of parameters and to carefully use them in a number of fieldssuch as medical, defence, commercial etc. for various applications. Real-timeimplementation of sensor based application requires a system which can read,store and process the sensor data using micro-controllers or FPGAs as processors.Figure 1 shown below, represents a real-time data acquisition system based ona FPGA processor. Such a system comprises of a single or multiple sensors,signal conditioning unit (filters and amplifiers) and analog to digital converters.The output of the analog to digital converter is generally connected to the inputof the processor (FPGA device in our case) for further signal acquisition andprocessing.

Figure 1: Block diagram of a FPGA processor based real-time sensor data acquisitionsystem.

It is important for FPGA processor to store the real time sensor valuesto an external memory device for signal processing using custom algorithms.For example, analysing sound/speech in real time requires recording of soundsignals using a microphone (sensor) using a high speed FPGA processor andthen storing the resultant sensor values into a floating point format to maintaina specific accuracy and resolution. Floating point number system in comparisonwith binary number system have a better dynamic range and are better in


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handling underflow and overflow situations during mathematical calculations(signal processing). In this way, when a sensor value is stored in floating pointformat provides a base for accurate signal processing.

In this paper, a pipelined implementation and hardware verification of customprecision floating point arithmetic on FPGA have been reported and discussed.Here, we assume that the reader is familiar with FPGA [1], its programmingusing Verilog HDL [2]-[3] and the single precision, double precision floatingpoint standards [4] defined by IEEE. Comparatively, floating point numbersystems have a better dynamic range than a fixed point number system; alsothey are better in handling underflow and overflow situations during mathe-matical calculations however the speed and complexity issues rises when animplementation on FPGA processors comes into consideration. Research hasbeen done to experiment various optimized implementations of IEEE singleprecision [7]-[10] and double precision [11]-[15] floating point arithmetic onFPGA. Algorithms for floating point implementation are complex in nature andwith the number of bits used in single or double precision made them utilize alarge area of the FPGA chip with a considerable processing time. Need of acustom precision floating point system arises when a real-time image or digitalsignal processing applications are to be implemented on an FPGA processor,where a requirement of high throughput in calculation and a balanced time-area-power implementation of the algorithm becomes an important requirement.In this way, an embedded designer can choose a suitable custom floating-pointformat depending upon the available FPGA space for the required embeddedapplication.

Table 1 shows the basic comparison between the 17-bits custom precision,IEEE standards of single, double and quadruple precision floating point numbers.

This paper is organized as section 2 presents the custom precision floatingpoint format in details. In section 3, we have described the algorithm andflowchart for the conversion of 12 bit signed binary number to 17 bits customprecision floating point number, the algorithm and flowchart for the conversionof 17 bits custom precision floating point number to a 12 bit signed binarynumber, along with their simulation results, synthesis summary and hardwareverifications. Section 4 concludes this paper with the scope of future work whichcan be extended in various ways.


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Table 1: Different floating point formats.

Custom Preci-sion

Single Preci-sion

Double Preci-sion

Quadruple Pre-cision

WordLength

17 bits 32 bits 64 bits 128 bits

Mantissa 10 bits 23 bits 52 bits 112 bitsExponent 6 bits 8 bits 11 bits 15 bitsSign 1 bit 1 bit 1 bit 1 bitBias 26−1-1=31 28−1-1=127 211−1-1=1023 215−1-1=16383Range About

4.3x109=(232)About3.5x1038=(2128)

About1.8x10308=(21024)

About1.2x104932=(216384)

Custom Precision Floating Point Format

Floating-point systems were developed to provide high resolution over a largedynamic range. Floating-point systems can often provide a solution whenfixed-point systems, with their limited dynamic range, fail. Floating-pointsystems, however, bring a speed and complexity penalty. Most microprocessorfloating-point systems comply with the published single- or double-precisionIEEE floating-point standard; while in FPGA-based systems often employcustom formats.

A standard floating-point word consists of a sign-bit S, exponent E, and anunsigned (fractional) normalized mantissa M, arranged as shown in the figure 2.

Figure 2: 17 bits Custom Precision Floating Point format.

The minimum number custom precision floating point number (1,6,10) formatcan represent is:


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(±0.0000000004656612873077392578125)10 or (±0.0000000000000000000000000000001)2.Minimum number representation in custom precision floating point format is(00000000000000000)1,6,10 for a positive number and (10000000000000000)1,6,10for a negative number.

The maximum number custom precision floating point number (1,6,10) formatcan represent is: (±4, 29, 49, 67, 296.00)10 or (±100000000000000000000000000000000)2.Maximum number representation in custom precision floating point format is(01111110000000000)1,6,10 for a positive number and (11111110000000000)1,6,10for a negative number.

Figure 3: Method of converting a fixed point decimal number in to a custom precisionfloating point number (1,6,10) format [5]-[6].


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Table 2: Some Examples values of 17-bit Custom Precision Floating-Point Format.

S.No. 17-bit custom precisionfloating-point format(1,6,10)

Equivalent decimal values

1 0 000000 0000000000 Represents a minimum number (+0)2 1 000000 0000000000 Represents a minimum number (−0)3 0 011111 0000000000 +1.04 1 011111 0000000000 −1.05 0 111111 0000000000 Represents a maximum number

(+∞)6 1 111111 0000000000 Represents a maximum number

(−∞)

Floating Point Operations on FPGA

Signed Binary to Custom Precision Floating Point Conversion

Considering the system defined in the figure 1, an embedded designer can choose8-bit, 12-bit or 16-bit analog to digital converters to adjust the required resolu-tion of the sensor value for an application. Texas Instruments ADS7828 [16] orany other similar 12-bit ADC is more suitable for the algorithm developed andpresented in the following section.

Algorithm 1 describes the step-wise approach of programming an FPGA forthe conversion of a 12-bit signed binary number in to a 17-bit custom-precisionfloating point number.

The flow diagram of the algorithm 1 is shown in the figure 4. Table 3 showsthe synthesis summary of hardware utilization and speed for the algorithm 1on different FPGA processors. Figure 5 shows the simulation results for thealgorithm 1 implemented using verilog HDL on Xilinx ISE Project NavigatorVer. 13.4 and ISE Simulator [17].

Custom Precision Floating Point to Signed Binary Conversion

Algorithm 2 defines the step-wise approach of programming an FPGA for theconversion of a 17-bit custom-precision floating point number in to a 12-bitsigned binary number. The flow diagram of the algorithm 2 is shown in the


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Algorithm 1 Converting a Signed Binary number (12 bits) in to a Custom-Precision (17 bits) Floating Point number (1,6,10) format.

Require: 12 bits signed binary number as input.Ensure: 17 bit custom-precision floating point number (1,6,10) format as

output.1: Store the value of input to a temporary register R1 (size 12 bits).2: Check for the sign-bit:3: if Sign-bit is equal to 1 (Input is a negative number): then Take 2’s

complement of the values stored in R1 register (input value) and store theresults to a temporary register R2 (size 12 bits).

4: else if Sign-bit is equal to 0 (Input is a positive number): then Storethe value of temporary register R1 to temporary register R2 without anymodifications.

5: end if6: Scan all the bit values of register R2 starting from (MSB − 1) towards LSB

and search for first HIGH (1) bit value.7: Count of the total bits towards right side (towards LSB) from the first

HIGH (1) bit found, and store this count to a temporary register R3 (size 4bits).

8: Store all the bits towards right side (towards LSB) from the first HIGH (1)bit found, to a temporary register R4 (size 10 bits).

9: Calculate the addition of the count stored in temporary register R3 withthe value of fixed bias* and store the results to a temporary register R5(size 6 bits). This forms the exponent value. Calculation of Fixed Bias* =2E−1 − 1 = 26−1 − 1 = 3110 or 0111112. (E is the number of bits allocatedfor exponent in the floating point format).

10: Normalize the value of register R4 (bit shifting towards MSB to fit the valuescompletely in 10 bits format). Store the resultant value to a temporaryregister R6. This forms the mantissa value.

11: Store the sign bit from the input value (as stored in register R1), valueof register R5 (exponent) and value of register R6 (mantissa) in a 17 bitscustom (1,6,10) format to a temporary register R7 (size 17 bits).

12: Connect the temporary register R7 to the output.13: 17 Bit custom-precision floating point number (1,6,10) format.


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Table 3: Synthesis Summary for 12 bit Signed Binary Number to 17 bit CustomPrecision Floating Point Conversion.

FPGA Pro-cessor

SpeedGrade

Numberof SlicesUsed

Numberof SliceFlipFlopsUsed

Numberof 4inputLUTsUsed

NumberofbondedIOBsUsed

MaximumFre-quency

Spartan 3EXC3S500E

-5 71 out of4656

70 out of9312

134 outof 9312

30 out of232

174.304MHz

Spartan 3EXC3S1200E

-5 71 out of8672

70 out of17344

134 outof 17344

30 out of250

174.304MHz

Spartan 6XC6SLX25

-3 77 out of30064

138 outof 15032

162 outof 486

30 out of226

212.770MHz

Virtex 4XC4VFX100

-12 83 out of42176

70 out of84352

157 outof 84352

30 out of576

338.324MHz

Virtex 5XC5VFX100T

-3 70 out of64000

94 out of64000

113 outof 339

30 out of680

394.120MHz

Virtex 6XC6VCX130T

-2 69 out of160000

120 outof 80000

136 outof 408

30 out of240

433.529MHz

figure 8.

Table 4 shows the synthesis summary of hardware utilization and speed forthe algorithm 2 on different FPGA processors. Figure 6 shows the simulationresults for the algorithm 2 implemented using verilog HDL on Xilinx ISE ProjectNavigator Ver. 13.4 and ISE Simulator [17].

Algorithms 1 and 2 have been tested and verified on Digilent NEXYS 2 FPGAboard [18] containing Spartan 3E [19] XC3S1200E FPGA processor as shown infigure 7. To verify the correctness of the algorithm different inputs were giventhrough different combinations of on-board switches and output was receivedthrough the LEDs connected to the I/O pins of the FPGA processor.


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Algorithm 2 Converting a Custom-Precision (17 bits) Floating Point number(1,6,10) format in to a Signed Binary number (12 bits).

Require: 17 bit custom-precision floating point number (1,6,10) format asinput.

Ensure: 12 bits signed binary number as output.1: Store the MSB value of input to a temporary register R1 (size 1 bit). This

is for the purpose of defining sign bit.2: Store the 10 bits from the LSB towards MSB to a temporary register R2

(size 11 bits). This is to be used as mantissa for further calculations.3: Assign the MSB bit of temporary register R2 as HIGH (1) to incorporate

the hidden 1 bit.4: Store the remaining 6 bits from the input to a temporary register R3 (size

6 bits). This is to be used as exponent for further calculations.5: Calculation of exponent value (in order to normalize the mantissa): Values

stored in register R3− Bias* = Value of exponent by which mantissa is tobe normalized. Store this value to a temporary register R4 (size 8 bits).Calculation of Fixed Bias* = 2E−1 − 1 = 26−1 − 1 = 3110 or 0111112. (E isthe number of bits allocated for exponent in the floating point format).

6: Normalization of mantissa value to fit in 11 bits:7: if the value stored in register R3 (exponent value) is equals to 0 (zero).

then the value of mantissa will become 0 (zero).8: end if9: if the value stored in register R4 (exponent count) is equals to 0. then

the value of mantissa is to be bit-shifted 10 times towards left (MSB) fornormalization.

10: end if11: if the value stored in register R4 (exponent value) is equals to 1. then




14: end if15: if the value stored in register R4 (exponent count) is equals to 3. then




18: end if


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19: if the value stored in register R4 (exponent value) is equals to 5. thenthe value of mantissa is to be bit-shifted 5 times towards left (MSB) fornormalization.








the value of mantissa is to be bit-shifted 1 time towards left (MSB) fornormalization.

28: end if29: Store the resultant value of mantissa after suitable bit-shifting (normaliza-

tion) to a temporary register R5 (size 11 bits).30: Check for the sign-bit stored in the register R1:31: if Sign-bit is equal to 1 (Input is a negative number): then Take 2’s

complement of the values stored in R5 register (normalized value of mantissa)and store the results to a temporary register R6 (size 12 bits).

32: else if Sign-bit is equal to 0 (Input is a positive number): then Storethe value of temporary register R5 to temporary register R6 without anymodifications.

33: end if34: Connect the temporary register R6 to the output.35: 12 bits signed binary number.


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Table 4: Synthesis Summary for 17 bit Custom Precision Floating Point to 12 bitSigned Binary Number Conversion.

FPGA Pro-cessor

SpeedGrade

Numberof SlicesUsed

Numberof SliceFlipFlopsUsed

Numberof 4inputLUTsUsed

NumberofbondedIOBsUsed

MaximumFre-quency

Spartan 3EXC3S500E

-5 56 out of4656

47 out of9312

100 outof 9312

30 out of232

199.222MHz

Spartan 3EXC3S1200E

-5 56 out of4656

47 out of9312

100 outof 9312

30 out of232

199.222MHz

Spartan 6XC6SLX25

-3 48 out of30064

72 out of15032

90 out of486

30 out of226

248.738MHz

Virtex 4XC4VFX100

-12 55 out of42176

47 out of84352

99 out of84352

30 out of576

340.833MHz

Virtex 5XC5VFX100T

-3 47 out of64000

61 out of64000

80 out of339

30 out of680

440.567MHz

Virtex 6XC6VCX130T

-2 47 out of160000

72 out of80000

90 out of408

30 out of240

461.563MHz

Conclusion and Future work

We have successfully implemented and tested the functionality of custom preci-sion floating point numbers on FPGAs. The main objective of this research isto develop and implement a real-time sensor data acquisition system based onFPGA. In order to achieve it, the following activities are planned be carriedout in future: Implementation of Multiplication, Addition/Subtraction andDivision algorithms on custom precision numbers on FPGAs, Implementationof I2C protocol to read serial ADC data on FPGA, Implementation of SDcard and display module on FPGA to store and display real-time sensor data.These algorithms would be helpful in handling physical connections, storageand display of incoming sensor data and implementation of some basic digitalsignal processing techniques.


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HCTL Open Int. J. of Technology Innovations and ResearchHCTL Open IJTIR, Volume 1, January 2013e-ISSN: 2321-1814ISBN (Print): 978-1-62776-012-6 References

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Accumulation on a Modern FPGA in Single and Double Precision,Field-Programmable Custom Computing Machines (FCCM), 2010 18thIEEE Annual International Symposium on, pp.105-108, 2-4 May 2010.

[15] Kumar, Y.; Sharma, R.K., Clock-less Design for Reconfigurable

Floating Point Multiplier, Computational Intelligence, Modelling andSimulation (CIMSiM), 2011 Third International Conference on, pp.222-226,20-22 Sept. 2011.

[16] Texas Instruments ADS7828 datasheet, Available online at: www.ti.

com/lit/ds/symlink/ads7828.pdf (last accessed on 26-Oct-2012).

[17] Xilinx ISE Project Navigator Ver. 13.4 and Xilinx ISE

Simulator, Available online at: http://www.xilinx.com/products/

design-tools/ise-design-suite/index.htm (last accessed on 26-Oct-2012).

[18] Digilent NEXYS 2 FPGA board, Available online at: http://www.

digilentinc.com/Products/Detail.cfm?Prod=NEXYS2 (last accessed on26-Oct-2012).


Page 22


www.ti.com/lit/ds/symlink/ads7828.pdf

www.ti.com/lit/ds/symlink/ads7828.pdf

http://www.xilinx.com/products/design-tools/ise-design-suite/index.htm

http://www.xilinx.com/products/design-tools/ise-design-suite/index.htm

http://www.digilentinc.com/Products/Detail.cfm?Prod=NEXYS2

http://www.digilentinc.com/Products/Detail.cfm?Prod=NEXYS2


[19] Xilinx Spartan3E FPGA Datasheet, Available online at: www.xilinx.

com/support/documentation/data_sheets/ds312.pdf (last accessed on03-Oct-2012).

This article is an open-access article distributed under the terms and con-ditions of the Creative Commons Attribution 3.0 Unported License (http://creativecommons.org/licenses/by/3.0/).

c© 2013 by the Authors. Licensed & Sponsored by HCTL Open, India.


Page 23


www.xilinx.com/support/documentation/data_sheets/ds312.pdf

www.xilinx.com/support/documentation/data_sheets/ds312.pdf




Figure 4: Flow diagram for conversion of a 12 bit Signed Binary Number in to a 17bit Custom Precision Floating Point Number - Pipelined approach


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Figure 5: Simulation Results for 12 bit Signed Binary Number to 17 bit CustomPrecision Floating Point Conversion

Figure 6: Simulation Results for 17 bit Custom Precision Floating Point to 12 bitSigned Binary Number Conversion

Figure 7: Digilent NEXYS 2 FPGA board hardware setup for algorithm testing andverification


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Figure 8: Flow diagram for conversion of a 17 bit Custom Precision Floating PointNumber in to a 12 bit Signed Binary Number - Pipelined approach


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An Enhanced TCPCorruption ControlMechanism ForWireless NetworkPreetam Suman and Amrit [email protected] and [email protected]

Abstract

Mobile Ad Hoc networks are collections of mobile nodes, dy-namically forming a temporary network without pre-existingnetwork infrastructure or centralized administration. Trans-

mission control protocol (TCP) provides connection oriented, reli-able and end to end mechanism. Comparing to wire networks, thereare many different characteristics in wireless environments. In thispaper an improved mechanism for TCP corruption control is pre-sented. It considers the influences sending rate to TCP sender’spacket not only by the congestion but also by the corruption. Thesending window size calculated after each transmission, based onnumber of corrupted packet. So, there is less packet drop in trans-mission. The comparative study of Enhanced TCP (ETCP) withother TCP variants is also presented on various parameters like mo-bility, size of network and the speed. The improved mechanism isimplemented with fewer overheads and is effectively improve relia-bility with small variances of throughput and delay. Implementationand Simulation is performed in QualNet 4.0 simulator.

Preetam Suman and Amrit SumanAn Enhanced TCP Corruption Control Mechanism For Wireless Network.

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Keywords

Wireless Network, Congestion Control, Corruption Control, TCP Variants.

Introduction

Transmission control protocol (TCP) [1, 2] is the predominant Internet protocoland carries approximately 90% of Internet traffic in today’s heterogeneouswireless and wired networks. TCP is widely used as a connection orientedtransport layer protocol that provides reliable packet delivery over unreliablelinks. TCP does not depend on the underlying network layers and, hence,design of various TCP variants is based on the properties of wired networks.However, TCP congestion control algorithms may not perform efficiently inheterogeneous networks.

Wireless networks have higher bit error rates due to weather conditions, obsta-cles, multipath interferences, mobility of wireless end-devices, signal attenuationand fading, which may lead to packet loss. Various TCP algorithms and tech-niques have been proposed to improve congestion and reduce the non-congestionrelated packet loss. TCP Tahoe [11], TCP Reno [13], TCP Reno with SelectiveAcknowledgement (SACK) [11], TCP NewReno [12], TCP Vegas [15], and TCPFACK [14] are examples of proposed end-to-end solutions. They are all proposedto improve network performance [3]-[9]. The end-to-end techniques are the mostpromising because they require changes only to the end systems instead to theintermediate nodes. These end-to-end control approaches are used in today’sdeployed networks. In Section 2, algorithm of ETCP is described. Descriptionof simulated network is given in Section 3, while simulation scenarios and resultsare described in Section 4, simulation methodology is described in Section 5conclusion and future work is explained with Section 6.

Corruption Loss Rate - The corruption loss rate defined as the packet lossrate because of corruption. Sending rate is not adjusted when the there is littlecorruption loss rate, but its required to decrease the sending rate rapidly toimprove the reliability when the corruption loss rate becomes higher. Otherwise,there will be more lost packets due to corruption and more packets will beretransmission, responding the poor transmission reliability and more energyconsumption of mobile hosts.


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The corruption loss rate define as:

Pe = m/n (1)

Where, Pe is the corruption loss rate defined in [10]. If TCP sender sends npackets in which m packets may be discarded due to weak wireless link.

The corruption loss rate decides by the bit error rate (BER) of wireless linklayer and the length (Length) of data frame:

Pe = 1− (1−BER)Length (2)

If the corruption loss rate Pe is higher than the certain lower limit Pemin, thesending rate will be decreased. Many factors decide the value of corruptionloss rate lower limit Pemin, mainly include: the kind of application; the lengthof data frame; the bit error rate of data link layer; the bandwidth and thetransmission delay of wireless network etc. Normally value of Pemin is 0.4.

Enhance TCP

ETCP (Enhanced Transport Control Protocol) is the improved TCP congestionand corruption control mechanism for wireless network. It considers the influ-ences to TCP sender’s packet sending rate not only by the congestion but alsoby the corruption. It is a good reference to apply the TCP to wireless networks.

Initial Window

The initial sending window is calculated by following formula:Iw= min (4 * SMSS , Max (2 * SMSS , 4380 byte))

Slow-Start Algorithm

The slow start algorithm is used to start a connection of ETCP and the periodsafter the value of retransmission timer exceed the RTO (retransmission timeout).In the start of ETCP, the size of cwnd will be initialized to 1.

The slow start algorithm describes as below:if (Receive ACKs && cwnd < ssthresh)

{cwnd = cwnd++;

}


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The slow start algorithm will be ended in two conditions. First, if the congestionwindow size reaches the slow start threshold size (ssthresh), the slow start willbe ended and then congestion avoidance takes over. Second, if there lose anypacket due to congestion or high packet loss rate due to corruption, the slowstart also will be ended and then fast recovery takes over.

Congestion Avoidance Algorithm

If the congestion window size (cwnd) is less than or equal to the slow startthreshold size (ssthresh), DW-TCP is in slow start; otherwise ETCP is perform-ing congestion avoidance.The congestion avoidance algorithm describes as below:if (Receive ACKs || (Receive Explicit Corruption Loss Notification && Corruption

Loss Rate Pe < Pemin))

{if (cwnd > ssthresh)

cwnd = 1+1/cwnd

else

cwnd++;

if (Receive Explicit Corruption Loss Notification)

Pe= (m/n);

If (Pe < Pemin)

Pemin = Pe;

temp=cwnd* Pemin;

cwnd=cwnd temp;

}In the algorithm, cwnd is the congestion window size; n is total number of pack-ets to be send; m is the number of lost packets due to wireless link corruption;Pe denotes the corruption loss rate.

Fast Retransmission and Fast Recovery

If the network congestion or heavy corruption, the fast recovery algorithm willbe taken. When the network congestion, set ssthresh to one-half the flightsize or double of SMSS (maximum segment size) window. if (Congestion

|| Heavy Corruption)

{if (Receive Same ACK 3 Times || Retransmission Timer Overtime) /* Congestion

*/


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{Ssthresh = max(flightsize/2 , 2*SMSS);

// Flightsize are those data which have no acknowledged.

if (Retransmission Timer Overtime)

{cwnd = 1; Exit and call slow-start;}else /* Receive Same ACK 3 Time */

cwnd = ssthresh;

}else if (Receive Explicit Corruption Loss Notification

&& Corruption Loss Rate Pe>=Pemin)

{temp=cwnd* Pemin;

cwnd=cwnd+ temp;

};if (Receive Explicit Loss Corruption Notification)

Pe= (m/n);

If (Pe < Pemin)

Pemin = Pe;

temp=cwnd*Pemin;

cwnd=cwnd - temp;

}

Computer Simulation

In this paper all the simulation work is performed in QualNet [11] wirelessnetwork simulator version 4.0. Initially number of nodes are 50, Simulationtime was taken 200 seconds and seed as 1. All the scenarios have been designedin 1500m x 1500m area. Mobility model used is Random Way Point (RWP).In this model a mobile node is initially placed in a random location in thesimulation area, and then moved in a randomly chosen direction between at arandom speed between [SpeedMin, SpeedMax]. The movement proceeds for aspecific amount of time or distance, and the process is repeated a predeterminednumber of times. Nodes in network moves with speed of 5 m/s to 30m/s, andwith pause time of 5s to 30s.

All the simulation work was carried out using TCP variants (Reno, Lite, Tahoe)with DSR routing protocol. Network traffic is provided by using File TransferProtocol (FTP) application. File Transfer Protocol (FTP) represents the File


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Transfer Protocol Server and Client.

Simulation Methodology

Parameters Scenario 1 Scenario 2 Scenario 3

Simulation Time constant constant constant

Node constant constant change

Area constant constant constant

Pause Time constant change constant

TCP Protocol change change change

Routing Protocol constant constant constant

Node Speed (m/sec) change constant constant

Table 1: Simulation Scenarios

Performance metrics used for this works are as follows:

Throughput is the measure of the number of packets successfully transmittedto their final destination per unit time. It is the ratio between the numbers ofsent packets vs. received packets.

Signal Received with error is the measure of signal received, but theyhave error. The error may be occurring due to noise or due to heavy traffic.

Bytes received are the measure of total packet received by server. Thepackets may be drop due to heavy traffic. So received packets may be varyaccording to traffic conditions.

Packet loss is the measure of total discarded packet due to corruption ordue to packet drop. It can be calculate by subtracting total received packets byserver with total sent packet by client.

Results and Analysis

Fig 1, 2 & 3 shows signal received with error of different variants with variationin speed of node, pause time and number of node in network. It has to beseen that ETCP has less error signal than other TCP variants. Due to optimal


Page 32



routing path between sender and receiver. When number of node in networkincreases than congestion also occurs, due to this reason, signals were distorted.

Figure 1

Figure 2


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Figure 3

Fig 4, 5 & 6 shows Packet loss of different variants of TCP with variation innode speed, pause time and number of node. It has to be seen that ETCP hasless packet loss than other TCP variants. It is due to proper sending windowsize, which is calculated according to number of discarded packets. So, receivercan receive those packets which are sent by sender.

Figure 4


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Figure 5

Figure 6

Fig 7, 8 & 9 shows the readings of total byte received for different TCPvariants with variation in speed of node, pause time and number of node innetwork. It has to be seen that receiver can receive maximum byte at ETCP,but it is sometimes less due to congestion in network. Sometimes nodes canmove faster, so nodes cannot get proper signal, due to this reason nodes cannotreceived packets.


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Figure 7

Figure 8

Fig 10, 11 & 12 shows throughput of different TCP variants with variationin node speed, pause time and number of node. Throughput is the ratio ofnumbers of sent packets with number of received packets. It has to be seenthat Throughput of ETCP is better than other TCP variants. Receiver receivemaximum packets and there are less packets were discarded, due to this reasonthroughput is better.

Conclusion

An enhanced TCP (ETCP) is proposed with a new calculation for sendingwindow and implemented it in a Mobile Ad-hoc Network in QualNet 4.0. It


Page 36



Figure 9

Figure 10

considers the influences sending rate to TCP sender’s packet not only by thecongestion but also by the corruption. The sending window for ETCP is calcu-lated according to packet corrupted in network. Extensive simulation studieswere undertaken to compare its performance with other standards TCP Reno,TCP Lite and TCP Tahoe over Ad-hoc Mobile Network. The simulation resultsshow that the performance of ETCP is better than other than other TCPvariants. The performance of TCP variants are analysed on various parameterslike mobility, size of network and the speed. The comparison of TCP variantsare performed using various performance metrics like signal received with error,total data packet received, total packet drop and throughput.


Page 37



Figure 11

Figure 12

From results of implementation it has be seen that the performance of ETCPis better in high density node because in this condition sender can get differentpaths through different nodes.

Packets can be corrupted due to congestion in network or heavy traffic, due tothis reason packet drop is fewer in less density network.

Signals also affected due to improper routing path in network, so maximumsignal were distorted when nodes in network are moving with speed of 5m/sec.


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Throughput depends on number of packet received and number of packetsloss. It is better in high density network, because receiver can receive maximumpackets when number of node in network is 50.

Future Work

The performance of ETCP can be measured in different wireless environmentsespecially those with high error rates. It can also be plan to build a flexible andlightweight transport protocol for the wireless side of ETCP which can adaptto changes in the wireless environment and can support planned disconnections.Presentation layer services can also be built on top of ETCP which will allowmobile applications to dynamically choose a format for data transmitted over thewireless medium. Other work includes testing throughput intensive applicationssuch as ftp and mosaic with ETCP.

References

[1] J. Postel, Transmission control protocol, RFC 793, Sept.1981.

[2] A. Gurtov and S. Floyd, Modeling wireless links for transport

protocols, ACM SIGCOMM Comput. Commun. Rev., vol. 34, no. 2,pp. 85-96, Apr. 2004.

[3] G. Holland and N. Vaidya, Analysis of TCP performance over mobile

ad hoc networks in Proc. ACM/IEEE Int. Conf. on Mobile Computing,Seattle, WA, USA, Sept. 1999, pp. 219-230.

[4] Y. Shang and M. Hadjitheodosiou, TCP splitting protocol for

broadband and aeronautical satellite network in Proc. 23rd IEEEDigital Avionics Syst. Conf., Salt Lake City, UT, Oct. 2004, vol. 2.

[5] J. Zhu, S. Roy, and J. H. Kim, Performance modeling of

TCP enhancements in terrestrial-satellite hybrid networks

IEEE/ACM Trans. Netw., vol. 14, no. 4, pp. 753-766, Aug. 2006.

[6] C.-H. Ng, J. Chow, and Lj. Trajkovic, Performance evaluation of

the TCP over WLAN 802.11 with the Snoop performance enhancing

proxy, OPNETWORK 2002, Washington, DC, Aug. 2002.

[7] W. G. Zeng, M. Zhan, Z. Li, and Lj. Trajkovic, Improving TCP

performance with periodic disconnections over wireless links,OPNETWORK 2003, Washington, DC, Aug. 2003.


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[8] W. G. Zeng and Lj. Trajkovic, TCP packet control for wireless

networks in Proc. IEEE Int. Conf. on Wireless and Mobile Computing,Networking and Communications (WiMob 2005), Montreal, Canada, Aug.2005, vol. 2, pp. 196-203.

[9] M. Omueti and Lj. Trajkovic, M-TCP+: using disconnection feedback

to improve performance of TCP in wired/wireless networks inProc. SPECTS 2007, San Diego, CA, USA, July 2007, pp. 443-450.

[10] Xu Chang-Biao, Long Ke-Ping, Yang Shi-Zhong. Corruption-based TCP

rate adjustment in wireless networks In: Chinese Journal of Com-puters, 2002, 25(4): pp.438-444.

[11] Scalable Network Technology, QualNet4.0 simulator tutorial and Qual-Net Forum, http://www.scalable-networks.com/forums/

[12] K.Fall, S.Floyd, Simulation Based Comparison of Tahoe, Reno and

SACK TCP, ACM SIGCOMM Computer Communication Review, Volume26 Issue 3, July 1996.

[13] S. Floyd, The NewReno Modification to TCP’s Fast Recovery

Algorithm, RFC 3782, April 2004.

[14] B. Qureshi, M. Othman, Member, IEEE, and N. A. W. Hamid, Progressin Various TCP Variants, February 2009.

[15] M. Mathis and J. Mahdavi, Forward acknowledgment: refining TCP

congestion control, in Proceedings of ACM SIGCOMM, pp. 181-191,1996.

[16] Lawrence S. Brakmo, Student Member, IEEE, and Larry L. Pe-terson, TCP Vegas: End to End Congestion Avoidance on a Global

Internet, OCTOBER 1995.

This article is an open access article distributed under the terms and con-ditions of the Creative Commons Attribution 3.0 Unported License (http://creativecommons.org/licenses/by/3.0/).

©2013 by the Authors. Licensed & Sponsored by HCTL Open, India.


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http://www.scalable-networks.com/forums/




Ultrasonic SensorsSupervision ofPetrochemical andNuclear PlantVimal Upadhyay, Krishna Kant Agrawal, Mukesh Chand andDevesh [email protected], [email protected], [email protected] [email protected]

Abstract

Piping in the oil and nuclear plants are subject to erosion orcorrosion inside pipe wall. This corrosion or erosion dependson chemical aggressively of fluids, operational conditions and

pipeline materials. In many cases inspection become tough whenpipes are mounted several meters above the ground for a humantesting personnel. Sometimes, inspection done during shut- downof plant or removal of surrounded armatures. For in service mainte-nance or inspection of these plants, there is always a desire for opti-mal solution. The NDT (Non Destructive Testing) developments formeasuring flow accelerated corrosion or thickness degradation. Ourfirst task is to deploy and connect ultrasonic sensor for measuringpipe wall thickness in such a design, their values can be evaluated ataccessible point.

Vimal Upadhyay et al.Ultrasonic Sensors Supervision of Petrochemical and Nuclear Plant.

Page 41



Keywords

Non Destructive Testing (NDT), Flow Accelerated Corrosion (FAC), UltrasonicTesting (UT), Pipe Inspection Gauge (PIG), Piezoelectric Transducer (PZT),Electromagnetic Acoustic Transducers (EMAT), Strong Static Magnetic Field(SSMF), Liquid Coupled Method (LCM), Wheel Coupled Method (WCM).

Introduction

In present scenario there is no single system which measures all pipelines. Inpresent era commonly used tool is PIG (pipe inspection gauge) that movesinside the pipe. Crawler move down to the pipeline independently and stop ifmajor defect assessment. The sensors are mounted on crawler; they are almostsmall in size, lightweight and required low power consumption. Therefore,the distance between measurement and evaluation can be bridge by cable (inorder of 100 meters). Pipe wall thickness degradation due to flow acceleratedcorrosion gave a birth to leaks and raptures in piping system which cannotbe identify at early stage. Ultrasonic examination methods are typically usedto monitor pipe conditions in terms of thickness, erosion and corrosion. Inthis paper we focus on design issues of ultrasonic system for rapid scanning ofsample model. Ultrasonic testing is completed with the help of ultrasonic waves(Primary wave) which uses 20 KHz to 200 KHz high frequency sound energy formaking accurate measurements of thickness, corrosion and erosion with the helpof sensors. Ultrasonic examinations can be conducted to known the propertiesof material including castings, forgings, geometry, welds, and composites. Wecollect a considerable amount of information related to turbine, boilers withthe help of instrument where human being approach is impossible. In thistechnique first we generate guided wave with the help of ultrasonic generatorsthan we collect information with the help of receiver (sensor). This gatheredinformation passed from Micro-channel plate detector for resolution and gettingmore accurate readings. Pipelines are worldwide used for distributing energyto end users. The pipeline deployment is well designed and required in servicemonitoring for natural degradation to overcome sudden failures. A mostlyfailure in pipeline occurs due to ageing factor of pipe system for examples leak,corrosion, erosion and raptures etc.


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Ultrasonic System for Pipe Wall Measurement

In 1980s high frequency sound waves are used for sample object inspection.The basic principle is shown in the figure 1. The working model of hand-held

Figure 1: Pulse echo Ultrasonic System for pipe wall measurement

ultrasonic gauge based on the principle of pulse echo method to determineaccurate pipe sample thickness and raptures. Pulses of ultrasonic energy arelaunched with the help of piezoelectric transducer, angle beam etc. Energy bandof ultrasonic testing varies 1-10 MHz. These energy pulses are reflected by insideand outside wall of the sample object. The thickness is measured by calculatingreflection time and speed of sound in steel pipe. For industrial perspectivethickness measurement accuracy required 0.001” (0.025 mm). Especially in caseof noisy areas we prefer high frequency transducers for more accurate results.To overcome pipeline surface roughness challenges we use lower frequencytransducers (5 MHz) for accurate results. The typical accuracy for in serviceinspection is 0.020” (0.5 mm). Ultrasonic tools require a large number of tinysensors, in the order of ten per inch diameter. Data processing and storagetime directly affect the speed of inspection. In early years (1989) inspectionspeed of ultrasonic system in the range of 3.0 mph. Now recent state of art inelectronics pushes up speed of inspection. Ultrasonic Testing gave an accuratereading in noise free pipes; lamination and inclusions on a pipe reduce accuracy.In ultrasonic testing misses to catch out defects lying behind laminations.Therefore applying ultrasonic gauge system we make a pipe free from debris ordeposits.


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Ultrasonic Crack Detection System

Most common methods which are used to determine cracks in pipeline:

1. Liquid Coupled Method.

2. Wheel Coupled Method.

3. Electromagnetic Acoustic Transducers.

These above methods are capable for crack detection but all have some limitations:-

In case of wheel coupled method numbers of sensors are limited to number ofwheels. The number of sensors in liquid coupled methods has many more incomparison to wheeled tool. Two common tools are:

1. Liquid Coupled Angle Beam Tool

2. Wheel Coupled Angle Beam Tool

Difficulties in angle beam tools are same as difficulties arise in wall thicknessmeasurement tool. For example:

1. Speed Restriction

2. To differentiate cracks from lamination and inclusion

After several attempts to above system EMAT (Electromagnetic AcousticTransducers) inspection system came in focus for determine cracks in pipewall thickness. EMAT ultrasonic testing technique operates at lower frequency(200-800 KHz) in comparison to PZT (1-20 MHz). The waves generated byEMAT are bounded by the geometry of sample object. The waves generallygenerated by EMAT are shown in figure 2. For generating above waves twothings are essential:

1. Strong Static Magnetic Field

2. Coil

Coils are used for creating localized eddy current in the sample object. Eddycurrent oscillates at the designed inspection frequency. Wave mode directlydepends on pipe wall thickness. If we make a small change in variable causea different wave mode, which affects result of inspected sample object. Thecoil near to sample object are generate sufficient amount of energy requiredto determine cracks even hidden by laminations. For long distance pipe wall


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Figure 2: Waves generated by EMAT

inspection, the coil is covered by thin polymers.

Advantages of EMAT in comparison to Liquid Coupled Method and WheelCoupled Method:

1. No need for liquid coupling media.

2. Bounded waves propagate in sample object.

Disadvantages of EMAT in comparison to Liquid Coupled Method and WheelCoupled Method:

1. Many modes.

2. Different results by different mode.

3. Implementation Challenges.

Simulation Models

Ultrasonic testing simulation models use numerous methods and physical equa-tions for predicting results of an experiment. The potential uses of simulationmodel classified into three categories as shown in Table ??. All above queriesexcept last three are cracked by UTSIM (Measurement model). Last threequeries are related to scan coverage modelling, scan coverage problems are sortout by a beam model.


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Table 1: Simulation Model Parameters

Ultrasonic reachthe region ofsample object?

Properties of thefield in region ofsample object?

Response fromthe incident fieldof sample object?

What is amplitude? Shape of beam? Time domain wave-form?

Beam passes throughconcave interface?

Phase curvature? Flow responsechange?

Beam spread when itpropagates into mate-rial?

Focal point? –X–

Beam bend? –X– –X–

Amplitude loses dueto coupling?

–X– –X–

–X– –X– –X–

Scan Optimization

Industrial objective towards scan optimization is to minimize in-service inspec-tion cost for accomplishing a specific task or optimum in service inspectionunder specified cost. Modelling objective towards scan optimization is to maxi-mum sensitivity for a given scan spacing. In scan optimization we focused onfollowing points:

1. Best location to place a probe.

2. Optimum wedge angle.

3. Optimum transducer coverage.

Scope of Modelling in Ultrasonic

Automated scans using longitudinal waves at normal incidence, automatedscans for deterministic and repeatable of accurate motion. Contact scans areexcluded due to variability in coupling. Two important spacing parametersindex and scan spacing are beneficial for chosen a coordinate system for exampleoptimum change in beam width along index direction. Qualities of coordination


Page 46



direction they are orthogonal by nature. Index coordinates direction used forradial cross section of the sample object. Scanning of sample object is modelledin lower dimension.

Figure 3: Scan Direction v/s Index Direction

Result and Conclusion

The above system reduce cost of non destructive testing and required timein petrochemical plant, also increase operating safety, minimized processingcost, reduce testing intervals and this system make easy continuous supervisionpossible. Advantages of above system in comparison to other models are: Noneed for liquid coupling media and Bounded waves propagate in sample object.Disadvantages of above system in comparison to other models are: Many modes,Different results by different mode, Implementation Challenges, etc.

Acknowledgement

We thank to our Honourable Director Sir (IIIT-Allahabad) for allowing us toperform this research work by providing excellent academic facility under hisprivileged guidance.

References

[1] Hideo Nishino, Simple method of generating for circumferential

shear horizontal waves in a pipe and their mode

identifications, Institute of Science and Technology, Japan 2006.


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[2] W. Harara, Pit-Depth Measurement on Large Diameter Pipes by

Tangential Radiography Using a Co-60 Gamma-Ray Source, RussianJournal of Non-destructive Testing, Vol. 40, No. 11, 2004.

[3] Calkins, F.T., Smith, R.D., and Flatau, A.B., An Energy-based

Hysteresis Model for Magnetostructive Transducers, IEEE Trans-actions on Magnetics, submitted 10/97.

[4] Dapino, M.J., Calkins, F.T., and Flatau, A.B., On Identification

and analysis of fundamental issues in Terfenol-D transducer

modeling, SPIE 1998, Proceedings on Smart Structures and IntegratedSystems, paper no. 23, Vol. 3329, 3/98.

[5] Glenn M. Light , Health Monitoring of Piping and Plate Using

the Magnetostrictive Sensor (MsS) Guided-Wave Technology,Southwest Research Institute San Antonio, TX 78228, 2010.

[6] K.Imano, Possibilities of non-destructive evaluation of a

pipe using air-coupled ultrasonic wave in the MHz range, IE-ICE 2008.

[7] http://www.ndt.org, Non Destructive Testing, 14 November 2009.

[8] J H BUNGEY, Non Destructive Testing in UK, Seiken Symposium2000.

[9] http://www.wikipedia.com, Non Destructive Testing.

[10] A P Ferrerira and P F Castro, NDT for assessing concrete strength,Seiken Symposium 2000.

[11] J F Hinslay, Text Book of Non destructive Testing.

[12] K Brandes, J Herther and R. Helmerich, Non-destructive testing

being essential part of the safety assessment of steel

bridges, Seiken Symposium 2000.

[13] N.Tamura and K.Takada, High Evaluation Inspection Vehicle,Seiken Symposium 2000.

[14] K R Maser and I sande, Application of Ground Penetration RADAR

technique for evaluation of Air field pavement, Seiken Sympo-sium 2000.


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[15] Y.H.Cha anb J H shu, Differential approach to Ultrasonic Testing

of Strength and Homogeneity of concrete, Seiken Symposium 2000.

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iic-hq.co.jp

[17] http://ndt-ed.org

This article is an open access article distributed under the terms and con-ditions of the Creative Commons Attribution 3.0 Unported License (http://creativecommons.org/licenses/by/3.0/).

c©2013 by the Authors. Licensed & Sponsored by HCTL Open, India.


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http://www.iic-hq.co.jp

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