Volume 2: Transceivers - Intel 2021. 1. 12.¢  Ch5 Ch4 Ch3 Ch2 Ch1 Ch0 Ch5 Ch4 Ch3 Ch2 Ch1 Ch0 Ch5 Ch4

  • View
    2

  • Download
    0

Embed Size (px)

Text of Volume 2: Transceivers - Intel 2021. 1. 12.¢  Ch5 Ch4 Ch3 Ch2 Ch1 Ch0 Ch5 Ch4 Ch3 Ch2 Ch1...

  • Volume 2: Transceivers

    Subscribe

    Send Feedback

    AV-5V3 2016.01.08

    101 Innovation Drive San Jose, CA 95134 www.altera.com

    https://www.altera.com/servlets/subscriptions/alert?id=AV-5V3 mailto:FPGAtechdocfeedback@intel.com?subject=Feedback%20on%20Arria%20V%20Device%20Handbook%20Volume%202:%20Transceivers%20(AV-5V3%202016.01.08)&body=We%20appreciate%20your%20feedback.%20In%20your%20comments,%20also%20specify%20the%20page%20number%20or%20paragraph.%20Thank%20you.

  • Contents

    Transceiver Architecture in Arria V Devices......................................................1-1 Architecture Overview................................................................................................................................ 1-2

    Transceiver Banks............................................................................................................................ 1-3 10-Gbps Support Capability in GT and ST Devices....................................................................1-8 Transceiver Channel Architecture................................................................................................. 1-8 PMA Architecture..........................................................................................................................1-10

    PCS Architecture........................................................................................................................................1-32 Transmitter PCS Datapath for Arria V GX, SX, GT, and ST Devices and Arria V GZ

    Standard PCS............................................................................................................................ 1-34 Receiver PCS Datapath for Arria V GX, SX, GT, and ST Devices and Arria V GZ

    Standard PCS............................................................................................................................ 1-39 10G PCS Architecture for Arria V GZ Devices......................................................................... 1-55 PCIe Gen3 PCS Architecture........................................................................................................1-62

    Channel Bonding....................................................................................................................................... 1-64 Bonded Channel Configurations................................................................................................. 1-64 Non-Bonded Channel Configurations........................................................................................1-64

    PLL Sharing.................................................................................................................................................1-65 Document Revision History.....................................................................................................................1-65

    Transceiver Clocking in Arria V Devices............................................................2-1 Input Reference Clocking............................................................................................................................2-1

    Reference Clock Network................................................................................................................2-5 Dual-Purpose RX/refclk Pin...........................................................................................................2-5 Fractional PLL (fPLL)......................................................................................................................2-6

    Internal Clocking......................................................................................................................................... 2-7 Transmitter Clock Network............................................................................................................ 2-8 Transmitter Clocking.....................................................................................................................2-18 Receiver Clocking.......................................................................................................................... 2-30

    FPGA Fabric–Transceiver Interface Clocking....................................................................................... 2-38 Transceiver Datapath Interface Clocking................................................................................... 2-40 Transmitter Datapath Interface Clocking...................................................................................2-40 Receiver Datapath Interface Clock.............................................................................................. 2-45 GXB 0 PPM Core Clock Assignment for GZ Devices.............................................................. 2-50

    Document Revision History.....................................................................................................................2-51

    Transceiver Reset Control in Arria V Devices....................................................3-1 PHY IP Embedded Reset Controller......................................................................................................... 3-2

    Embedded Reset Controller Signals.............................................................................................. 3-2 Resetting the Transceiver with the PHY IP Embedded Reset Controller During Device

    Power-Up..................................................................................................................................... 3-4

    TOC-2 Transceiver Architecture in Arria V Devices

    Altera Corporation

  • Resetting the Transceiver with the PHY IP Embedded Reset Controller During Device Operation.....................................................................................................................................3-5

    User-Coded Reset Controller..................................................................................................................... 3-6 User-Coded Reset Controller Signals............................................................................................3-7 Resetting the Transmitter with the User-Coded Reset Controller During Device Power-

    Up ................................................................................................................................................ 3-8 Resetting the Transmitter with the User-Coded Reset Controller During Device

    Operation.....................................................................................................................................3-9 Resetting the Receiver with the User-Coded Reset Controller During Device Power-Up

    Configuration............................................................................................................................3-10 Resetting the Receiver with the User-Coded Reset Controller During Device Operation..3-11

    Transceiver Reset Using Avalon Memory Map Registers.....................................................................3-12 Transceiver Reset Control Signals Using Avalon Memory Map Registers.............................3-12

    Clock Data Recovery in Manual Lock Mode......................................................................................... 3-13 Control Settings for CDR Manual Lock Mode.......................................................................... 3-14 Resetting the Transceiver in CDR Manual Lock Mode............................................................ 3-14

    Resetting the Transceiver During Dynamic Reconfiguration..............................................................3-15 Guidelines for Dynamic Reconfiguration if Transmitter Duty Cycle Distortion

    Calibration is Required During Device Operation..............................................................3-15 Transceiver Blocks Affected by the Reset and Powerdown Signals.....................................................3-16 Transceiver Power-Down..........................................................................................................................3-18 Document Revision History.....................................................................................................................3-18

    Transceiver Protocol Configurations in Arria V Devices.................................. 4-1 PCI Express................................................................................................................................................... 4-2

    PCIe Transceiver Datapath............................................................................................................. 4-4 PCIe Supported Features.................................................................................................................4-6 PIPE Transceiver Channel Placement Guidelines....................................................................... 4-9 PCIe Supported Configurations and Placement Guidelines.................................................... 4-12 PIPE Transceiver Clocking........................................................................................................... 4-15

    Gigabit Ethernet......................................................................................................................................... 4-18 Gigabit Ethernet Transceiver Datapath.......................................................................................4-21

    XAUI............................................................................................................................................................4-25 Transceiver Datapath in a XAUI Configuration........................................................................4-26 XAUI Supported F