Wafer Process - .:: Khoa Cong Nghe Thong Tin va Truyen Thong

©2007. Renesas Technology Corp., All rights reserved.

October, 2007

Wafer Process

Overseas Design Support CenterShigeru Shimada

For University VerFor University Ver11..11

©2007. Renesas Technology Corp., All rights reserved.2

Contents of Wafer Process

1.1.What is semiconductor?What is semiconductor?2.2. Why silicon is mot popular?Why silicon is mot popular?3.3. N type and P type SiliconN type and P type Silicon4.4. Why silicon wafer is round?Why silicon wafer is round?5.5. Crystal growth technologyCrystal growth technology6.6. What is MOS?What is MOS?7.7. Basic steps of LSI wafer processBasic steps of LSI wafer process


Contents of Wafer Process -continued

8. Explanation of component process8. Explanation of component process-- Oxidation, Plasma, CVD, Sputtering, LithographyOxidation, Plasma, CVD, Sputtering, Lithography(Stepper and Scanner), Device Isolation, (Stepper and Scanner), Device Isolation, Dry Etching, Plasma ashing, Ion Implantation, Dry Etching, Plasma ashing, Ion Implantation, Annealing, Ohmic contact, Barrier metal,Annealing, Ohmic contact, Barrier metal,and CMP)and CMP)

9. Modern CMOS Process 9. Modern CMOS Process 10. Reference10. Reference


What is a SemiconductorSemiconductor?

A semiconductor is a material that behaves inbetween a conductor and an insulator. At room temperature, it conducts electricity moreEasily than an insulator, but less readily than a conductor. At very low temperatures, pure or intrinsicsemiconductors behave like insulators. At highertemperatures though or under light, intrinsic semiconductors can become conductive. The addition of impurities to a pure semiconductorcan also increase its conductivity.


What is a SemiconductorSemiconductor?

glass germanium goldrubber silicon cupperceramic aluminum

10 ohm・cm810 ohm・cm

-4Resistivity

Insulator Semiconductor Conductor


Why Silicon is a most popular Semiconductor?Why Silicon is a most popular Semiconductor?Silicon exists everywhere.High quality Oxide can be made on Silicon.

Raw materialRaw material are silica stone and silica sand made from SiO2. It needs the electric power to make metal Silicon, so the countries where the electric power cost is low are the producing countries.They used to be China, Brazil, Russia, South Africa and Norway, and very recently, Australia,Malaysia and Viet Nam are coming up.

Raw material Metal Silicon Poly Crystal siliconSingle Crystal Silicon(Eleven Nine:99.999999999%)

Crystal pulling method : Czochralski (CZ) method,Floating Zone method


Crystal structure of Silicon

Silicon belongs to the cubic crystal system and has a diamond structure.

This is characterized by having each atom symmetrically surrounded by four equally spaced neighbors.


Crystal planes

(100) plane(100) plane (110) plane(110) plane (111) plane(111) plane


Periodic Table

5 B

6 C

7 N

13 Al

14 Si

15 P

31 Ga

32 Ge

33 As

Group IIIGroup III IVIV VV

+-

---

--

--

---

-

--


N type and P type Silicon

Silicon crystal is rarely used in the pure state.Usually, some impurity called a dopant is added insmall controlled amount.If a boron atom is substituted for a silicon atom in thesilicon lattice, the boron atom with only three ofavailable electrons would be able to form bonds toonly three of the four adjacent silicon atom and a hole would be formed.


N type and P type Silicon - Continued

-

Si14+-

- -

Si14+--

-

Si14+--

--

-

Si14+-

- -

-

-

Si14+-

- -

-

Si14+-

-

Si14+--

-

Si14+--

-

-

B5+

-

-

-

-- -

Si14+-

- -

Si14+--

-

Si14+--

--

-

Si14+-

- -

-

-

Si14+-

- -

-

Si14+-

-

Si14+--

-

Si14+--

-

-

-

-

-

-- -

Si14+ -+-

---

--

--

---

-

--


It is very easy for an electron from a nearby siliconto silicon bond to fall intothis hole and effectively move the hole away from the boron atom.Since the boron atom will accept an electron, boron and the other elements ofGroup III(B, In, Ga) are refered to as acceptors.Silicon with acceptor is called as P type silicon, since “Positive” holes aregenerated and contribute a current flow.


If a Group V atom, such as phosphorus, is introducedinto the silicon lattice, it will have an extra electronwhich may easily break away, becoming a conductionelectron.The phosphorus is refered to a donor, since it donatesan electron to the conduction band. Other donors areAs and Sb.Silicon with donor is called as N type silicon, since“Negative” electrons are generated and contributethe current flow.

Si14+-

- -

Si14+--

-

Si14+--

--

-

Si14+-

- -

-

-

Si14+-

- -

-

Si14+-

-

Si14+--

-

Si14+--

-

-

-

-

-

-- -

-P15+

-


Properties of Silicon and Silicon Oxide


Why Silicon wafer is round?

Single-crystal Silicon Silicon / wafer


Crystal Growth TechnologyCrystal Growth Technology

FZFZmethodmethod

Polycrystalrod

Heat Coil Seed crystal

Melting

Seeding

Single-crystalsilicon

CZCZmethodmethod

Heater

FZ method

CZ methodSeed crystal

Silicon melt

Quartz Crucible SeedingSingle-crystal silicon

Reference : Seibundo Shinkosha Inc. Guide with semiconductor pictures (1995)

1420 1420 ℃℃


What is MOS?

M(Metal)-O(Oxide)-S(Semiconductor)

MetalOxide

Semiconductor

MOS Structure


Basic structure of MOS TransistorElectrode: Highly doped Poly-SiliconSource and Drain: Highly doped N+ DiffusionGate Oxide: Silicon Oxide

Electrode

p-Type Substrate

Gate Oxide

GateDrainSource

Substrate

N+

N channel MOS Transistor

Circuit symbol

N+


Basic Steps of LSI wafer processA) Thin Film formation:

Oxidation: Thermal OxidationCVD(Chemical Vapor Deposition): Deposition of Poly-Silicon, Silicon Nitride, Silicon Oxide

Evaporation, Sputtering: Aluminum, Metal, Silicide (Alloy of Silicon and other metal)Plating: Cu

B) PatterningPhotolithography: Forming photo-resist patterns using Ultra-Violet beamEtching: Wet or Dry etching using Photo-resist as a masking material


Basic Steps of LSI wafer process - ContinuedC) Introduction of impurity

Diffusion:Diffusion of Solid or vapor phaseIon Implantation:Ionized impurity bombardment using electric field

D) Cleaning: Wafer cleaning using acid or ultra pure water

These four steps are repeated during wafer process.


Principle of Oxidation

1. Dry OxidationOxidation in Dry OxygenUsed to form the thin oxideSi+O2 (Gas) SiO2

2. Wet OxidationOxidation in steamUsed to form the thick oxideSi+2H2 O(Gas) SiO2+2H2(Gas)

Since the diffusion coefficient of Since the diffusion coefficient of H2 O is larger thanis larger thanO2 , the wet oxidation can form thicker oxide in, the wet oxidation can form thicker oxide inshorter time.shorter time.


Plasma

A A plasmaplasma is typically an is typically an ionized gasionized gas, and is usually , and is usually considered to be a distinct phase of matter in considered to be a distinct phase of matter in contrast to solids, liquids, and gases because of its contrast to solids, liquids, and gases because of its unique properties. unique properties. ““Ionized" means that at least one electron has been Ionized" means that at least one electron has been dissociated from a proportion of the atoms or dissociated from a proportion of the atoms or molecules. molecules. The free electron charges make the plasma The free electron charges make the plasma electrically conductive so that it responds strongly electrically conductive so that it responds strongly to electromagnetic fields. to electromagnetic fields.


Typical PECVD (Plasma Enhanced CVD) equipment configuration

RFRF--power inputpower input

PlasmaPlasma

Gas InletGas Inlet

Gas OutletGas Outlet

GroundGround

ElectrodeElectrode

Silicon waferSilicon waferHeaterHeater


Principle of CVDThe material gas is transferred to wafer surfacewhere the reaction occurs and the reaction productdeposits on wafer.

Energy(heat, plasma, light, etc)

Material gas Silicon wafer thin film and byproduct

Thermal decomposition:SiH4 →

Si ＋2H2

Oxidation:SiH4 ＋

2O2 →

SiO2 ＋

2H2O

Reaction:3SiH4 ＋

4NH3 →

Si3N4 ＋

12H2


Sputtering

Sputtering is a physical process whereby atoms Sputtering is a physical process whereby atoms in a solid target material are ejected into the gas in a solid target material are ejected into the gas phase due to bombardment of the material by phase due to bombardment of the material by energetic ions. It is commonly used for thinenergetic ions. It is commonly used for thin--film film deposition.deposition.


Sputtering - Continued

MatchingMatchingNetworkNetwork


Argon PlasmaArgon Plasma

Sputtering Gas Inlet (Sputtering Gas Inlet (ArAr))

VacuumVacuum

GroundGround

ElectrodeElectrode

Silicon waferSilicon wafer

TargetTargetRFRFGeneratorGenerator


What is Lithography Technology?This is a technology where semiconductor circuit patterns formed on photo-mask(mask) are repeatedly built on a wafer with high accuracy.

Film Forming

Resist coating

Expose

Develop

Etching or ion implantation

Resist removal

Next process

Wafer process flow chart

Si wafer

Film forming process

Resist Coating Expose mask pattern

Resist pattern formation

Etching Resist removal

(Developing)

Photo-mask

CMP (Planarization)

FilmFilm


PhotoresistThere are two types of photoresist, one is “positive (posi)” resist and the other is “negative (nega)” resist. When posi resist is exposed and developed, the resist of exposed portion is dissolved and when nega resist is exposed and developed, the exposed portion remains.We use posi resist for fine patterning.


Photoresist coating

Spin CoaterSpin Coater

Photoresist is dropped on Photoresist is dropped on a wafer, then the wafer is a wafer, then the wafer is spun to spread the resist.spun to spread the resist.Photoresist is sensitive to Photoresist is sensitive to a short wave length.a short wave length.So a light of longer wave So a light of longer wave length is used in the clean length is used in the clean room.room.


Photolithography Machine Formation

For example refer to Cannon

KrF

sstepper FPA-3000EX6 illumination system

Wafer

Light source

Illumination system

Reticule (mask)

Reduction projectionlens

<Parameter related to exposure>Light source : Exposure wavelengthIllumination : σ, Variable illuminationMask : Phase shift mask,

magnificationReduction projection lens: NA, aberrationWafer stage: X,Y, Z position, Positioning

accuracy

Manufacturers• Nikon • Cannon • ASML

1st Zoom condenser

2nd Input lens

Relay optics

1st Zoom condenser

Masking blade

High eyes lens

1st input lens

ND filter

Image shift

Wafer stage

Condenser lens

Beam monitor

ReticuleStopper

Collimator lens

Excimer laser

Projection lens

Laser overdraw


Types of Photolithography Machines - Stepper and Scanner

Stepper The target area for exposure (shot) is illuminated thoroughly and exposed entirely.

Mask

Wafer

The area exposed to light

Scanner The target area for exposure (shot) is illuminated partially in the form of a slit, and exposed by synchronously scanning the reticule and the wafer stage.


Schematic diagram of an RF-powered plasma etch system

MatchingMatchingNetworkNetwork


RFRFGeneratorGenerator

PlasmaPlasma

Gas InletGas Inlet Gas OutletGas OutletGroundGround

ElectrodeElectrode

PlasmaPlasmasheathssheaths

Silicon waferSilicon wafer


Dry Etching

Figure 1 ::Example of etching flow

Table 1 Main processed film

Film to be etched Photoresist

Deposition Photo-lithography

Removal of photoresist

Etching

Insulation film SiO2, Si3N4, Low-k materialWiring material AlCu, W, WSi2, CoSi, TiN, Poly-Si, Pt, Ru

High dielectric material Ta2O5, BSTAntireflection film Organic ARC, Inorganic ARC (p-SiON, etc.)

ARC:AntiARC:Anti--Reflection Reflection CoatingCoating

BST:(Ba,Sr)TiOBST:(Ba,Sr)TiO 33


Dry Etching - Continued

P.R

Poly-Si

Anisotropic etching

SiO2

P.R

Isotropic etching

SiO 2

Figure 2Cross-section of etching

LResist

SiO2

LEtch

CD shift: LResist - LEtch

Poly-Si Poly-Si Poly-Si


Reaction during Dry Etching

Generation of etching seeds

Absorption of etching

seedsDissociation

of etchingseeds

Detachment of adsorbent

carbon

Plasma

Formation of reaction products

Detachment of reaction products


Plasma ashing

In semiconductor manufacturing In semiconductor manufacturing plasma ashingplasma ashing is is the process of removing the photothe process of removing the photo--resist from resist from an etched wafer. an etched wafer. Using a plasma source, a monatomic reactive Using a plasma source, a monatomic reactive species is generated. species is generated. Oxygen or fluorine are the most common reactive Oxygen or fluorine are the most common reactive species. species. The reactive species combines with the photoThe reactive species combines with the photo--resist resist to form ash which is removed with a vacuum pump.to form ash which is removed with a vacuum pump.Typically, monatomic (single atom) oxygen plasma Typically, monatomic (single atom) oxygen plasma is created by exposing is created by exposing oxygen gas (O2) to ionizing radiation. oxygen gas (O2) to ionizing radiation. At the same time, many free radicalsAt the same time, many free radicalsare formed which could damage the wafer. are formed which could damage the wafer.


Plasma ashing - Continued

Newer, smaller circuitry is increasingly susceptible Newer, smaller circuitry is increasingly susceptible to these particles. to these particles. Originally, plasma was generated in the process Originally, plasma was generated in the process chamber, but as the need to get rid of free radicals chamber, but as the need to get rid of free radicals has increased, many machines now use has increased, many machines now use a downstream Plasma configuration, where plasma a downstream Plasma configuration, where plasma is formed remotely and channeled to the wafer. is formed remotely and channeled to the wafer. This allows electrically charged particles time to This allows electrically charged particles time to recombine before they reach the wafer surface, recombine before they reach the wafer surface, and prevents damage to the wafer surface.and prevents damage to the wafer surface.


Ion ImplantationIon implantation is used to alter the surface properties of semiconductor materials.By doping the desired elements on the semiconductor substrate, or in the thin film on the substrate, PN junction is formed or surface properties are controlledby thermal treatment, recovery of dislocated crystal or implanted impurity atoms are substituted at the lattice point and activated electrically (referred to as Anneal).(Usage)•

Well formation

• Isolation between devices

• Source drain formationetc.

(Requirement from device)•

Shallow junction formation


Features of Ion ImplantationCan highly control the concentration and implantation depth. Photo-resist can be used as a mask for a selective implantation. (Room temperature process)Can dope at low concentration.

Conventional impurity doping technology such as thermal diffusion has replaced the thermal diffusion with ion implantation.


Implantation for Vth control

If the acceptor ion is implanted to NMOS, then Vth of NMOS is increased.If the donor ion is implanted to NMOS, Vth of NMOS is lowered.Vice verse to PMOS.

Delta Vth = Qimp/CoxWhere Qimp=q*N, N=Dosage of implantation and Cox is GateCapacitance. q=1.60217733×10-19 (C).Cox=ε0 *εr /Tox(ε0 =8.85E-12F/m, εr =3.9)


Purpose of Annealing

Annealing is done for the purpose of

1. Damage relaxation from the bombardment of impurity

2. Activation of doped impurity3. Diffusion of doped impurity


Model of defect recovery and ion activation by annealing

Si atomDopant ion

DescriptionAlignment model of Si atomProcess flow

Before implantation

After implantation

After annealing

Ion beam

Si atoms are aligned & bonded. However, only Si atoms may allow a small current to pass.

Due to ion Implantation, dopant and Si atoms collide, alignment is disturbed (defect occurred), and the covalent bonds break.

In this case, implanted ions are not bonded to Si atoms, but is in between Si atoms. (Interstitial atom)

In this condition, a current does not flow even though dopant ion exists. (Inactive condition)

By annealing, the alignment of Si atoms is recovered, and ions also get bond to Si. Therefore a current can flow. (Ion activation)


Ohmic contact and barrier metal

Ohmic Contact

An ohmic contact refers to the contact between a metal and a semiconductor to allow carriers toflow in and out of the semiconductor. An ideal ohmic contact must have no effect on device performance, i.e., it must be capable of delivering the required current with no voltage drop between the semiconductor and the metal.

In real life, therefore, an ohmic contact must have a contact resistance that is as small as possible, to make it negligible in comparison to the bulk or spreading resistance of the semiconductor.


Materials which form ohmic contact to Silicon

Semiconductor

1.12 n,p CoSi2 Direct Reaction* 9001.12 n,p TiSi2 Direct Reaction* 9001.12 n,p W Si2 Direct Reaction* 10001.12 n,p TaSi2 Direct Reaction* 10001.12 n,p PtSi Direct Reaction* 600-7001.12 n,p Al Evaporation -1.12 n (1% Sb) Evaporation -

AlloyTemp.

Si

BandgapEnergy Type

ContactMaterial Technique(s)


Barrier MetalA barrier metal is a material used in integrated circuits to chemically isolate semiconductorsfrom soft metal interconnects, while maintaining an electrical connection between them. For instance, a layer of barrier metal must surround every copper interconnection in modern copper-based chips, to prevent diffusion of copper into surrounding materials. As the name implies, a barrier metal must have high electrical conductivity in order to maintain a good electronic contact, while maintaining a low enough copper diffusivity to chemically isolatethe copper conductor from the silicon below.


CMP - Chemical-Mechanical Polishing

SlurrySlurry

Polishing TablePolishing Table

Polishing PadPolishing Pad

Wafer (facing down)Wafer (facing down)

Wafer carrierWafer carrier

SiliconSiliconOxideOxide

Polishing padPolishing padSlurrySlurry

CloseClose--up of wafer/pad interfaceup of wafer/pad interface


Modern CMOS TechnologyFollowings are the typical CMOS wafer process.


Device Isolation - Comparison of LOCOS and STIComparison of below figures illustrates both similarities and the differences in LOCOS (Local Oxidation of Silicon) and STI (Shallow Trench Isolation). Both process produce thick SiO2 regions laterally isolating adjacent device structure. However, STI produces more compact structures because there is very little lateral encroachment of the isolation structure into adjacent active regions. STI is used below 0.35um process.

LOCOSLOCOS

STISTI

Thermally oxidized SiO2Thermally oxidized SiO2

CVD deposited SiO2CVD deposited SiO2


Active Region Formation

Active Region means the region where Active Region means the region where aactive devices such as NMOS and PMOS ctive devices such as NMOS and PMOS transistors are formed.transistors are formed.

Following slides show the wafer process Following slides show the wafer process using LOCOS device isolation.using LOCOS device isolation.STI process is explained as an option process.STI process is explained as an option process.


Following initial cleaning, an SiO2 layer is thermally grown on the silicon substrate. A Si3N4 layer then deposited by LPCVD. Photoresist is spun on the wafer to prepare for the first masking operation.

PhotoresistPhotoresist

Si, (100), P Type, 5~50 ohmSi, (100), P Type, 5~50 ohm--cmcm

Si3N4 (80nm)Si3N4 (80nm)SiO2 (40nm)SiO2 (40nm)

LPCVD: Low Pressure CVDLPCVD: Low Pressure CVD


Mask 1 patterns the photoresist.

PhotoPhoto--mask(Reticule)mask(Reticule)

Photoresist (Photoresist (PosiPosi type)type)

Si, (100), P Type, 5~50 ohmSi, (100), P Type, 5~50 ohm--cmcm

Si3N4 (80nm)Si3N4 (80nm)SiO2 (40nm)SiO2 (40nm)


The Si3N4 layer is removed where it is not protected by the photoresist by dry etching.


After photoresist stripping, the field oxide is grown in an oxidizing ambient (1000 C 90 min. in H2O). The thickness is about 0.5um. The oxidation extends under the nitride edge because the oxidant (H2O) can diffuses sideways.

Field region: Isolation regions between Active regions.Field region: Isolation regions between Active regions.


Process option for Device Isolation - Shallow Trench Isolation -


After Mask 1 defines the photoresist, the Si3N4, SiO2 and Si trenches are successively plasma etched to create the shallow trenches for isolation.


A thin “liner” oxide is thermally grown in the trenches. The nitride prevents any additional oxidation on the top surface of the wafer.


SiO2 is deposited to completely fill the trenches. This would typically requires 0.5 -1 um of SiO2 to be deposited, depending on the trench depth and geometry.


The deposited SiO2 layer is polished back using CMP to produce a planar structure.


N and P WELL Formation


Photoresist is used to mask the regions where PMOS devices will be built using Mask 2. A boron boron implant provides the doping for the P wells for the NMOS devices.

BoronBoron

P Type ImplantP Type Implant


Photoresist is used to mask the regions where NMOS devices will be built using Mask 3. A phosphorus phosphorus implant provides the doping for the N wells for the PMOS devices.

PhosphorusPhosphorus

P Type ImplantP Type ImplantN Type ImplantN Type Implant


A high temperature drive-in (1000~1100 C and 4 to 6 hours) completes the formation of the N and P wells. Well depth will be 2 to 3 um after the wafer process finishes.

N WellN Well P WellP Well


Gate FormationBefore forming Gate oxide, channel implant Before forming Gate oxide, channel implant ( Vth controlled implant) is done.( Vth controlled implant) is done.Vth is given by the following equation where QVth is given by the following equation where QII isisimplant dose.implant dose.

This equation assumes that the entire implant dose This equation assumes that the entire implant dose is located in the near surface region, is located in the near surface region, inside the MOS channel depletion region.inside the MOS channel depletion region.


After spinning photoresist on the wafer, Mask 4 is used to define the NMOS transistors. A boron implant adjusts the N-channel Vth.


BoronBoron

PP


After spinning photoresist on the wafer, Mask 5 is used to define the PMOS transistors. A arsenic implant adjusts the P-channel Vth.


ArsenicArsenic

PPNN


After etching back the thin oxide to bare silicon, the gate oxide (~10nm) is grown for the MOS transistors.

N WellN Well P WellP WellPPNN


A layer of polysilicon (0.3~0.5um) is deposited. Ion implantation of phosphorus follows the deposition to heavily dope the poly. This can produce low-sheet-resistance poly layers.



Photoresist is applied and Mask 6 is used to define the regions where MOS gates are located. The polysilicon layer is then etched using plasma etching.



LDD (Lightly Doped Drain) FormationDecreasing the channel length in the device Decreasing the channel length in the device to 0.5um without reducing the supply voltage to 0.5um without reducing the supply voltage increases the average field to about 10 increases the average field to about 10 VcmVcm ..This high field is large enough to cause This high field is large enough to cause a problems in semiconductor devices.a problems in semiconductor devices.Such problems are often called Such problems are often called ““hot electronhot electron””problems.problems.Carriers at high energies can cause impact Carriers at high energies can cause impact ionization which creates additional holeionization which creates additional hole--electron pairs.electron pairs.LDD structure is applied to relax the field.LDD structure is applied to relax the field.

55 -- 11


Mask 7 is used to cover the PMOS devices. A phosphorus implant is used to form the LDD (extension) region in the NMOS devices.


PhosphorusPhosphorus

NN-- ImplantImplant


Mask 8 is used to cover the NMOS devices. A boron implant is used to form the LDD (extension) region in the PMOS devices.


BoronBoron

NN-- ImplantImplantPP-- ImplantImplant


A conformal layer of SiO2 is deposited on the wafer in preparation for side-wall spacer formation.




Etch-back process

After oxide is deposited, and without any mask, oxide is etched using anisotropic dry etching. Oxide at the steps remains un-etched.

Oxide depositionOxide deposition

Anisotropic dry etching

Deposition is Deposition is isotropic.isotropic.


The deposited SiO2 layer is etched back anisotropically, leaving sidewall spacers along the edges of the polysilicon.




Source/Drain Formation


After growing a thin “screen” oxide, photoresist is applied and Mask 9 is used to protect the PMOS transistors. An arsenic implant then forms the NMOS source and drain regions.

N WellN Well P WellP WellN+ ImplantN+ ImplantPP-- ImplantImplant

ArsenicArsenic

PPNN


After applying photoresist, Mask 10 is used to protect the NMOS transistors. A boron implant then forms the PMOS source and drain regions.

N WellN Well P WellP WellN+ ImplantN+ ImplantP+ ImplantP+ Implant

BoronBoron

NN PP


A final high-temperature drive-in (900 C, 30 min. or 1000-1050 c, 1min.) activates all the implanted dopants and diffuses junction to their final depth.

N WellN Well P WellP WellNN PP

P+P+ N+N+N+N+P+P+


Contact and Local Interconnection Formation


Un masked oxide etch removes the SiO2 from the device source drain regions and from the top surface of the polysilicon.


P+P+P+P+ N+N+N+N+


Titanium is deposited on the wafer surface by sputtering.


P+P+P+P+ N+N+N+N+


The titanium is reacted in an N2 ambient, forming TiSi2 where it contacts silicon or polysilicon and TiN elsewhere.


P+P+P+P+ N+N+N+N+

TSi2TSi2 TiNTiN


Photoresist is applied and Mask 11 is used to define the regions where TiN local interconnects will be used. The TiN is then etched.


P+P+P+P+ N+N+N+N+


After stripping the photoresist, a conformal SiO2 layer is deposited by LPCVD.


P+P+P+P+ N+N+N+N+


CMP (Chemical-Mechanical Polishing) is used to polish the deposited SiO2 layer. This planarizes the wafer surface.


P+P+P+P+ N+N+N+N+


Photoresist is spun onto the wafer. Mask 12 is used to define the contact holes. The deposited SiO2 layer is then etched to allow connections to the silicon, polysilicon and local interconnect regions.


P+P+P+P+ N+N+N+N+


A thin TiN barrier/adhesion layer is deposited on the wafer by sputtering, followed by deposition of a W layer by CVD.


P+P+P+P+ N+N+N+N+

TiN barrier/adhesion layerWW


CMP is used to polish back the W and TiN layers, leaving a planar surface on which the first level of metal can be deposited.


P+P+P+P+ N+N+N+N+


Aluminum is deposited on the wafer by sputtering. Photoresist is spun on the wafer and Mask 13 is used to define the first level of metal. The Al is then plasma etched.


P+P+P+P+ N+N+N+N+

AluminumAluminum


The steps to form the second level of Al interconnect follow those in previous slides from P.84-89. Mask14 is used to define via holes between metal1 and metal2. Mask15 is used to define metal2.


P+P+P+P+ N+N+N+N+


The last step in the process is deposition of a final passivation layer, usually Si3N4 deposited by PECVD. The last Mask16 is used to open holes in this layer over the bonding pads (not shown).


P+P+P+P+ N+N+N+N+


The advantage of Cu wiring

The advantages of Cu wiring over Aluminum are as follows.

1.Lower resistivity than Aluminum.(Al:2.8u ohm cm, Cu:1.7u ohm cm)Can be thinner than Al with the same resistance, which reduces capacitance.

2.Higher melting point and less electro-migration.3.Less stress-migration.


The advantage of Cu wiring - Continued

The disadvantages1.Cu is one of the harmful elements to Si and SiO2.2.Cannot be deposited by CVD.3.Cannot be dry-etched.4.Weak cohesion to SiO25. TDDB lifetime is shorter than Al and W.

(TDDB:Time Dependence on Dielectric Breakdown )

Damascene process is the best one for Cu.


Metal1 formation - Damascene process


P+P+P+P+ N+N+N+N+

Interlayer dielectric (IDL), insulator between Interlayer dielectric (IDL), insulator between metal is deposited. IDL is polished.metal is deposited. IDL is polished.MetalMetal--1 Photo is done and IDL is etched.1 Photo is done and IDL is etched.Barrier metal (not shown) are deposited.Barrier metal (not shown) are deposited.



P+P+P+P+ N+N+N+N+

Cu seed is sputtered, then plated to fill the recess.Cu is polished back using CMP.

Metal 1Metal 1


Metal2 formation - Dual Damascene process


P+P+P+P+ N+N+N+N+

Insulator, Etching stopper and insulator between Metal1 and Metal2 are deposited. Via1 is opened.



P+P+P+P+ N+N+N+N+

Metal2 photo is done and insulator is etched.



P+P+P+P+ N+N+N+N+

Barrier metal is deposited (not drawn).Cu (seed) is sputtered and plated to fill the recess.Cu is polished back by using CMP.Via and Metal recess formation is called Dual damascene process.


Comparison of wiring structure

N WellN Well P WellP WellNN PPP+P+P+P+ N+N+N+N+

N WellN Well P WellP WellNN PPP+P+P+P+ N+N+N+N+


Complete Cross Section



P+P+P+P+ N+N+N+N+

GateGateGateGate

DrainDrainDrainDrain SourceSource SourceSource

Sub (N WELL)Sub (N WELL) Sub (P WELL)Sub (P WELL)DDGGSSDDGGSS

NN--MOSMOSPP--MOSMOS


Reference

SILICON VLSI TECHNOLOGYSILICON VLSI TECHNOLOGY--Fundamentals, Practice and ModelingFundamentals, Practice and ModelingBy J.D. Plummer, M.D. Deal and P.B. GriffinBy J.D. Plummer, M.D. Deal and P.B. GriffinPrentice Hall, 2000Prentice Hall, 2000

©2006. Renesas Technology Corp., All rights reserved.

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Wafer Process - .:: Khoa Cong Nghe Thong Tin va Truyen Thong