Web Notes 365 11F

ECET 365, Digital Logic and Circuit Design

Course Notes,

VHDL Design Projects,

and Examples

Spring, 2011

©William E. Barnes, P.E.

office: GITC 2101 phone: 973-596-8190 email:

b a r n es W @ nj it. ed u

mailto:[email protected]

ECET 365 Notes W. Barnes

Three Questions

Dear Students,

Below are three questions to ask yourself at the beginning and during this course. The first question is very specific to the digital design course and the other two apply not just to this course but to any other courses you might take as well.

1. How do hardware, software, and mathematics all synergistically conjoin in this subject?

2. How can I help my classmates, and thus myself, to learn in this course?

3. Why do I want to, and how can I, become a more active learner?

Brief Table of Contents for these Notes

Please bring the notes to every class since we will be using them

extensively. The next two pages are the detailed Table of Contents in

which you will seethe notes are divided into sections:

• General Course Information, pages 2 – 8

• Part I, Combinational Logic, pages 9 – 46

• Part II, Sequential Logic, pages 47 -76

• Appendix A, Software assignment and Software Projects, pages 78

-87

• Appendix B, VHDL Examples, pages 88 – 98• Appendix C, Forms (you will need and will receive an electronic

version of these), pages 99 - 101

Page 2

PageThree Questions and Contents of Notes 2

Intro, Course Purpose, Objectives, 5Grading, Homework, Projects 6

Tests and Exams, Missed Tests 6Partnerships 6

Professional Meeting, Technical Article 7Installing the Software 7

Software Hints 8


T a b l e o f C o ntents

(brief Table of Contents on previous page)

Part I, Combinational LogicThe Gates 9

Example Using Alternate Gate Symbols 10Boolean Algebra Theorems 11

Boolean Exercises & Intro. to NAND and NOR Logic 12A Formal Method for Using a Karnaugh Map 14

Example of Karnaugh Map Definitions 15In class review for Karnaugh Mapping 16Using Zeros in the K-map to form POS 17

Variable Entered Maps 18Major CAD Tools and Tasks 20

So m e P ractica l C on si d erati on s : A) Implementation StrategiesB) Physical Characteristics of Logic FamiliesC) Data SheetsD) Different Implementations of an XOR

21-26

Introduction to Decoders and Multiplexers 27Mux’d 4 digit display using a decoder 28Expanding Decoders and Multiplexers 29

Combinational Logic from Decoders and Mulitplexers 30& Major Review Example

PROMS, Decoders, Multiplexers 31TDM Example 32

Number systems 34-38Arithmetic Circuits Summary 39

Adder/Subtractor Logic 40Comparator 41

Memory System Design 42Decoder Take Home Assignment/Quiz 43

Hazards and Glitches 44ASICs 45SPLDs 46

Part II, Sequential LogicIntroduction to Sequential Logic 47

Introduction to Latches and Flip-Flops 48-50Master-Slave & Edge Triggered Flip Flops 51

Setup and Hold Times 52Forming One Flip-Flop From Another 53 - 54

Page 3

Index 88Simple VHDL Example 89

Selected Signal Assignment to Generate Combinational Logic 90Comparator 91

Combinational Logic in vhdl Using Internal Signal andConcatenation

92

Process and Case Statement for Combinational Logic 93Components, Instantiation, and Structure 94

Up counter 95Up/Down counter 96

Moore FSM 97Mealy FSM 98

Index 99Professional Society Meeting Report Form 100

Technical Journal Article Report Form 101


Tabl e of Conte nt s c onti nue d

Introduction to State Diagrams 55Flip-flop Characteristic Equations 56

Analysis Procedure for Sequential Logic 57Sequential Analysis Example 58

Introduction to Registers and Counters 59Asynchronous and Synchronous Counters 60 - 61

Using Universal Binary Counters 62 - 63• Counter Design: 64-70

Basic Procedure 64Flip-flop Excitation Tables 65

Down counter w/’T’ 66Non-binary sequence w/’D’ 67

Non-binary sequence w/’JK’ 68In-class Design Assignment 69Counter w/repeated outputs 70

Finite State Machine Design Procedure 71State Reduction 72-74

State Assignment Guidelines 75FSM Design Examples # 1 & 2 76-77

Appendix A, Software Assignment and ProjectsIndex 78

First Software Assignment 79Project Report Requirements 80

Project 1 81Typical Project Grading & Table of Contents 82

Projects 2 - 4 83 - 87

Page 4

Appendix B, vhdl Examples

Appendix C, Forms


IntroductionThe following pages contain most of the notes for the combinational logic part of the class and some introductory material for the sequential logic. Many of the pages are intentionally not complete so that they can be developed in class. Scan through and keep this packet and bring to each class. It is the responsibility of each student to attend class and keep up with the reading and homework. In class you will get the perspective of the instructor but, as juniors and seniors in a BSET program, you should also be studying the text as well as supplemental material such as industrial magazines like EDN, which frequently has excellent tutorials on the latest digital technology.

The text by Brown and Vranesic is excellent. Pay particular attention to Introduction, Concluding Remarks and Solved Problems for each chapter. Also, the references in each chapter are very good. Also, The software used (included with the text) is also excellent but, as with any powerful softwarepackage, it requires some diligence to learn. Each group of two students must submit their own solutions to the projects; i.e., one report per group. Also, students should start using the software immediately by trying the examples in the text.

Co u r se P u r p os e : To expand on the first course in digital electronics, taught at the Associate level, into the areas of design using common techniques plus the use of VHDL and other CAD tools. Students will become knowledgeable in the areas of digital simulation, sequential logic, and finite state machines as well as strengthening their knowledge of traditional digital logic.

Cou rse Ob jecti ves

By the end of the course you should be able to do the following:

1. Combinational Logic. Analyze and design basic combinational logic systems. Develop, simplify and implement (with various types of gates) sum of products (SOP) and product of sums (POS) expressions. Analyze and design decoder logic including memory systems for microcomputers. Analyze and design logic using multiplexers including their use in time division multiplexing systems. Distinguish between the various programmable logic devices and draw logic using the short hand logic commonly used in PLDs.

2. Sequential Logic. Analyze and design basic sequential logic systems. Analyze various circuits, including determination of waveforms and state diagrams, with SR, D, JK and T flip-flops. Design and analyze various counters made up of the four types or flip-flops or using universal counters. Design state machines in an efficient manner.

3. Software. Simulate and trouble shoot simulations of the types of logic studied in the course. Use the VHDL language to design, simulate and troubleshoot both combinational and sequential logic using the CAD software. Present the results in a well-documented report with all logic andtiming diagrams computer generated.

4. Professionalism, Professional Societies and Lifelong Learning. Appreciate the value of professionalism in your class work, projects and career as well as the usefulness of, and role of professional societies in, lifelong learning.

Page 5

Homework 10 % Tests 25 %Projects 30 % Final Exam 25 %

Professional Society Meeting attendance 5 % Technical Journal Report 5 %


Gr adi ng:

Note: regardless of other grades, to pass the course, a student must have a passing test average.

H o m e w o r k : In regard to doing the homework, please keep in mind the Chinese proverb: "I hear and forget, I see and remember, I do and understand." Homework will be collected and must:

• Show the assignment number clearly on the first page• Be stapled• Have the problems in the given order assigned• Be on time for full credit, half credit for 1 week late, no credit after that.

.

P r oj ect s: Four projects will be assigned, valued at 5, 5, 10 and 10 points for a total of 30 % of the final grade. The students are expected to learn the software. It is strongly urged that students start learning the software immediately by performing the tutorial in Appendix B3 of the textbook. The projects are to be done by the students in groups of two, submitting one report per group alternating who writes the report. Projects may NOT be submitted via email. Note regarding late projects: projects submitted late will be reduced in grade by 15 %/week. See Projects and software assignment in Appendix A

T e s t s a n d E xa m s : All tests will be closed book (the lowest test grade will be dropped) For the final exam, one sheet of notes will be permitted.

M i ss e d T e s t s: Only one makeup test will be given, it will be fair but challenging. Missing the final exam without a valid excuse results in a zero grade for the exam.

A W o r d a b o u t P a rt n er s hip s: Students will partner with other students for the projects. Just like in industry, if you are assigned a partnership on a project you are expected to act professionally and work with your partner as best as possible. There is a clear, strong correlation between low or failing test grades and partners who don’t do their share of work or who copy from other groups.

Page 6


Pro fessi o na l So ci ety Meeti ng Attenda nce

In the interest of increasing student awareness and appreciation of professional societies and the value of life long learning, every student is required to attend at least one meeting of a professional society and submit a one-page report of the meeting. The IEEE society is very active at NJIT and has numerous presentations throughout the year on campus and at nearby locations (Go to h tt p :// w e b.n jit . e du / ~ i eee n j/ NE W S L ETTE R .h tm l for latest schedule). ACM also has local meetings. See the report forms for the meeting at the end of these notes. The re po r t m us t be h a nd e d i n w it h i n a w ee k af t e r a tt e nd i ng t he m ee ti n g . The form to be used is at the end of these notes.

Techni ca l Jo urna l Arti cl e

For the same reasons as stated above, during the semester every student is required to read and report on one relevant article from a technical journal (such as Circuit Cellar, IEEE Spectrum, EDN, Electronic Design, Nuts and Volts). J ou r n a l s not li s t e d n ee d p re-a pp r ov a l . Hard copies of these magazines may be available but you can also go to their web sites where numerous issues are archived. To enhance your understanding of the impact of technology on society and possibly, vice versa, the article must have at least some part related to issue and not be purely technical. Do not use any articles more than twoyears old. The form to be used is at the end of these notes and will also be emailed to you. Journal reports are acceptable only up through the 12th week of the semester.

I ns ta lli ng the So ftw a re

• The Quartus II software is available on the disk that comes with the book or can be downloaded for freefrom altera.com.

• Each student needs to create an account at Altera to get a licensing file, which is required for the software to work. Quartus II Version 7 that comes with the 3rd Edition Text book requires a license file. Version 8 and higher no longer requires a license file. You can download the latest version from the website which no longer requires a license file, it just requires you to open an account with them.

• Create Account: https:// www . altera . c o m / m y altera/ m al - index.jsp?referer=https%3a%2f%Error! Hyperlink reference not valid.

• A fte r A cc ount C reati on: https:// www . altera . c o m / do w n l o a d /lice n si n g /free _ s o ft w are/lic - q2 w e b. j s p You will be prompted for your computer NIC (Mac) Address. Then, a license file will be emailed to you.

Page 7

http://www.altera.com/download/licensing/free_software/lic-q2web.jsp

http://www.altera.com/myaltera/mal-

http://web.njit.edu/~ieeenj/NEWSLETTER.html


Hints for the Software

Students may submit what they consider to be helpful hints for the use of the software in this course. Every hint used will result in 5 points added to the student's most recent quiz.

NOTE: some of these hints are for the previous software generation (Max Plus) so they need to be updated and points will be given even though the hint is the same as long as it is checked.

1. Be sure you go through all the steps as outlined in the tutorial for starting a new project. The new project wizard works very nicely. If you leave a project and come back into Quartus, click on File>Open Project (do n ’ t use the open folder symbol) and then double-click on the project of interest.

2. Briefly, the steps for simulation (after successful compilation) are:(a) File> New > (tab)Other Files > Vector Waveform File - gets you to the waveform window(b) Save under the same name as your project name(c) click on Edit > Endtime and enter the end time of your waveform (160 ns, for example) (d) click on View> Fit in Window(e) click on Edit > Insert Node or Bus> NodeFinder … NOW Be sure to set the pins to a ll and then click List(f) select all the nodes you want and the click on ‘>’(g) you can now enter the waveforms of your inputs using the icon on the left under the arrow or you can

enter the waveform as a clock by selecting the node of interest > right click > value > clock, then select appropriate settings

(h) once input waveforms are set, select simulator tool >functional simulation, exit that menu and click onProcessing > Generate Functional Simulation Netlist

(i) finally! Click on Processing>start simulation

3. File names: once you are in a project, use that s a m e n a m e for all files associated with that project.

4. (P. Khade) P ro b l e m : size of printout from graphic editor is too small. S o l u ti o n : Go to ‘File,’ ‘size,’ and select dimension in inches (11x17 usually is a good size). OR: select entire circuit with mouse (turns red), go to ‘Edit’,‘Copy,’ place cursor in desired section of WORD document, go to ‘Edit,’ ‘Paste-special option,’ click OK, now you adjust size in your document.

5. (P. Khade) P ro b l e m : simulating wrong (usually previous) circuit. S o l u ti o n : When opening waveform simulator, click on icon that looks like three joined boxes in hierarchical fashion, ‘Change project name to current file,’ and continue with simulation.

6. (Q) If compiler is not selectable, be sure a project is open and the same name as the file.7. Using the template: open your template and immediately use file/save as to save under the name of the new

project you are starting. Then be sure to set the project to the current file. Also, keep in mind that the entity name must be the same as your file name so be sure to change all instances of entity name (at least three).

8. Be careful that you know what compiler you are in: you can switch between timing and functional SNF extractor after selecting “Processing” from the tool bar.

9. You may group and ungroup signals in the simulator by right clicking on the signal(s).10. Problem: when printing waveforms, you get too much. Solution: Under file, change the “endtime.”11. (J. Vida) You can see the circuitry or information (like input and output parameters) of any chip you want by

double clicking the device. For example, if you want to see the circuitry of a 3-to-8 counter, insert it and double click it.

12. (L. Pinchinat) AND5 and NAND5, and several other devices are not in the primitives library but can be created simply by typing the name into the symbol name box and then OK. A box will appear on the screen, double clicking the symbol will show how it is created.

13. (M. Kholaif) Accessing decoders: double click on your diagram file to open the Symbol window, in Libraries openOthers, open maxplus2. From the list select 74137 ( 3:8 active high decoder ) or 74138 ( 3:8 active low decoder) or74153M (4:1 multiplexer), etc.

Page 8

A B F

0 0 00 1 01 0 01 1 1

A B F F'

0 00 11 01 1


The Gates

Na m e Gr a ph i c S y m b o l s A l g. F un ct i on T r u t h T a bl e

AND

Standard: Alternate:

F = A●B

OR

INVERTER

BUFFER

NAND

NOR

XOR

XNOR

Page 9

EN


Exam pl e s usi ng al ter nate (e qui val e nt) gate sy m bol s

I. Given a digital chip with an active high enable line:

EN

a. Use a single gate that will allow the use of X and Y, two active high signals, to enable the chip.

b. Revise (a) to allow either X and Y to enable the chip or two other signals, S and T, when they are both low.

a. b.

II. Given a second chip with an active low enable line:

EN

a. Make up a single gate that will allow the use of X and Y, two active low signals, to enable the chip; i.e., when X and Y are both low the gate will generate a low signal to enable the chip. What gate do you actually end up using?b. Revise (a) to allow either X and Y to enable the chip or two other signals, S and T, when they are

both high.a. b.

Page 10


BOO LEAN ALG EBRA

Postulate: Basic axiom not requiring proof

Theorem: expression proven by postulates or already proven theorems

Dual: expression formed by interchanging 0<-->1 and AND <--> OR

(1)

P o s tu l a tes

0 + 0 = 0

D u a l s 1 • 1 = 1

C o mm ents

OR

(2) 0 + 1 = 1 1 • 0 = 0 and

(3) 1 + 0 = 1 0 • 1= 0 AND

(4) 1 + 1 = 1 0 • 0 = 0 Definitions

(5) 0′ = 1 1′ = 0 INVERTER

The o re m s

(6) X • 0 = 0 X + 1 = 1

(7) X + 0 = X X • 1 = X

(8) X + X = X X • X = X

(9) X • X′ = 0 X + X′ = 1

(10) (X′)′ = X N/A

(11) X + Y = Y + X XY = YX Commutative Law

(12) X + X′Y = X + Y X(X′ + Y) = XY

(13) X + XY = X X (X + Y) = X

(14) (X + Y) ′ = X′Y′ X′ + Y′ = (XY)′ ** DeMorgan’s Theorem

(15) (X + Y) + Z = X + (Y + Z) X (YZ) = (XY)Z Associative Law

(16) ( X + Y) (X + Z) = X + YZ X (Y +Z) = XY + XZ Distributive Law

** DeMorgan's Theorem is particularly useful for:• Forming complements of functions [change operator and complement variables]• Developing alternate, equivalent, symbols for gates

1. Complement: change operator and complement variables (inputs)2. Complement output

Page 11


In-class Review Exercises for Boolean Algebra and

Introduction to NAND and NOR Logic Implementations

1. Prove Theorem 13 two ways: Boolean algebra, and truth table

2. Simplify the following and draw the logic (simplified and unsimplified) for each:

a. (x + y′)′ =[Hint: use DeMorgan’s Theorem]b. [(x′ + y)z]′ =

c. A′BC′ + ABC′ + ABC =

d. [(AB)(B + C)] ′What single gate can implement your result?

3. Implement F = AB + CB', an SOP expression, two ways:

a. AND-OR-INVERT logic

b. NAND logic (which theorem allows you to do this?)

4. Implement F = (A+B)(A'+C), a POS expression, two ways:

a. OR-AND-INVERT logic

b. NOR logic (which theorem allows you to do this?)

5. Given: F1 = XY + Z and F2 = XY + Z′

Develop a truth table for F1 and F2 and then implement F1 and F2 as follows:

a. with AND-OR-INVERT logic b. with NAND gates

Page 12


I n-cl as s R eview E x e r ci s es C o ntinued

6. Investigating the exclusive-or gate:

a. Develop a truth table for the e x c l u si v e -or gate

b. Write a SOP expression

c. Convert the SOP expression to POS by applying DeMorgan’s Theorem twice

d. Implement the exclusive-or four ways by using the expressions from (b) and (c) and using different types of gates

e. Find, from your Boolean algebra of (c), the SOP and POS expressions for the exclusive-nor

f. Examine the truth table in (a) and explain why the exclusive-or may be referred to as an active-high-output inequality detector or an active-low-output equality detector

7. Implement F = ABC using three input AND gate(s) and using two input AND gate(s)

8. Implement F = (ABC)′ using three input NAND gate(s) and using two input NANDgate(s).

9. Compare and contrast (6) with (7). Can you draw a conclusion (hint: look at the dual of Boolean Algebra theorem 15)?

10. Given F(x,y,z) = Σm(0,1,3,4)

a. Write F in ca no ni ca l form (both SOP and POS)*b. Implement (a) with NAND gates and invertersc. Simplify F with a Karnaugh map (intuitive approach)d. Implement (d) with NAND gates and inverterse. Use a Karnaugh map to find a simplified POS expression (compare with (a))f. Implement (e) with NOR gates and inverters

*F = x'y'z' + x'y'z + x'yz + xy'z' and F = (x + y '+ z)(x' + y + z')(x' + y' + z')(x' + y' +

z)

Page 13


A Formal Method for Reducing an Expression Using a Karnaugh Map

Co n s tr u ct i n g Th e Map

• n variables require a map of 2n boxes; thus, 3 variables require 8 boxes, 4 variables require 16 boxes,5 variables require 32 boxes, etc.

• Every adjacent box must change by only one variable; thus the boxes are labeled 00, 01, 11, 10.

• “Don’t care" terms exist when certain input conditions don't occur and/or output permitted to be a 0 or 1 for a given input condition (binary to BCD converter is a good example).

D ef i n i t i o ns

On-set: all input combinations where the output is one*.

Implicant: a single minterm or group of minterms that can be combined together.

Prime Implicant: an implicant that can't be combined with another to form a larger implicant.

Essential P.I.: a Prime Implicant containing at least one minterm not contained in any other PrimeImplicant.

Pro cedure

A group of:

• 2 adjacent '1's will eliminate one variable• 4 adjacent '1's will eliminate two variables• 8 adjacent '1's will eliminate three variables

(1) Find a '1' within a single PI. This is an essential PI and all the 1's in it need not be examined again. If it is a true PI, it will always be as big a group as possible.

(2) Repeat (1) until all essential PI's have been found.

(3) Choose the minimum number of PIs that cover all the remaining 1's.

*Note: The K-map can also be simplified using zeros as the on-set resulting in an expression for f′. f can then be implemented using an (output) inverter or applyDeMorgan's Theorem to create POS logic.

Page 14

1 11 1 1

1 1


AN EXAMPLE FOR THE KARNAUGH MAP DEFINITIONS

00 01 11 1000011110

Without writing the expressions, just draw the following on a separate piece of paper.

I m plicants ( single minterm or group of minterms that can be combined together): On set (all input combinations where the output is one): 7

Pairs: 7

Quad: 1/ total = 15

Pri m e I m plicants ( can't be combined with another to form a larger implicant):

Pairs: 3

Quad: 1/ total = 4

Essential Pri m e I m plicants ( PI containing at least one minterm not contained in any other PIs):

Pairs: 2

Quad: 1/ total = 3

Page 15

11 1 11 1

1


In-class Review Exercises for Karnaugh Mapping

USING THE TECHNIQUES FROM THE PREVIOUS PAGES, DO THE FOLLOWING.

1. Represent the following in Karnaugh Maps and simplify:

a. F(A,B,C) = Σ (1,3,6,7)

b. F = AB + A′BC′D + A′B′(CD + C′D′)

2. Given the following Karnaugh map:

WX 00011110

YZ00 01 11 10

a. Find the simplest sum of products expression for F. b. Use the zeros to find F′c. Implement your equations for (a) and (b). How can you make (b) into F (two ways)?d. Compare the costs of implementations in (c)

3. Using Karnaugh maps find the simplest sum of products expressions for the following(using the ‘don’t cares’ where applicable):

a. F (W,X,Y,Z) = Σm(0,1,3,5,8,12,14) + Σd(2,4,7)

b. F (A,B,C,D) = Σm(4,5,6,8,9,10,13) + Σd(0,7,15)

4. Draw the logic for 3(a) and 3(b) and check that the outputs are what you expect for the don’t cares.

Page 16


Another Example of Using Zeros in the K-Map to Form POS Functions

Given the following truth table:

Input OutputA B C F0 0 0 00 0 1 00 1 0 10 1 1 01 0 0 11 0 1 11 1 0 11 1 1 0

1. a. Draw the K-map and use the zeros to form F'

b. Apply DeMorgan's Theorem to find F as a POS expression

c. Draw the logic using NOR gates

2. Prove that the logic in 1.c is correct with respect to the given truth table

Page 17

AB

0 1

C′C′ 1 (C + C′)


Variable Entered Maps (VEMs)

Advantage: increases amount of variables in a map by at l east one

Method for one additional variable

(This approach will also be used later for implementing logic using multiplexers)

1. Create a new column in the truth table with f as a function of the least significant variable2. Fill in the K-map using the new truth table, only leaving out zeros3. Combine 1’s as with a standard map but also combine all like groups (be sure to

cover all 1’s AND all variables in map)

Example: F = Σ (2,4,6,7)

INPUTS OUTPUTA B C F F(C)0 0 0 0 00 0 1 00 1 0 1 C′0 1 1 01 0 0 1 C′1 0 1 01 1 0 1 11 1 1 1

(In this case C was assumed to be the least significant variable)

01

F = A B + B C′ + A C′ (check with a standard Karnaugh map)

Other Problems to try:

1. F(A,B,C,D) = Σm(1,4,5,6,9,12)

2. F = wx′yz + w′xy′z + wx′yz′ + wxy′z + w′x′y′z = Σm( ? ) (Canonical?)

3. Y(a,b,c,d,e) = Σm(3,6,7,11,12,13,14,15,19,22,23,24,25,26,27,28,29,30,31) Hint: result contains only four simple terms (See partial solution on next page.)

Page 18

Dec. Val. (abcd) e Y Y(e)16 8 0

100

18 9 01

01

20 10 01

00

22 11 01

11

24 12 01

11

26 13 01

11

28 14 01

11

30 15 01

11

cd00 01 11 10


Partial Solution forY(a,b,c,d,e) = Σm(3,6,7,11,12,13,14,15,19,22,23,24,25,26,27,28,29,30,31)

Dec. Val. (abcd) e Y Y(e)0 0 0 0 0

1 02 1 0 0 e

1 14 2 0 0

1 06 3 0 1

1 18 4 0 0

1 010 5 0 0

1 112 6 0 1

1 114 7 0 1

1 1

Ab00

01

11

10

Page 19


Major CAD Tools and Tasks

(ref. Sections 2.9 and 4.12 in Brown/Vranesic)

• Design Entry

1. Schematic capture (disadvantage- may be unique to software) and/or

2. VHDL text*

• Initial Synthesis and Functional Simulation

1. Generates (translation or compiling) an initial circuit based on the design entry2. Verifies circuit functionality using designer’s inputs

• Logic Synthesis and Optimization

Applies optimization techniques to create an equivalent but better circuit

• Physical Design

Technology mapping- designs optimized circuit in the selected target technology (PLD orFPGA, etc.)

• Timing Simulation

Simulates circuit considering delays in the physical design

• Chip Configuration

Implements design in the actual chip.

*VH DL Desi g n Approa ches

Behavioral Using descriptions of required behaviors to describe the design

Dataflow Using Boolean equations to define I/O relationships

Structural Using internal signals to connect predefined components (sub- circuits)

Page 20


Some Practical Considerations

• Implementation Strategies

• Physical Characteristics of Some Logic Families

• Data Sheets

• Number of Transistors and Logic Levels in an Exclusive-Or

Note: The information on the next several pages will be supplemented by instructor notes and by figures from the text book, including hardware information describing and showing the transistor circuits comprising standard logic gates and transmission gates.

Page 21

BC00 01 11 10


So me Pra ctica l Co ns idera tio ns Co ntinued

A. Implementation StrategiesGiven F(A,B,C) = Σ(1,3,5)

1. Reduce with a Karnaugh map and write the Sum of Products expression:

A

01

F = The map, if done properly, gives us the simplest possible pure SOP.

2. Implement (1) with NAND gates and inverters:

NOTE: The number of gates plus the total number of inputs is an indicator of cost. However, normally inverters are not counted because inverted inputs are usually available.

Logic: Cost (including inverters):

3. Factor the expression from (1) and now implement with AND-OR-INVERT gates:

New Equation:

New Logic: Cost (including inverters):

Page 22


4. Repeat (3) but use a NAND to simplify.

New Logic: Cost (including inverters):

5. Discuss the implications the three different implementations in terms of reliability, cost, landscape area, delay, etc.

Page 23


So me Pra ctica l Co ns idera tio ns Co ntinued

B. Physical Characteristics of Some Logic Families

Family Typical Typical *Speed Typical Maximum *** WorstPropagation Power Power Fanout Clock Rate Case Noise

Delay Dissipation Product (MHz) Margins (ns) (mW) pW-s (mV)

74 9 10 90 10 35 400

74LS 9.5 2 19 20 45 700

74ALS(Enhanced LS)

4 1.2 4.8 20 70 300

ECL .3 25 7.5 25 1400 150

74HC** 10 1.5 15 50 20 1400

74AHC** (Advanced

High Speed)

3.7 .006 .02 50 130 550

*NOTE: (speed)(power) = a figure of merit ....... to be minimized, units are pico Watts-seconds or pico Joules

**CMOS

*** Noise Margin is the maximum noise signal that can be tolerated by a gate[low level NM = ∆VL = VIL(max)- VOL(max);high level NM = ∆VH = VOH (min) - VIH(min)]

Page 24


S ome Practi cal Con si d erati on s Con tinu ed

Da ta Sheets

Data Sheets for logic devices may be found at manufacturers’ web sites. A good approach is to go through the ECE Labs web site ( h tt p :// w e b.n jit . e du / ~ g il h c / ) and from there through the “Useful Links” to one of the manufacturers or distributors.

What you find on the data sheets:

• Written Description of the Device• Function/Truth Tables• Internal logic diagram• Boolean Expressions• Pin-Outs of the Package• Some of the Transistor Circuitry• Operating Specifications (such as temperature limits, supply voltages)• Recommended Operating Conditions• Electrical Characteristics• Switching Characteristics

Using the information from the data sheet, the user can calculate (if not explicitly given) such things as power consumption and fan-out for the individual devices as well as accumulate values based on chips being used.

One very good web site for data sheets is www.onsemi .com /

T AKE -HO ME ASS IGNME NT

Look up four different d i g it a l devices and choose and print out a different part of each data sheet. The cover sheet of your homework should contain the following summary table:

Device # Device Name Part of data sheetExample: 74LS138 1 of 8 Decoder Switching Characteristics

(1)(2)(3)(4)

For above example,At the onsemi.com web site, enter 74LS138 in the Product Search window and then click on

Search. Next click on Datasheet to get the pdf file.

Or, at the onsemi.com web site, enter 1-of-8 decoder in the Product Search window, click onSearch. You will then see the 74138 listed in the Design Resources table.

Page 25

http://www.onsemi.com/

http://web.njit.edu/~gilhc/


S ome Practi cal Con si d erati on s Con tinu ed

Number of Transistors and Logic Levels in an E x c l u si v e- O r With Different Implementations of CMOS Logic

N o te: Need to study CMOS logic and Transmission Gates First

Logic for Transmission Gate Implementation Proving with a Truth Table

X

X Y S T F

S0 0 0 Z 0

Y

T F

Co mpa ri ng 3 Ty pes o f XO R I mpl ementa ti o n (a l l us e CMO S):

Devices (# transistors) ImplementationAND,OR,INVERT NAND TRANSMISSION GATES

1. NOTs (2 each) 4 4 4ANDs (6 each) 12

OR (6 each) 6

2. NANDs ( 4 each) 12

3. SWITCHES (2 each) 4

TOTAL # ofTransistors:

22 16 8

Logic Levels (not counting inverters):

2 2 1

Page 26

Input Output

A B D0 D1 D2 D3

S(elect) Y (OUTPUT)

0 A

1 B


INTRODUCTION TO DECODERS AND MULTIPLEXERS

• Design a 2:4 decoder having active high inputs and active low outputs (usingNAND gates):

NOTE: Only one output active for any given input condition- often referred to as one-hot encoded.

A D0

D1B

D2

D3

Now design a 3:8 decoder (what are the inverters doing in original circuit)?Make a ‘138 which has two active low and one active high enable. And use two ‘138’s to make a 4:16 decoder.

Now add an active low enable line.

• Design a 2:1 multiplexer having the following functi o n table:

S

AY

B

How can you now design a 4:1 multiplexer from 2:1’s?

[NOTE: Multiplexers can also be constructed from transmission gates, see Figures 3.60 and 3.62 inBrown and Vranesic.]

Page 27

1 33 0 2 0


Arithmetic circuitry Loads four BCD digits

Into temporary registers

E MS digit

register

E Digit register

E Digit register

E LS digit register

Decoder/ Demultiplexer Sequentially enables each Of four digits

Digital bus

E 0

174139

2

3

A1 A0

Digit decoder And driver

circuitry

Decodes BCD into Seven-segment And drives display

Digital bus

MSD LSD

E E E E

Block Diagram of a Multiplexed 4-Digit Display

Four-digit Display,

Each digit On ¼ of the time

Ref: Kleitz

Page 28


Expanding Decoders and Multiplexers• In-class exercise for decoders

1. G i v e n only two 3:8 (1 of 8) decoders, each with active low outputs, three enables (two active low and one active high) and only one inverter.

D e s i g n a 4:16 decoder with two enable lines, one active high and one active low, labeling

everything. S how that your design works for an input of 7 (0111) and an input of C (1100).

• In-class exercise for multiplexers

2. Labeling everything, design an 8:1 multiplexer using two 4:1 multiplexers and one 2:1 multiplexer. Show that with the select value at six (110) input six, w6, will appear at the output of your 8:1 multiplexer.

Page 29


COMBINATIONAL LOGIC

FROM DECODERS AND MULTIPLEXERS

• Decoders (Based on fact that all minterms are generated):Select decoder based on number of inputsSelect output gate (AND or NAND) based on number of ones vs. number of zeros- look at alternative

symbols

• Multiplexers (Hardware is essentially a decoder with an output gate):For efficiency set up truth table as with Variable Entered Maps. This is actually an application of

Shannon’s Expansion Theorem, which states:

F(W1,W2, …, WN) = (W1)′•(0, W2, …WN) + (W1)•(1, W2, …WN)

See examples 6.5 and 6.6 in Brown/Vranesic text.

• Example: (student or instructor may wish to do the example below first) Implement the following sets of functions minimally with decoders with appropriate gates, then with multiplexers and compare your results.

I. II.F1(w,x,y) = Σ (2,3,4) F1(A,B,C,D) = Σ (0,1,2,4,9)F2(w,x,y) = Σ (0,1,2,5,7) F2(A,B,C,D) = Σ (1,2,3,4,7,8,9,11,13,15)

Major Revi ew Prob l em (4 d i ff eren t app roach es to i mp l emen t a comb i n ati on al l ogi c p robl em)

Given: F(W, X, Y, Z) = Σm(0,2,5,7,8,13,15) + Σd(10)

Implement as (and indicate the output for 1010 in each case): I. An SOP using NAND gatesII. A POS using NOR gates III. A 4:16 or two 3:8 decoders IV. An appropriate multiplexer

Page 30


EXAMPLES OF IMPLEMENTING COMBINATIONAL LOGIC

WITH PROMS, DECODERS AND MULTIPLEXERS

Implement an adder/subtractor cell (input: M,x, y, Ci output: S, Co)

(1) Using 8:1 multiplexersmethod: group the truth table in pairs (with constant values of the most significant bits) and write the output as

a function of the least significant bit(2) Using decoders with NAND (or AND) gates

method: a decoder implements all possible minterms; thus, using an OR one can select the proper terms for the output

(3) Using a PROMmethod: determine the number of address lines based on the number of inputs and determine

the size of the "words" stored based on the number of outputs(4) Using a K-map reduce the expressions as much as possible and then implement with exclusive-ors and/or NANDs.(5) Compare the implementations of (1) through (4) in terms of number of connections, number of devices and reliability.

FUNCTION TABLE

M OUTPUT0 x + y + Ci

1 x - y - Ci

PARTIALLY COMPLETED TRUTH TABLE

INPUT OUTPUTM x y CI Co S

0 0 0 0 0 00 0 0 10 0 1 00 0 1 10 1 0 0 0 10 1 0 10 1 1 00 1 1 1 1 11 0 0 01 0 0 1 1 11 0 1 01 0 1 1 1 01 1 0 01 1 0 11 1 1 01 1 1 1 1 1

Page 31


Time Division Multiplexing (TDM) Data Transmission Example

Notes for the example on the following page:

1. On the left is a transmitter (TX) which multiplexes four data lines.

2. On the right is a receiver (RX) which de-multiplexes 1 data line into four.

3. Given the data values at the inputs and using the waveforms from the counter, draw what will appear on ‘T.’

HOMEWORK:

• Draw in the waveforms for the outputs of the de-multiplexer. Keep in mind thatthe de-multiplexer is actually a decoder using the enable line for the input and askyourself what the output will be for the lines that are not activated (as you know only one output can be active at any time.

Con ti nu ed o n Nex t Pag e

Page 32


Time Division Multiplexing

See Notes and Homework assignment on previous page.

Page 33


Number Systems

1. Number of symbols and counting in the various number systems

2. Weights and conversion between various systems and the decimal system

3. Conversion between binary and hexadecimal

4. Why hexadecimal is so useful:• less digits than decimal or binary• easy conversion with binary

5. Two’s complement n o t a t i on (expressing both positive and negative numbers)

6. Recognizing positive and negative numbers in binary and hex

7. Expressing addresses in hexadecimal notation

Page 34


Number System Conversion Practice

Complete the following table:

Decimal Binary(using 8 bits)

Hexadecimal(using 2 digits)

270000 1010

4A1100 0111

8865

111EC5D

0011 1111

(Solution on next page)

Page 35


Number Conversion Solution

Decimal Binary(using 8 bits)

Hexadecimal(using 2 digits)

27 0001 1011 1 B10 0000 1010 0 A74 0100 1010 4 A

199 1100 0111 C 7136 1000 1000 8 865 0100 0001 4 1

111 0110 1111 6 F236 1110 1100 E C93 0101 1101 5 D63 0011 1111 3 F

Page 36


Signed Number Practice and Review Questions

(Assume an 8-bit data byte and signed numbers will use 2’s Complement Notation)

1. What is the range of unsigned binary numbers? to

2. Express # 1 in decimal. to

3. Express # 1 in hexadecimal. to

4. What is the range of positive binary numbers? to

5. What is the range of negative binary numbers? to

6. Express # 4 and # 5 in decimal.

to and to

7. Express # 4 and # 5 in hexadecimal.

to and to

Complete the following table for signed numbers:

Decimal Binary (use 8 bits) Hex (use 2 digits)

+ 32- 32-128

1010 0001F FE E

0111 00114 9

Perform the following operations on decimal numbers using 8-bit signed binary numbers:

1. 20 + 432. 43 – 203. 20 – 434. – 20 – 435. 110 – 1006. 100 – 1107. 100 + 110 (explain your result)

(Solution on next page)

Page 37


Signed Number Practice and Review Questions SOLUTIONS

(Assume an 8-bit data byte and signed numbers will use 2’s Complement Notation)

1. What is the range of unsigned binary numbers? 000 0 000 0 to 111 1 111 1

2. Express # 1 in decimal. 0 to 255 .

3. Express # 1 in hexadecimal. 0 0 to FF .

4. What is the range of positive binary numbers? 000 0 000 0 to 011 1 1111 .

5. What is the range of negative binary numbers? 111 1 111 1 to 100 0 0000 .

6. Express # 4 and # 5 in decimal.

0 to + 127 . a nd - 1 to –128 . ( no te tha t 25 6 d iffere nt va lue s re p re se nted )

7. Express # 4 and # 5 in hexadecimal.

0 to 7 F a nd FF to 80 .

Complete the following table:

Decimal Binary (use 8 bits) Hex (use 2 digits)

+ 32 0010 0000 20- 32 1110 0000 E0-128 1000 0000 80- 95 1010 0001 A1-1 1111 1111 F F

- 18 1110 1110 E E+ 115 0111 0011 73+ 73 0100 1001 4 9

Perform the following operations on decimal numbers using 8-bit signed binary numbers:

8. 20 + 43 = (0001 0100) + (0010 1011) = 0011 11119. 43 – 20 = (0010 1011) + (1110 1100) = 0001 011110. 20 – 43 = (0001 0100) + (1101 0101) = 1110 100111. – 20 – 43 = (1110 1100) + (1101 0101) = 1100 000112. 110 – 100 = (0110 1110) + (1001 1100) = 0000 101013. 100 – 110 = (0110 0100) + (1001 0010) = 1111 011014. 100 + 110 (explain your result) = (0110 0100) + (0110 1110) = 1101 0010#14 is incorrect for signed numbers (exceeds limits for 8-bit numbers) but correct for unsigned numbers.

Page 38


Arithmetic Circuits Summary

I. Review of Adders

II. Subtraction using 2’s complement and programmable inverters (XORs)

III. Using CAD tools to design, simulate and implement arithmetic logica. Straightforward implementation with numerous stages and/or instantiation

b. Using pre-defined sub-circuits- Library of Parameterized Modules (LPM)i. Parameterized means adaptable to be used in a variety of ways by setting parameters

ii. Quartus LPM is a library of technology independent macro-functionsiii. LPM_ADD_SUB is a good representative example

c. Using VHDLi. Structural (connecting together sub-circuits) using a previously created file (requiring a

USE statement) as a COMPONENT which is declared in the new file (Figs. 5.22 and5.23) and also for each instance - instance name: component name PORT MAP (list of inputs and outputs in proper order but if used in a different order then use syntax ofsub-circuit name => new instantiated name, …)

ii. Create a PACKAGE, usually from a previously created file (Fig. 5.24) or as part of the original file,

Page 39


Adder/Subtractor Logic Using Two’s Complement

Notes:1. Draw a block diagram2. Create a function table3. Discuss the exclusive-or as a programmable inverter4. Assuming the full adder has two levels of delay, discuss the delay before Cout is valid and the

idea of look-ahead carry logic

Page 40


Co mpa ra to r Ci rcui t

► See VHDL Comparator file in VHDL Appendix, page 90

Page 41


Memo ry Sy s tem Desi g n Exa mpl e

Design a memory system for a microprocessor having a 16 bit address bus of which half is multiplexed with an 8 bit data bus. Use 74LS373 chips to de-multiplex the DA bus. Assume you have 16 k RAM chips and 8 k ROM chips. The ROM section should be placed in the highest memory address area. Use decoders for memory chip selection. Included control signals: (RD)’, (WR)’, IO/(M)’ and ALE. Once designed, show in what memory chips the following addresses will be located:1234H, 68E6H, 0A111H, 0FFFFH.

Page 42


Decoder Take Home Assignment/Quiz (partnerships allowed)

Using what is given below, on a single sheet of paper:

A. Design the memory section for an 8088 based microcomputer. Because a hardware reset causes the processor to fetch an instruction from location 0FFFF0H, this area of memory must contain a ROM or PROM.

B. Indicate on your memory system in which memory chips each of the following addresses are located:

2F06AH 890E2H 0BDEC0H 0F0000H

Given:

S i gn al s f rom th e 8088

• Control signals to be used: ALE, RD, WR, IO / M

• Multiplexed Buses: AD0 -- AD7, A16S -- A19S

• Non- Multiplexed Address Bus: A8 -- A15

Avail ab l e Ch i p s (you may n ot n eed al l of th ese chip s)

• 2:4 decoders with active low outputs and one active low enable line

• 3:8 decoders with active low outputs and three enable lines (2 active low, one active high)

• unlimited supply of two-input NANDs and inverters

• two 64k PROMs (data size = 1 byte) with a single active low chip select and active low output enable (for reading)

• eight 128 k static RAMs (data size = 1 byte) with a single active low chip select and a R / W input

• two 74LS373 devices for demultiplexing

Page 43


Hazards and Glitches

Def ini ti on s

Glit c h : an unwanted pulse at output of a logic networkH azard : a built-in potential for a glitch

St a tic H azard : output expected to remain un c h a ng e d but may change due to a hazardD y n a m ic H azard : output has potential to change more than once when it's supposed to go through a single change

No t e s : • In all cases the assumption is that only one input bit changes at any instant of time which is required anyway for

asynchronous sequential circuits, where hazards may cause a problem• Hazards are not generally a problem in combinational circuits and in synchronous sequential circuits because the flip

flop inputs only need to be stable within the setup and hold times of the flip flops

Static Zero Hazard: Dynamic Hazard:

Remedi es

(1) Hazard free design (often means "redundant"

gates) (2) Strobing so that output is only sampled after

glitches (3) Slower clocks to eliminate dynamic hazards

(4) Using only two-level logic and designing those two levels as hazard free

S tati c H azard E xampl e

Given that f = Σ (0, 1, 3, 4)

(a) simplify using a K-map and draw the logic

(b) Examine for the case of ABC = 000 --> 001

(c) Examine for the case of ABC = 001 --> 000

(d) Explain the problem in terms of prime implicants

(e) Correct with a redundant gate and check

T esti n g f or Gli tch es w i th a Si mul ator

• Hold the constant bits with a switch or tie to one or zero.

• Simply attach a clock to the variable that changes.

Page 44


Application Specific I ntegrated Circuits, ASICs

A dv a n t a g e s :

(1) Better system performance (high speed, low power) (2) Smaller system size (reduced chip count)(3) Lower system cost (assembly, board area, inventory) (4) Higher system reliability (fewer interconnects)(5) Security (design difficult to copy by reverse engineering) (6) Substantial amount of available software

ASIC Design Alternatives

Se m i -cu s t o m C u s t o m

(few or no steps customized) (many, or all, steps customized)

PLD CPLD FPGA GA Standard Cell Full Custom(a) (b) (c) (d) (e) (f)

<<---------------------------------------------------------------------------------------------------->>fast time to market high design complexity possible easy to change design lower per unit cost

longer design timechanges difficult and costly

C o mm ent s :

(a) Programmable Logic Device (PLD)• generally an AND-OR array with latches• small combinational and sequential implementations possible

(b) Complex PLD (CPLD)• comprised of 'PAL-like' blocks with interconnection wires and I/O blocks• usually support in-system programming (ISP) using a JTAG port

(c) Field Programmable Gate Array (FPGA)• chip is a large array of same type of cells, usually volatile LUTs (loaded from

PROM on power-up)• cells are interconnected by the user via CAD tools

(d) Gate Array (GA)• chip is a large array of same type of cells• interconnect during final masking steps

(e) Standard Cell• chip is an array of different types of standard cells• interconnect cells during later masking steps

(f) Full custom• entire chip is designed to meet the customer's specifications• inexpensive for very high volume applications

Page 45


Simple Programmable Logic Devices, SPLDs

(Specifically designed to implement logic functions)

Tw o Ma jo r Ty pes :

1. PLA - SOP implemented with fuses at AND’s, OR’s, Inverters

2. PAL - similar to PLA but NO fuses at OR’s (less flexible but cheaper, faster and easier to program)

C o ntr a s t w i th a R O M

a ROM with 16 address lines and 8 output lines has 216 x 8 = 65,536 locations

a typical PLA with 16 address lines and 8 output lines might store only 96 words (16 x 96 x 8)

Metho d o f PLA desi g n:

1. Determine block diagram with I/O lines defined from design specifications

2. Simplify expressions for f and f′ using K-map

3. For each output, select f or f′ depending on simplicity of implementation

4. Form a PLA program tablea. list product terms and number themb. list inputs for each product term (paths between inputs and AND’s)

where 1 : if unprimed (a path),0 : if primed (path from complemented input),- : if absent (no path)

c. list paths between AND’s and OR’s (outputs)where 1 : if product term present,

- : if no path or connection d. under outputs

where T : if output inverter is bypassedC : if output complemented by inverter

5. Draw the logic in shorthand notation

Page 46


Introduction to Sequential Logic

Defi ni ti o ns

Combinational Logic: outputs are uniquely determined by the present state of the inputs

Sequential Logic: a system containing combinational logic AND memory elements and whose output depends on the input, output and the past.

Two types of sequential logic:

1. Asynchronous- Output depends on order and values of input and can change at any instant

Essentially combinational logic with feedback and delay

Delay provided by gates themselves, latches, or transmission lines

2. Synchronous- Outputs change at discrete instants of time

Values stored in latches/flip-flops

Synchronization usually provided by a master clock

The flip flop is the basic storage element and will store one bit. The output of the flip flop corresponds to what is stored inside.

Basi c Functi onal Equati ons (where E= ex cit ati on, S = present st at e, O= out put , and I= i nput ):

Type of Logic Excitation (E) Next State Output Counter E = f(S) St+1 = f(E) O = f(S) Moore E = f(S,I) St+1 = f(E) O = f(S) Mealy E = f(S,I) St+1 = f(E) O =f (S,I)

Page 47

Rq00 01 11 10


Introduction to Latches and Flip-Flops

Desi gn a a NAND l atch (f li p -f l op s w i th cl ock s w il l soon f oll ow ):

Criteria:• Two active low inputs, S (set) and R (reset)• If set is active, the latch will go to one; if reset is active, the latch will go to zero• Active high output, Q• If both inputs are active, the condition is invalid and the outputs are “don’t cares”• If both inputs are inactive, the latch should store the previous value• Use the convention of present state is lower case q, next state capital Q

Desi g n

Block Diagram:

Truth Table:

INPUT OUTPUTDescriptionS R q (Present State) Q (Next State)

0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1

Simplifiy with a Karnaugh Map:

S01

Q = f (S, R, q) = (the characteristic equation for a NAND latch)

On a separate paper, draw the logic using NAND gates(NOTE FEEDBACK FOR ‘REMEMBERING’ PRESENT STATE)

Page 48


In trodu cti on to L atch es an d Fli p -Fl op s Con tinu ed

I n -c l a s s A ssi gn m e n t : Design an active high input latch using NOR gates (HINT: recall that NORlogic uses POS, so use the zeros in the K-map)

Enh an ci n g t h e NAND l at ch :

1. Add NANDs at the input to allow for an enable line a. How else does this affect the latch?b. Why is this called a ‘gated latch’?

2. Add additional inputs to the output gates for (PRE)' and (CLR)'. How does the enable line affect these inputs?

3. Convert the NAND latch into a 'D' latch (how does this affect the 'invalid' condition?)

Page 49


In trodu cti on to L atch es an d Fli p -Fl op s Con tinu ed

Rev i ew o f NAND l at ch wit h an ex amp l e o f an al yzi n g a si mp l e s equ en ti al ci rcu it :

Given a three input (X,Y,EN) and single output (Z) device. Included are two latches: (1) an active lowSR and (2) a gated SR with a CP (L EVEL CLOCK or enable) input. The excitation equations are S1 = S2 = X, R1 = R2 = Y and EN is tied to CP of SR2. The output equation is Z = Q1 ⊕ Q2.

1. Draw the logic2. Complete the timing diagram below for Q1, Q2, Z (use cross-hatching for unknown

values) LOGIC:

X

Y

EN

Q1

Q2

Z

Page 50


Ma s ter-Slav e a nd E dg e T rigg ered Flip Flo ps

I. Convert the NAND latch into a 'JK' latch by using feedback (how does this affect the 'invalid' condition? why may the JK oscillate in the toggle mode?)

II. Create a master-slave flip flop using two D latches (the critical gate is the inverter between the two clocks).

III. Create a positive edge triggered D flip flop by using a D latch with an AND (in front of the level- triggered clock) but having one input through an inverter to create a glitch. Refer back to the notes on hazards and glitches on page 45 in these notes. To create negative edge triggering, just realize we need clk AND not-clk to be ZERO.

IV. See next page for information regarding setup and hold times.

Ex amp l e o f edg e t ri gg eri ng : an al yzi n g a si mp l e s eq u en ti al ci rcu i t

Given a three input (X,Y,clk) and single output (Z) device. Included are two negative-edge-triggered flip-flops: (1) an SR and (2) a JK. The excitation equations are S =J = X, R = K = Y. The output equation is Z = Q1 + Q2.

1. Draw the block diagram and the logic2. Assuming Q1 and Q2 start at 0, complete the timing diagram below for Q1, Q2, Z.

BLOC K DIAGR AM LOGIC

c lk

X

Y

Q1

Q2

Z

Page 51


Setup and Hold Times

Keep in mind:1. Times are measured using the 50 % points on switching waveforms2. This material applies not just to single flip flops but is also of concern for chips

Active Edge of clock or trigger: the edge (either positive/rising, or negative/falling) that triggers a synchronous device to accept digital input states.

Race Condition: A condition that occurs when a digital input level, 0 or 1, is changing state (to 1 or 0)at the same time as the active clock edge making the recognized input level undetermined.

Setup Time: The length of time that the inputs of a digital device must be stable b ef o r e the active edge of a clock, to avoid the race condition.

Hold Time: The length of time that the inputs of a digital device must be stable af t e r the active edge of a clock to avoid the race condition. For newer devices the hold time may actually be zero.

E xerci se

A. Fill in the following table based on the data sheets for the given devices (first row filled in for you):

Device # Device Description tsu

(min)

th

(min)

tPLH

(max)

tPHL

(max)74LS76 JK with positive edge

trigger20 ns 0 ns 20 ns 30 ns

74LS10974LS74

B. Complete waveforms for Q illustrating tsu, th, tPLH and tPHL for a D flip flop having values of 20ns,5ns, 20ns, and 30 ns, respectively. Assume D goes high at 150 ns and low at 300ns; that Q starts at 0; theclock pulses start at 200 and 350 ns; clock pulse widths are 2 ns each. Assume positive edge triggering.

D

clk

Q

Page 52

Kq00 01 11 10


Forming one Flip-Flop from Another

Note: It is much easier to convert a two input FF to a one input FF (such as JK to T or SR to D) than a one input FF to a two input FF.

Example Problem: C onvert a D Fli p-Fl op i nt o a J K

The inputs are J, K, PS (q). The output is: NS (Q).Note what we are doing is designing combinational logic whose inputs are J, K, and q and whose output is D. Therefore, Fill in the State Table:

Input Output Flip FlopInput*

J K q Q D0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1

*Ask yourself what value at D will cause the flip flop to go from the given q to the desired Q?

Use a K-map to reduce the equation for D:

J

0

1

D =

Draw the logic on the next page.

Page 53


Forming one Flip-Flop from Another cont’d.

Draw the Logic (assuming a positive edge triggered ‘D’ flip flop) and check:

Questions:

1. What’s an easy way to create a D flip flop from a JK?

2. How can we change the triggering from positive to negative edge?

Page 54


Introduction to State Diagrams(Using Edge-Triggered Flip-Flops)

Keep i n mind :

• State (and output) appear inside the circle• There should be as many arrows leaving each circle as there are possible combinations of inputs• Use ordered pairs when there is more than one input and/or more than one output• The clock is not shown but is always assumed present

Dr a w st a t e d ia g r a m s fo r :

1. D flip-flop

0 1

2. SR flip-flop (use “don’t cares” where appropriate)

0 1

3. JK flip-flop (use “don’t cares” where appropriate)

0 1

4. T flip-flop

0 1

Page 55

In Outq S R Q0 0 0 00 0 1 00 1 0 10 1 1 d*1 0 0 11 0 1 01 1 0 11 1 1 d*

SR00 01 11 10

d 11 d 1

In Outq D Q0 0 00 1 11 0 01 1 1

In Outq J K Q0 0 0 00 0 1 00 1 0 10 1 1 11 0 0 11 0 1 01 1 0 11 1 1 0

JK00 01 11 10

1 11 1

In Outq T Q0 0 00 1 11 0 11 1 0

0

0


Flip-flop Characteristic Equations (Assume clock present in all cases.)

SR q

1

Thus, Q = S + R′q

* Never occurs if FF properly used

DThus, Q = D

JK q

1

Thus, Q = q'J + qK'

T

Thus, Q = q ⊕ T

Summary: Type Characteristic Equation

SR S + qR′D DJK q′J + qK′T T ⊕ q

Page 56


Analysis Procedure for Sequential Logic

1. Write the Flip-Flop e x c it a ti o n e qu a ti on s and ou t pu t e qu a ti on s directly from the given diagram. (FF inputs and external outputs as functions of FF present states and external inputs.)

2. Write the st a t e e qu a ti on s by combining excitation equations with the characteristic equation for the particular type of FF used.

3. Construct a state table and state diagram from state equations.

4. Draw the resulting state and external output waveforms for a given input sequence.

Page 57


Sequential Analysis Example

Given the following e x c it a ti on e qu a ti ons for a sequential circuit consisting of one input, x, one output, Y, and two flip flops, numbered as 0 and 1:

S0 = x′q1 S1 = xq0′R0 = xq1′ R1 = x′q0

The ou t pu t e qu a ti on is: Y = xq1′q0

a. Is this a Mealy or Moore machine?b. Draw the logic (assume RS flip flops with negative-edge-triggered clock). c. Redraw the logic in simplified form.d. Determine the state equations.e. Construct a state table a nd state diagram.f. Complete the timing diagram below (ASSUME THAT THE FLIP-FLOPS ARE INITIALLY AT 00). g. Repeat (e) using a state table (w/o finding the state equations)

b. LOGIC:

c lk

1 2 3 4 5 6 7 8

x

Q1

Q0

Y

Page 58


• Introductory Definitions for Registers

Register: a group of binary cells (for storage) which responds to a clock edge

Counter: a register that goes through a predetermined sequence of states changing with the clock

Gated Latch: register that responds du r i n g a pulse (as opposed to a flip-flop)

Memory Unit: collection of storage cells and their associated circuits necessary forInput/Output(interfacing is usually tri-state) and selection (decoding)

• Types of Counters

Ripple: Clock inputs, except the first, are connected to the previous flip flop

Synchronous: Each flip flop is tied to clock input, thus all change at the same time

Ring: Output of last stage of register feeds input of first stage (also calleddecimal counter because the FF that is high indicates how manypulses or a divide-by-n device, where n= number of stages, because input frequency is divided by n). If a single one in the counter, often the case, then we have one-hot encoding.

Johnson: Output of c o m p l e m e n t of last stage feeds input (also called a twisted ring counter or a divide-by-2n device, n = number of stages)

Page 59


Asynchronous (Ripple) Counters

Q0 Q1 Q2 Q3

clk

1 1 1 1T T T T

c lk

1 2 3 4 5 6

Q0

Q1

Q2

Q3

count 3 4 5 6 7 xxxx 8 9

No te:

1. All 'T' inputs are tied to '1.

2. All clocks, except the first are tied to the output of the previous flip-flop.

3. Logic is easy to analyze by starting with LSB, Q0, then examine Q1Q0, etc.

5. The responses are all 'ideal' at each negative edge except at clock pulse 5 to show the(exaggerated) delay and illegal states.

Page 60


Design a Synchronous Counter

• A synchronous counter will change state only with the clock and every flip flop's clock input is tied to the external clock.

• Looking at the ripple, or asynchronous, counter timing diagrams we see that each subsequent flip flop will toggle only when a l l the previous flip flops are set.

• Thus, for example, Q2 will toggle when Q1 a nd Q0 are both one.• Also, add an input that will enable the count when it is one and totally disable it

when it is zero.

Des ig n

Page 61


Using Universal Binary Counters

I. Draw and label a 4-bit binary up counter that has four parallel inputs (I0 – I3), four outputs (O0 – O3)a Count Enable (CE), an asynchronous active low clear (CLR), negative edge triggered clock (clk), a synchronous load input (LD), and a carry out (CO).

II. Using the counter from (I), design a modulo-8 (8 states) counter and draw a state diagram for

each: A. Making use of the CLR input

B. Using the LD input

C. Using the LD input but starting at 5 (0101)

Page 62


Using Universal Binary Counters Continued

III. Draw a modulo-100 counter using two counters from (I). Have the counter start at 1710.

Page 63


Counter Design Procedure

• Draw the state diagram

• Construct Next State Table with flip flop inputs using excitation tables (next page)

• Simplify with K-maps making sure to use Present States (NOT Next States) as inputs

• Check for self-correction

Page 64


Co unter Desi g n Co nti nued

Flip-Flop Excitation Tables

Derive the excitation tables for the Flip-Flops based on their operations. The SR flip flop is already filled in below. Note the use of don’t cares.

**** Question to keep in mind when working with the following tables: what input to the flop-flop is needed to cause Q to change from a given Present State to desired Next State?

SR (won’t be used in our problems)

q Q S R

0 0 0 X0 1 1 01 0 0 11 1 X 0

D

q Q D

0 00 11 01 1

JK

q Q J K

0 00 11 01 1

T

q Q T

0 00 11 01 1

Page 65


Co un te r D e s i gn Co n t inu e d

Example I. Design a 3-bit binary down counter using ‘T’ flip flops

A. S t at e Di agram :

B. Nex t S t at e Tabl e (hi nt : i f we want t he fli p fl op t o t oggl e what does t he T i nput need t o be)

P.S. N.S.T Inputs

T2 T1 T0000001010011100101110111

C . Karnaugh M aps

q1 q0 q1 q0 q1q0q2 00 01 11 10 q2 00 01 11 10 q2 00 01 11 100 0 01 1 1

T2 = T1 = T0 =

D. Logi c and S el f-C orrecti on C heck (W hy not needed for t hi s ex am pl e? )

Page 66


Co un te r D e s i gn Co n t inu e d

Example II. Design a 3-bit non-binary sequence counter using ‘D’ flip flops to repetitively count in the following sequence: 0-1-2-4-5-6, etc.

A. S t at e Di agram :

B. Nex t S t at e Tabl e:

P.S. N.S.D Inputs

D2 D1 D0000001010011100101110111

C . Karnaugh M aps

q1 q0 q1 q0 q1q0q2 00 01 11 10 q2 00 01 11 10 Q2 00 01 11 100 0 01 1 1

D2 = D1 = D0 =

D. Logi c and S el f-C orrecti on C heck (W hy needed for t hi s ex am pl e? )

Page 67


Coun ter Desi gn Con tinu ed

III. Repeat (II) using JK flip-flops, check for self-correction, and compare your solution with (II):

Recall the Excitation table first (making use of don't cares!):

q Q J K0 00 11 01 1

P.S. N.S.JK Inputs

J2K2 J1K1 J0K0000001010011100101110111

q1 q0 q1 q0 q1 q0q2 00 01 11 10 q2 00 01 11 10 q2 00 01 11 100 0 01 1 1

J 2 = J 1 = J 0 =

q1 q0 q1 q0 q1 q0q2 00 01 11 10 q2 00 01 11 10 q2 00 01 11 100 0 01 1 1

K2 = K1 = K0 =

Page 68


Co unter Desi g n Co nti nued

In-Class Counter Design Problems

Problem: design a three bit up/down binary counter with a mode input such that if M=0 it will count up and if M=1 it will count down.

Design (come up with the input equations) the counter two ways (and check each for self correction) with T flip-flops and with JK flip-flops. Implement (draw the logic) the combinational logic for the T flip-flops two ways: with NANDs and with a decoder.

Page 69


Coun ter Desi gn Con tinu ed

Design a counter with some repeated outputs.1 7 3 1 6 5 3 repeat. (useful in certain control systems applications)

S olu ti on

Notice that the outputs ‘1’ and ‘3’ each occur twice. This will be designed most easily using aMoore machine.

1. Draw a state diagram using letters for the states (making use of Moore notation).

2. Construct a state table showing P.S., N.S. and output

3. Determine the number of flip flops needed based on the number of states and assign binary values to the states using a K-map.

4. Construct a new table (using the binary values for the states) including P.S., N.S., Outputs, and inputs to the flip flops (use JK flip flops)

5. Using K-maps develop the excitation equations and the output equations.

6. If necessary, check for self-correction and draw the logic.

7. Using the table in (4) design with D flip flops and a decoder for the combinational logic. (Why does it make sense to use D’s rather than JK when using the decoder?)

8. Using the logic, show the case of switching from an output of 5 to an output of 3 and distinguish between going from an output of 7 to an output of 3 (in terms of the states of the machine).

It is recommended that you now look at the vhdl examples in the Appendix. These files are called “Up Counter” (up3.vhd) and

“Up/Down Counter”( ud3.vhd)

Page 70


Finite State Machine (FSM) Design Procedure

1. Draw a block diagram showing labeled inputs and outputs.

2. Construct a state diagram and then a state table.

Some degree of minimization is helpful because: more states require more flip-flops and more complex next-state logic. Also PLD's have a limited number of flip-flops. In general less logic means shorter critical timing paths (allowing faster clocks), shorter design times, and less costly manufacturing.

3. Minimize states using state reduction theory. The following three methods of minimizing states are illustrated by examples on the next few pages.

• GROUPING BY CLASS table reduction:

I. Assume F = abc... (a product of all present states)II. Us i ng ou t pu t s , determine the number of classes and separateIII. Within each class, determine next state class for each present stateIV. Create new classes based on III. (be careful not to combine originally different classes;

i.e., different outputs)V. Repeat III and IV until a unique set of classes remains.

• A second method is the IMPLICATION TABLE which is time consuming when done by hand but is efficiently implemented with a computer program.

• A third method is the MERGER DIAGRAM which is particularly useful for incompletely specified tables.

4. Assign binary numbers to each state.• Number of states determines the number of required flip-flops.• Assign in such a way that combinational circuitry is reduced, i f practi cal which is difficult

because of the many possible combinations. But there are some guidelines that may be followed.

5. Decide on the kind of flip-flops to be used.JK is most versatile but D is easiest when not concerned with reduction.

6. From the minimized state table derive minimized equations for all flip-flop excitations and outputs (or use decoder and/or multiplexer).

7. Draw logic diagrams and/or simulate.

Page 71


F S M c o n t inu e d

STATE REDUCTION

Example Using Partitions

Table to be reduced: (a) using Grouping by Class (partitioning)

(b) using an Implication Table

(c) using a Merger DiagramPresent

StateNext State Output

x = 0 x = 1 x = 0 x = 1S0 S3 S1 0 0S1 S4 S0 0 0S2 S6 S5 0 1S3 S0 S3 1 0S4 S0 S3 1 0S5 S2 S1 0 0S6 S0 S4 1 0

(A) Grouping by class (first separate by outputs and then look at next states):

A B C(SO S1 S5)(S2)(S3 S4 S6)

Page 72



(B) Implication Table

S t a t e Re d uc ti o n C o n ti nued

Includes one square for each possible pair of states with rows for all states except first and columns for all states except the last.

1. Fill in x's first (x means a particular pair are not equal)(a) state S2 is different from all others, thus its row and column will be all x's(b) starting w/column S0 see that S0 and S3 are different because outputs are different and soplace an x. Continue checking all boxes.

2. Look for any pairs exactly the same and place a check --(S3,S4)

3. Look for implied pairs(Imply means two states don't go to same next state but equivalent next states- also must have same outputs):

(a) (S0,S1) have same outputs as does each pair of the blank boxes left. Looking at next states ofS0 and S1, we see that if S3 = S4 then S0 = S1 or S3, S4 implies S0,S1.(b) Looking at S1 and S5,we see that if S2 = S4 and S0 = S1, then S1 = S5(c) Fill in remaining blanks with the implications.

4. Check implications(a) x placed in (S0,S5) box because implication (S2,S3) is an x, etc.(b) check placed in (S0,S1) box because S3 = S4.(c) complete the table

5. Draw a merger diagram to assure correct combining of states.

Thus, S0 and S1 are equivalent states. Also S3, S4 and S6 are equivalent to a single state.

S1

S2

S3

S4

S5

S6

S0 S1 S2 S3 S4 S5

Page 73



St a t e Red ucti o n Co nti nued

C. State Reduction using a Merger Diagram for an Incompletely Specified Table

I. Construct a Merger Diagram from the state tableA. Create a circle of dots with one (labeled) dot for each state, then work around circle starting

with state A and all its possibilities (keep in mind outputs must be equal; for example B & C can’t be combined).

B. Draw a solid line between states which are equivalent (unspecified states can be considered as“don’t cares”). For example, A and B in the table below are equivalent states.

C. Draw a broken line between states that have implications and write the implication in parentheses at the brake of the line. For example, A and E will have a broken line and (B,C) will be written in the break.

II. Simplify the Merger DiagramA. Examine the implications as you would in an Implication Table.B. Redraw the diagram with only solid lines (those previously there plus implications that are

compatible). Note that two states joined by a solid line can be replaced by a single state but three states would need three lines and four states would need six (including the diagonals).

III. Rewrite the simplified state table- there may be some “don’t cares” left

Simplify the following table:

N OTE S (1) -/- indicates that the next state and the output are unspecified and considered a “don’t care” (2) notice that there are two inputs- assume x and y

Present State Next State/Output for inputs (XY)XY= 00 01 10 11

A C/0 -/- A/0 -/-B -/- E/0 B/0 D/1C D/0 B/1 -/- -/-D C/0 A/1 E/0 -/-E B/0 -/- A/0 E/1

ME RGE R DIAGRAMS :

Original: Revised:

Page 74


Now, form a new table:FS M con tinu ed

State Assignment Guidelines

Concept: By careful selection of the binary assignments, the 1's in the next-state and output maps will be clustered. Then the functions will be reduced and the combinational logic will be reduced. Note that the assignment maps are only functions of the present state (not of the inputs).

Method

• Chose all zeros, or all ones, for the reset or initial state because it’s easy to force asynchronously

• High Priority: assign as adjacents the present states with same next state for the same input transition [look down a next state column (of a particular input value) for same states and then look back to present states]

• Medium Priority: assign as adjacents the next states of the same present state (look at a present state and then across the row at its next states)

• Low Priority: assign as adjacents the present states having the same output for a given input

Example

1. After drawing the state diagram, use the method just listed to assign binary numbers to the reduced table below (from the implication table example) and implement using D Flip-flops

2. Purposefully assign binary numbers to the state contrary to the results of (1) and implement using Dflip-flops.

3. Compare and contrast the solutions from (1) and (2).

Page 75


Present State Next Statex = 0 x = 1

Outputx = 0 x = 1

a c a 0 0b c d 0 1c a c 1 0d b a 0 0

Page 76


FSM Design Example # 1

Design a state machine such that whenever there is a consecutive occurrence of Input, x, equal to one, the output, y, will be ‘1’ and will reset. Design two ways: (1) as a Moore machine and (2) as a Mealy machine. Compare and contrast the two solutions in terms of the amount of logic and how the output waveforms will differ.

Example:

X 0 1 0 1 1 1 0 1 1Y 0 0 0 0 1 0 0 0 1

1. Moore- using JK with positive edge triggering a. state diagramb. state table & check to see if reducible c. assign binary values to statesd. rewrite state table with binary values and inputs to flip flops e. etc.

2. Mealy- (let output be Z) using JKs with positive edge triggering and an inverter to buffer the clocka. state diagramb. state table & check to see if reducible c. assign binary values to statesd. rewrite state table with binary values and inputs to flip flops e. etc.

clk

X

Q

Y

Q1

Q0

Z

Page 77


FSM Design Example # 2

Design a machine to detect the sequence 1011 and output a one. See the example below.

X 0 1 1 0 1 1 0 1 1 0 1 1Y 0 0 0 0 0 1 0 0 1 0 0 0

1. (Mealy or Moore)a. state diagramb. state table & check to see if reducible c. assign binary values to statesd. rewrite state table with binary values and inputs to flip flops e. etc.

2. (If time allows, complete design using method not employed in 1 and compare)

Page 78


Appendix A, Software Assignment and Four Projects

Pag es

First Software Assignment (PERFORMED INDIVIDUALLY) 79

Project Report Requirements 80

Project 1 (Schematic Capture and VHDL) 81

Typical Project Grading and Typical Table of Contents for Reports 82

Project 2 (Simplification, NAND Implementation, Selected Signal,CASE, Parity, and Redundant Logic) 83 – 84

Project 3 (Adder/Subractor, Controlled Logic, ALU) 85 - 86

Project 4 (Counters, Sequence Detector Moore Machine) 87

Page 79


First Software Assignment

I.A. Install the software on your computer

B. Read and follow directions in Appendix B of the text to create a project for practice

C. (1)Follow all the steps in Appendix B.3 to create and simulate the same function the authors use in the text book, but use Fsss = X1X2 + (X2)′X3, and p r i n t ou t t he l o g i c a nd s im u l a ti on . The sss inFsss are the last three digits of one partner’s 8-digit id number.(2) Also, develop a truth table and show that the simulation agrees with your truth table.

II.A. (1) Using the same approach as in I.C. above, simulate a system having two inputs, A and B, and two outputs, F1sss and F2sss where F1sss = (A + B) ' using a NOR and also F2sss = (A' B') using an and with two inverters. Think of F1 and F2 as a system with two inputs, A and B, and two outputs, F1 and F2. P r i n t ou t t he l o g i c a nd s im u l a t i on.

(2) Also, draw a block diagram for this system.

B. Answer the follow question: Are the outputs F1sss and F2sss the same for a given input? Briefly explain your answer.

NOTES:1. This project does not require all the documentation listed on the next page.2. Al l st udent s do t hi s i ndi vi duall y, not as groups.

Page 80


P r oj ec t ( 1 t h r o u gh 4) R e p o r t R e qui re m e n t s:

• Pages numbered

• Table of Contents

• Table of figures (each appropriately named)

• Introduction, or abstract, Discussion (integrated into report), and Conclusion (on last page)

• Brief description of work distribution between partners

• Everything clearly labeled

• All truth tables, Karnaugh maps (preferably not hand-wrtten), state diagrams and tables

• Clear, hand-written check (in pencil) on computer printouts of the simulation

• Schematics and timing diagrams printed from the computer

• Timing diagrams printed logically - inputs in order on top, outputs beneath the inputs (any waveforms not labeled are useless!)

• All VHDL Files must contain the following comments at the beginning.

- - name1 (ID #xxx-xx-xxx), name2 (ID #xxx-xx-xxx), name3 (ID #xxx-xx-xxx)- - Date- - Project Number and Section

- - space

Page 81


Project 1: Schematic Capture and VHDL Due: Week 5

R e f ere n ce : Section 2.9 and 2.10 and Appendix B, Brown and Vranesic, Fundamentals of DigitalLogic with VHDL Design, McGraw-Hill.

Ob j ect i v e : Students will demonstrate proficiency in designing and simulating simple circuits with appropriate software.

I.A. Review the tutorial in Appendix B.3, “Design Entry Using Schematic Capture”B. Perform the tutorial in Appendix B.4, “Design Entry Using VHDL.” Print out the simulation; but fo r y ou r vhd l si m u l a ti o n u s e Z ss s as t h e ou t pu t v ar i a b l e w h ere ss s are t h e l a s t t h ree d i g it s o f on e p ar t n er ’ s st ud e n t i d nu m b er, t h i s a pp r o ach w il l a ls o b e u s ed i n su b s e qu e n t p r o j ec ts .

II. Given:

Block Diagram:

XFsss

Y

Z

Req uir em ents :3 Inputs labeled as X, Y, Z with X the MSB Active Low Output labeled as FsssO p erati on: The device will output a ‘0’ when X and Y are different (for example, if they are both zero it will output a ‘1’ but if one is zero and the other is one, it will output a zero)

A. Design and simulate using schematic capture. Do not simplify your design- you will be i m p l e m e n ti n g t h e ca non i cal f o r m .B. Simplify your equation from (A) using Boolean Algebra (showing the theorems you used) and check your algebra using a Karnaugh Map. Simulate your new equation using schematic capture.C. Using your equation from (A), create a VHDL file and simulate, but change the output variable to Gttt, where ttt are the last three digits of another partner’s SID.

Notes:1. See project documentation requirements on previous page.2. The next page shows how this project will be graded (note the check countstowards the simulation part of the grade!).

Page 82


Typical Project Grading (PROJECT 1)

ecet 365Project 1

Name(s)

T of C &T of F 5Pages #’d 5Abstract 10Discussion 10Conclusion 10Spelling/Grammar 10Work distribution 10

I (B)VHDL code 15

Simulation 15 (Label/order/correct)

IITruth Table 10

Equations 10

Logic & Simulations 20

VHDL & Simulation 20

E.C.Total: 150

Typical Table of Contents (Using Project 1 as an example)

PageIntroduction …………………………... 3Part I.B, vhdl of Appendix B.4……… 3

Simulation of I.B…………... 4Part II., Truth table and equation…… 5

Logic for II A ……………… 6Simulation for II A…………. 6 vhdl for II B………………… 7Simulation for II B…………. 7

Work Distribution…………………….. 8Conclusion…………………………….. 9

List of FiguresFig. I.1 Simulation of B.4…………… 4Fig. II.1 Logic for II A……………… 6Fig. II.2 Simulation for II.A………… 6Fig. II.3 Simulation for II B………… 7

Page 83


Project 2: Simplification, NAND Implementation, Selected Signal, CASE, Parity, and Redundant Logic

Objective: Students will learn and verify knowledge of the basic operations of a digital CAD system. They will demonstrate an ability to design, simplify, implement and simulate simple combinational circuits. Included will be the use of schematic capture and vhdl and the introduction of selected signal assignment, CASE and concatenation in a vhdl file.

Block Diagram for parts I and II (think of this system as one large circuit with four inputs and two outputs):

AB F1

CD F2

I. Given: F1sss (A,B,C,D) = Σ m(0,4,6,12,14) + Σd(5,8) andF2ttt (A,B,C,D) = Σ m(1,3,4,6,9,12,14) + Σd(10,11)

Simplify using K-maps, implement minimally (sh ar i ng g a t e s wh er e poss i b l e ), using only NAND gates and inverters, and simulate. Hint: you should only need 2-input NANDs plus inverters. Implement with schematic capture and simulate.

II.

A. Repeat (I) in vhdl using Selected Signal Assignment. Include an internal signal, called ABCD, by concatenating A with B with C with D. See Part III, vhdl Examples section of these notes for help.

B. Once you have successfully compiled, print out the equations that Quartus II generates for F1sss and F2ttt. The symbols for the operators used by the software are as follows: & = AND, ! = NOT, # = OR, and $ = XOR. I n y our re po r t show t h e se e qu a ti ons a nd, us i ng B oo l ea n a l g e b ra , show how t h e y ar e e qu i v a l e n t t o t he e qu a ti ons y ou d e v e l op e d i n p ar t I .

• In version 8, in order to obtain the equations files when you compile: click on Tools Options General Processing Automatically generate equation files during compilation. TheAnalysis & Synthesis and Filter Compilation reports will have a section referring to theseseparate files.

• An alternative approach is to go to Processing Start Start Equation Writer (Post-Synthesis), Wait for Quartus to finish generating the equation, then go to File Open and select file with “map.eqn: extension (be sure the Types is set to All Files). The equation will open as a text file.

PROJECT 2 CONTINUED ON NEXT PAGE

Page 84


Project 2 Continued

III.(a.) Design a redundant combinational circuit (as shown below having inputs R, S, T and outputs Rx, Sx,Tx, P1, P2) to generate ODD parity (Ex. If the input is even parity the parity bit will be 1 but if the inputis odd parity the parity bit must be 0). The five bit number LxMxNxP1P2 will sometimes have evenparity but the four bit numbers RxSxTxP1 and RxSxTxP2 must each always be odd parity. Implementand simulate with redundant circuits: (1) with NOR (you’ll need a product-of-sums expression) logicand the other (2) with exclusive-or gate and possibly one exclusive-nor gate. There will be three DATAbits at the input and the output will be five bits, including the two parity bits, which should always beequal.

(b.) Use VHDL code employing C AS E wit hi n a PR OC ES S for P1 only- no need to implement P2. SeePart III, vhdl Examples section of these notes for an example using CASE. Compare your results.

Block Diagram for Part III:

R

S NOR logicT

XOR logic

RX SX TX

P1

P2

E xtra Cred i t (on l y f or rep orts sub mi tted on ti me):Repeat part I using a 4:16 decoder with external gates.

Page 85


Project 3: Adder/Subractor, Controlled Logic, and ALU

Objective: Students will learn how to design arithmetic logic using knowledge gained in ECET 365 lectures and independent research. Through using simulation software they will be able to draw and simulate their designs and also develop and save their own devices to be used as building blocks in more sophisticated designs.

Problem Statement: The ultimate goals of this project are to: (1) Design and test an adder/subtractor(2) Develop combinational logic using multiplexers(3) Build larger circuits from previously designed logic

I. Design and simulate a Full Adder circuit using minimal NOR gates for the carry out and XOR gates for the sum. Use x, y, cin for the inputs, Ssss and Cttt for the outputs and use the file name ADDsss. Under file select ‘Create Symbol Files for Current File.’ Then simulate it again using the default symbol. Be sure to show (a) truth table, (b) Karnaugh maps, (c) Boolean algebra, (d) final equations used in your solution, and (e) the symbol for ADDsss (find in the directory as addsss.bsf). These details may vary slightly based on what version of Quartus II you are using.

II. Creating a four bit adder/subtractor (hint: see section 5.3.3 in Brown/Vranesic text and logic on page40 of these notes):

A. Design and test a four-bit adder/subtractor employing ADDsss from I as a component (pasteinto your graphical design file by right clicking on screen and selecting “Enter Symbol …).

B. Using four instantiations of ADDsss with XORs, and inverters, create, test and save a new device called ADDSUBsss. If you like, you may want to create an intermediary device that is just a four-bit adder. Print the symbol for ADDSUBsss.

4A

Sum4 M(ode) Sum

4B

1 A + B

C 0 A - B

M

From the diagram, you can see there are 9 inputs and 5 outputs.NOTE: with mode=1, your logic must add and with mode=0, it must subtract!

PROJECT 3 CONTINUED ON NEXT PAGE

Page 86


+Project 3 Continued

P art II conti nuedDo not try to simulate all possible input combinations (there would be 29 = 512 possibilities!) but thefollowing six operations with signed numbers must be shown, g r oup i ng t he s e t s of b it s so t h e y ar e rea d a b l e a s h e x i n y our s im u l a ti on , in your printout to prove that your logic simulates properly with thefirst number A and the second number B. A l l s i x ca s e s m us t be p r i n t e d on on l y one p a g e , no t s i x p a g e s .Include the following table in your report. Perform operations indicated; e.g. the first operation is 6 plus and -3, not 6 minus + 3.

OperationResults

OperationResults

ExpectedAnswer (Dec.)

Test Result(Binary)

ExpectedAnswer (Dec.)

Test Result(Binary)

6 + (-3) -4 – 77 + 4 0 – (-5)7 – 4 6 – 8

Q1: For an eight bit machine, the limits of signed numbers are -128 through + 127. What are the limits for signed numbers a n d unsigned numbers for the four-bit adder/subtractor you just designed?

Q2: Which operations in the above table produce incorrect results and why? Make use of your answer for Q1.

III. Given the following f un ct i on t a bl e for a simple ALU device (where A and B are binary inputs, C1 and C0 are control inputs and F1 and F2 are outputs):

C1 C0 F1 sss F2ttt0 0 A B (A B)′0 1 A+ B (A+B)′1 0 A⊕B (A⊕B)′1 1 A plus B A minus B

A. Draw a block diagram and then create a truth table from the function table (Hint: design your truth table in the order: C1 C0 A B F1sss F2ttt)B. Implement and Simulate part A with two 8:1 multiplexers. (Hint: C is the MSB in the 81mux and for the 74151 chip- you can use either.)C. Implement and Simulate part A using a decoder (check what is the MSB in the decoder you use) and any other gates necessary. Instead of F1 and F2, use Msss and Nttt as your outputs.

IV. Your Brown/Vranesic text provides possible vhdl code in Figure 6.48 for the 74381 ALU chip.A. Draw a block diagram for Figure 6.48B. Implement and simulate the code in your software. Show all functions for Table 6.1 in the

text using A = 0171, B = 1001 in the simulation and show a check that your results arecorrect.

C. Revise (A) in a new file as follows: change the data input words to 8 bits, which shouldrequire only changing a few lines of code! Test using A = 0FH , B = EFH.

D. What are the limits for signed and unsigned numbers of the new device in part C?

D o c u me n t a ti on: Follow usual report requirements at beginning of this section, Plus and be sure to

respond to any questions given in the procedure.

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Project 4: Counters and a Sequence Detector Using a Moore Machine

I. Design and simulate a modulus-9 (it will count from 1 to 9) up-counter t w o w a y s as follows:1. Using an available up/down binary counter (from the software library- suggestion: 74192 or 74193)

with parallel load and any necessary gates labeling the outputs as Q3 through Q0 (LSB). {Hi n ts : (1) it is critical to know what is the MSB for a particular counter (for example the 74192 chip has ‘D’ as the MSB). (2) In the74192, the LD and CLR inputs are both asynchronous and (3) whichever clock input is not being used must betied high.}

2. Using VHDL. See Part III, vhdl Examples section, of these notes for help.

Q u esti on: If the input clock has a frequency of 1 MHz, what will be the frequency of the MSB of the counter?

II. Using JK flip flops, design and simulate a counter, which will count through the eight digits of one partner’s student ID number. Design as a Moore machine. Be sure to show your binary assignments.

III. Design and simulate a t h ree - b i t up/down counter to the specifications of the following function table. Use D flip-flops a nd use a decoder for the combinational logic. The key to this problem is a correct, carefully constructed, state table.

Inputs OperationClr M

0 X clear all flip flops1 1 count UP in Gray code1 0 count DOWN in Gray code

N o tes : 1. There is an asynchronous clear that can be implemented easily without being part of the formal design.2. You may wish to research the Gray code. When counting in Gray only one bit changes at a time.

Hint: Counting up: 000→ 001 → 011, etc. Counting do w n: 100 →101 → 111, etc.

M A

B

CLR

IV. A. Design a Moore machine, and simulate the sequential logic which will detect the sequence ‘1101’ and output a ‘1’. Be sure to show state reduction and your binary assignments. In your simulation show the sequence:001110101100100, which should output a ‘1’ once.

B. Repeat part A using vhdl.

Do c u m e n t a t i o n : This is an informal report, but be sure to include: all block diagrams; state diagrams;state tables; Equations and K-maps where needed; and answers to any questions.

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Appendix B, VHDL Examples

Topic Page

A Simple VHDL Example 89

Selected Signal Assignment to Generate Combinational Logic 90

Comparator 91

Combinational Logic Using Internal Signal and Concatenation 92

CASE Assignment within a Process to Generate Combinational Logic 93

Components, Instantiation, and Structure 94

Up Counter 95

Up/Down counter 96

‘101’ Sequence Detector using a Moore machine 97

‘101’ Sequence Detector using a Mealy machine 98

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A Simple VHDL Example

Declares code will use ieee library.

Tells the VHDL compiler to use the file defining std. logic (part of ieee library).

LIBRARY ieee;

USE ieee.std_logic_1164.all;

Comment. -- 3-input majority circuit with active low output

ENTITY majority ISThis construct is used to declare the I/O signals. Filename must be same as entity (in this case majority).

PORT (a,b,c: IN STD_LOGIC;f: OUT STD_LOGIC);

END majority;

This construct is used to specifythe circuit's functionality- in termsof structure, or data flow, orbehavior. *

ARCHITECTURE arch1 OF majority IS BEGIN

f <= (NOT a AND NOT b) OR (NOT b AND NOT c) OR (NOT a AND NOT c);

END arch1;

Assignment statement

*See table on page 20

Notes:1. Signal names must begin with a letter and may not be VHDL keywords.

2. Keywords are capitalized by convention; however, VHDL is not case sensitive.

3. ENTITY and ARCHITECTURE must both be given names (in this case majority and arch1). The f il e n a m e m us t be t he s a m e a s t he En tit y n a m e .

4. Comments start with '--'.

5. STD_LOGIC includes 0, 1, Z, - where 'Z' is high impedance (a tri-state condition) and '-' is don't care.

6. VHDL does not assume any precedence of logic operators. Therefore, parentheses should be used. For example, f <= ( ) OR ( ) OR ( ).

7. A little history: Initially the two main purposes for VHDL were its use as a documentation language for complex circuits and its use for modeling behavior of digital logic. Now it is a very popular CAD tool for design. The first standard, IEEE 1076, was effected in 1976 and then revised as IEEE 1164 in1993.

E x erc i s e :

1. Draw a block diagram showing inputs and outputs for the VHDL code above.2. Draw the logic gates for the VHDL code above.3. Using a truth table, show that the output will be a zero when at least two of the inputs are one.

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Combinational logic in vhdl using Selected Sig na l Ass ig nment

--selectex.vhd to implement F1 = m(0,1,2,5,7) and F2 = m(0,5,6)-- Illustrates use of:

-- selected signal assignment for combinational logic (note punctuation)-- vectors-- specifying single and multiple bits with ' and '', respectively

LIBRARY ieee;USE ieee.std_logic_1164.all;

ENTITY selectex ISPORT ( w : IN STD_LOGIC_VECTOR(2 DOWNTO 0); -- 3 bit vector

f1, f2 : OUT STD_LOGIC);END selectex;

ARCHITECTURE behavior OF selectex IS BEGIN

WITH w SELECTf1 <= '0' WHEN "011", -- Single and Multiple Bit Delimiting

'0' WHEN "100",'0' WHEN "110",'1' WHEN OTHERS; -- Note use of OTHERS

WITH w SELECTf2 <= '1' WHEN "000",

'1' WHEN "101",'1' WHEN "110",'0' WHEN OTHERS;

END behavior;

N o te s on t he w av e f o rms : To set up count in hex: right click on node, select ‘overwrite’, then ‘count value’ To ungroup vector: right click on node, select ‘ungroup’

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Comparator using vhdl(See Combinational logic section for design using gates, page 41)

LIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_unsigned.all; -- allows use of arithmetic statements (in this case < , >, =)

ENTITY comparator ISPORT (A,B : IN STD_LOGIC_VECTOR(3 DOWNTO 0);

AeqB, AgtB, AltB : OUT STD_LOGIC);END comparator;

ARCHITECTURE Behavior OF comparator IS BEGIN

AeqB <= ‘1’ WHEN A = B ELSE ‘0’; AgtB <= ‘1’ WHEN A > B ELSE ‘0’; AltB <= ‘1’ WHEN A < B ELSE ‘0’;

END Behavior;

Page 92

( A, B, C : IN STD_LOGIC;P : OUT STD_LOGIC) ;

END comb_sel;


-- VHDL Combinational Logic W/ I nterna l Si g na l , Co nca tena ti o n, & Sel ected Si g na l

-- generates odd parity as an example of using selected signal assignment-- Note:-- use of an internal signal, S-- concatenation of signals to create S-- use of 'others'-- a single bit is delimited with ' and multiple bits with "


ENTITY comb_sel IS PORT

ARCHITECTURE arc OF comb_sel IS

SIGNAL S : STD_LOGIC_VECTOR (2 DOWNTO 0); --Defining an internal signal

BEGINS <= A & B & C; --Concatenation

WITH S SELECTP <= '1' WHEN "000", --Single and multiple bit delimiting

'1' WHEN "011",'1' WHEN "101",'1' WHEN "110",'0' WHEN OTHERS;

END arc;

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-- CA SE A ssi g n m ent w i th i n a P r o ce s s to Generate Combinational Logic

-- Creates odd and even parity-- CASE must be used within a Process, which allows for sequential assignment statements-- (those in which the ordering of the statements may affect the meaning of the code)-- note the keywords and punctuation within the case which is inside the process


ENTITY comb_case ISPORT ( a,b,c : IN STD_LOGIC ;

pe, po : OUT STD_LOGIC ); END comb_case;

ARCHITECTURE arc OF comb_case ISSIGNAL s: STD_LOGIC_VECTOR (2 DOWNTO 0);

BEGINs <= a & b & c; -- create s by concatentationPROCESS (s) -- Sensitivity List, if s changes then process startsBEGIN

CASE s IS -- Make S the selection signalWHEN "000" => -- if s = 000, (note use of =>)

po <= '1'; -- then po = 1 and pe = 0pe <= '0';

WHEN "011" =>po <= '1';pe <= '0';

WHEN "101" =>po <= '1';pe <= '0';

WHEN "110" =>po <= '1';pe <= '0';

WHEN OTHERS =>po <= '0';pe <= '1';

END CASE; -- note we need three ENDsEND PROCESS;

END arc;

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Co mpo nents , I ns ta nti a ti o n, a nd Structure

• vhd l f or a f u l l add er:

LIBRARY ieee;USE ieee.std_logic_1164.all; ENTITY fladr IS

PORT (Ci, x, y : IN STD_LOGIC; S, Co : OUT STD_LOGIC);

END fladr;

ARCHITECTURE arc OF fladr IS BEGIN

S <= x XOR y XOR Ci;Co <= (x AND y) OR (Ci AND x) OR (Ci AND y);

END arc;

• Vhd l f or 4 b i t add er u si n g f l ad r as a comp on en t (as su mi n g f l ad r i s avail abl e)

LIBRARY ieee;USE ieee.std_logic_1164.all; ENTITY adr4bit IS

PORT (Cin, x3, x2, x1, x0, y3, y2, y1, y0 : IN STD_LOGIC;s3, s2, s1, s0, Cout : OUT STD_LOGIC);

END adr4bit;

ARCHITECTURE structure OF adr4bit ISSIGNAL c1, c2, c3, : STD_LOGIC; -- define internal signalsCOMPONENT fladr -- declare intention to use fladr as component

PORT ( Ci, x, y : IN STD_LOGIC;s, Co : OUT STD_LOGIC);

END COMPONENT;

BEGIN-- four instantiations of the Component fldr-- format used as follows:-- Instance Name: Component Name PORT MAP( I/O using positional association )

bit0: fladr PORT MAP ( Cin, x0, y0, s0, c1); bit1: fladr PORT MAP ( c1, x1, y1, s1, c2); bit2: fladr PORT MAP ( c2, x2, y2, s2, c3); bit3: fladr PORT MAP ( c3, x3, y3, s3, Cout); END structure;

T o und er s t a n d t h e a b ove f il e s, d r aw t h e l og i c f or f l adr a n d s tr u ct u re / b l o c k d i ag r am of adr4b it , b ei n g caref u l w i th si gn al l ab el s

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-- Up Counter-- file: up3.vhd name: wb-- date: 11/03, rev’d. 11/07,11/10-- brief description: Simple 3-bit Up Counter w/asynchronous clear and Count Enable

LIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_unsigned.all; -- allows use of arithmetic statements (previously used in ALU)---- RECALL: OR is used for ORing, thus + can be used for addition or incrementing (line 7 below)--ENTITY up3 IS

PORT (clrn : IN STD_LOGIC; --active low/asynch. clearce, clk : IN STD_LOGIC; --Count Enable and Pos. Edge clockcount : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)); - -3-bit count values

END up3;

ARCHITECTURE Behavior OF up3 ISSIGNAL q : STD_LOGIC_VECTOR (2 DOWNTO 0) ; -- Use For State Of Machine

BEGINPROCESS (clk, clrn) -- recall: any signal changing in sensitivity list starts process (1) BEGIN (2) IF clrn = '0' THEN -- active low asynch. Clear (3)

q <= "000"; --if here, basic IF was satisfied (4)ELSIF (clk'EVENT AND clk = '1') THEN -- attribute ‘EVENT added to variable clk (5)

-- and test for ‘1’ : thus, pos. edgeIF ce = '1' THEN (6)

q <= q + 1; -- increment state if ce is 1 at clock edge (7) END IF; (8)

END IF; (9) END PROCESS; (10) count <= q; -- assign state value to count output signal (11)

END Behavior;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -A l go rit hm f or c oun ter :

If clk or clrn is active, enter the process: 1 2If asynchronous clear is active, then set state to 0 and exit the process: 3 10 (won’t do ‘else’) Otherwise (else), if a positive edge a nd if CE =1, increment state: 5 6 7 8 9 10

Otherwise (CE not 1, don’t do increment (7): 5 6 8 9 10Exit Process

Set count (output) equal to state internal signal (11)

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-- Up/Down counter, Enhances Up Counter on previous page-- (ud = 0, count down; ud=1, count up)-- file: ud3.vhd name: wb-- date: 11/03, rev’d. 11/07, 4/10-- brief description: 3-bit up counter MODIFIED TO BE UP/DN

LIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_unsigned.all; -- allows use of arithmetic statements (increment or decrement)

ENTITY ud3 ISPORT (clrn, ce, clk, ud : IN STD_LOGIC; -- ud is new

count : OUT STD_LOGIC_VECTOR(2 DOWNTO 0));END ud3;

ARCHITECTURE Behavior OF ud3 ISSIGNAL q : STD_LOGIC_VECTOR (2 DOWNTO 0) ; -- state of the machine

BEGINPROCESS (clk, clrn) BEGINIF clrn = '0' THEN -- active low asynch. clear

q <= "000";ELSIF (clk'EVENT AND clk = '1') THEN -- testing for ‘1’ : pos. edge

IF ce = '1' AND ud = '1' THENq <= q + 1; -- count up if ce = 1 and ud are 1

ELSIF ce = '1' AND ud = '0' THENq <= q - 1; -- count down if ce = 1 and ud is 0

END IF; END IF;END PROCESS;count <= q; -- assign state value to count output signal

END Behavior;

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-- 101 Detector using a Moore machine-- State Diagram is developed first but rest will be taken care of by the software-- Note: First use of TYPE to create a new signal type, which must be carefully definedLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;

ENTITY moore101 ISPORT (clk, x, resetn : IN STD_LOGIC;

y : OUT STD_LOGIC ); END moore101;

ARCHITECTURE arc OF moore101 ISTYPE state IS (a, b, c, d); -- enumerate type by giving all its possible values, names,

-- (in this case a,b,c,d) letting software handle binary valuesSIGNAL q: state; --Now define internal signal q as type state

BEGINPROCESS (resetn, clk) BEGIN

IF resetn = '0' THEN -- Asynchronous Resetq <= a; -- making 'a' the reset state

ELSIF (clk'EVENT AND clk = '0') THEN -- neg. edge triggeringCASE q IS -- using state as selection signal

WHEN a =>IF x = '0' THEN

q <= a; -- if state is 'a' and x is 0, then stays at 'a'ELSE q <= b; -- but if x is 1, then goes to'b'END IF;

WHEN b =>IF x = '0' THEN

q <= c; ELSE q <= b; END IF;

WHEN c =>IF x = '0' THEN

q <= a; ELSE q <= d; END IF;

WHEN d =>IF x = '0' THEN

q <= a; -- ResetELSE q <= b; END IF;

END CASE; END IF;

END PROCESS;

y <= '1' WHEN q = d ELSE '0'; -- output is 1 only for state 'd'

END arc;

**DRAW BLOCK AND STATE DI AGRAM S

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-- ‘101’ Detector using a Mealy machine-- State Diagram is developed first but rest will be taken care of by the software

LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;

ENTITY mealy101 ISPORT (clk, x, resetn : IN STD_LOGIC;

y : OUT STD_LOGIC ); END mealy101;

ARCHITECTURE arc OF mealy101 ISTYPE state IS (a, b, c); -- same as last example (moore101) at this pointSIGNAL q: state;

BEGINPROCESS (resetn, clk) BEGIN

IF resetn = '0' THEN -- Asynchronous Resetq <= a; -- making 'a' the reset state

ELSIF (clk'EVENT AND clk = '0') THEN -- neg. edge triggeringCASE q IS -- using state as selection signal

WHEN a =>IF x = '0' THEN

q <= a; -- if state is a and x is 0, then stays at aELSE q <= b; -- but if x is 1, then goes to bEND IF;

WHEN b =>IF x = '0' THEN

q <= c; ELSE q <= b; END IF;

WHEN c =>IF x = '0' THEN

q <= a; ELSE q <= b; END IF;

END CASE; END IF;

END PROCESS;

PROCESS (q, x) -- needed for Mealy machine, testing if x changes w/o clk edgeBEGIN

CASE q ISWHEN a => y <= '0'; -- if state is a, and x = 0, then y = 0 regardless of xWHEN b => y <= '0'; -- same with state bWHEN c => y <= x; -- at state c, if x=0, then y =0, but x=1 yields y =1

END CASE; END PROCESS;

END arc;

**DRAW BLOCK AND STATE DI AGRAM S

Page 99


Appendix C, Forms

for reporting Journal Article and attendance at a Professional Society Meeting

(Registered students will receive an electronic version of these forms to be submitted via email.)

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Report on Attendance at Professional Society Meeting, Complete all sections and submit via email

Your Name:Date and Time of Event:

Location:Professional Society:

Approx. Number of attendees:Presentation Topic:

Presenter and his/her background:

Summary of presentation:

Page 101


Technical Journal Article Report, Complete all sections and submit via email

Your Name:Journal:Date of Issue:Pages:Title of Article:Author:Why you chose this article:

Summary of Important Points including a societal issue as discussed above):

Article’s Discussion of Societal Effects and Your Thoughts on this:

References Given for Further Research:

What you liked and didn’t like about the article:

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NOTES:

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Documents

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