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Wide division ratio range programmablefrequency divider with close-to-50%output duty-cycleJianhui Wu a , Shengyang Wang a & Fuqing Huang aa National ASIC System Engineering Research Center, SoutheastUniversity , Nanjing 210096, ChinaPublished online: 24 Aug 2011.

To cite this article: Jianhui Wu , Shengyang Wang & Fuqing Huang (2011) Wide division ratio rangeprogrammable frequency divider with close-to-50% output duty-cycle, International Journal ofElectronics, 98:9, 1239-1246, DOI: 10.1080/00207217.2011.593145

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International Journal of ElectronicsVol. 98, No. 9, September 2011, 1239–1246

Wide division ratio range programmable frequency divider with

close-to-50% output duty-cycle

Jianhui Wu*, Shengyang Wang and Fuqing Huang

National ASIC System Engineering Research Center, Southeast University,Nanjing 210096, China

(Received 28 July 2010; final version received 17 May 2011)

A novel wide division ratio (DR) range programmable frequency divider ispresented in this article, which is based on the proposed divide-by-2/3/4 cell. Thedivider’s output is buffered by a divide-by-2 cell; hence, it can achieve the close-to-50% output duty-cycle. The DRs can be set via the convenient provisions ofbinary bits. When the DR is even, the output duty-cycle is exactly 50%. If the DRis odd, the output duty-cycle is k/(2 kþ 1), where k is a natural number, therefore,it becomes close-to-50% with an increasing k. A divider with eight DR controlbits, which can realise the DRs from 8 to 511, is implemented in standard 0.18mmcomplementary metal-oxide semiconductor technology, the die area is 0.02mm2.The measured results show that the divider can obtain 44.4–50% output duty-cycle which corroborates with the calculation.

Keywords: programmable frequency divider; divide-by-2/3/4 cell; division ratio;duty-cycle

1. Introduction

In recent years, considerable research has been conducted on the high-performanceprogrammable frequency dividers design (Jan and Michiel 1996; Krishnapura and Kinget2000; Vaucher, Locher, Sedvallson, Voegeli, and Wang 2000; Lo and Luong 2002;Romano, Levantino, Pellerano, Samori, and Lacaita 2002; Fahim and Elmasry 2003; Shu,Edgar, Jose, and Embabi 2003; Yang, Yu, Liu, Wang, and Lu 2006; Zhang, Islam, andHaider 2007). However, most of them are focused on the applications in radio frequency(RF)-integrated circuits, mainly the usage in phase locked loops (PLLs) which generate thelocal oscillating signals. In this case, since the phase and frequency detector (PFD) isgenerally edge triggered, high-operating frequencies, wide division ratio range, binary DRcontrols and low-power consumption are the main desirable features of the divider withregardless of the duty-cycle. But, when the divider is used to generate the variable clocksignals, such as for switched-capacitor filters (SCFs), digital systems with different power-states (Zhang et al. 2007) and the recently presented low-noise complementary metal-oxidesemiconductor (CMOS) harmonic oscillator (CHO) system (Michael et al. 2007;McCorquodale et al. 2008), which is expected as the replacement of the crystal oscillators(XOs), the 50% duty-cycle becomes to be the most desirable feature.

*Corresponding author. Email: wjh@seu.edu.cn

ISSN 0020–7217 print/ISSN 1362–3060 online

� 2011 Taylor & Francis

DOI: 10.1080/00207217.2011.593145

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In this article, a programmable divider with close-to-50% output duty-cycle for anyDR is presented. The following section describes the systematic solution. Section 3 ismainly about the architecture of the proposed divider and the operation principle. Finally,Sections 4 and 5 give the measured results and conclusions, respectively.

2. Prior art and the proposed solution

A published work proposed by Zhang et al. has illustrated the architecture of theprogrammable frequency divider with close-to-50% output duty-cycle. It made a deepprogress based on the original structure (Vaucher et al. 2000), which had given muchelicitation in the design of the high-performance frequency divider. However, it combinedtwo solutions to obtain the close-to-50% output duty-cycle, and added too manyadditional logic gates. This may reduce the divider’s flexibility and require muchadditional layout effort.

As we all know, it is easy to obtain the 50% output duty-cycle for the even DRs. Therealisation is using a divide-by-2 cell to buffer the output of the divider core which candivide the input signal at any DR. So, the difficulties will be coming up only when thedivider operates at the odd DRs.

The simple way to resolve the problem mentioned-above is by designing a divider with0.5 DR step size. Then, the 50% duty-cycle can be easily achieved after a divide-by-2 cell.To the best of our knowledge, the sub-integer divider is designed either based on a 1/1.5divider cell (Yang et al. 2006) or using phase-switching technique (Jan and Michiel 1996;Krishnapura and Kinget 2000; Lo and Luong 2002; Fahim and Elmasry 2003; Shu et al.2003). The single 1/1.5 divider cell (Yang et al. 2006) mainly contains two multiplexers andfour D-latches, which consumes 1.5 times of the current of the first 2/3 stage. Hence, itgreatly increases the power consumption almost by 75%. For the low-power phase-switching technique (Jan and Michiel 1996; Krishnapura and Kinget 2000; Lo and Luong2002; Fahim and Elmasry 2003; Shu et al. 2003), it only forms the dual-modulus pre-scaler, therefore, two extra digital counters needed to be designed to broaden the DRrange. These may reduce the divider’s reusability and flexibility (Vaucher et al. 2000).

Here, we propose a smart way to mitigate the problem when the divider operates at theodd DRs. First, we set the output that is buffered by a divide-by-2 cell. For even DRs, theoutput duty-cycle is exactly 50%. As to odd DR 2mþ 1, where m is a natural number, wecan set that half of the output period contains m/mþ 1 input periods, and the other halfperiod of the output signal equals mþ 1/m input periods. Then the output duty-cycle canbe easily obtained

Duty cycle ¼m

2mþ 1or

mþ 1

2mþ 1ð1Þ

From the Equation (1), the output duty-cycle will become closer-to-50% withincreasing m, therefore the increasing DR.

3. The proposed divider architecture

Based on the analysis in the above section, the proposed structure of the programmablefrequency divider can be constructed. It mainly contains a divider core similar to thestructure cascaded the 2/3 divider cells which is presented in Vaucher et al. (2000) and

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a divide-by-2 cell adopted as a buffer which gives the divider’s output. For the even DRs,

the divider in Vaucher et al. (2000) can be directly used as the divider core. For the oddDRs, the divider core must operate between two modes divide-by-k/kþ 1, the switching

process can be easily enabled by the output signal.Here, a design issue should be addressed. If k is an even, then the first 2/3 stage of the

divider core is working at divide-by-2 mode. Hence, when the divider core needs to switchto divide-by-kþ 1 mode, we can only change the first 2/3 stage into divide-by-3 mode

correspondingly. It is apparently that if the first 2/3 stage already works at the divide-by-3

mode (k is odd), then how to achieve the other divide-by-kþ 1 mode. There are two waysto realise: one way is simply changing the whole DR of the divider core. But it will affect

too many binary DR control bits, which results in the complicated timing issue. The other

way, also the proposed method is adding an extra mode divide-by-4 to the first 2/3 stage,then it turns to be a divide-by-2/3/4 cell. The choice of designing a divide-by-2/3/4 cell is

that the 2/3 cell is mainly composed of two D flip-flops (DFFs), by which the maximum

DR can be achieved is 4. It will be more convenient to achieve the goal. Details of thedesign of the divide-by-2/3/4 cell are discussed below.

3.1. Divide-by-2/3/4 cell

The proposed divide-by-2/3/4 cell is a modification to the 2/3 cell presented in

McCorquodale et al. (2008), which is shown in Figure 1. When the modulus controlMC is high, the divide-by-2/3 block always divides by 2. That is, the output from the left

DFF is isolated, and the block works just as a divide-by-2 cell. If the modulus control MC

is low, the divide-by-2/3 cell operates at the division factor of 3.From Figure 1, we can see that there are two DFFs in the divide-by-2/3 cell.

Consequently, the maximum DR should be 4, it can be extended simply by adding a

control signal to cut-off the feeding back path to the AND gate. But when the dividingmodes are extended to 3, it needs at least two enabled signals to fully represent all the

situations. Here, we call them the DR control bits P0, P1. Due to that the divider cell

operates at the divide-by-3/4 only once during the whole output period of the divider core,a pulse as the enabled signal is needed to switch the dividing mode. Fortunately, the

Modout signal (M1) from the subsequent 2/3 cell is suitable, it is the same as the cascaded

2/3 cells structure (Vaucher et al. 2000). Moreover, the divider’s output signal should befed back as an extra control signal which has been discussed before, it is named M2.

The divide-by-2/3/4 cell is shown in Figure 2, all the control signals are used to enable

the divide-by-2/3/4 cell swallow proper signal at proper time. To reduce the propagation

delay, the logic gates are combined together as possible, which are shown in dashed frame

Figure 1. Architecture of the divide-by-2/3 block in McCorquodale et al. (2008).

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in Figure 2. The details of the operating principle will be illustrated in the following

section.

3.2. The whole divider structure

The novel divider is depicted in Figure 3. It consists of a divide-by-2/3/4 cell followed bythe 2/3 cells. Here, the logic implementation of the cascaded 2/3 cells can be referred toVaucher et al. (2000). The output is taken from a DFF output, which feeds back the

inversed output signal to the input D to form a divide-by-2 block, which is triggered by theMo signal of the second stage. This ensures the output duty-cycle close-to-50%, and

Figure 2. The proposed divide-by-2/3/4 cell.

Figure 3. The proposed frequency divider.

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obtains the desirable feature of low jitter. Besides, it should be noted that the divide-by-

2 cell is triggered by the negative-edge signal. This eliminates the potential glitches in 2/3/4

divider cell. Also, the divide-by-2 block can be triggered by the Mo signal from other

proper stage, but the jitter would be accumulated with the number of the stage increased.The first stage divide-by-2/3/4 cell’s modulus control M1 is connected to the second

stage’s Mo, and M2 is directly connected with the reversed signal of the divider’s output, as

shown in Figure 3. Both of them are used to switch the divider’s operation mode together

with binary DR control bits P1, P0, which are listed below.When P1P0¼ 00, the divide-by-2/3/4 cell only works as a divide-by-2 cell, has nothing

to do with the two modulus controls M1 and M2.When P1P0¼ 01, the divide-by-2/3/4 cell will swallow one extra period of the input

signal within a complete output period, which means the divider cell operates at divide-by-

3 mode once of a complete output period. This is enabled by the both modulus controls

M1 and M2 become high.When P1P0¼ 10, the divide-by-2/3/4 cell will swallow one extra period of the input

signal during half of the output period, which means the divider cell operates at divide-by-

3 mode twice of a complete output period. This is enabled by the modulus control M1

becomes high.As for the last situation P1P0¼ 11, the divide-by-2/3/4 cell will be forced into divide-

by-3 mode once at one half of the output period, and divide-by-4 mode once at the other

half of the output period. The former is enabled byM1 becomes high andM2 becomes low,

the later occurs when both of them are high.It is similar to the operation of the simple 2/3 cell, only the working states are doubled.

For more clearly understanding, the transient simulation results have been shown in

Figure 4.Based on the analysis above, we can calculate the DR achieved by the binary bits

P0, . . . ,Pn as follows:when P1P0¼ 00,

DR0 ¼ 2 � ð2 � P2 þ � � � þ 2n�1 � PnÞ ¼ 22 � P2 þ � � � þ 2n � Pn ð2aÞ

If P1P0¼ 01,

DR1 ¼ 2 � ð2 � P2 þ � � � þ 2n�1 � PnÞ þ 1 ¼ 1þ 22 � P2 þ � � � þ 2n � Pn ð2bÞ

If P1P0¼ 10,

DR2 ¼ 2 � ð1þ 2 � P2 þ � � � þ 2n�1 � PnÞ ¼ 2þ 22 � P2 þ � � � þ 2n � Pn ð2cÞ

Otherwise, P1P0¼ 11,

DR3 ¼ 2 � ð1þ 2 � P2 þ � � � þ 2n�1 � PnÞ þ 1 ¼ 1þ 2þ 22 � P2 þ � � � þ 2n � Pn ð2dÞ

Thus, the above four equations can be combined to express the DR for all cases,

DR ¼ 20 � P0 þ 2 � P1 þ 22 � P2 þ � � � þ 2n � Pn ð3Þ

It is the same as the DR equation derived in Vaucher et al. (2000). This means that the

simple binary bits can be used to set the DR directly. The maximum DR is determined by

the number of cascaded 2/3 cells, the minimum DR depends on the number of 2/3 cells

which are not be cascaded with OR gate forward.

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The minimum DR of the proposed structure can be achieved is 8. According to theanalysis and illustration above, when the DR is even, output duty-cycle is exactly 50%.If the DR is odd, the output duty-cycle is k/(2kþ 1), where 2kþ 1¼ n. Hence, theduty-cycle would be closer-to-50% with an increasing DR n.

4. Measured results

The proposed divider was implemented and fabricated in Chartered 0.18-mm RF CMOSprocess. The photograph of the die is shown in Figure 5, the dimension is115� 170 mm2

¼ 0.02mm2. The supply voltage is 1.8V. There are eight DR control bits,which can realise the DRs from 8 to 511. To generate high input frequency, a wide bandvoltage controlled oscillator (VCO) was included in the chip, which was tuned by sixcapacitance array, and can provide the frequency from 1.8 to 3GHz. An oscilloscopeAgilent Infiniium MSO8104A was used to measure the output frequency and check theoutput duty-cycle.

The measured results of the proposed divider with different DRs are depicted inFigure 6. The input frequency from VCO is 2.75GHz. The waveform displayed is through

Figure 4. Transient simulation results of the outputs of divide-by-2/3/4 cell and the entire divider.

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a low-pass filter with 200MHz bandwidth which is included in the test apparatus. Due to

the parasitical capacitor with PADs, the output waveforms become sinusoidal with output

frequency increased by decreasing the DRs. This may also affect the accuracy of measured

duty-cycle. However, from the illustrations, we can see that the output duty-cycle

becomes closer-to-50% with the odd DR increased. For even DR, the test results are

around 44–50%.

Figure 6. Measured results of the proposed divider, fin¼ 2.75GHz (a) DR¼ 165,fout¼ 16.65864MHz and duty-cycle¼ 49.3%, (b) DR¼ 405, fout¼ 6.790637MHz and duty-cycle¼ 49.7%.

Figure 5. The photograph of the die.

Table 1. Comparison with the published work.

DRrange

Outputduty-cycle

(%)Fabricationtechnology

Chipdimension(mm2)

Powerdissipationat 2.5GHz

This study 8–511 44.4–50 0.18 mm RF CMOS 0.02 1.8V� 5.2mA¼ 9.4mWZhang

et al. (2007)8–510 44.4–50 0.18 mm RF CMOS 0.1 1.7V� 8.7mA¼ 15mW

(whole design)

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5. Conclusions

A wide DR range programmable frequency divider with close-to-50% output duty-cycle ispresented in this article. It is based on a proposed 2/3/4 divider cell, and has convenientprovisions of binary DR control bits. The proposed divider has been verified by the testresults, the close-to-50% output duty-cycle has been achieved. Comparison with thesimilar work in Table 1 shows that the proposed design achieves better efficiency.

Acknowledgements

This study is supported by the National Natural Science Foundation of China (no. 60871079). Theauthors thank the co-workers from National ASIC System Engineering Technology Research Centerof China, for the support of this study.

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