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SOLUTIONS FOR A PROGRAMMABLE WORLD Xcell journal Xcell journal 7 シリーズ FPGA で消費電力を半減 複数の FPGA でコンピューティング フィールドを構築した リコンフィギャラブル システム FPGA 内の SerDes デザインを 検証するアプローチを比較 イノベーションの新時代を担う Zynq-7000 EPP 75・76 合併号 2012 SPRING ARM AXI4 を サポートする FPGA で 核融合実験への 道筋を切り開く ページ 28

Xcell Journal 日本語版 75 & 76 合併号

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Xcell Journal 日本語版 75 & 76 合併号では、デュアルARM Cortex™-A9 MPCoreプロセッサとプログラマブル ロジックを緊密に統合した新しいクラス のデバイスであるZynq-7000エクステンシブル プロセッシング プラットフォームを詳細に解説したカバーストー リーや、ザイリンクス7シリーズ デバイスにおいていかに消費電力化を実現しているかを紹介した記事が掲載され ています。

Text of Xcell Journal 日本語版 75 & 76 合併号

  • S O L U T I O N S F O R A P R O G R A M M A B L E W O R L D

    Xcell journalXcell journal7 FPGA

    FPGA

    FPGA SerDes

    Zynq-7000 EPP

    7576 2012 SPR ING

    ARM AXI4 FPGA

    28

  • L E T T E R F R O M T H E P U B L I S H E R

    ACM FPGA Steve Trimberger 2011 6 ACM (Association for Computing and Machinery : ) Trimberger 1988 FPGA EDA 175 Trimberger EDA () (Trimberger)Trimberger ASIC VLSI Technologies Trimberger FPGA (Field Programmable Gate Array) (Trimberger)ASIC FPGA Trimberger FPGA Bill Carter Trimberger

    FPGA FPGA FPGA 1 Trimberger 175 IC Trimberger Automated Performance Optimization of Custom Integrated Circuits

    An Introduction to CAD for VLSIField Programmable Gate Array Technology 3 EDA FIRST Robotics (Trimberger 1 2011 )ACM Steve Trimberger FPGA

    Mike Santarini

    Steve Trimberger

    ACM

    Xcell journal Mike Santarini [email protected] +1-408-626-5981

    Jacqueline Damian

    Scott Blair

    / Teie, Gelwicks & Associates

    [email protected]

    [email protected]

    Xcell Journal 7576

    2012 3 1

    Xilinx, Inc2100 Logic DriveSan Jose, CA 95124-3400

    141-0032 1-2-2 4F

    2012 Xilinx, Inc. All Right Reserved.

    XILINX Xcell Xilinx PowerPC IBM

    Xilinx, Inc.

    Xilinx, Inc.

    Printed in Japan

  • VIEWPOINTS

    Letter From the Publisher

    ACM 2

    Cover Story

    7 FPGA 12

    Cover Story Zynq-7000 EPP

    44

    2828

    1212

  • XCELLENCE BY DESIGN APPLICATION FEATURES

    THE XILINX XPERIENCE FEATURES

    Xcellence in High-

    Performance Computing

    FPGA 22

    Xcellence in Scientific Applications

    ARM AXI4 FPGA 28

    7 5 7 6

    11

    20

    21

    27

    34

    PALTEK43

    56

    Xcell Journal http://japan.xilinx.com/xcell/henko/

    Xcell Journal http://japan.xilinx.com/xcell/toroku/

    3535

    2222

    Xperts Corner

    FPGA SerDes 35

    Ask FAE-X

    FPGA 44

    Xplanation: FPGA101

    FPGA 50 5050

  • 4 Xcell Journal 7576

    COVER STORY

    Zynq-7000 EPP

    Mike SantariniPublisher, Xcell JournalXilinx, [email protected]

    Zynq-7000 EPP Sets Stage for New Era of Innovations

  • http://japan.xilinx.com/ 5

    2 ARM Cortex-A9 MPCore IP (Xcell Journal 71 & 72 : http://japan.xilinx.com/publications/archives/xcell/ issue71-72/xcell71_72.pdf)2011 3 (EPP) Zynq - 7000 EPP 4

    28nm Zynq-7000 ARM Cortex-A9 MPCore NEON 1 (L1) 2 (L2) ( 1) FPGA Zynq-7000 EPP ARM FPGA (OS)

    ARM (SoC) FPGA FPGA Zynq-7000 EPP

    Zynq-7000 2 ARM Cortex-A9 MPCore IP

    C O V E R S T O R Y

  • SoC Zynq-7000 EPP

    Larry Getman Zynq-7000 EPP FPGA

    2 2 ASIC 1 FPGA FPGA ASIC

    C O V E R S T O R Y

    1 FPGA MPU Zynq-7000 EPP ARM

    6 Xcell Journal 7576

  • Getman Zynq-7000 2 FPGA Getman ASIC FPGA ASIC FPGA ASIC SoC ASIC ASIC 28nm Zynq-7000 EPP 28nm SoC 15 ASIC ASIC (Getman)Zynq-7000 EPP Getman

    Zynq-7000

    Zynq-7000 EPP Vidya Rajagopalan ARM AMBA AXI (Advanced Extensible Interface) ARM Cortex-A9 MPCore I/O ARM ARM FPGA AXI4 2 IP IP ARM (Rajagopalan)Getman 1 IP Zynq-7000 EPP Zynq-7000 EPP USBSDIOUARTSPII2CGPIO CAN CAN CAN

    Zynq-7000 EPP (Getman)Zynq-7000 2 512KB L2

    Zynq-7000 EPP 256KB FPGA (Getman)DDR 3 DDR (Double Data Rate) ASSP Zynq-7000 LPDDR2DDR2DDR3 DDR (Rajagopalan)Zynq-7000 EPP IP Zynq-7000 EPP / IP (Xcell Journal 67 & 68 : http://japan . x i l i n x .com /pub l ica t ions/archives/xcell/xcell67_68.pdf ) ARM Connected Community OSIP Zynq-7000 EPP Zynq-7000 EPP

    C O V E R S T O R Y

    http://japan.xilinx.com/ 7

  • Zynq-7000 EPP ISE Design Suite ( 2)Getman

    Eclipse (SDK) ARM Development Studio 5 (DS-5 ) ARM RealView Development Suite (RVDS ) ARM Linux Zynq-7000 2 Cortex-A9 CPU

    CPU Linux VxWorks OS (RTOS) Linux (USB SDIOUARTCANSPII2CGPIO) OS/RTOS (BSP)

    4 Zynq-7000 EPP 4 () ARM

    Cortex-A9 (MPCore) 2 CPU Cortex A9 MPCore NEON (3D / ) Cortex-A9 L1 ARM ARMv7 32 ARM 16 /32 Thumb Jazelle 8 Java L2 SRAMDMA ARM CoreSight ARM (ETB) (ITM) AXI 4 Zynq-7030 Zynq-7045 12.5Gbps 1.9M 5.2M ASIC (125k 350k ) DSP 480 GMAC 1080 GMAC Zynq-7010 Zynq-7020 430k 1.3M ASIC (28k 85k ) DSP 58 GMAC 158 GMAC 12 1MSPS ADC (x2) A/D (XADC) XADC Virtex FPGA 2 12 ADC 17 500kHz

    Zynq-7000 EPP 4 ARM 430K 3.5M ASIC

    C O V E R S T O R Y

    8 Xcell Journal 7576

  • ARM ISE Design Suite EPP IP Xilinx Platform Studio ISE (Getman)

    AXI ARM ARM FPGA AMBA IP IP Zynq-7000 7 FPGA 1

    AXI

    AXI 2

    Zynq-7000 EPP

    2011 2012 (ES) ARM Cortex-A9

    MPCore Zynq-7000 EPP 15 japan.xilinx.com/zynq

    2 Zynq-7000 EPP

    C O V E R S T O R Y

    http://japan.xilinx.com/ 9

  • COVER STORY

    7 FPGA

    12 Xcell Journal 7576

    How Xilinx Halved Power Draw in 7 Series FPGAs

  • 7 FPGA () 2011 3 28nm FPGA 7 FPGA I/O ( 28Gbps) 7 FPGA Taiwan Semiconducto r M anu fac tu r i ng Company (TSMC) FPGA 28nm HPL FPGA 7 FPGA FPGA FPGA

    FPGA 50%

    Mike SantariniPublisher, Xcell JournalXilinx, [email protected]

    C O V E R S T O R Y

    http://japan.xilinx.com/ 13

  • FPGA AC FPGA FPGA 10 DC ()

    130nm IC 90nm65nm45nm 45nm 30% 60%

    IC Microsoft Xbox 360 NVIDIA ASIC (EDN Taking a Bite out of Powerhttp://www.edn.com/article/460106-taking_a_bite_out_of_power_techniques_for_low_power_asic_design.php) 24 365

    FPGA (ASIC ) FPGA 3D

    FPGA HPL

    2010 7 FPGA (Xcell Journal 71 & 72 7 FPGA : http://japan.xilinx.com/publications/archives/xcell/issue71-72/xcell71_72.pdf) 28nm FPGA TSMC High Performance, Low power (HPL) High-k (HKMG) HPL FPGA (LP) (HP) Dave Myron LP HP MPU FPGA LP HP (Myron)

    C O V E R S T O R Y

    14 Xcell Journal 7576

  • FPGA ASIC Myron TSMC FPGA FPGA HPL ( 1 ) HPL 7 FPGA (Myron)HPL 28nm HP Vcc 28nm HP 2 28nm HPL 28nm HP FPGA (Vcc=1V) (Vcc=0.9V) 28nm LP 70% HPL Vcc=0.9V 0.9V 20% 7 FPGA Voltage ID (VID) Vcc 7 VID

    VID 7 FPGA 7

    Myron FPGA HPL 7 3 Zynq -7000

    (EPP) FPGA ASMBL 7 ( Artix -7 FPGA Kintex -7 FPGA Virtex-7 ARM Cortex -A9 MPCore Zynq -7000 EPP) ( Zynq-7000 EPP ) 1

    HP LP FPGA FPGA Virtex-6 Spartan-6

    FPGA (Xcell Journal 67 & 68 : http://japan.xilinx.com/publications/archives/xcell/xcell67_68.pdf) IP 7 FPGA 5 ( Inside Intel Core

    Higher PerformanceLower Leakage

    Throttled PerformanceHigher Leakage

    Perfo

    rman

    ce

    Power

    28HPLOptimal forFPGAs

    28LPBest for Cell Phones

    28HPBest for GPUs

    Virtex-7Kintex-7

    Artix-7 Arria-V

    Cyclone-V

    Stratix-V

    28HPL Process Optimized for FPGAs

    1. FPGA HPL

    C O V E R S T O R Y

    http://japan.xilinx.com/ 15

  • Microarchitecture : http://software.intel.com/file/18374/) FPGA (Myron) 2006 INTEL CORE 1 Myron 1 1 7 FPGA

    IP IP High-k HPL FPGA 7 FPGA PLL I/O 7 RAM RAM 30%

    High-k HPL

    7 (Myron) I/O ( 3)

    FPGA Matt Klein FPGA = fclkCLVDD

    C FPGA DSP48

    Higher Power Region for GPUs

    Better Performance / Power

    28 HP28 HPL28 LP

    Increas

    ing Vt

    0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6

    100

    10

    2

    1

    0.1

    Leak

    age

    Powe

    r

    Performance

    Lower Power Region for FPGAs

    2. 28nm HPL28nm HP 28nm LP

    C O V E R S T O R Y

    16 Xcell Journal 7576

  • 1V 0.85V 28nm FPGA (Klein) Klein fclk FPGA 7 FPGA (CE)

    3 FPGA 1 8 1 CE CE ISE ISE -power high -power XE Klein 30% 18% 1% (Klein)

    RAM RAM 1 Klein RAM sel RAM RAM RAM RAM ISE CE RAM CE RAM 70% 30% RAM CORE Generator XST RAM

    Current FPGAPower Budget

    Lower FPGAPower Budget

    Increase SystemPerformance

    Tota

    l Pow

    er Rearchitected Transceivers

    Multimode I/O Control

    Intelligent Clock Gating

    Power Binning and Voltage Scaling

    HPL Process

    7 Series Innovations

    TransceiverPower

    I/O Power

    DynamicPower

    MaxStatic Power

    60%30%

    25%

    65%

    3. 50% 7

    C O V E R S T O R Y

    http://japan.xilinx.com/ 17

  • 75% (Klein)

    I/O I/O FPGA I/O I/O 7 FPGA I/O 50% 75% DDR2 DDR3 I/O IBUF () DC DC 50% (Klein) IBUF 7 FPGA I/O IBUF IBUF 7 I/O 75% (Klein)7 VCCAUX 2.5V 1.8V PLLIDELAY VCCAUX 30% Virtex-6 FPGA

    XPower Estimator (XPE) 7 GTP GTH XPE ( 13.2) Myron 6.75Gbps Artix-7 GTP Spartan-6 GTP 60%

    Virtex-7 GTH 96 Virtex-7

    28nm FPGA Myron

    7 ( ) Myron 28nm HPL 28nm 1V () 4

    Dis

    tribu

    tion

    Slower Faster

    7 Series-2LEVCCINT = 0.9V

    7 Series-2LEVCCINT = 1V

    7 Series C-GradeVCCINT = 1V

    Slower Leakier

    Absolute Speed

    C-Grade Parts -2LE (1V) -2LE (0.9V)VCCINTStatic PowerDynamic Power

    1VNominalNominal

    1V-45%

    Nominal

    0.9V-55%-20%

    One Part, Dual Voltage

    Full -2 performance, 100C Screened for performance & power Standard binning process

    ~ -1 performance, 100C Screened & voltage scaled Extra power reduction

    4. 28-nm HPL

    C O V E R S T O R Y

    18 Xcell Journal 7576

  • -2L -2L 1V C I -2 100 -2LE C 45% -2LE 0.9V 0.9V C 55% 20%

    28nm

    FPGA 7 FPGA 7 http://www.xilinx.com/publications/technology/power-advantage/7-series-power-bench-mark-summary.pdf http://seminar2.techonline.com/regis-tration/wcIndex.cgi?sessionID=xilinx_jun1411 TechOnline

    ISE 13.2

    XPE ( 5) 7 GTP GTH 7 7 28 nm 7 FPGA (WP389 : http://japan.xilinx.com/support/docu-mentation/white_papers/j_wp389_Lowering_Power_at_28nm.pdf) 7 http://japan.xilinx.com/products/technology/power/index.htm

    6

    Actual HardwareBenchmark Results

    Kintex-7 FPGA PowerEstimator Results

    vs.

    Using the same reference design.First 28nm silicon demonstrates

    >50% power savings.

    Close correlation withestimator tool results

    Static Power: 3.6 WTotal Power: 6.5 W

    Static Power: 0.9 WTotal Power: 3.1 W

    5. FPGA XPower Estimator (XPE)

    C O V E R S T O R Y

    http://japan.xilinx.com/ 19

  • KintexTM-7 FPGA ACDCAcquisition, Contribution, Distribution and Consumption1.0

    TB-7K-325T-IMG

    FPGA Kintex-7 FPGA XC7K325T-FFG900

    Memory DDR3 2Gbit x 4

    FMC connector HPCHigh Pin Countx 2 LPCLow Pin Countx 2

    SERDES 12.5GbpsGTX8ch2HPC

    4K2K TV/4K2K

    //SMPTE 2022/EthernetAVB

    video over IP

    HDMIDVIDisplayPortV-by-OneHSEthernetLVDSPCIe

    221-0056 4 TEL045-443-4016 FAX045-443-4058http://ppg.teldevice.co.jp/

    PLD

    inrevium

  • FPGA

    XCELLENCE IN HIGH-PERFORMANCE COMPUTING

    Igor A. KalyaevDirectorKalyaev Scientific Research Institute of Multiprocessor Computer Systems Southern Federal University [email protected]

    Ilya I. LevinDeputy Director of ScienceKalyaev Scientific Research Institute of Multiprocessor Computer Systems Southern Federal [email protected]

    Evgeniy A. SemernikovHead of LaboratorySouthern Scientific Centre of the Russian Academy of [email protected]

    22 Xcell Journal 7576

    Reconfigurable System Uses Large FPGA Computation Fields

  • 20 CPU FPGA FPGA () Kalyaev Scientific Research Institute of Multiprocessor Computer Systems FPGA (RCS) FPGA FPGA RCS RCS FPGA 1 RCS FPGA FPGA CAD (Computer-Aided Design) FPGA RCS

    X C E L L E N C E I N H I G H - P E R F O R M A N C E C O M P U T I N G

    FPGA

    http://japan.xilinx.com/ 23

    Reconfigurable System Uses Large FPGA Computation Fields

  • 1 RCS FPGA 1 RCS () cadr cadr () () cadr () RCS 1 HPC RCS RCS 2 Kalyaev Scientific Research Institute of Multiprocessor Computer Systems (SRI MCS SFU) FPGA 1.2GHz LVDS RCS ( )

    X C E L L E N C E I N H I G H - P E R F O R M A N C E C O M P U T I N G

    2 RCS ( Virtex FPGA )

    1 (RCS)

    24 Xcell Journal 7576

  • RCS 16V5-75 RCS 50 GFLOPS (16 Virtex-5 FPGA ) 6 TFLOPS (1,280 Virtex-5 FGPA ) 5 ST-1R 4 16V5-75 6U RCS-0.2- CB 4 200 GFLOPS ST-1R 256 Virtex-5 FPGA (XC5VLX110) LVDS ( 3)Orion RCS ( 4) 20 TFLOPS 19 1,536 Virtex-5 FPGA 250 GFLOPS 16V5-125OR LVDS 1 1U 4 16V5-125OR 16V5-75 16 FPGA 4 16V5-125OR FPGA 16 LVDS Orion 1 RCS-0.2-CB Orion

    RCS

    RCS

    FPGA RCS RCS 2 RCS FPGA

    FPGA RCS FPGA

    X C E L L E N C E I N H I G H - P E R F O R M A N C E C O M P U T I N G

    (GFLOPS/dm3)

    (GFLOPS)

    DSP

    RCS-0.2-CB 16.7 647.7 423.2 535.2

    Orion 64.9 809.6 528.7 669.0

    3 256 Virtex-5 FPGA LVDS ST-1R

    1 RCS-0.2-CB Orion

    http://japan.xilinx.com/ 25

  • 1/2 1/3 Fire!Constructor COLAMO Argus IDE () COLAMO / / IP

    RCS (RCS ) RCS COLAMO 4 Pascal

    RCS FPGA Argus cadr

    cadr Fire!Constructor RCS FPGA Fire!Constructor IP RCS FPGA VHDL (*.vhd ) ISE FPGA (*.bit)

    RCS RCS Scientific Research Centre of Supercomputers and Neurocomputers ( : )

    BTO 100 RCS Virtex-5 Virtex-6 FPGA 100 GFLOPS 10 TFLOPS FPGA RCS RCS http://parallel.ru/

    4 20 TFLOPS Orion

    X C E L L E N C E I N H I G H - P E R F O R M A N C E C O M P U T I N G

    26 Xcell Journal 7576

  • ARM AXI4 FPGA

    XCELLENCE IN SCIENTIFIC APPLICATIONS

    Billy Huang PhD Researcher

    Durham University / CCFE

    [email protected]

    Dr. Roddy Vann Assistant Professor

    University of York

    [email protected]

    Dr. Graham Naylor Head of MAST Plasma Diagnostics and Control

    Culham Centre for Fusion Energy (CCFE)

    [email protected]

    Dr. Vladimir Shevchenko Senior Physicist

    Culham Centre for Fusion Energy (CCFE)

    [email protected]

    Simon FreethyPhD Researcher

    University of York / CCFE

    [email protected]

    28 Xcell Journal 7576

    Bottling a Star Using ARMs AXI4 in an FPGA

  • FX C E L L E N C E I N S C I E N T I F I C A P P L I C A T I O N S

    http://japan.xilinx.com/ 29

    ( 1) ( ) 1 1 Culham Centre for Fusion Energy (CCFE) 100 200 ITER (International Thermonuclear Experimental Reactor) 20 ITER () (http://www.iter.org/) 1 CCFE (http://www.ccfe.ac.uk/)

    ( 2) () 6GHz 40GHz (RF) ( 3 ) FPGA 250MHz 250MHz (ADC) 8 16 ( 90 2 )16 250MHz 14 0.5 14 2 32 0.25GB/s 8GB/s 0.5 4GB ADC FPGA (FMC) FPGA FMC I/O 1

    ARM AXI4 FPGA

  • 2010 Virtex-6 LX240T ML605 2 4DSP FMC108 (8 ) ADC 2 8GB/S FPGA 2011 1 ARM AMBA AXI4 ISE

    AMBA AXI4

    AXI4

    Linux Virtex-6 MicroBlaze DDR3 SDRAM MicroBlaze IP PLB PLB 64 32 NPI 2GB/S 400MHZ 64 ( 8 ) AXI4 4GB/S 6.4GB/S 2 1 AXI_V6_DDRX (AXI ) 1 System Generator AXI Master PCore PCore AXI External Master 1 Xilinx Platform Studio (XPS) MicroBlaze DDR3 5GB/S AXI

    XPS AXI

    MicroBlaze FPGA MicroBlaze Linux Linux MicroBlaze Linux FPGA PC SSH FPGA System ACE (MS-DOS ) Linux

    FPGA 0.5 2GB Linux UDP Gigabit Ethernet MicroBlaze 0.5MB/s 0.5 1 FireStark

    X C E L L E N C E I N S C I E N T I F I C A P P L I C A T I O N S

    1. CCFE Mega Amp Spherical Tokamak (MAST)

    2. PCB

    30 Xcell Journal 7576

  • UDP AXI Ethernet DMA MicroBlaze Linux FPGA 2GB 60 70 6KB 2 70MB/s MicroBlaze 100MHz DMA FPGA PC 129s13s (PC ) FPGA FPGA

    MAST

    10MHz 250MHz 10MHz ADC FPGA 10 10 2 2 FPGA 4ns ADC 8ns (8ns 360 )5 8(5/360)= 111ps 3.3cm DIP

    2 SMA FPGA FMC () ADC FPGA 2 SMA 2 4 10MHz ADC

    FPGA IODELAY FMC ADC ADC ADC 250MHz 2ns IODELAY 125ps

    X C E L L E N C E I N S C I E N T I F I C A P P L I C A T I O N S

    3. MAST RF 6GHz 40GHz FPGA

    250MHz

    4. 2 FPGA

    http://japan.xilinx.com/ 31

  • MMCM (Mixed Mode Clock Manager)1 MMCM MMCM 10MHz 250MHz ADC BUFGMUX_CTRL IDDR 10MHz 10MHz 2 BUFGMUX_CTRL () IGNORE0 IGNORE1 1 ADC DDR

    (SDR) I/O IDDR 1 2 SAME_EDGE_PIPELINED 1 FPGA (FMC) FPGA FPGA Virtex-6 FPGA FMC ML605 Virtex-6 FMC FPGA

    FPGA VHDL Verilog Project Navigator Project Navigator System Generator System Generator ( ) FFT IP / MicroBlaze System Generator (PCore) XPS ADC FIFO CORE Generator FIFO 256 125MHz 200MHz NGC PCore XPS .mpd .pao .bbd FPGA CompactFlash SystemACE Impact CompactFlash ( SDK ) MicroBlaze

    X C E L L E N C E I N S C I E N T I F I C A P P L I C A T I O N S

    5. ML605 4DSP FMC108 ADC FMC/PMOD FPGA

    ADC ADC SSMC SMA

    32 Xcell Journal 7576

  • Xilinx Platform Studio (XPS) XPS Create IP CORE Generator IP AXI4 IP (SDK) SREC CompactFlash FAT SREC () mbstrip g

    91KB BRAM 1 Virtex-6 PlanAhead PlanAhead Zynq -7000 (Xcell Journal 75 & 76 Zynq-7000 EPP ) Zynq MicroBlaze 10 MicroBlaze MicroBlaze ARM Cortex -A9 MPCore

    Zynq MicroBlaze Physical Address Extension 32 4GB RAM

    FPGA ( 5) 10GB/s (80Gbit/s) 15,000 ITER 1 FPGA AXI4 Virtex-6 FPGA

    CCFE (Durham University) (Centre for Advanced Instrumentation) (University of York) (Plasma Institute) EPSRC EP/H016732 RCUK Energy Programme EP/I501045 EURATOM CCFE European Communities Linux John Linn MicroBlaze Linux

    X C E L L E N C E I N S C I E N T I F I C A P P L I C A T I O N S

    6. ITER - 500MW

    http://japan.xilinx.com/ 33

  • ww

    w.a

    ldec

    .com

    /jp

    FPGA Designand Simulation

    Made Easy

    FPGA Designand Simulation

    Made Easy

    2012 Aldec Xilinx Aldec, Inc. Xilinx, Inc.

    160-0022 1-34-15 9F

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  • FPGA SerDes

    XPERTS CORNER

    / /

    Chris SchalickVice President of Engineering and CTOGateRocket, [email protected]

    http://japan.xilinx.com/ 35

    More Than One Way to Verify a Serdes Design in FPG

  • FPGA FPGA SerDes ( / ) SerDes SerDes FPGA SerDes 1 2 SerDes SerDes IP SerDes

    SerDes

    1 SerDes 2 SerDes back-to-back

    SerDes

    FPGA

    FPGA SerDes SerDes SerDes IP FPGA SerDes 10Gbps Virtex-5 GTP_DUAL SerDes 100Mbps 3.75Gbps 8 I/O 342 184 9 5 SerDes [1] SerDes 17 15

    FPGA SerDes 2 68 70 730 8 2730 SerDes SerDes FPGA SerDes FPGA SerDes

    / FPGA SerDes FPGA SerDes SerDes 1 SerDes 2

    36 Xcell Journal 7576

    X P E R T S C O R N E R

  • FPGA SerDes

    SerDes () FPGA SerDes FPGA 3 ASIC FPGA 500,000 RAM / / IP FPGA SerDes

    SerDes 1 FPGA SerDes 8b10b 8 10

    256 FPGA SerDes SerDes XAUIPCI ExpressRapidIO FPGA SerDes IP IP ( ) FPGA IP IP

    ( IP ) IP IP 2 XAUI 59 4 55 XAUI FPGA SerDes

    X P E R T S C O R N E R

    1 8b10b FPGA

    http://japan.xilinx.com/ 37

  • IP

    SerDes 1 SerDes FPGA SerDes 1 FPGA SerDes 1 FPGA FPGA 2

    3 1 1 (ACK) FIFO FIFO ( ()) FIFO FIFO () FPGA SerDes FIFO

    RTL HDL RTL FPGA SerDes FPGA RTL

    X P E R T S C O R N E R

    2 XAUI FPGA

    38 Xcell Journal 7576

  • 1 SerDes 3 RTL RTL 30 SerDes RTL

    FPGA SerDes SerDes 8b10b ( 1) 10Gbps XAUI ( 2) 2 XAUI

    XGMII XAUI 8.1 CORE Generator XAUI [2] 2 GateRocket [3]

    1 : SERDES

    FPGA SerDes SerDes () () SerDes

    3

    4 SerDes

    http://japan.xilinx.com/ 39

    X P E R T S C O R N E R

  • 4 1 8b10b SerDes 2 XAUI SerDes I/O XAUI GTP_DUAL SerDes SerDes FPGA 2 1 1 SerDes SerDes SerDes 1 1 2 XAUI 18 8b10b XAUI

    2 : 2 SERDES

    FPGA SerDes FPGA SerDes SerDes 2 1 SerDes

    ( 5 ) 1 2 XAUI 59 SERDES

    CPU

    (%) ( )

    GTP_DUAL 71% 41.8

    XAUI 11% 6.5

    10.6% 6.3

    7.4% 4.4

    1 XAUI

    5 SerDes

    40 Xcell Journal 7576

    X P E R T S C O R N E R

  • SerDes 2 1 59 101 2 1 8b10b SerDes 100% 2 SerDes 32 2 64

    3 : SerDes

    FPGA SerDes

    SerDes SerDes FPGA 5 7

    4 :

    FPGA

    FPGA FPGA RTL FPGA RTL (HDL) HDL FPGA FPGA SerDes PCB 1 2 SerDes 2 XAUI FPGA SerDes 59 18

    SerDes 1

    SerDes 64

    -

    1

    1

    SerDes 18

    SerDes 101

    -

    18

    59

    2 8b10b

    3 XAUI

    http://japan.xilinx.com/ 41

    X P E R T S C O R N E R

  • FPGA EDA GateRocket RocketDrive

    5 :

    1 SerDes SerDes 1 8b10b 8b10b / SerDes SerDes XAUI CORE Generator ( 2)XAUI 1 8b10b SerDes

    SerDes 59

    5 1 8b10b 2 XAUI 2 3 2 ( 2 SerDes ) SerDes SerDes SerDes ( 1)SerDes ( 3) SerDes

    SerDes FPGA

    SerDes 2730 SerDes GateRocket 2 SerDes ASIC SerDes FPGA GateRocket http://www.GateRocket.com

    [1] Virtex-5 FPGARocketIO GTP (2008 12 )http://japan.xilinx.com/support/docu-mentation/virtex-5_user_guides.htm

    [2] XAUI (2010 4 )japan.xilinx.com/support/documenta-tion/ip_documentation/xaui_ug150.pdf

    [3] : Intel Xeon CPUX3363 @ 2.83GHz6MB 16GB DDR3 (PC2-5300/667MHz)

    42 Xcell Journal 7576

    X P E R T S C O R N E R

  • FPGA

    ASK FAE-X

    E. SrikanthSolutions Development Engineer

    Xilinx, Inc.

    [email protected]

    44 Xcell Journal 7576

    How Do I Reset My FPGA?

  • FPGA FPGA FPGA FPGA

    FPGA 7 1 8 D (CLK) High (CE) High SR SR / / ( 1 )

    RTL RTL RTL ( 2a)SR

    (FDCE FDPE ) SR SRVAL SR (FDSE FDRE ) SR SRVAL INIT INIT (GSR) FPGA / /

    / / 1 RTL / / / 1 SR FPGA

    1 SR / / / SR 4 1

    ()

    A S K F A E - X

    D

    CEQ

    CK

    CR

    1

    (a) (b)

    INIT

    SRVAL

    signal Q:std_logic:=1;....async: process (CLK, RST)begin if (RST='1')then Q

  • 1 ( 2 ) SR PERIOD 2

    1 : SR

    SR SR SR

    3 ()

    2 SR (SRVAL=1) SR

    2 :

    3 (clk_a) FPGA ( Clock-Capable ) MMCM PLL (Phase-Locked Loop) MMCM

    PLL MMCM PLL

    3 : MMCM PLL FPGA

    4 FPGA FPGA SR High RTL Low / / /

    A S K F A E - X

    D Q

    CK

    SR

    rst_pin

    rst_clk_aSR

    D Q

    CK

    clk_a

    3

    46 Xcell Journal 7576

  • LUT 1 Low HDL High I/O FPGA

    4 : High

    A S K F A E - X

    D Q

    CK

    SR SRD Q

    CK

    SR

    Flip-Flop

    CLK

    SR

    Flip-Flop

    CLK SR

    Flip-Flop

    CLK

    MMCM

    Asynchronous Reset

    Clock Domain A

    To SR ports

    D Q

    CK

    SR SRD Q

    CK

    SR

    Flip-Flop

    CLK

    SR

    Flip-Flop

    CLK

    SR

    Flip-Flop

    CLKAsynchronous Reset

    CLKB

    CLKA

    Clock Domain B

    To SR ports

    ExternalReset Pin

    Global ClockInput Pin

    MMCMLock

    4 FPGA

    FDC0

    FDP1

    FPGA

    RAM

    000000001111111110101011111111111100000000

    Configuration

    RESET

    5 FPGA

    http://japan.xilinx.com/ 47

  • FPGA FPGA ( RAM ) 5 FPGA FPGA RTL 6 RTL FPGA signal (VHDL ) reg (Verilog ) INIT

    RAM RAM BRAM RAM

    (GSR) FPGA GSR

    A S K F A E - X

    signal reg: std_logic_vector (7 downto 0) := (others

  • (Z-1) /

    8 : DSP48E1 RAM

    RTL / /

    FPGA FPGA 7 japan.xilinx.com/training

    Srikanth Erusalagandi

    FPGA 2010 1 MosChip Semiconductors 6

    INIT GSR STARTUPE2 GSR GSR GSR FPGA INIT GSR GSR

    5 : GSR

    GSR

    RTL FPGA RTL FPGA SRLLUTRAM RAM GSR

    32 RTL 32 RTL SRL32E 32 SRL32E RTL 6 : SRLLUTRAM RAM SRL RAM

    7 LUT ( 7) LUT/SR LUT

    7 : FPGA

    ( RAM DSP48E1 ) RAM DSP48E1

    A S K F A E - X

    http://japan.xilinx.com/ 49

  • FPGA101

    FPGA

    Glenn SteinerSenior Manager of Technical Marketing

    Xilinx, Inc.

    [email protected]

    Dan IsaacsDirector of Technical Marketing

    Xilinx, Inc.

    [email protected]

    50 Xcell Journal 7576

    Demystifying FPGAs for Software Engineers

  • ASSP (APPLICATION-SPECIFIC STANDARD PRODUCT) ASSP ASSP FPGA 50 70% FPGA FPGA 1 FPGA FPGA FPGA FPGA FPGA

    FPGA

    FPGA (Field-Programmable Gate Array) IC (PCB) 1 FPGA

    ANDORNOT (CLB)

    I/O

    FPGA

    http://japan.xilinx.com/ 51

  • HDL ( Verilog VHDL) HDL C Verilog 8 (www.asic-world.com/ )

    //-----------------------------------------// Design Name : up_counter// File Name : up_counter.v// Function : Up counter// Coder : Deepak//-----------------------------------------module up_counter (out , // Output of the counterenable , // enable for counterclk , // clock Inputreset // reset Input);//----------Output Ports------------------- output [7:0] out;//------------Input Ports------------------ input enable, clk, reset;//------------Internal Variables----------- reg [7:0] out;//-------------Code Starts Here------------always @(posedge clk)if (reset) begin out

  • (3)

    FPGA 1

    : FPGA : FPGA C C++ FPGA Eclipse Eclipse Eclipse 2 Eclipse

    F P G A 1 0 1

    hello world

    : FPGA ASSP : ASSP FPGA FPGA FPGA 32 RISC OS MMU FPGA

    ASSP

    : FPGA : FPGA

    : OS : OS MicroBlaze LinuxThreadXMicroC/OS-IIeCos OS

    1

    http://japan.xilinx.com/ 53

  • : : FPGA 1 FPGA

    : : ASSP (UARTGPIO ) Linux

    : FPGA

    :

    : FPGA : ASSP FPGA 200 500

    FPGA

    1.

    2. (BSP)

    3. 4. 5. ()

    345 1 2 Eclipse

    Eclipse () ( )

    PCI I/O

    PCI Express UART 16550

    USB ADCDAC /PWM

    I2C /

    SPI ADC

    Gigabit Ethernet MAC

    Ethernet MAC Lite (SDRAMDDRDDR2DDR3)

    CAN ( SRAM)

    FlexRay Compact Flash DMA

    MOST

    1 ( )

    2 Eclipse IDE

    F P G A 1 0 1

    54 Xcell Journal 7576

  • (BSP) Eclipse [File][New] [Xilinx C Project] C Eclipse Makefile Makefile [Project Name] 1 BSP OS BSP

    Eclipse

    FPGA FPGA Eclipse [Tools] [Program FPGA] FPGA [Debug] [Release] pg [Run] [Release]

    Eclipse

    3 Eclipse

    FPGA

    FPGA FPGA FPGA Eclipse FPGA FPGA FPGA IP OS

    3 Eclipse

    F P G A 1 0 1

    http://japan.xilinx.com/ 55