Xcell Journal 日本語版 81 & 82 合併号

S O L U T I O N S F O R A P R O G R A M M A B L E W O R L D

Xcell journalXcell journal8 18 2 2013

Zynq SoC MicroBlaze

18

Zynq SoC

FPGA

FPGA

All Programmable 1

FPGA / CPLD PLCC68

FPGA

ACM/XCM

Spartan-6

FPGA Board100

5"LCD

FPGA

ICFPGA/CPLDPLCC68ICFPGACPLDICFPGACPLDFPGA/CPLDI/OIO2

RoHS

RoHS

XP68-02PLCC 68 Spartan-3AN FPGA

XC3S200AN-4FTG256C 50I/O 3.3V 50MHz ROMFPGA

6 IC

RoHS

XP68-03

UTL-021

PLCC 68 Spartan-6 FPGA

XC6SLX45-2CSG324C 50I/O 3.3V 50MHz ROM 6 IC

RoHS

XCM-306Spartan-6 LX TQG144 FPGA

XC6SLX4-2TQG144C XC6SLX9-2TQG144C

DDR2 SDRAM

MRAM

RoHS

XCM-110/110ZSpartan-6 FGG484 FPGA

XC6SLX45-2FGG484CXC6SLX75-2FGG484CXC6SLX100-2FGG484CXC6SLX150-2FGG484C

800 480 5TFT LCD

DDR2 SDRAM

RoHS

RocketI/O

MRAM

XC6SLX45T-2FGG484CXC6SLX75T-2FGG484CXC6SLX100T-2FGG484CXC6SLX150T-2FGG484C

XCM-020Spartan-6 LXT FGG484 FPGA

Virtex-5

XCM-109Virtex-5 FFG676

XC5VLX30-1FFG676CXC5VLX50-1FFG676CXC5VLX85-1FFG676CXC5VLX110-1FFG676C

RocketI/O

XCM-107Virtex-5 LXT FFG665

FPGA

EDX-007

XC5VLX30T-1FFG665CXC5VLX50T-1FFG665C

Spartan-6 LX XC6SLX4-2TQG144C FPGA

SDRAM

RoHS

RoHS

RoHS

RoHS

XC6SLX45-2FGG484CXC6SLX75-2FGG484CXC6SLX100-2FGG484CXC6SLX150-2FGG484C

XCM-018/018ZSpartan-6 FGG484 FPGA

MRAM

DDR2 SDRAM

5VTolerant5V I/O

XP68-01PLCC 68PIN Spartan-6 FPGA

XC6SLX16-2CSG225C 50I/O 3.3V 50MHz ROM 6 IC

RoHS

USBCong

USBComm

RoHS

XC6SLX45-2FGG484CXC6SLX75-2FGG484C

XCM-019YSpartan-6 FGG484 FPGA

RoHS

XC6SLX45-2FGG484CXC6SLX75-2FGG484C

XCM-019Spartan-6 FGG484 FPGA

L E T T E R F R O M T H E P U B L I S H E R

Zynq-7000 All Programmable SoC

5 Xcell Journal 28nm All Program-mable Vivado 2008 CEO Moshe Gavrielov

2008 28nm FPGA Zynq -7000 All Programmable SoC / 3D IC 3D 1

28nm Zynq-7000 SoC 28nm 1GHz ARM Cortex -A9 MPCore IC 28nm Zynq-7000

Zynq-7000 All Pro-grammable SoC ( ) Zynq-7000 2011 CMP Media (EE Times EDN UBM) SoC Product of the year IET Innovation Award Elektra (European Electronics Industry) Embedded System Product of the Year Award 2012

Electronic Products Magazine Product of the Year Microprocessor Report Analyst Choice Award

Zynq All Programmable SoC Zynq-7000

Zynq-7000 Web Zynq-7000 All Programmable SoC Avnet ZedBoard.org (www.zedboard.org) UBM All Programmable Planet (www.programmableplanet.org) (http://japan.xilinx.com/training/index.htm) (http://forums.xilinx.com/)

Zynq-7000 (http://japan.xilinx.com/japan/sales/store.htm) ZedBoard

Xcell Journal

Mike Santarini

Xcell journal Mike Santarini [email protected] +1-408-626-5981

Jacqueline Damian

Scott Blair

/ Teie, Gelwicks & Associates

[email protected]

[email protected]

Xcell Journal 8182

2013 6 10

Xilinx, Inc2100 Logic DriveSan Jose, CA 95124-3400

141-0032 1-2-2 4F

2013 Xilinx, Inc. All Right Reserved.

XILINX Xcell Xilinx

Xilinx, Inc.

Xilinx, Inc.

VIEWPOINTS XCELLENCE BY DESIGN APPLICATION FEATURESLetter From the Publisher

Zynq-7000 All Programmable SoC 1

Xcellence in Wireless Communications

Zynq SoC 10

Cover StoryAll Programmable 1 4

10

THE XILINX XPERIENCE FEATURES

8 1 8 2

2

Xpert Corner

Zynq SoC MicroBlaze 18

Xplanation: FPGA101

FPGA 24

Xplanation: FPGA 101

30

Xplanation: FPGA 101

FPGA 34

Excellence in Magazine & Journal Writing 2010, 2011

Excellence in Magazine & Journal Design and Layout 2010, 2011, 2012

24

18

34

COVER STORY

Moving a Generation Ahead with All Programmable Devices

4 Xcell Journal 8182

28nm All Programmable SoC 3D IC FPGA 1

All Programmable 1

http://japan.xilinx.com/ 5

C O V E R S T O R Y

Mike SantariniPublisher, Xcell JournalXilinx, [email protected]

28nm 1 FPGA FPGA All Pro-grammable 3D IC SoC All Pro-grammable (All) (AMS) 3D IC ( 1) All Programmable BOM CEO Moshe Gavrielov 2008 28nm 1 2 TSMC FPGA HPL (High Performance, Low Power) 28nm All Programmable (Xcell Journal 75 & 76 ) EDA

5 28nm 10 All Programmable

Zynq-7000 All Programmable SoC Zynq -7000 All Programmable SoC (System-on-Chip) EE Times 2011 Innovation of the YearAll Programmable SoC 3 (I/O ) / FPGA 1990 FPGA BOM OS 2000 FPGA FPGA Virtex-4 FX Virtex-5 FX FPGA PowerPC CPU

All Programmable 1

Virtex FX FPGA FPGA FPGA 2008 Zynq-7000 All Pro-grammable SoC ( /

) Zynq-7000 All Pro-grammable SoC 1GHz ARM A9 ARM AXI4 Zynq Time-to-Market FPGA

Zynq-7000 IP I/O FPGA FPGA All Programmable SoC 2010 2011 All Programmable SoC Zynq 1 Zynq FPGA CPU

C O V E R S T O R Y

Portfolio: All ProgrammableFPGAs, SoCs, and 3D ICsAvailable Today

All Programmable

FPGA Family First shipped: Q1, 2011

Delivering one extra node of power and performance

All Programmable

SoC First shipped: Q4, 2011

Integrating FPGA, CPU,DSP, AMS

All Programmable

3D ICs First shipped: Q3, 2011

Integrating 2x logic andserdes bandwidth

1 : 28nm All Programmable


DSPFPGA AMS Zynq-7000 All Programmable SoC Xcell Journal 75 & 76 9

All Programmable 3D IC28nm All Program-mable 3D IC2004 IC Si (TSV) 3D IC (SSI) I/O 10,000 3D IC All Programmable 3D IC SSI Xcell Journal 77 & 78 2012 3D IC Virtex-7 2000T 4 FPGA

28nm IC (68 ) FPGA 200 (ASIC 2,000 ) FPGA 2 1 20nm SSI Virtex-7 2000T ASIC 3D IC 1 2012 2 All Program-mable 3D IC Virtex-7 H580T (Xcell Journal 79 & 80 ) Virtex-7 2000T 4 / FPGA 3D IC Virtex-7 H580T 3D IC Virtex-7 H580T 2 FPGA 28G 8 28Gbps 48 13.1Gbps 58 CFP2 2x100G Virtex-7 H580T 5 1 BOM Virtex-7 H580T

28nm 3D Virtex-7 H870T 3 FPGA 2 8 16 28Gbps 72 13.1Gbps 876,160 Virtex-7 H870T 400G 3D IC 400G 1

All Programmable FPGA 1985 11 ASIC 1,000 FPGA XC2064 FPGA FPGA ASIC 2 ASIC FPGA All Programmable FPGA I/O/ FPGA () All Programmable FPGA / All Programmable SoC 3D IC

C O V E R S T O R Y


FPGA 1 28nm FPGA 28nm (1) 1 (2) 1 (3) SERDES (4) (QoR) 28nm Kintex -7

K325T ( ) 2011 3 28nm 28nm All Programmable TSMC HPL 35 50% All Programmable FPGA 1 ( 2) 28nm FPGA ( 3) ( RAMDSP ) 1.2

2 ( 1.5 ) 1 All Program-mable FPGA FPGA 28nm FPGA / FPGA BOM

VIVADO 28nm All Programmable Vivado ( 4) 4 500

C O V E R S T O R Y

2 : 35%


3D IC FPGA SoC Vivado Design Suite QoR 3 50% 20% 4 1 Vivado

Xcell Journal 79 & 80

Vivado All Programmable Vivado QoR

Vivado IP IP Time-to-Market Vivado C AXI C RTL IP Vivado C RTL (All) AMS 3D IC All Programmable FPGASoC 3D IC BOM 2008 2006 1 20nm FPGA 2 SoC 3D IC Vivado 1 SoC 3D IC

C O V E R S T O R Y

Altera Quartus

Vivado

RTL IP 10

C IP

28nm

C 100 C RTL 4

RTL 3 100

IP IP 4 5

4 ECO 3 LUT 20% 3

35%

Time-to-Market 4 3 3 1

3 : 28nm FPGA 1 All Programmable

FPGA

4 : Vivado Time-to-Market



XCELLENCE IN WIRELESS COMMUNICATIONS

Zynq All Programmable SoC Vivado HLS

Baris OzgulResearch ScientistXilinx, Dublin, [email protected]

Jan LangerResearch ScientistXilinx, Dublin, [email protected]

Juanjo NogueraResearch ScientistXilinx, Dublin, [email protected]

Kees VissersDistinguished EngineerXilinx, [email protected]

Software-Programmable Digital Predistortion on the Zynq SoC

Zynq SoC

(DPD) (PA) DPD 3G/4G (DFE) DPD PA PA DPD DPD DFE FPGA DPD DFE ARM Zynq -7000 All Programmable SoC

Zynq-7000 All Programmable SoC 1 All Programmable SoC DFE Zynq-7000 DPD Vivado (HLS)

Zynq Zynq-7000 SoC 2

1 1GHz ARM Cortex -A9 2 I/O FPGA 2 ARM 128 NEON (SIMD) 2 Zynq-7000 FPGA AXI4 FPGA 2

X C E L L E N C E I N W I R E L E S S C O M M U N I C A T I O N S

Software-Programmable Digital Predistortion on the Zynq SoC

MemoryControl

6/10GSerdes

OpticalModules

CPRI/OBSAIMaster

DigitalUp-

conversion(DUC)

CrestFactor

Reduction(CFR)DigitalDown-

conversion(DDC)

DigitalPre-

distortion(DPD)

CPRI/OBSAIMaster

6/10GSerdes

SPI/I2C UARTSARM A9:DPDUpdate

ARM A9:O&MRTOS

Memory

GPIODAC

JESD204Or LVDS DAC

ADC

ADC

ADC

JESD204Or LVDS

JESD204Or LVDS

1 Zynq All Programmable SoC


DMA C VHDL Verilog Vivado HLS

/ Vivado HLS ( ) (DMA )

HLS (RTL)

RTL HLS C/C++ / C/C++ 3 MATLAB C/C++ ( ) DSP FPGA DSP FPGA C/C++ (gcc ) C/C++ HLS ( ) 2 FPGA ( )


Softw

are

Desi

gn F

low Software

Development

SW/HWPartitioning

SoftwareRefinement

Vivado HLSRefinement

Profiling

SW Compiler

Executable

HW Synthesis

Bitstream

2


FPGA HLS (C/C++ ) RTL

C/C++ RTL Vivado ISE/EDK

FPGA FPGA C/C++ C RTL

DPD 3G/4G W-CDMA (Wideband Code Division Multiple Access Signal) OFDMA (Orthogonal Frequency Division Multiple Access) (PAPR : Peak to Average Power Ratio) PAPR PA PA


Reference C/C++ Code

Manual Code Restructuring

C/C+

+ Co

deVe

rifica

tion

Implementation C/C++ Code

RTL Output

Bitstream

Vivado HLSTool

Constraints

Directives

Vivado(ISE/EDK)

CrestFactor

ReductionPredistorter

x z y0PA

coefficients

LS Estimator

CC AMC

Alignment

y

Antenna

Hardware

Software +Accelerators

3

4 (DPD)


PA PA 1 DPD PA 4 DPD PA ( PA D/A A/D RF ) PA PA PA yo PA y

z PA DPD 4 (LS) DPD 4 (AMC) LS (CC) CC DPD

LS DPD DPD DPD DPD

4 z y MATLAB 2 1 x86 gprof 2 ARM gprof Zynq All Program-mabale SoC CPU CPU 2 1 5 ARM 3 AMC


Autocorrelation matrix computation

Alignment

Coefficient computation

97%

0%3%

32 32

32

multiply multiply

32

64 64

5

6 NEON 2 32 32


AMC 97% 4 ARM AMC

ARM SIMD NEON 128 AMC 64 6 NEON 2 NEON NEON C

C 2 NEON ARM NEON NEON

3 Vivado HLS AMC AMC DPD C++ RTL AMC C/C++ FPGA DSP (DSP48) 2 C/C++ C/C++ (shortint ) Vivado HLS C++ AMC FPGA 7 C++ ) DSP48 AMC


1: typedef struct {2: ap_int real;3: ap_int imag;4: } CINT32;5:6: typedef struct {7: ap_int real;8: ap_int imag;9: } CINT64;10:11: CINT64 CMULT32(CINT32 x, CINT32 y){12: CINT64 res;13: ap_int preAdd1, preAdd2, preAdd3;14: ap_int sharedMul;15:16: preAdd1 = (ap_int)x.real + x.imag;17: preAdd2 = (ap_int)x.imag - x.real;18: preAdd3 = (ap_int)y.real + y.imag;19:20: sharedMul = x.real * preAdd3;21: res.real = sharedMul - y.imag * preAdd1;22: res.imag = sharedMul + y.real * preAdd2;23: return res;24: }

3 pre-adders

3 multiplicationsinstead of 4

Non-standard bit-widths

1: void amc_accelerator_top(_)2: {3: #pragma HLS allocation instances=mul limit=3*UNROLL_FACTOR operation4:5: 6: CINT64 Marray[MSIZE];7:8: #pragma HLS array_partition variable=Marray cyclic factor=UNROLL_FACTOR dim=19:10:11:#pragma HLS resource variable=Marray core=RAM_2P12: 13: label_compute_M: for (int i=0; i < MSIZE; ++i)14: {15:#pragma HLS pipeline16:#pragma HLS unroll factor=UNROLL_FACTOR17: 18: }19: 20: }

Limit the number of multiplications

Partition based on the unrolling factor

Resource mapping

Loop pipelining and unrolling

7

8


4 4 7 3 1 ( DSP48 ) 3 4 Vivado HLS 3 33 32 65 C++ 4 2 32 C/C++ ( 64 ) 32 64 HLS 4 64 64 DSP48 7 C++ C++

Vivado HLS 33 32 3 4 DSP48 AMC AMC C++ Vivado HLS C 8 (UNROLL_FACTOR) Vivado HLS 3 7 CMULT32 8 3 HLS 3xUN-ROLL_FACTOR 8

15 16 Vivado HLS RTL 11 Marray RAM

Advanced eXtensible Interface (AXI) AXI AXI4 AXI Zynq (ARM) DMA 9 AXI AXI4-Lite AXI4-Lite AXI AXI4-Lite ID


ARM CoreSight Multicore and Trace Debug

NEON/FPU Engine

Cortex-A9 MP Core32/32/KB I/D Caches

512 KB L2 Cache

Timers/Counters

General Interrupt Controller

Amba Switches Memory

AXI4-Lite Interconnect

AXI FIFO

AMC Accelerator s

s

m m

NEON/FPU Engine

Cortex-A9 MP Core32/32/KB I/D Caches

Snoop Control Unit (SCU)

256 KB On-Chip Memory

DMA Configuration

9


ID AXI AXI4-Lite 9 AXI FIFO / AXI4-Stream AXI4-Lite AMC Vivado HLS AXI4-Lite

Zynq-7000 SoC 10 DPD Zynq 7045 Zynq-7000 SoC ZC706 Vivado HLS AMC 250MHz Vivado HLS Vivado HLS 3% 10 1.250

AMC AMC 2 NEON 2 AMC AMC 70 DPD 2 DPD NEON DPD DPD DPD


1250

Upda

te T

ime

(ms) 1000

750

500

250

0Original Optimized NEON PL Accelerator

CC

AMC

Alignment

3% Zynq 7045

70x speed-upfor AMC

10 ZC706


Get on Target

Xcell journal PR

Xcell Journal

10,000 HP iPad

Xcell Journal

E-mail [email protected]

XPERTS CORNER

How a MicroBlaze Can Peaceably Coexist with the Zynq SoC

Zynq SoC MicroBlaze


Xilinx Zynq -7000 All Program-mable SoC Zynq (APU) Cortex -A9 1 MicroBlaze MicroBlaze 1 Cortex-A9 1 MicroBlaze 2 Cortex-A9 MicroBlaze 2 ( ) APU MicroBlaze APU ( APU )

Zynq Soc Micro-Blaze 1 APU MicroBlaze MicroBlaze (PS) ZC702 Zedboard PS (PL) MicroBlaze PS MicroBlaze

PS PL PS Cortex-A9 (SCU)PS PL PS PL 6 PS PL

X P E R T S C O R N E R

Processor Systemwith Dual Cortex-A9s

Programmable Logicwith MicroBlaze

?

1 - PS PL MicroBlaze PS MicroBlaze

Bill KafigSenior Content Development Engineer

Xilinx, Inc.

[email protected]

Praveen VenugopalSolutions Development Engineer

Xilinx, Inc.

[email protected]

Zynq All Programmable SoC MicroBlaze


ACP PS Cortex-A9 PL AXI Extended Multi-plexed Input and Output (EMIO)

Zynq-7000 APU PL (PCIe

RAMDSP48 ) MicroBlaze 6 AXI AXI (ACP) 3 AXI PS PL 2 AXI PL 2 ( 2) AXI AXI PL AXI PL MicroBlaze AXI PS 4 (64 ) AXI 4 PS PS ( 3) 4 PL (DDR) DDR DDR Cortex-A9 AXI 4 AXI (service me now)


(ACP) PS PL 1 32 AXI ACP (SCU) SCU L1L2 DDR

I/O Peripherals

APB Register Access

Debug (DAP)

L2 Cache Memory

DMA (8 channels)

General-PurposeMaster AXI

32-bit

General-PurposeSlave AXI

32-bit

Central Interconnect

Programmable Logic

OCM

DDR Memory Controller

L2Cache

CentralInterconnect

AXI_HP toMemory

Interconnect(64-bit paths)

AXI HP 0

AXI HP 1

AXI HP 2

AXI HP 3

M1

M2

M0FIFO

FIFO

FIFO

FIFO

3 - DDR (OCM)

2 -



PS PL PS 54 PS EMIO PS PL I/O PL PL PS PL AXI DDR DMA 5

: PS 4 PL 1 AXI

: PS (GIC) PS 16

CPU 4 (IRQ0IRQ1FIQ0FIQ1) PL (PS ) 28

: PS PS CPU CPU SEV ( ) PS WFE ( )

AXI DDR : PS AXI PL AXI PL PL PS 1 DDR / (urgent/arb) PS DDR 4 AXI DDR

DMA : PS REQ/ACK PL

DDR DDR PS IOP MicroBlaze PS MicroBlaze PS MicroBlaze 4 ( ) DDR 4 (HP) AXI ( ) 1 4 64 AXI Micro-Blaze AXI4-Lite HP

PS Design

MicroBlaze (PL)Design

GIC

BRAMController

BRAM

Cont

rolle

r

BRAM

Cont

rolle

r

BRAMController

DCM_locked

BRAMMicroBlaze

Local AXI PeripheralGPIO

intc

BRAM

DDR

MIO IOP

BLOCK

Interruptfrom UART

Interruptfrom Timer

GPIO LED 8bit

DLMB ILMB

Cortex A9

HPS-AXI (x4)S_AXI_HP3S_AXI_HP2S_AXI_HP1S_AXI_HP0

Inte

rrupt

from

UAR

T

B D

ata

Side

B In

terru

ptio

n Si

de

TTC Waveformclk S-AXI (x2)

M_AXI_GP0 S_AXI_GP0

100

MH

z cl

kre

set_

n

8 LEDs

142

3

4 (1) DDR (2) PS IOP (3) MicroBlaze PS (4) MicroBlaze PS


PS DDR DMA (OCM) DMA 1 RAM ( )PS BRAM MicroBlaze / BRAM MicroBlaze PS PS PL / (TTC) 1 100 ( )TTC PS TTC PS TTC MicroBlaze (AXI ) PS MicroBlaze

5 2 2 ( PS MicroBlaze ) PS PS MicroBlaze MicroBlaze PS PL

AXI4 DDR AXI-Lite

32 PL DDR HP DMA PS UART / (TTC) M_AXI_GP0 BRAM BRAM PL ( ) PS MicroBlaze BRAM Micro-Blaze 64Kbyte PS HP DDR


MicroBlaze GPIOBRAM 3 TTC PWM ( ) UART GPIO ZC702 8 LED BRAM

PS BRAM B2 1 S_AXI_GP0 PS 1 MicroBlaze DDR

IOP PS S_AXI_GP0 ( )

S PL MicroBlaze S_AXI_GP0 IOP 0xE000_0000 0xE02F_FFFF MicroBlaze MicroBlaze

Cortex-A9Software

Realm

MicroBlazeSoftware

Realm

Shared:Interrupt sources

Clock(s)

Overlap:BRAM addressesIOP addressesDDR memory addresses

5 -



PS IOP DDR BRAM IOP MicroBlaze Cortex-A9 (TRM) ( 8 19

UART )

B B 2 DDR DDR BRAM

Xilinx Plat-form Studio Cortex-A9 MicroBlaze 6 Zynq-7000 Cortex-A9 ( ) T MicroBlaze RAM MicroBlaze MicroBlaze 16 ASCII PS IOP

MicroBlaze DDR DDR BRAM Cortex DDR MicroBalze + MicroBalze X MicroBlaze Zynq-7000 PS AXI MicroBlaze ( PL ) IOP OCM DDR IOP PL PS

PS - Cortex-A9 PL - MicroBlaze

TTC Interrupt

Wait fortic

BRAM

UARTInterrupt

UARTInterrupt

Wait forchar

Increment the tic counterSet the BRAM offset

and address

Get the occurencecounter from BRAM

Set the LEDs Decrementthe LED

Convert to hex ACSII

Send char pair via UART

Build a buffer with checksum and write to DDR

Increment the occurrencecounter

Occurrence= limit?

Send msg via serial port

Validate DDR memory

LEDs

DDR Memory(data space)

6 Cortex-A9 MicroBlaze


How to Implement State Machines in Your FPGA

Adam TaylorPrincipal Engineer

EADS Astrium

[email protected]

XPLANATION: FPGA 101

FPGA


FPGA 1 Moore Mealy 2 2 Moore Mealy Richards (http://en.wikipedia.org/wiki/Richards_controller/ )

1 MOORE ( ) MEALY 2 (FPGA ) FPGA

1 1 (ASM ) ASM ( 2) ASM 3

1. : (Moore )

2. :

3. : Mealy

ASM ASM VHDL

MOORE MEALY Moore Mealy

X P L A N A T I O N : F P G A 1 0 1

FPGA


2

2

4 CASE MOORE ( ) MEALY

( ) 3

2 Moore 1 3 Moore Mealy Moore Mealy Mealy Moore Mealy RS232

VHDL VHDL

TYPE state IS (idle, led_on, led_off) ;

( 1) 2 1 1 2


Start

Toggle

Toggle

LED_OFF LED_ON0

0

1

IDLE

Start

Toggle

LED_OFF LED_ON

0

IDLE

Toggle1

1

Op = 0

Op = 1

Op = 0

Start

Toggle

Toggle

1 0

1 0

1 0

Led_on

Idle

Led_off

Start

Toggle

Toggle

1 0

1 0

1 0

Led_on

Idle

Led_off

Op = 1

Op = 0

1 LED / Moore ( ) Mealy

2 1 : Moore ( ) Mealy



:

: 1

: 1 High 1 Low

=

)2(10)(10

LOGStatesLOG

CeilFlipFlops

: 5

: 5 50

: 50


SIGNAL current_state : state := idle;

ATTRIBUTE syn_encoding STRING;

ATTRIBUTE syn_encoding OF current_state : SIGNAL IS sequential;

sequential gray onehot 3 ( ) safe syn_encoding Idle =

00led_on = 01led_off = 10 Idle = 11led_on = 10led_off = 01 3

3 Moore ( ) Mealy


2 1 2 2 n



ATTRIBUTE syn_keep BOOLEAN;

ATTRIBUTE syn_keep OF current_state : SIGNAL IS TRUE;

FPGA Moore Mealy



ATTRIBUTE syn_encoding STRING;

ATTRIBUTE syn_encoding OF current_state : TYPE IS 11 10 01;

Xilinx XST FSM Option USER Synopsys Synplify FSM Compiler 2 ( Xcell Journal 7374 FPGA )


4 VHDL Moore ( ) Mealy


!!

FPGA

FPGA

FPGA/SoC

FPGA FPGA FPGA /CPLD

FPGA

FPGA

FPGA FPGA

30! FPGA

: All Programmable SoC OS : All Programmable SoC OS

AMBA AXI4

FPGA PlanAhead 1 2 3

Zynq-7000 All Programmable SoC C

: All Programmable SoC OS

15! FPGA

ISE Design Suite

http://japan.xilinx.com/webseminar/

All Programmable FPGA SoC3D IC

New!!New!!

Web Seminar

Zynq-7000

Zynq-7000 EPP

28nm 7 FPGA


FPGA

Debugging High-Speed Memories


FPGA SRAM/SDRAM FPGA SRAM/SDRAM Virtex-4 Virtex-5 FPGA Virtex-6 Virtex-7 (MIG) IP ISE MIG FPGA (BIST)

FPGA CORE Generator MIG DDR-II SRAMDDR2 SDRAMQDR-II SRAM 1 CORE Generator MIG3.6.1 7 MIG MIG (GUI) FPGA MIG VHDL Verilog (RTL)

(UCF) RTL UCF MIG MIG MIG MIG FPGA Web

FPGA 3 1 FPGA 2 FPGA FPGA 3 MIG

BIST MIG MIG FPGA MIG


David J. EastonFounder

DesignVerify Ltd.

[email protected]


BIST VDD 1.8V 10%

2 : DDR2 SDRAM VIRTEX-5 2 Virtex-5 FPGA 250MHz DDR2 SDRAM BIST 1 BIST VREF

0FA5 0 1 (PRBS) BIST BIST BIST 2 ( DDR-II SRAMDDR2 SDRAM QDR-II SRAM) MIG FPGA FPGA PC FPGA FPGA BIST


3 BIST JTAG

1 : DDR-II SRAM VIRTEX-4 1 Virtex-4 FPGA 200MHz DDR-II SRAM BIST FPGA

Clock Generator& Reset

HostInterface

MIGCore

BISTHost Memory

FPGA

1 CORE Generator MIG FPGA

2 MIG



VREF VREF

3 : QDR-II SRAM Virtex-5 3 Virtex-5 FPGA 250MHz QDR-II SRAM 2 1 cal_done 2 BIST FPGA RTL FPGA ( ) MIG QDR-II SIM_ONLY 200 SIM_ONLY 0 200s 1 QDR-II K/K# CQ/CQ# K/K# CQ/CQ#

(PLL) K/K# CQ/CQ# FPGA PLL 20s K/K# SIM_ONLY K/K# PLL CQ/CQ#

BIST SIM_ONLY K/K# 200s SIM_ONLY SIM_ONLY SIM_ONLY

( PC ) FPGA ISE 3 FPGA 3 SIM_ONLY DesignVerify FPGA CPLD http://www.designandverify.com/

Visual Board Inspection

Check Power Supplies

JTAG Test Board

Check Clocks and Frequencies

Check FPGA Timing Closure

Check FPGA Reset Methodology

Run Built-In Self-Tests

Check Power Supplies During BIST

Run BIST Over Temperature

3



Nuts and Bolts of Designing an FPGA into Your Hardware

Adam TaylorPrincipal Engineer

EADS Astrium

[email protected]

FPGA


FPGA PCB FPGA HDL 1 2 FPGA

FPGA FPGA FPGA DSP

Spartan-6 LX Spartan-6 LXT I/O SRAM FPGA Spartan-3AN


PCB FPGA FPGA


FPGA DC/DC ( A/D D/A ) FPGA ISE XPower Analyzer


FPGA 0.9 1.5V FPGA http://www.origin.xilinx.com/prod-ucts/design_tools/logic_design/xpe.htm FPGA

FPGA

Config Memory NVRAM

Power Supplies

Core Voltage

I/O Voltages

Misc. Voltages

Ad

dress

Data

Co

ntro

l

Config

CANIF

RX Data

TX Data

Reset

Clock

Clock[7:0]

DisplayIF

Syncs

Red

Green

Blue

JTAG Connector

JTAG

Pixel Clock

1



PCB 0.1 (100kHz 1GHz ) (PSRR) PSRR

1 (PPM) +/-50PPM +/-100PPM A/D D/A A/D D/A S/N LVDS LVPECL LVCMOS LVTTL (EMI)

A/D D/A FPGA 2 DLLDCM PLL 1 1 3 FPGA ( )

IsolatingDC/DC

IP Voltage Switching Regulator

Switching Regulator

Switching Regulator

Intermediate

VoltageCore Voltage

I/O Voltage

Misc. VoltageLinear

Regulator

Reset Reset

2


( ) FPGA

FPGA ( ) PCB PCB CAD DXF

PCB PCB PCB PCB PCB 50 100

FPGA EMI FPGA ( SRAM FPGA RAM )FPGA


FPGA

I/O FPGA I/O I/O I/O FPGA I/O Mentor Graphics I/O Designer I/O PlanAhead I/O (HSSL) HSSL I/O

ClockSelection

Prime Clock

Redundant Clock

ClockFan-Out

Clock[0]

Clock[1]

Clock[2]

Clock[3]

Clock[4]

Clock[5]

Clock[6]

Clock[7]

PixelClock

Pixel Clock

3



PCB 4 PCB PCB


Voltage / Ground Plane




Micro Via and Breakout

Top (Component Mounting) Layer 1

Layer 2

Layer 3

Layer 4

Layer 5

Layer 6

Layer 7

Layer 8

Layer 9

Layer 10

Layer 11

Layer 12

Layer 13

Layer 14

Micro Via and Breakout

Bottom (Component Mounting)

50-OhmSingle-EndedSignals

50-OhmSingle-EndedSignals

100-OhmDierentialSignals

4 14 PCB

5 -- Virtex-5 DC

PCB 2 3 5 7 Mentor Graphics HyperLynx SI PI FPGA 5 FPGA PI

JTAG ( ) (m ) FPGA

FPGA DONE LED LED

ChipScope FPGA FPGA



1. FPGA : FPGA ( ) FPGA

2. : ( )

3. : FPGA

4. JTAG : FPGA JTAG JTAG

5. : FPGA

6. : PCI Express CANRS422 RS232

7. : FPGA A/D D/A

8. : ( SRAM) ( FRAM )

9. :

9

FPGA E-Learning I/O Architecture Wizard Foorplan Editor

VHDL

VHDL

Verilog System Verilog

Verilog

Vivado

VivadoFPGA

System Verilog

VivadoFPGA

S6

7

Chip Scope Pro

FPGA

AMS

Virtex-5 IPPCIe

IO

SimlinkMathWorks

C : Vivado HLS

SystemGenerator DSP

DSP

Zynq

Zynq

Zynq

Vivado FPGA

Linux

avnet.co.jp/design/training/

xilinx.shinko-sj.co.jp/training/index.html

ppg.teldevice.co.jp/

www.paltek.co.jp/seminar/index.htm

Japan.xilinx.com/training/

I/O SoC

() TEL(045)443-4016 [email protected] () TEL(03)5792-8210 [email protected] () TEL(045)477-2005 [email protected]() TEL(03)6361-8086 X-Proshinko-sj.co.jpCopyright 2013 Xilinx, Inc. All rights reserved. ARMEUARM Limited

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