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THE AUTHORITATIVE JOURNAL FOR PROGRAMMABLE LOGIC USERS Issue 49 Summer 2004 R Xcell journal Xcell journal THE AUTHORITATIVE JOURNAL FOR PROGRAMMABLE LOGIC USERS ISSUE 49, SUMMER 2004 XCELL JOURNAL XILINX, INC. COVER STORY Celebrating 20 Years of Leadership COVER STORY Celebrating 20 Years of Leadership Designing High-Speed Serial Links Designing High-Speed Serial Links SIGNAL INTEGRITY Issues, Tools, and Methodologies High-Speed Interconnect Debugging MGT Designs Power Distribution Networks BACKPLANES Next-Generation Serial Backplanes Create ATCA-Compliant Designs Mesh Fabric Switching DSP XtremeDSP Kit-II Increase Image Processing System Performance Low-Cost Co-Processing SIGNAL INTEGRITY Issues, Tools, and Methodologies High-Speed Interconnect Debugging MGT Designs Power Distribution Networks BACKPLANES Next-Generation Serial Backplanes Create ATCA-Compliant Designs Mesh Fabric Switching DSP XtremeDSP Kit-II Increase Image Processing System Performance Low-Cost Co-Processing

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Page 1: Xcell Journal Issue 49

T H E A U T H O R I T A T I V E J O U R N A L F O R P R O G R A M M A B L E L O G I C U S E R S

Issue 49Summer 2004

R

Xcell journalXcell journalT H E A U T H O R I T A T I V E J O U R N A L F O R P R O G R A M M A B L E L O G I C U S E R S

ISSUE 49, SUMM

ER 2004XCELL JOURNAL

XILINX, INC.

COVER STORYCelebrating 20 Years of Leadership

COVER STORYCelebrating 20 Years of Leadership

Designing High-SpeedSerial Links

Designing High-SpeedSerial Links

SIGNAL INTEGRITY

Issues, Tools, andMethodologies

High-Speed Interconnect

Debugging MGT Designs

Power DistributionNetworks

BACKPLANES

Next-Generation SerialBackplanes

Create ATCA-CompliantDesigns

Mesh Fabric Switching

DSP

XtremeDSP Kit-II

Increase Image ProcessingSystem Performance

Low-Cost Co-Processing

SIGNAL INTEGRITY

Issues, Tools, andMethodologies

High-Speed Interconnect

Debugging MGT Designs

Power DistributionNetworks

BACKPLANES

Next-Generation SerialBackplanes

Create ATCA-CompliantDesigns

Mesh Fabric Switching

DSP

XtremeDSP Kit-II

Increase Image ProcessingSystem Performance

Low-Cost Co-Processing

Page 2: Xcell Journal Issue 49

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©2004 Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124. Europe +44-870-7350-600; Japan +81-3-5321-7711; Asia Pacific +852-2-424-5200; Xilinx is a registered trademark, Spartan and XtremeDSP are trademarks, and The Programmable Logic Company is a service mark of Xilinx, Inc.

Page 3: Xcell Journal Issue 49

AAs I was preparing to write this editorial, I asked myself: “What did I do in the past that was relativelysimple then, but has gotten vastly more complicated now?” The answer was tuning up a car’s engine.

I’ve always liked cars. As a teenager, I would get together with my buddies on weekends to extractthe finest performance from our machines. We lived for the automotive trinity: high speed, loudsounds, and great looks.

I remember replacing the spark plugs, which were factory-set to a gap clearance specific to my car’sengine. However, this factory setting was rarely correct. If the gap was too wide, I tapped the end ofthe spark plug on the garage floor and remeasured. If it was too tight, I used a screwdriver to spreadopen the electrode, widening the gap.

Tuning up a car’s engine used to be quite easy. I wasn’t concerned with tight tolerances – close wasgood enough. But advances in automotive technology have made it virtually impossible for me towork on my car anymore.

Similarly, advances in PCB technologies pose far more difficult engineering challenges today thanthey did just a short time ago. Feature size reduction, market demands, and the need for reducedpower consumption have driven core voltages down and operating frequencies up. These changes insignal voltage and frequency require new design practices that take into account electrical effects thatcould previously be ignored.

This issue features a section on signal integrity issues, tools, and methodologies pertaining to high-speed PCB design. We also have a section on end-to-end programmable solutions for line cards andhigh-speed serial backplanes. Together with many of our partners, Xilinx is addressing these issues tohelp you resolve the technical difficulties that affect performance, system development, and productintroduction schedules.

As the new Managing Editor for Xcell, I’d like your feedback on the signal integrity series in thisissue, as I endeavor to continually improve the magazine. Please visit our website atwww.xilinx.com/si_xcell.htm, where you will find a short survey form.

L E T T E R F R O M T H E E D I T O R

Xilinx, Inc.2100 Logic DriveSan Jose, CA 95124-3400Phone: 408-559-7778FAX: 408-879-4780©2004 Xilinx, Inc.All rights reserved.

Xcell is published quarterly. XILINX, the Xilinx logo,CoolRunner, RocketChips, Rocket IP, Spartan, StateBENCH,StateCAD, Virtex, Virtex-II, and XACT are registered trade-marks of Xilinx, Inc. ACE Controller, ACE Flash, AllianceSeries, AllianceCORE, Bencher, ChipScope, ConfigurationLogic Cell, CORE Generator, CoreLINX, Dual Block, EZTag,Fast CLK, Fast CONNECT, Foundation, Gigabit Speeds…andBeyond!, HardWire, HDL Bencher, IRL, J Drive, Jbits, LCA,LogiBLOX, Logic Cell, Logic Professor, MicroBlaze, MicroVia,MultiLINX, NanoBlaze, PicoBlaze, PLUSASM, PowerGuide,PowerMaze, QPro, Real-PCI, RocketIO, RocketPHY, SelectIO,SelectRAM, SelectRAM+, Silicon Xpresso, Smartguide,Smart-IP, SmartSearch, SMARTswitch, System ACE, TestbenchIn A Minute, TrueMap, UIM, VectorMaze, VersaBlock,VersaRing, Virtex-4, Virtex-II Pro, Virtex-II Pro X, Virtex-IIEasyPath, Wave Table, WebFITTER, WebPACK,WebPOWERED, XABLE, XAPP, X-BLOX+, XC designated prod-ucts, XChecker, XDM, XEPLD, Xilinx Foundation Series, XilinxXDTV, Xinfo, XtremeDSP, and ZERO+ are trademarks, andThe Programmable Logic Company is a service mark ofXilinx, Inc. Other brand or product names are registeredtrademarks or trademarks of their respective owners.

The articles, information, and other materials included inthis issue are provided solely for the convenience of ourreaders. Xilinx makes no warranties, express, implied,statutory, or otherwise, and accepts no liability with respectto any such articles, information, or other materials ortheir use, and any use thereof is solely at the risk of theuser. Any person or entity using such information in anyway releases and waives any claim it might have againstXilinx for any loss, damage, or expense caused thereby.

Close Isn’t Good Enough Anymore

Xcell journalXcell journal

Forrest CouchManaging Editor

EDITOR IN CHIEF Carlis [email protected]

MANAGING EDITOR Forrest [email protected]

ASSISTANT MANAGING EDITOR Charmaine Cooper Hussain

XCELL ONLINE EDITOR Tom [email protected]

ADVERTISING SALES Dan Teie1-800-493-5551

ART DIRECTOR Scott Blair

Page 4: Xcell Journal Issue 49

For Synchronous Signals, Timing Is EverythingMentor Graphics highlights a proven methodology forimplementing pre-layout Tco correction and flight timesimulation with Virtex-II and Virtex-II Pro FPGAs.

T A B L E O F C O N T E N T S

High-Speed PCB Design: Issues, Tools, and MethodologiesIn this series on signal integrity, Xcell explores tools andmethods you can use to combat signal and power integritydistortions throughout product development.

Celebrating 20 Years of LeadershipCelebrating 20 Years of Leadership

When the Xilinx founders created their first business plan in 1984, they agreed on a lofty goal: “To be the leading company designing, manufacturing, marketing, and supporting user-configurable logic arrays for the application-specific market.”

58C O V E R S T O R Y

9

58

The Next Gold StandardThe Advanced Telecom Compute Architecture standardhas great potential for widespread adoption in next-generation infrastructure applications.

66

16

Page 5: Xcell Journal Issue 49

Secure Your ConsumerDesign with CoolRunner-II CPLDsCoolRunner-II CPLDs offer unique features to ensure a more secure design and reduce the risk of reverse engineering. 92

Create ATCA-CompliantDesigns Xilinx and Avnet have released a new design kit that reduces time to market for a wide range of serial backplane applications.

65

S U M M E R 2 0 0 4, I S S U E 4 9 Xcell journalXcell journalBackplane CharacterizationTechniquesHigh-bandwidth measurements of backplane differential channels are critically important for all high-speed serial links.

31

Better... Stronger...FasterVirtex-II Pro FPGAs offer marked performance advantages over a competing device.

53

Celebrating 20 Years of Leadership . . . . . . . . . . . . . . . . . . . .6

High-Speed PCB Design: Issues, Tools, and Methodologies . . . . .9

Interfacing SMA Connectors to Virtex-II Pro MGTs . . . . . . . . . .12

For Synchronous Signals, Timing Is Everything . . . . . . . . . . . .16

Designing High-Speed Interconnects for FPGAs . . . . . . . . . . . .20

Accurate Multi-Gigabit Link Simulation with HSPICE . . . . . . . .24

Eyes Wide Open . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Backplane Characterization Techniques . . . . . . . . . . . . . . . . .31

A Low-Cost Solution for Debugging MGT Designs . . . . . . . . . .36

Tolerance Calculations in Power Distribution Networks . . . . . . .40

High-Speed PCB Design Resources . . . . . . . . . . . . . . . . . . . .44

The FPGA Dynamic Probe . . . . . . . . . . . . . . . . . . . . . . . . . .47

Xilinx 6.2i Design Tools . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Better ... Stronger ... Faster . . . . . . . . . . . . . . . . . . . . . . . .53

The Next Gold Standard . . . . . . . . . . . . . . . . . . . . . . . . . . .58

Next-Generation Serial Backplanes . . . . . . . . . . . . . . . . . . . .62

Create ATCA-Compliant Designs . . . . . . . . . . . . . . . . . . . . . .65

Ethernet Aggregation with GFP Framing in Virtex-II Pro . . . . . .68

Mesh Fabric Switching with Virtex-II Pro FPGAs . . . . . . . . . . .71

Programming Flash Memory Using the JTAG Port . . . . . . . . . .77

Developing the New Platform Flash PROM . . . . . . . . . . . . . .80

Accelerate and Verify Algorithms with XtremeDSP Kit-II . . . . . .82

Increase Image Processing System Performance with FPGAs . .85

Enabling Low-Cost DSP Co-Processing with Spartan-3 FPGAs . .88

Secure Your Consumer Design with CoolRunner-II CPLDs . . . . .92

Improving Synplify Pro Performance for FPGA Designs . . . . . .94

Virtex-II and Spartan-3 Aid Wireless Control Networking . . . . .97

Creating Pb-Free Packaging . . . . . . . . . . . . . . . . . . . . . . . .100

TechXclusives: A Valuable Source of Information . . . . . . . . . .104

Reference Pages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109

To subscribe to the Xcell Journal or to view the web-based Xcell Online Journal, visit www.xilinx.com/publications/xcellonline/.

Page 6: Xcell Journal Issue 49

By Xilinx Staff

In 1984 when Xilinx was founded, config-urable logic arrays were viewed as exoticcuriosities, the semiconductor industry wasmired in a slump, and the personal computer– destined to become the driving force in sili-con consumption – had just been introducedto skeptical reviews. That’s why many peoplethought that Xilinx founders Ross Freeman,Bernie Vonderschmitt, and Jim Barnett wereoverly ambitious with their written missive.But the driving force in their plans was thegoal of leadership – that sometimes vague,often elusive goal that all high technologycompanies seek but few ever attain.

Today, everyone in the industry knowsthat the Xilinx founders made good on theirpromise. As we enter our third decade as thepreeminent supplier of programmable logicdevices (owning more than 50 percent of themarket), we increasingly find that our tech-nology is the preferred choice for most digitallogic designs. By almost any definition, Xilinxis setting a new standard for success.

Indeed, today’s stated vision makes ourfounding fathers’ objective seem comparativelytame. As Xilinx celebrates its 20th year inbusiness, our market leadership is unques-tioned and our current goal stretches far intouncharted territory: “To put a programmabledevice in every piece of electronic equipmentwithin the next 10 years.” This guiding prin-ciple is etched into the mind of every Xilinx

Celebrating 20 Years of Leadership

Xilinx CEO Wim Roelandts in the Xilinx Hall of Patents.

6 Xcell Journal Summer 2004

When the Xilinx founders created their first business plan in 1984,they agreed on a lofty goal: “To be the leading company designing,manufacturing, marketing, and supporting user-configurable logicarrays for the application-specific market.”

Page 7: Xcell Journal Issue 49

employee around the world, and is theemotional force behind the steady streamof innovation and operational excellencefor which Xilinx is known.

Leadership Starts from WithinTalk to our CEO Wim Roelandts aboutleadership, and you won’t hear a lot aboutmarket share dominance, a litany of indus-try firsts, or impressive statistics that typifymost companies’ definitions of what itmeans to be a leader. Instead, Wim speakspassionately about core values, manage-ment philosophy, corporate culture, andbuilding a legacy. That’s why the secondXilinx company goal is: “To build a compa-ny that sets a new standard for managinghigh-tech companies.” Xilinx was namedThe Best Managed SemiconductorCompany by Forbes magazine in 2004, justone indicator that this goal is now a reality.

Wim’s own style draws upon his years ofexperience at Hewlett-Packard, somethingof a high-tech pioneer itself in terms of cor-porate culture with its legendary “HP Way.”But he makes it clear that his team’s goal forXilinx is a new, unique style of management:one that combines the best of traditionalhard-driving, top-down, win-at-all-costsapproaches with “softer,” consensus-orient-ed, people-centric models. And he insistsyou can have the best of both worlds. “Wehave a culture where people are treated withrespect, where there is consensus manage-ment, and still we are a leader. How do wedo it? Through innovation! We have aprocess that fosters innovation, and withinnovation comes leadership.”

VP of Human Resources Peg Wynndescribes the competitive attitude at Xilinxlike this: “We’re fierce competitors withhearts of gold.” That competitive attitudehas led to no shortage of innovation andindustry firsts at Xilinx during its first 20years, as more than 900 patents attest. Sucha record of achievement is the result of awell-thought-out process to inspireemployees to greatness, with a business

well as earn us a top-10 rating in Fortunemagazine’s “Best Places To Work” for thelast four years.

Innovation and LeadershipXilinx has put the structure in place tomake all employees and partners success-ful. It begins with focus. From our incep-tion in 1984, Xilinx strategy has relied ona partnership model through which wedevelop mutually beneficial relationshipswith experts in manufacturing, sales, andother activities that are impractical for usto do ourselves. For example, companyfounder Bernie Vonderschmitt essentiallyinvented the fabless semiconductor modelon a handshake agreement with Seiko in1984. That agreement saw the first Xilinx-designed chips roll off the manufacturinglines at Seiko’s plants. Today, Xilinx relies– and in fact, drives forward – our manu-facturing partners as we reach new mile-stones together.

Since 1984, Xilinx has developed anextensive and growing “ecosystem” of part-nerships for a wide variety of needs. Wepartner with experts in sales, design tools,intellectual property cores, and chip designservices – a strategy that has allowed anunwavering focus on our own areas of corecompetence: designing, marketing, andsupporting our programmable chips. “Youcan only be a leader in a few areas so youhave to define where you want to be aleader and use partners to complementwhat you do,” says Wim. “We want to bea leader in technology and in innovation.To do that, we need partners and therealways has to be something in it for thepartner – it has to make them better. Ourphilosophy on partnerships is that itshould minimally be a ratio of 51 to 49, infavor of our partner.”

The Xilinx track record of innovation isimpressive. Since inventing the FPGA in1984, Xilinx has progressively achievednew technological milestones ahead of itscompetition, and set new standards for

model that allows the company to focus onwhat it does best.

A Holistic Management PhilosophyXilinx leadership is based on its ability tocontinuously innovate. Therefore, its man-agement philosophy is based on simpletenets:

• People want to do a good job and theycome to Xilinx to do their best work

• Work has to have meaning and value

• The company must provide a sense of community

• There must be an opportunity for personal growth

• Everyone should be an owner.

Because of this, a rare team attitudeexists at Xilinx that is not often found inthe hallways and meeting rooms of otherhigh-technology companies. It mesheswith a sense of quiet confidence that per-vades the company. In fact, about theonly “leadership” statistic that Wim likesto spend any time discussing is anemployee retention percentage that is theenvy of the industry. “We have set thestandard for employee turnover in ourindustry. It’s something like five or sixpercent, compared to an average in themid 20s in our business.”

Wim talks a lot about the importance ofwalking the talk, or as he puts it, “main-taining consistency and credibility” withthe employee base as well as with the com-pany’s other stakeholders: partners, cus-tomers, and shareholders. It’s one reasonwhy he is fanatical about returning e-mailsfrom employees, and moves his office everyyear to a new location “to get a differentperspective on the company.” Such an atti-tude underpins a sense of values andintegrity that has led Xilinx to be voted the“Most Respected Public Company” by itspeers in the Fabless SemiconductorOrganization (FSA) two years in a row, as

Summer 2004 Xcell Journal 7

Since inventing the FPGA in 1984, Xilinx has progressively achieved new technological milestones ahead of its competition.

Page 8: Xcell Journal Issue 49

semiconductor design. Most recently, wewere the first to produce productiondevices in 90 nm process geometries. Alongwith Intel™, we are also producing themost chips on state-of-the-art 300 mmwafers – both testaments to the designprowess of our engineering teams. Notcontent to rest on our laurels or followtrends, Xilinx management proudly pointsto the ratio of employees working on futurebusiness activities: about three-quarters ofthe company.

“Being a leader means taking risks,” saysVP of Marketing Sandeep Vij. “And theculture here at Xilinx rewards risk-taking.The whole concept behind our technology– programmability – was based on a giant

risk by the founders. That’s what inspiresinnovation. Because of the way we are setup, every employee feels like an owner,people feel like they are part of a team;they’re part of something beyond an indi-vidual contribution.” And with innovationcomes leadership, although it’s not alwaysan overnight effect.

In fact, Sandeep looks at the first 20years of Xilinx in two distinct phases.First was the decade that saw the first fewgenerations of products take shape; mar-ket adoption of programmable technolo-gy happened on a gradual basis. Nextcame the decade when Xilinx productsbecame more mainstream; new mile-stones were reached – including one mil-lion devices shipped, one billiontransistors on a chip, and $1 billion inrevenue. “Leadership is different thanbeing a winner,” Sandeep notes. “In ourview of the world, there can be more thanone winner – in fact, that’s required

because we want our partners to win too.There are a lot of intangibles in being aleader. A leader evokes respect. A leaderinspires people to follow. A leader has tolook at what’s happening today and see itsimpact on the future. That’s what thefounders of Xilinx did 20 years ago, andthat’s what we must continuously do now.”

Leading the Way to the FutureWim likes to call Xilinx a reconfigurablecompany, a tribute not just to the innovativetechnology the company delivers to a widerange of electronics companies, but also tothe flexible management style that he sees asessential to survival in high technology. “Thechallenge is in keeping Xilinx nimble andresponsive. Every day we change. Whetherit’s the technology, a business process, or ourgeographical focus, we have to be comfort-able with change. And we have to continueto re-innovate from within.” What elsewould you expect from the company thatinvented programmable chips?

Original Xilinx MissionStatement 1984

To be the leading company designing, manufacturing, marketing, and supporting

user-configurable logic arrays for the application-

specific market.

Xilinx’s strategies to be the leading company are:

1. Maximize our strengths in product architecture and design

2. Complement our strengths witha long-term fab partner who hashigh quality, high volume, com-petitive cost capability, and state-of-the-art process technology

3. Provide a logic solution that is easier to design-in and morecost-effective than SSI/MSI, PALS,and gate arrays with densities of4,000 to 5,000 unit cells

4. Provide support for all user volumes with both softwired and hardwired products

5. Develop and support design tools to minimize the customer’sdesign efforts

8 Xcell Journal Summer 2004

Page 9: Xcell Journal Issue 49

by Suresh Sivasubramaniam Senior Design EngineerXilinx, [email protected]

Philippe GarraultTechnical Marketing EngineerXilinx, [email protected]

RocketIO™ transceivers are a standard fea-ture on the most advanced Xilinx FPGAs.Our first-generation transceivers operate inthe 1-3.125 Gbps bandwidth, while the lat-est generation transceivers have an operat-ing bandwidth of up to 10 Gbps.

These data rates mean that bit periodand signal rise and fall times are extremelysmall. Designing physical links/channelson a PCB for these high-speed deviceswith small amplitude and timing budgetsnecessitates a careful analysis of the possiblesignal integrity (SI) and power integrity(PI) distortions.

SI/PI issues and reduced amplitude andtiming budgets are not limited to just high-speed serial links. In recent years, theamount of logic cells inside Xilinx deviceshas grown tremendously. Additionally, thepin count on device packages has gone froma few to more than a thousand. IncreasedI/O performance, in conjunction with thelarge number of I/Os available, means thatfor each of your new designs, a lot moretransistors are switching more often.

High-Speed PCB Design:Issues, Tools, and Methodologies

High-Speed PCB Design:Issues, Tools, and Methodologies

Summer 2004 Xcell Journal 9

In this series on signal integrity, Xcell explores tools and methods you can use to combat signal and power integrity distortions throughout product development.

In this series on signal integrity, Xcell explores tools and methods you can use to combat signal and power integrity distortions throughout product development.

Table of Contents:

Ten Reasons Why Performing SI Simulations is a Good Idea . . . . . . . 11

Interfacing SMA Connectors to Virtex-II Pro MGTs . . . . . . . . . . . . . . . 12

For Synchronous Signals, Timing Is Everything . . . . . . . . . . . . . . . . . 16

Designing High-Speed Interconnects for High-Bandwidth FPGAs. . . . . . 20

Accurate Multi-Gigabit Link Simulation with HSPICE. . . . . . . . . . . . . . 24

Eyes Wide Open . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Backplane Characterization Techniques . . . . . . . . . . . . . . . . . . . . . . 31

A Low-Cost Solution for Debugging MGT Designs . . . . . . . . . . . . . . . 36

Tolerance Calculations in Power Distribution Networks . . . . . . . . . . . . 40

High-Speed PCB Design Resources . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table of Contents:

Ten Reasons Why Performing SI Simulations is a Good Idea . . . . . . . 11

Interfacing SMA Connectors to Virtex-II Pro MGTs . . . . . . . . . . . . . . . 12

For Synchronous Signals, Timing Is Everything . . . . . . . . . . . . . . . . . 16

Designing High-Speed Interconnects for High-Bandwidth FPGAs. . . . . . 20

Accurate Multi-Gigabit Link Simulation with HSPICE. . . . . . . . . . . . . . 24

Eyes Wide Open . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Backplane Characterization Techniques . . . . . . . . . . . . . . . . . . . . . . 31

A Low-Cost Solution for Debugging MGT Designs . . . . . . . . . . . . . . . 36

Tolerance Calculations in Power Distribution Networks . . . . . . . . . . . . 40

High-Speed PCB Design Resources . . . . . . . . . . . . . . . . . . . . . . . . . 44

www.xilinx.com/si_xcell.htm S I G N A L I N T E G R I T Y

Page 10: Xcell Journal Issue 49

Additional requirements for the effi-cient design of high-speed buses may bedictated by the needs of a specific applica-tion. For example, a 266 MHz, 64-bitDDR RAM interface will be sensitive toskew between the different byte lanes.Large parallel buses also have the potentialto generate simultaneous switching output(SSO) noise and voltage droop. All of thesefactors translate into the need to manage thetransient current demands of a particularapplication through proper design of thepower distribution system (PDS).

Resistance, Inductance, and Capacitance Pull the StringsIn general, SI and PI issues arise whendesigners pay inadequate attention to thesebroad categories:

• Termination schemes

• Skin effect (frequency-dependentattenuation)

• Dielectric losses

• Impedance discontinuities/reflections

• Data coding (DC balanced codes, runlength, channel memory)

• Equalization/pre-emphasis

• Inter-symbol interference

• Crosstalk

• Decoupling/bypassing in power distribution

• Board stack-up

• Signal edge rates.

The common denominator in theseproblems is poor management of the three“bad boys” of electric circuits: resistance,inductance, and capacitance (Figure 1). Inaddition, you must understand andemploy the right measurement tech-niques in the lab to accurately measureand validate designs against simulationsor design specifications.

Bill Hargin believes that “ForSynchronous Signals, Timing IsEverything.” His article outlines a methodfor extracting correction values that can beapplied to the clock-to-out and flight timenumbers. The resulting timing values inthe datasheet are representative of the actu-al load and topology of your design. Thistechnique specifically applies to source-synchronous links.

Predicting the interconnect perform-ance of high-speed links made of complexvia, connector, and trace structures is noeasy task. However, as Ansoft’s LawrenceWilliams explains in “Designing High-Speed Interconnects for High-BandwidthFPGAs,” combining electromagnetic, cir-cuit, and system simulations greatly helpsin the design of reliable and fast data trans-mission channels.

When designing multi-gigabit asynchro-nous channels, you must carefully analyzethe link’s physical and electrical properties.In his article, “Accurate Multi-Gigabit LinkSimulation with HSPICE,” Dr. ScottWedge explains how the combination of anEM solver, coupled transmission lines, S-parameter support, and SPICE and IBISmodeling to the HSPICE® circuit simula-tor helps accurately account for high-speedsignal distortions.

With “Eyes Wide Open,” Steve Bakershows you how to use the RocketIO DesignKit for ICX™ to evaluate pre-layoutoptions (such as placement, connectors, orstackup) as well as post-layout options (suchas detailed routing structures) to achievehigh-speed serial link performance.

As much as Xilinx recommends SI simu-lation and analysis before manufacturing aPCB, there are two very valuable lab instru-ments that you can use on prototype/explo-ration boards. With these instruments, youcan characterize interconnect properties andhigh-speed signal behavior, explore differenttopology performances, or extract simula-tion models. In his article, “Backplane

The objective is to build systems rightthe first time.

Minimize SI/PI EffectsIn this special series on signal integrity, wehave assembled articles that will provide youwith practical and technical resourcestowards achieving that goal. From character-ization and model extraction techniques inthe lab to methods for simulating signaldegradations of synchronous parallel/asyn-chronous serial systems to case studies, thisseries covers many aspects of SI.

In a sidebar to this article, XilinxPrincipal Engineer Austin Lesea lists “TenReasons Why Performing SI Simulations isa Good Idea.” Although this may soundvery familiar to some of you, understand-ing the benefits of performing SI analysisthroughout the design cycle can help youachieve your performance, reliability, andtime-to-market goals.

“Interfacing SMA Connectors toVirtex-II Pro MGTs” details Warren Millerand Vince Gavagan’s experience designingthe interface between Virtex-II Pro™multi-gigabit transceivers (MGTs) and SubMiniature version A (SMA) connectors forthe Virtex-II Pro Aurora Design Kit.Through prototyping and time domainreflectometry (TDR) measurements, theyillustrate how SMA connector choice influ-ences signal quality.

Figure 1 – The three bad boys of electric cir-cuits (Courtesy of Educator’s Corner/AgilentTechnologies)

The common denominator in these problems is poor management of the three“bad boys” of electric circuits: resistance, inductance, and capacitance.

10 Xcell Journal Summer 2004

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Summer 2004 Xcell Journal 11

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Characterization Techniques,” Eric Bogatinexplains the need for making measurements,illustrating the concept of measurement andmodel bandwidth. He also discusses SMAlaunches, information contained in TDRtraces, and differential S-parameters.

In “A Low-Cost Solution for DebuggingMGT Designs,” Joel Tan presents a solu-tion comprising a bit-error rate testingmodule connected to a flexible on-chiplogic analyzer core, both implemented inFPGA fabric. Together with theChipScope™ Pro software suite, these two

components allow you to perform diagnos-tic testing, debugging, and development ofan MGT system without the use of expen-sive lab equipment such as logic analyzersand BERT testers.

And in “Tolerance Calculations in PowerDistribution Networks,” Sun Microsystems’Istvan Novak walks you through differentscenarios of bypass capacitor configurationsto demonstrate the importance and influ-ence of the capacitors’ technology, value, andnumber in designing a decoupling/powerdistribution network.

ConclusionWe hope you will find in this seriesinstructive material on the sources ofSI/PI effects, along with practical infor-mation about the resources and toolsavailable to you. Our experience tells usthat careful simulations, analysis, andmeasurements of PI and SI effects early inthe design process guarantees first-timesuccess more often than not.

If you’d like to send us feedback aboutthe topics discussed, please e-mail us at [email protected]

by Austin LeseaPrincipal Engineer, Advanced Products GroupXilinx, Inc.

Not so long ago, the rise and fall times ofsignals, the coupling from one trace toanother, and the de-coupling of powerdistribution on a PCB were tasks thatwere routinely handled by a few simplerules. Occasionally, you might use theback of an envelope, scribbling down afew equations to make sure that thedesign would work.

Those days are gone forever. Sub-nanosecond, single-ended I/O rise andfall times, 3 to 10 Gb transceivers, andtens of ampere power needs at around 1Vhave all led to increased engineeringrequirements.

Your choice is simple: simulate nowand have a working result on the firstPCB, or simulate later after a series offailed boards. The cost of signal integritytools more than outweighs the cost ofmaking the board over and over with suc-cessive failures.

In keeping with the theme of this spe-cial issue, here are my 10 best reasons whysignal integrity engineering is a good idea:

1. You’re tired of making PCBs over and over and still not having them work.

Seriously, without simulating all signals, aswell as power and ground, you risk makinga PCB that will just not work. IR (voltage)drop, inadequate bypassing or de-coupling,crosstalk, and ground bounce are just a fewof the possible problems.

2. You’re tired of being late to market andwatching your competition succeed.

Every time you have to fix a problem witha PCB, it necessitates a new or changed lay-out, a new fabrication, and another assemblycycle. It also requires the re-verification of allparameters. Taking the time to do thesethings right has both monetary and competi-tive advantages.

3. You’re tired of spending all this money, only to scrap the first three versions of PCBs and all of the components that went with them.

See reason number two.

4. Your eye pattern is winking at you.

If the eye pattern of a high-speed serial linkis closing, or closed, it’s likely that the linkhas a serious problem and will have dribblingerrors – or worse, will be unable to synchro-nize at all. You must simulate every elementof the design to assure an error-free channel.

5. All 1s or all 0s suddenly breaks the system.

Unfortunately, many systems do not have achoice of what data may be processed. Oftenthe data pattern will create conditions that, ifnot simulated a priori, will cause errors inthe system.

6. Hot and cold, fast and slow, and high and low voltages cause failures.

Without simulating the “corners” of the sil-icon used as well as the environmental fac-tors, you’re playing Russian Roulette withfive of the six chambers loaded.

Ten Reasons Why Performing SI Simulations is a Good Idea7. You cannot meet timing, and you

are unable to find out why.

Poor signal integrity is the primary causeof adding jitter to all signals in a design.Ground bounce, crosstalk, and reflectionsall conspire to add jitter. And once added,jitter is virtually impossible to remove.

8. The FCC Part 15 or VDE EMI/RFItest fails every time you test a board.

Radiated and conducted radio frequencyemissions, as well as susceptibility to radiofrequency sources, is a sign of poor SIpractices. Fixing the problem by shieldingincreases the system cost substantially, andmay not even be possible in extreme cases.

9. Customers complain, but when youget the boards back, you don’t findany problems.

One of the biggest problems with SI isthat the errors and failures observed are dif-ficult to correlate and sometimes impossi-ble to find. Was it a problem with voltage,temperature, or with the data pattern itself?It might have been someone turning lightson and off (ground disturbance). Don’t riska return that cannot be fixed.

And last, but certainly not the least:

10. Your manager has suggested thatyou look for other employment.

Do not let this happen to you. Stay cur-rent, educated, and productive. Get theright tools to do the job. Realize that signalintegrity engineering is a valuable and irre-placeable skill in great demand in today’sdesign environments.

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by Warren MillerVP of Marketing [email protected]

Vince GavaganDesign [email protected]

While designing the Avnet Design ServicesVirtex-II Pro™ 3.125 Gbps Aurora DesignKit, we found that there were a variety ofoptions for the interface between theVirtex-II Pro multi-gigabit transceivers(MGTs) and the SubMiniature version A(SMA) connectors on the board. After try-ing a few of these options and measuringthe results on the prototype board, we dis-covered that the signal integrity perform-ance of the interface varied widelydepending on the type of SMA connectorused, the location, and characteristics of theboard traces.

In this article, we’ll review several specif-ic design options and their impact on signalintegrity. Our test results will show why thefinal “optimal” design was selected. We’llalso provide detailed measurements on thesignal integrity of the final design.

Interfacing SMA Connectorsto Virtex-II Pro MGTsInterfacing SMA Connectorsto Virtex-II Pro MGTs

12 Xcell Journal Summer 2004

SMA connector choice has a surprising effect on signal integrity.SMA connector choice has a surprising effect on signal integrity.

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Avnet Virtex-II Pro Aurora Design KitThe Aurora Design Kit includes the AvnetDesign Services Virtex-II Pro evaluationboard and its associated documentation,board support package, applications code,and example designs. The Aurora referencedesign has been ported to the board; anexample design communicating betweenserial ports at 3.125 Gbps demonstrates thefeatures and capabilities of the design kit.The circuit board used in the design kit isshown in Figure 1.

The hardware features of the evaluationboard include the user FPGA, on-boardmemory, on-board communications,expansion, and configuration. A completeblock diagram of the board’s hardwarecomponents is shown in Figure 2.

The user FPGA is a Virtex-II ProXC2VP7-FF896 device that includes anembedded PowerPC™ processor, eighthigh-speed serial I/O channels, andRocketIO™ MGTs.

The high-speed communications func-tions of the board include eight SMA con-nectors (TX/RX pairs for two RocketIOports) with board-configurable loop-backfor two RocketIO transceivers and pads forfour additional RocketIO ports.

The connectors featured on boardinclude two 140-pin general-purpose I/Oexpansion connectors (AvBus), up to 30LVDS pairs, and a standard 50-pin 0.1-inch header for custom expansion.

You can configure the FPGA via twoXilinx XC18V04-VQ44 PROMs, aParallel IV cable for JTAG, and fly-wiresupport for Parallel-III and Multilinx™configuration cables.

Mictor™ connectors are available toaccess the remaining high-speed I/O sig-nals (MGTs) on the device for test or char-acterization.

Prototype DesignWhen we first received the prototypedesign from the manufacturing house, wetested the MGT-to-SMA connections. Inpreliminary testing, we used a loop-backconnection over an SMA cable from oneMGT to another. No FR4 of significantlength was inserted.

Test packets were simple 00 to FF datawords (256 bytes) with idle sequences(k28.5, d21.4, d21.5, d21.5) betweenpackets. We captured eye diagrams usingthe repeating idle sequence (Figure 3).Although the eye opening is fairly clean,the pattern is a repeating idle sequence andthus doesn’t provide a very extensive test.

During our initial prototype testing, wesent several thousand packets successfully.However, testing additional boards

Memory includes Micron™ DDRSDRAM (64 MB) for use as code storagespace for the PowerPC and packet storagefor serial I/O ports. Communication canalso occur over a standard RS-232 serialport for simple monitor or debug functions.

An included 5.0V AC/DC power supplyprovides up to 22.5W for the on-board TexasInstruments™ 3.3V 6A module andNational Semiconductor™ linear regulators.

Summer 2004 Xcell Journal 13

Clocks(4)

AVBus

Power SupplyTexas Instruments

PT5401ANational Semiconductor

LP3961ELP3966ELP2995M

SMA(4)

SMA(4)

PPC Debug

P4 JTAG

Config/JTAG

Proms18V04(2)

MicronDDR SDRAM

(64 MB)MT46V16M16 (2)

Console

50-pin Header

LED 7 –Seg

Mictor Pads

LEDs(8)

Switches(8)

ConfigurableLoop-back

Rocket IO

Rocket IO

181 I/O68 I/O

4 I/O

47 I/O

32

Virtex-II ProXC2VP7-FF896

Figure 1 – The Avnet Virtex-II Pro evaluation board. The eight SMA connectors are located in the upper middle of the board, very close to the FPGA.

Figure 2 – Block diagram of the Aurora Design Kit circuit board

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revealed that performance was not repeat-able, and in fact was much worse for themajority of boards. Because these initialboards used -5 speed grade parts, we sur-mised that the errors could be attributed tothe 2.0 Gbps limitation of the -5 speedgrade devices.

Yet procurement of -6 speed grade partsrevealed that this was not the case; a sub-stantial number of errors continued tooccur. Because the design includes twoRocketIOs that are looped back via FR4 onthe board in addition to the SMA break-out, we repeated the test using the non-SMA loop-back. These tests yieldedsubstantially better results. In fact, the non-SMA loop-back was capable of 3.125 Gbpswith identical payload and zero errors.

During these tests, we performed TimeDomain Reflectometry (TDR) on theboard as well, with results shown in

Figure 4. After reviewing these results, weconcluded that although the boardimpedance was matched very well, asevere impedance mismatch existed at theSMA connectors.

This information suggested we shouldlook more closely at the layout, and we

determined that during thedesign phase, a stub was over-looked. As the FPGA and SMAsboth reside on the top (compo-nent) side of the PCB, and thetraces are also on layer one (a 100Ohm differential impedancemicro-strip), a stub is created atthe through-hole SMA.

Prior to a board spin, twoboards were used to test the theory.Testing unmodified boards with15 inches of FR4 (using an FR4characterization board) yielded thefollowing results:

We modified the poorer performingboard by cutting the through-hole stubprotruding from the backside of the boardand grinding the stub flush with the back-side of the board.

With stubs cut, we observed the follow-ing results:

With stubs filed flush, we obtained thefollowing results:

This seemed to be a promisingapproach, so we decided to try anotheroption to eliminate the stub before doing are-layout of the board. The SMAs wereremoved from board #2 and placed on thebackside of the board. This effectivelyremoved the stub, since the via and centerSMA conductor became part of the intend-ed transmission line.

Testing this modified board yielded zeroerrors. This confirmed our finding that the

14 Xcell Journal Summer 2004

Board #1:

# of packets # byte errors

Test 1 0x10000 (65,536) 136

Test 2 0x10000 (65,536) 306

Board #2:

# of packets # byte errors

Test 1 0x10000 (65,536) 5527

Test 2 0x10000 (65,536) 8270

Board #2:

# of packets # byte errors

Test 1 0x10000 (65,536) 168

Test 2 0x10000 (65,536) 273

Board #2:

# of packets # byte errors

Test 1 0x10000 (65,536) 115

Test 2 0x10000 (65,536) 134

Figure 3 – Eye diagrams of 2.5 Gbps (left)and 3.125 Gbps(right)

Figure 4 – Initial TDR results

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stub was the cause of the unacceptableerror rate and that a layout change wasrequired to remove the stub.

Because we wanted to keep the SMAson the top side and minimize modifica-tion to the existing microstrip, a boardspin was required. Noting the perform-ance of surface-mount SMAs in simula-tion, we decided to proceed with a similarSMA configuration for the board spin.

Revision of the Prototype DesignThe prototype board was redesigned toeliminate the stub by using a surface-mountSMA connector. More extensive testingwould also be necessary to further verify theoperation of the new board design.

In addition to FR4 characterization,we chose to use a more exhaustive test pat-tern to validate the performance of thenew board. Furthermore, partial reconfig-uration would allow on-the-fly adjust-ments to MGT parameters such aspre-emphasis and differential swing. Theresults are shown in Figure 5.

The test setup parameters were:

• MGT 4 connected through a 12-inchRG 316 cable (Johnson 415-0029-012)to a 20-inch FR4 trace on the XilinxMGT characterization board (Xilinx)

• Pre-emphasis at 25% (setting 2 of 0-3)and differential swing of 600 mV (setting 2 of 0-4)

• Test pattern is PRBS32 (using the XilinxBERT design)

• MGT 6 connected through 24-inchRG316 (manufacturer unknown) to 15-inch FR4 characterization board (Xilinx)

• Pre-emphasis at 25% (setting 2 of 0-3)and differential swing of 600 mV (setting 2 of 0-4).

• Test pattern is PRBS32.

We ran the test until the 16550 UARTtimed out (an evaluation-licensed core); thetotal frames are shown in Figure 6. Note thatthere are no errors; hence the bit error rate iszero. Also, the error factor is defined on pagenine and table 2 in Xilinx Application NoteXAPP661 as the shortest gap between errors,expressed in frames. Becausethere are no errors, it makessense that this would be infinite.

The final TDR test resultsare shown in Figure 7. A carefulreading of the results shows a50% improvement over the pre-vious reading and confirms theimprovement of the new design.

ConclusionDuring the design phase, you must be verycareful to identify all sources of trace andstub length. In particular, watch for a mis-match between your choice for through-hole or surface-mount SMA devices andthe layout of your traces between the SMAconnector and the Virtex-II Pro FPGA. Wefound it was easy to control the length andimpedance of the traces, but we overlookedthe impact SMA connector choice had onthe signal integrity.

Detailed design files and test measure-ments are available with the purchase of anAvnet Design Services Virtex-II Pro 3.125Gbps Aurora Design Kit. You can order thekit, part number ADS-XLX-V2PRO-EVLP7-6, for $599.

This design kit is just one of many avail-able to speed the development cycle forcomplex processor, communications,FPGA, DSP, and networking applications.All of our design kits are modular and canaccept matching add-on modules, applica-tions software, design and debug tools, andcompatible IP cores. For more informa-tion, visit www.avnetavenue.com.

Summer 2004 Xcell Journal 15

Figure 7 – TDR measurement results of the revised design show a 50% improvement, supporting the bit error rate test results.

We found it was easy to control the length and impedance of the traces, but we

overlooked the impact SMA connector choice had on the signal integrity.

Figure 5 – MGT settings

Figure 6 – Test results

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For Synchronous Signals, Timing Is Everything For Synchronous Signals, Timing Is Everything

16 Xcell Journal Summer 2004

Mentor Graphics highlights a proven methodology for implementing pre-layout Tco correction and flight time simulation with Virtex-II and Virtex-II Pro FPGAs.

Mentor Graphics highlights a proven methodology for implementing pre-layout Tco correction and flight time simulation with Virtex-II and Virtex-II Pro FPGAs.

by Bill HarginProduct Manager, HyperLynxMentor Graphics [email protected]

We’ve all heard the phrase “timing iseverything,” and this is certainly the casefor the majority of digital outputs onmodern FPGAs. Timing-calculationerrors of 10 or 20 percent were fine at 20MHz, but at 200 MHz and above, they’reabsolutely unacceptable.

As Xilinx Senior Field ApplicationsEngineer Jerry Chuang points out, “Thetoughest case usually is a memory orprocessor bus interface. Most designersknow that they have to account for Tco(clock-to-output) as it relates to flighttime, but don’t really know how.”

Another signal integrity engineeringmanager who preferred to remain anony-mous explains, “We’ve got lots of thingsthat hang on the hairy edge of working.That’s one of the reasons why they giveyou so many knobs to turn on newermemory interfaces.”

To complicate matters, manufacturerdatasheets and application notes usemultiple, often-conflicting definitions ofmany of the variables and proceduresinvolved, requiring you to investigate theconventions used by manufacturer A ver-sus manufacturer B. Most of the recentlypublished signal integrity books eithergloss over the subject or avoid it alto-gether. We hope that this article willserve to blow away some of the fog andreinforce some standard definitions.

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System Timing for Synchronous SignalsAn FPGA team will typically place androute an FPGA according to their specifictiming requirements, leaving system-leveltiming issues to be negotiated later with thesystem-design team. With the sub-nanosec-ond timing margins associated with manysignals, it’s common for the system side tobe faced with PCB floor-planning changes,part rotation, and sometimes the need tonegotiate pin swaps with the FPGA team toaccommodate timing goals. Proactive, pre-layout timing analysis and some carefulaccounting can keep both the FPGA andsystem teams from spending a month ormore chasing timing problems.

Two classes of signals pose problems forFPGA designers and their downstream coun-terparts at the system level: timing-sensitivesynchronous signals and asynchronous,multi-gigabit serial I/Os. We’ll concentrate onparallel, synchronous designs in this article.

MarginsThe system-timing spreadsheet for syn-chronous designs is based on two “classic”timing equations:

Tco_test(Max) + Jitter + TFlight(Max) + TSetup < TCycle

Tco_test(Min) + TFlight(Min) > THold

Or, once Tco_test is corrected, becomingTco_sys, as outlined in this article:

Tco_sys(Max) + Jitter + Tpcb_delay(Max) + TSetup < TCycle

Tco_sys(Min) + Tpcb_delay(Min) > THold

Each net’s timing is initially set up witha small, positive timing margin. This mar-gin is allocated to the TFlight(Max) andTFlight(Min) values (or Tpcb_delay[Max]and Tpcb_delay[Min], respectively) in thepreceding equations; these are timing con-tributions of the PCB interconnect betweeneach net’s driver and receivers.

If there is insufficient margin left todesign the interconnects, either the siliconnumbers need to be retargeted andredesigned, or the system speed must beslowed. Figure 1 shows how timing marginsshrink relative to frequency.

There are two ways to come up with theinterconnect values for the timing spread-

what that will be. Knowing what loading thevendor assumed when publishing Tco is crit-ical so that you can adjust for the differencebetween that load and your real one.

The Recipe for a ProblemAs shown in Figure 2, if the reference load issignificantly different from the actual loadthat the output buffer will see in yourdesign, the sum of the datasheet and PCB-interconnect timing values will not repre-sent actual system timing. Actual or totaldelay may be represented as:

Total Delay = Tco_sys + Tpcb_delay

≠ Tco_test + Tpcb_delay

where Tpcb_delay is the extra intercon-nect delay between the time at which thedriver switches high or low until a givenreceiver switches.

Note that this “PCB delay” is not justthe time it takes for a signal to travel alongthe trace (sometimes called “copper delay”

sheet. Some signalintegrity tools auto-matically make calcu-lations that produce asingle “flight-time”value. However, espe-cially for designers justlearning about thetiming challenges ofhigh-speed systems, atwo-step approach ismore instructive. First,you learn how to cor-rect a datasheet’s driverTco value to match the behavior in your realsystem; second, you add the additional delaybetween the driver and each of its receivers.

Data Book ValuesInitially, timing spreadsheets are populatedwith values from the silicon vendor’s databook. You’ll need first-order estimates fromsilicon designers on the values of Tco andsetup and hold times for each system com-ponent. You can usually obtain this datafrom the component datasheet.

Test and Simulation Reference LoadsTo arrive at the datasheet value for yourdrivers’ Tco, standard simulation test loads(or reference loads) provide an artificialinterface between the silicon designer andthe system designer.

You’d prefer, of course, to have Tco spec-ified into the actual transmission-lineimpedance you’re driving on your PCB, butthe silicon provider has no way of knowing

Summer 2004 Xcell Journal 17

0 20 40 60 80 100

300 MHz

100 MHz

30 MHz

10 MHz

< 1 ns

4 ns

14 ns

70 ns

Clk to QSetup/HoldTrace DelayMargin

+-

+-

Tco into a non-standard test load

Tco into actual interconnect load

Driver

Driver Receiver

Transmission Line

Test Load

ReferenceWaveform

ActualWaveforms

Tco_test

Tpcb_delay

Vih

Vm

Vm

Tco_sys

Figure 1 – Drastically narrowed system-timing margins, as clock frequency moves from 10 to 300 MHz, are shown in red.

Figure 2 – If the reference load and the actual load in your design differ, you’ve got to make an adjustment in your system timing spreadsheet to compensate.The red driver waveforms illustrate the difference, and the impact, on Tco.

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or “propagation delay”). Here, Tpcb_delayaccounts for effects such as ringing at thereceiver, as shown in Figure 3. Its value could(on a poorly terminated net) easily be longerthan the simple copper delay.

Calculating accurate timing involvesmore than finding Tpcb_delay. If the dif-ference between Tco_sys and Tco_test issignificant – even in the neighborhood of100 ps – your board may not functionproperly if you don’t account for the differ-ence. But because Tco_test is a value creat-ed with an assumed test load, it almostnever matches Tco_sys, the clock-to-out-put delay you’ll see in your actual system.

For example, Lee Ritchey, author of “Getit Right the First Time” and founder of theconsulting firm Speeding Edge, was hired toresolve a timing problem on a 200 MHzmemory system. After digging into thedesign, he found that unadjusted datasheet

values were used, based on Tco values thatwere measured on a 50 pF load rather thansomething resembling the design’s 50 Ohmtransmission-line load. As a result, thisimproper accounting “threw timing off byjust over one nanosecond,” he says. “That’s20 percent of the total timing budget, amajor error.”

In the following sections, we’ll see howyou can correct Tco_test to become Tco_sys,avoiding this type of error altogether.

The ProcessMeasuring Tco_testTo measure Tco_test, you need to set up asimulation with just the driver model andthe datasheet test load. Though they’re anoptional sub-parameter in the IBIS specifica-tion, most IBIS models (including XilinxIBIS models) contain a record of the testload (Cref, Rref, Vref ) and the measurementvoltage (Vmeas) to use with these values.Figure 4 shows these values for theLVTTL8F buffer in the Virtex-II Pro™ IBISmodel, as well as a generic reference load dia-gram taken from the IBIS specification.

Once you’ve gathered these load valuesfrom the IBIS model, you simulate risingand falling edges, and for each, measurethe time from the beginning of switchinguntil the driver pin crosses the Vmeasthreshold. These are the Tco_test values.

Obtaining “Tcomp,” the Timing-Correction ValueNow you need to calculate a compensationvalue, Tcomp, that will convert the datasheetTco value into the actual Tco you’ll see inyour system. Tcomp is the delay between thetime the driving signal, probed at the output,crosses Vmeas into the silicon manufacturer’sstandard reference load, and the time itcrosses Vmeas for your actual system load.Tcomp is then used as a modification to theTco value from the vendor datasheet, asshown in Figure 5.

The revised computation of actual delayfrom the previous equation is then:

Total Delay = Tco_sys + Tpcb_delay= (Tco_test + Tcomp) + Tpcb_delay

Note that Tcomp may be negative or pos-itive, depending on whether the actual load

in your system is smaller or larger than thestandard test load. Traditionally, silicon ven-dors used capacitive test loads (like 35 pF) tomeasure Tco; almost all real PCB transmis-sion lines do not present as heavy a load, soTcomp is usually negative in this situation.

Xilinx, for its current generation ofFPGAs, uses a 0 pF test load for outputdriver wave shape accuracy. Real transmis-sion lines will represent a different load –some mixture of inductance, capacitance,and resistance. Because the transmission-line load is heavier than a 0 pF “open load,”Tcomp will be positive. Simulation is theonly way to accurately predict the exactvalue of Tcomp.

Simulating Tpcb_delayAt this point in the process, you’ve complet-ed the first step in finding accurate delays foryour timing spreadsheet, and you’ve compen-sated the datasheet Tco to match your realsystem load. Next, you need to determineTpcb_delay, the additional delay caused bythe interconnect from driver to receiver.

A signal integrity simulator is the onlyway to accurately do this, because only asimulator can account for subtle effects likereflections, receiver input capacitance, lineloss, and so forth.

From here, we’ll explore some detailedexamples based on Xilinx-provided IBISmodels – the process of calculating Tcompand then using the HyperLynx™ simulatorto determine an interconnect’s Tpcb_delaythrough pre-layout topology analysis. Youcould enter the values that we come up withdirectly into your system-timing spreadsheet.

The process using Mentor Graphics’HyperLynx product is straightforward. Youlook up the manufacturer’s test load in theIBIS model (see Figure 4), enter it in theLineSim schematic, set up your actual inter-connect topology just below the referenceload, and begin a simulation, probing atboth drivers so that you can measure Tcompand Tpcb_delay, as shown in Figure 6.

Running the Numbers on a Real ProblemAn important design for an electronic equip-ment manufacturer had a Xilinx FPGA talk-ing to a bank of SRAMs at 125 MHz,meaning the cycle time (Tcycle) was 8 ns.

18 Xcell Journal Summer 2004

Figure 3 – “PCB delay” refers to the differencebetween the driver waveform switching throughVmeas and the waveform at the receiver as itswitches through Vih (rising) or Vil (falling).Finding this value requires simulation, not just asimple “copper-delay” calculation.

Figure 4 – Mentor Graphics’ HyperLynx VisualIBIS Editor, a free tool for navigating the 50,000-plus lines of Xilinx Virtex-II Pro, Virtex-II, andSpartan IBIS models, shows reference load infor-mation for an LVTTL8F buffer as well as theassumed connections – from the IBIS specification– for Cref, Rref, and Vref in the insert.

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The Xilinx datasheet specified Tco as 4 ns (i.e.,Tco_test). The SRAM’s setup time was 2 ns.

Some of the traces connecting the FPGAto an SRAM were six inches long; a signalintegrity simulation showed a worst-casemaximum PCB delay (to the receiver’s “far”threshold) of 2.5 ns. This yielded in thedesign’s timing spreadsheet a total time of 4 + 2.5 + 2 = 8.5 ns (Tco_test + Tpcb_delay+ Tsetup), violating the 8 ns cycle time.

However, the Tco value, when correctedfor the actual design load, was 4-1.2 = 2.8 ns(Tco_sys = Tco_test + Tcomp), meaningthat the actual total delay value was 2.8 + 2.5 + 2 = 7.3 ns (Tco_sys + Tpcb_delay+ Tsetup), leaving an acceptable timing margin of 700 ps.

Note that in this calculation, we meas-ured to the time at which the receiver signalcrossed the farthest-away threshold to getthe worst-case, longest possible Tpcb_delay.For a rising edge, we measured to the lastcrossing of Vih; for a falling edge, to the lastcrossing of Vil.

ConclusionFor seamless interaction between the FPGAdesigner and the system designer, it’s prudentto do as much pre-layout, “what-if” analysisas possible. And, though not covered explicit-ly in this article, you can also verify that yourlaid-out printed circuit boards meet yourtiming requirements using a post-layout sim-ulator with batch analysis capabilities.

Some Mentor products that perform thistype of analysis are HyperLynx, ICX, andXTK. Running these simulations, you’re revis-ing simulated representations of interconnectcircuits in minutes as compared to the weeksrequired to spin actual PCB prototypes.

The new HyperLynx Tco simulator isavailable on Mentor Graphics’ website,www.mentor.com/hyperlynx/tco/. Included withthe Tco simulator are the Virtex-II Pro,Virtex-II™, and Spartan™ IBIS models;boilerplate schematics that will help you makeadjustments to data book Tco values; and adetailed tutorial on Tco and flight-time cor-rection that parallels this article.

Summer 2004 Xcell Journal 19

+-

+-

Tco into a non-standard test load

Tco into actual interconnect load

Driver

Driver Receiver

Transmission Line

Test Load

ReferenceWaveform

ActualWaveforms

Tco_test

Tpcb_delay

Total Delay

Vih

Vm

Vm

Tco_sys

TcompFlight Time

What is “Flight Time”?

In this article, we’ve shown conceptu-ally how Tco values specified into asilicon vendor’s test load can be cor-rected on a per-net basis to give theactual clock-to-output (Tco) timingyou’ll see on your PCB, and thenadded to the additional trace delaysbetween drivers and receivers to giveaccurate timing values. However, sig-nal integrity (SI) tools actually dealwith corrected timing values in a dif-ferent (but equal) way.

The most convenient outputfrom an SI tool is a single number –called “flight time” – shown inFigure 5 as (Total Delay - Tco_test)or (Tpcb_delay - Tcomp). You canadd this value to the standard databook Tco values in your timing spread-sheet to give the same effect as the two-step process described in this article.

When an SI tool calculates timingvalues, it 1) simulates each driver modelinto the vendor’s test load, measures thetime for the output to cross the Vmeasthreshold, and stores the value(Tco_test); 2) simulates the actual netsin the design and measures the time atwhich each receiver switches (TotalDelay); and 3) for each receiver, sub-tracts the driver-switching-into-test-loadtime from the receiver time (Total Delay– Tco_test). The resulting flight time isa single number that can be added toeach net’s row in a timing spreadsheet,and that both compensates Tco_test foractual system loading and accounts forthe interconnect delay between driverand receiver.

The term “flight time” is some-what unfortunate, although it’sbecome the industry standard. Thename suggests the total propagationdelay between driver and receiver, butthe value calculated is actually thedelay derated to compensate for thereference load. For old-style capaci-tive reference loads (e.g., 50 pF),flight time can even be negative.

Figure 5 – Tcomp, highlighted here, can be used to “compensate” for data book Tco values in system timing calculations. Tcomp is positive when the actual load exceeds the reference load, and negative when thereference load is larger. Signal integrity tools actually use a one-step process that combines the effect ofTcomp and Tpcb_delay into a single value called “flight time” (see sidebar, “What is Flight Time?”).

Figure 6 – Total Delay, Tco_test, Tcomp, Tco_sys,and Tpcb_delay, as well as flight time, are allmeasurable for this falling-edge waveform usingMentor Graphics' HyperLynx software.

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by Lawrence Williams, Ph.D.Director of Business DevelopmentAnsoft [email protected]

The push toward FPGA platform solutionswith high-bandwidth DSP and gigahertz-speed I/O functionality has led to devicesthat place greater demands on PCB design.The high serial data rates of Xilinx Virtex-II Pro™ FPGAs (3.125 Gbps) and Virtex-II Pro X™ FPGAs (10 Gbps) requirecareful signal integrity design for propersystem operation.

In this article, we’ll explain how to com-bine commercial electromagnetic (EM)software with circuit and system simulationto characterize transmission lines, vias, andconnectors for systems that incorporatehigh-bandwidth FPGAs [1]. We used two-dimensional EM simulation to extract qua-sistatic circuit models for the PCBtransmission lines and three-dimensionalEM simulation to extract models for viasand connectors. For end-to-end simula-tions, we applied a convolution simulator.Thus, it’s possible to achieve reliable datatransmission with proper use of moderndesign tools.

High-Performance PCB DesignPCB designers aim to create interconnectsthat reliably transmit high-speed serial sig-nals. Transmission lines, via structures, andconnectors are the building blocks of thedesign – and all have their particular chal-lenges. These structures are designed indi-vidually to meet particular metrics and arethen assembled into a system-level intercon-nect to evaluate end-to-end performance.

The most common PCB transmissionstructures are the microstrip and striplinetransmission line; they are easy to con-struct, and you can use both for signalingat gigabit speeds. Designers have also usedsingle-ended lines successfully for lowerspeed designs; modern gigabit designs usedifferential signaling because of the advan-tages of noise immunity and reliable cur-rent return paths. The key parametersassociated with PCB transmission lines arethe characteristic impedance, delay, inser-tion loss, and crosstalk.

Designing High-Speed Interconnects for High-Bandwidth FPGAs

20 Xcell Journal Summer 2004

Commercial EM software combines with circuit and system simulation to achieve reliable data transmission.

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Via structures allow you to route circuittraces between layers of a multilayer board.Vias are particularly useful for transitioningfrom the pins of a ball grid array or connec-tor down to stripline traces within theboard. The most common and inexpensivevia structure is the “through-hole” via.

Alternatives to the through-hole via arethe blind via and the back-drilled via.Although these alternatives generally pro-vide higher performance, most high-vol-ume designs continue to use the lower costthrough-hole via. Key issues in the designof through-hole via structures are untermi-nated via stubs and antipad radii.

Connectors provide an electrical andmechanical interface between circuitboards, or between boards and cabling.Connector performance is highly depend-ent on the escape-routing PCB interface.Designs can succeed or fail depending onthe choice of route layer and resultant viastub length, antipad dimensions, boardmaterials, and escape-routing layout.Additionally, transmission bends withinconnectors skew the transmission path andcan lead to mode conversion.

Electromagnetic Model ExtractionThe most common printed circuit boardmaterial is FR4. Although inexpensive forcircuit fabrication, FR4 suffers significantdielectric losses at high frequencies. Typicalmaterial properties for FR4 are �r = 4.2and loss tangent tand = 0.022.

An alternative to FR4 is to use a lowerloss Getek™ material. Getek II’s materialproperties are �r = 3.4 and loss tangenttand = 0.006. Figure 1 depicts a layer with-in a typical backplane board. The layerheight is 0.272 mm (10.7 mils); trace widthis 0.125 mm; trace separation is 0.250 mm.Half-ounce copper plating for the tracesprovides a trace thickness of 0.7 mils.

We performed simulations using thetwo-dimensional, quasistatic finite elementsimulator within the Ansoft Q3D softwaresuite. The stripline geometries weredesigned to provide nominally 100 Ohmsof differential impedance, and simulationsconfirmed that the impedance was within4% of the nominal value.

Figure 2 depicts three methods by

Although accurate, MoM simulationsare also the most computationally expen-sive. A compromise that offers the accuracyof planar EM simulations and some of thespeed of circuit simulation is to use a com-bination of the two (Figure 2B). AnsoftDesigner allows you to subdivide intercon-nects into a model with circuit elementsand EM elements. Circuit elements areused for long, uniform sections of the cou-pled transmission line. EM simulation isused for all coupled line bends, as shown inFigure 2. This “solver on demand”approach automatically calls the planar EMsolver whenever a bend is encountered.

Figure 3 plots the results of the three sim-ulation methods outlined in Figure 2. Allmethods accurately predict the insertion loss.The circuit model cannot provide meaning-

which you can model the PCB intercon-nects. The simplest is to use a coupled-linecircuit model (Figure 2A), found in popu-lar high-frequency circuit simulators likeAnsoft Designer™. In this instance, theinterconnect is modeled with a uniformdifferential coupled transmission line with-out any discontinuities.

On the other end of the modeling spec-trum is a full-wave planar EM field simulatorbased on the method of moments (MoM)(Figure 2C). The Ansoft Designer PlanarEM simulator separates the traces into thou-sands of triangular elements. Numerical sim-ulations compute the current flow on alltriangles based on the EM coupling betweenthem. As such, these computations com-pletely characterize signal transmission andreflection on the interconnect.

Summer 2004 Xcell Journal 21

BS W

εr = 3.4, tanδ = 0.006

Layer B W S Zse Zd Zcom

S10 0.272 0.125 0.250 49.15 96.05 25.13All dimensions are in millimeters

Figure 1 – Two-dimensional quasistatic simulations performed on stripline transmission structures using Ansoft Q3D. The table lists single-ended, differential, and common impedances.

Figure 2 – You can model PCB interconnects using various methods. Circuit models (A) are the simplest and least expensive computationally; planar EM (MoM) simulations (C)

are most expensive computationally but also the most accurate; a combined circuit + planar EM (B) provides accurate results with relatively low computational effort.

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ful return loss, as it does not contain any ofthe coupled line bends. The circuit plus pla-nar EM method (solver on demand) pro-vides return loss results that are in closeagreement with the planar EM results. Thismethod provides accurate results with agreatly reduced computational expense.

ViasA common signal integrity design practiceis to place high-speed route layers on oppo-site sides of the board in order to avoidopen-circuit via stubs [2]. Figure 4 depictstwo via structures: a best case and worstcase. The best case occurs when routingfrom the top layer to layer S10, as this

results in a very short (10.75mil) via stub. The worst caseoccurs when routing to layerS1, leaving a very long (123.95mil) via stub.

Figure 5 plots the inser-tion and return loss of an iso-lated differential viacomputed using the three-dimensional full-wave fieldsolver Ansoft HFSS. Thesolid blue curve representsthe via that transitions to

layer S1. This is considered the worst case,as it has a very significant open-circuitedvia stub and an associated resonance in theinsertion loss near 6.5 GHz. The dashedred curve represents the via that transi-tions to layer S10. This is considered thebest case, as it provides a very flat inser-tion loss response to 10 GHz, and returnloss is good to roughly 4.5 GHz.

Another consideration when designingvias are the antipads that exist on all powerand ground layers. Figure 6 depicts two dif-ferential via structures with antipad radii of0.5 mm and 0.7 mm. You can improve per-formance by using the larger antipad radius

[2]. We performed simulations using AnsoftHFSS to predict the performance of each.

Figure 7 shows the swept frequencyresults for both via antipad radii for differ-ential vias routing to layer S1 (worst case).As you can see in the plot, a significantincrease in bandwidth is possible with thissimple modification. The resonance in the

22 Xcell Journal Summer 2004

VHDM Connector

Best

Cas

e

Route Layer: s10(Via Stub: 10.75 mil)

VHDM Connector

Wor

st C

ase

Route Layer: s1(Via Stub: 123.95 mil)

Antipad Radius: 0.5 mm(From Layout)

Antipad Radius: 0.7 mm(Test Case)

Figure 3 – PCB interconnect simulationresults show that allmethods outlined inFigure 2 accurately predict insertion loss.Return loss cannot bepredicted with the circuit model alone.

Figure 4 – Vias that transitionfrom the top to thebottom of a boardprovide minimalopen-circuited viastubs and “best-case”performance.

Figure 5 –“Through-hole” via performance assimulated usingAnsoft HFSS. Note the sharp resonance in theinsertion loss for the worst-case viarouted to layer S1.

Figure 6 –Antipad radiishould be suffi-ciently large toavoid capacitivecoupling to powerand ground.

Figure 8 – MolexVHDM-HSD connector as modeled in Ansoft HFSS

Figure 7 – Differential via performance for layer S1 (worst-case) routing for two antipad radii

▼▼

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insertion loss has been pushed up from6.5 GHz to roughly 7.75 GHz. This isone of the simplest modifications thatcan be made to a PCB board file andshould be considered for all high-per-formance designs.

ConnectorsA common connector used to transitionbetween boards and differential coaxialcables is the Molex™ very high densitymetric-high-speed differential (VHDM-HSD). Ansoft HFSS performed simula-tions of such a connector (Figure 8). Onone side of the connector are three twin-ax cables; on the other side is a backplaneboard with its associated escape routing.

Figure 9 plots the insertion andreturn loss versus frequency for theVHDM connector without the escaperouting. This connector provides a veryflat insertion loss across the band. Returnloss is below 10 dB up to 3 GHz.

Results for the connector (includingall escape routing) are computed by cas-cading S-parameters from the individualHFSS models for the connector and thebackplane escape routing. Including thebackplane board, escape routing to themodel has a significant effect.

Figure 10 plots the differential S-parameters for a channel containing aworst case via transition that leaves a longunterminated via stub. The performanceof the VHDM connector is dominatedby the sharp resonance of the via stubthat manifests itself at 6.5 GHz.

System SimulationIt is possible to cascade results generatedfrom EM and circuit simulations to get afull system simulation. Figure 11 plotscircuit simulation results displaying theinsertion and return loss up to 10 GHz.As expected, the channel has a responsesimilar to a low pass filter.

We performed time domain simula-tion using the system simulator inAnsoft Designer. This simulator uses aconvolution algorithm to process thefrequency domain channel data withuser-defined input bitstreams.Insertion and return loss are included

in the simulation. A 3.2 Gbps pseu-do-random bit source with a 1Vpeak-to-peak amplitude and 125 psrisetime was applied to the channel.The channel was terminated in sin-gle-ended 50 Ohm resistors.

Figure 12 shows the resulting eyediagram as very clear and open,despite the significant channelimpairments in the frequency domainresults. We did not apply any pre-emphasis in the simulation. You

should anticipate thatsome pre-emphasis wouldsharpen the time-domainresponse.

ConclusionModern platform FPGAdevices provide widebandwidth processing andhigh-speed I/O. Serial I/Owith speeds in the gigabit

realm creates new challenges for PCBdesigners.

You can solve the high-speed I/Ochallenges posed by modern platformFPGA devices using EM, circuit andsystem simulators. Although wefocused our attention on the passiveinterconnect in this article, it is possi-ble to include nonlinear I/O driversand receivers in the simulation toobtain additional insight to systemperformance. Indeed, you can use anew tool from Ansoft calledNexxim™ to simulate all circuitbehavior for systems including EM-based models, linear, and nonlinearcircuits. Visit www.ansoft.com formore information about AnsoftDesigner and Nexxim.

References[1] Williams, L., S. Rousselle, and B. Boots,“Cray Supercomputer 3.2 Gb/s SerialInterconnect Simulation Using Full-waveElectromagnetics,” in DesignCon 2004Conference Proceedings, Santa Clara,CA, Feb. 2-5, 2004.

[2] Williams, L., S. Rousselle, and B. Boots, “Circuit board design for 10Gbit XFP optical modules.” EDN, May 29, 2002, pp. 63-70.

Summer 2004 Xcell Journal 23

Figure 9 – Differential S-parameters for the Molex VHDM-HSD connector in isolation

Figure 10 – Differential S-parameters for the Molex VHDM-HSD connector with backplane escape routing. This worst-case channel with large via stub

shows signature resonance at 6.5 GHz.

Figure 11 – Full-channel cascaded performance using themodels developed from EM simulations up to 10 GHz

Figure 12 – Full-channel eye diagram using convolutionsystem simulator in Ansoft Designer for the cascaded

model with a 125 ps risetime

VHDM Connector

Wor

st C

ase

Route Layer: s1(Via Stub: 123.95 mil)

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With a built-in EM solver, coupled transmission lines,S-parameter support, and IBIS I/O buffer models,HSPICE provides a comprehensive multi-gigabit signal integrity simulation solution.

With a built-in EM solver, coupled transmission lines,S-parameter support, and IBIS I/O buffer models,HSPICE provides a comprehensive multi-gigabit signal integrity simulation solution.

Accurate Multi-Gigabit Link Simulation with HSPICEAccurate Multi-Gigabit Link Simulation with HSPICE

24 Xcell Journal Summer 2004

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by Scott Wedge, Ph.D.Sr. Staff EngineerSynopsys, [email protected]

The Xilinx Serial Tsunami Initiative hasresulted in a host of multi-gigabit serial I/Osolutions that offer reduced costs, simplersystem designs, and scalability to meet newbandwidth requirements. Serial solutionsare now deployed in a variety of electronicproducts across a range of industries.Reduced pin count, reduced connector andpackage costs, and higher speeds havemotivated the trend towards serialization oftraditionally parallel interfaces.

RocketIO™ multi-gigabit transceivers(MGTs), for example, offer tremendousperformance and functionality for connect-ing chips, boards, and backplanes at gigabitspeeds. Whether your application isInfiniBand™, PCI Express™, or 10Gigabit Application Unit Interface(XAUI), RocketIO MGTs offer ideal inter-face solutions.

However, the transition from slow, widesynchronous parallel buses to multi-lane,multi-gigabit asynchronous serial channelsintroduces new physical and electricaldesign challenges that traditionally fallmore into the realm of radio frequency(RF) design than digital I/O design. Thephysical characteristics of the signal chan-nel must be known and carefully controlledto ensure proper performance. At suchhigh data rates, you must take into accounta long list of analog, RF, and electromag-netic effects to guarantee a working design.

Life in the Fast LaneReliable operation of multiple transmit andreceive lanes running up to 3.125 Gbpsrequires special attention to power condi-tioning, reference clock design, and to thedesign of the lanes themselves. You mustmatch the differential signal trace lengthsto tight tolerances. A length mismatch of1.4 mm will produce a timing skew ofroughly 10 ps, which is appreciable at thesedata rates. You must carefully control traceimpedances and keep reference planesintact to avoid mismatches and signalreflections. Spacing between lanes must be

• Lossy, coupled transmission line mod-eling with the W-element

• Single-ended and mixed-mode S-parameter modeling with the S-element

• I/O buffer modeling with I/O BufferInformation Specification (IBIS) models and encrypted netlists.

Getting from Maxwell to ModelsAccording to electromagnetic theory, at highfrequencies every millimeter of metal willinfluence electrical behavior. As depicted inFigure 1, one challenge in multi-gigabit SI isto reduce the significant aspects of EM the-ory into something useful for circuit-levelsimulation. Maxwell’s equations must bereduced to something manageable; youmust analyze the electromagnetic character-istics of the interconnect system to build anappropriate model for circuit simulation.

HSPICE includes a built-in electromag-netic field solver for computing the electri-cal characteristics of coupled transmissionline systems. The solver is ideal for multi-lane, multi-gigabit applications. It uses aGreen’s function boundary element and fil-ament method that yields very accurateresistance, inductance, conductance, and

adequate to avoid crosstalk, but remainspace-efficient.

Meeting these challenges requires usingsignal integrity (SI) simulations to uncoverand help solve potential problems beforefabrication. This is nothing new, but thetrick is to now take into account severalpreviously ignored factors that are detri-mental to gigabit link design.

Consider the traces. Perhaps by nowyou’ve grown accustomed to using trans-mission lines in signal integrity simula-tions. But simple lossless, uncoupledtransmission line models are just not goodenough for MGT links. Frequency-dependent conductor and dielectric losses– especially in FR4 – are substantial andmandate a more sophisticated approach.Your basic gigabit trace is a differential cou-pled transmission line with considerableloss and must be treated as such to findoptimal driver pre-emphasis settings.

To address these and other problems,HSPICE® provides a comprehensive set ofSI simulation and modeling capabilities tohelp you achieve the necessary accuracy formulti-gigabit SI simulations. HSPICEincludes:

• Built-in electromagnetic (EM) solvertechnology for trace geometries

Summer 2004 Xcell Journal 25

S-element Single-Ended ScatteringParameters

S-element Mixed-Mode Scattering Parameters

W-element LossyCoupled TransmissionLine RLGC Models

Figure 1 – Achieving accurate gigabit signaling channel simulations mandates the use of models that can take into account key electromagnetic effects.

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capacitance (RLGC) matrices for the typesof differential traces you’ll need for gigabitdesign. You need only perform a fieldsolver analysis for each unique cross-sec-tional geometry.

HSPICE field solver analysis will pro-duce a characterization of the interconnectsystem in terms of distributed RLGCmatrices. Frequency-dependent loss effectsare included in the Rs and Gd matrix ele-ments. Be sure to enable these field solveroptions; at gigabit data rates these lossescan be substantial.

The conductor losses ( ) and dielec-tric losses ( ) are both significant at3.125 Gbps, and must be well modeled todetermine your pre-emphasis needs forlong lane lengths. Don’t guess when speci-fying your material properties. The relativedielectric constant (4.2-4.7 for FR4) willinfluence line impedance (C matrix) values; electrical conductivity (5.8e7 forcopper) will show up as skin effect (Rmatrix) losses; and dielectric loss tangentvalues (typically 0.015-0.03 for FR4) willshow up as substrate (G matrix) losses.

Fortunately, board manufacturers aregetting better at measuring and sharingsuch information. Many accurate W-ele-ment RLGC matrix models are availabledirectly from vendors. Be sure to verify thatfrequency-dependent Rs and Gd values areincluded to ensure that loss modeling wastaken into account. HSPICE’s built-in EMsolver is also well suited for copper cablegeometries in cases where manufacturersdo not have W-element models available.

Mixed-Mode Scattering ParametersAs shown in Figure 2, accurate SI simula-tion of multi-gigabit links involves a varietyof models. For certain package, trace, con-nector, backplane, and cable sections,measured data or very accurate three-dimensional EM solver data is often avail-able in the form of scattering parameters(Figure 3).

S-parameters represent complex ratiosof forward and reflected voltage waves.Used as an alternative to other frequencydomain representations (such as Y- or Z-parameters), S-parameters lack the dramaticmagnitude variations that other representa-

26 Xcell Journal Summer 2004

Figure 2 – Simulations for MGT chip-to-chip, backplane, and copper cable applications combine a diverse set of models for accurate signal integrity predictions.

Figure 3 – Typical scattering parameters for an interconnect system showing the transmission coefficient(S21) for one interconnect (violet), the reflection coefficient (S11) for the same interconnect (green), and thecoupling coefficient (S31) between adjacent interconnects (light blue) over a frequency sweep of 0-10 GHz.

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tions have associated with high-frequencyresonance. In addition, they can be meas-ured directly with vector network analyz-ers. With differential traces the norm forXAUI and other links, mixed-mode S-parameters are particularly useful. Theyprovide a means to characterize a differen-tial trace in terms of its differential, com-mon-mode, and cross-coupled behavior.

HSPICE provides single-ended andmixed-mode S-parameter modeling capa-bility through the S-element. You can inputS-parameter data in Touchstone™ file,CITI file, or table formats. Make sure yourS-parameter data covers as broad a frequen-cy range as possible with good sampling.

HSPICE will apply convolution calcu-lations that need high-frequency values forcrisp simulations of waveform rises andfalls. If you have data up to 20 or 40 GHz,use it. A frequency range nine times yourdata rate (28 GHz for 3.125 Gbps) is con-sidered optimal, although often hard tocome by. Good low-frequency data(including DC) is also important fordirect-coupled applications.

Beware of “measurement noise” with S-parameters. A poor network analyzer cali-bration can result in S-parameter data thatwill make your passive traces appear tohave gain. HSPICE also supports S-param-eter modeling for active devices, as is com-mon with some RF/microwave designs.HSPICE uses a convolution algorithm forS-parameter modeling that is not limited topassive devices, avoiding the creation ofintermediate, reduced-order modelsrequired by other time-domain simulationapproaches. HSPICE uses the S-parameterresponse directly for maximum accuracy.

I/O Buffer Modeling Ideally, you can perform SI simulationsusing transistor-level models and netlistsfor the input/output buffers. This level ofdetail may be unwieldy, but is sometimesnecessary. The IBIS standard provides ameans of encapsulating the key electricalcharacteristics of I/O buffers into accuratebehavioral models. These models includedata tables for buffer drive and switchingability, and package parasitic information.These models may or may not be appro-

priate for high-speed applications,depending on their intended use. Be sureto check the notes in the header of yourIBIS model files so that you’re not push-ing the model outside its range of validity.There is also a new IBIS InterconnectModeling Specification (ICM) forexchanging S-parameter and RLGCmatrix data for connectors, cables, pack-ages, and other types of interconnects.

Another advantage of IBIS is that itallows vendors to deliver good buffer mod-els to their customers without disclosingproprietary design information. This is alsoaccomplished with encrypted HSPICEnetlists. Multi-gigabit transceiver modelingis particularly difficult, so be prepared tosee several buffer modeling approaches.

In the case of RocketIO transceivers,Xilinx provides special MGT models verifiedwith HSPICE; visit the Xilinx SupportSPICE Suite at www.xilinx.com/support/software/spice/spice-request.htm for moreinformation. Whether you’re using IBIS,SPICE netlist, or encrypted buffer models,HSPICE provides the most comprehensiveand validated solution available.

Don’t Skimp on the SPICESo now you’ve got S-parametermodels based on measureddata, W-element trace modelsbuilt from EM solvers, andaccurate I/O buffer models.Are you ready to simulate?Maybe not. You may still bemissing lumped R, L, and Cvalues needed to capture all theparasitic effects in your design.Are you using AC couplingcapacitors? At gigabit frequen-cies, no passive component

behaves completely as expected. Even cou-pling capacitors must be modeled aslumped RLC circuits to capture resonanceeffects. Using off-chip terminations? Thesame is true with resistors. Are you leavingout any package lumped RLC or S-param-eter models? Thankfully, manufacturersare getting better at providing accurateSPICE models for most of their compo-nents. You just need to ask.

ConclusionMulti-gigabit signal integrity simulationsmust take into account a great deal of pre-viously ignorable effects. Every trace is atransmission line, and you must accountfor every bump, bend, turn, and millimeterof metal with appropriate electrical models.

HSPICE is constantly being improvedto better address these accuracy needs for multi-gigabit SI simulation. The W-element has been enhanced for faster andmore accurate modeling of frequency-dependent losses in coupled transmissionlines. HSPICE’s built-in EM solvers canbuild accurate W-element models based ontrace geometries (Table 1). The S-elementhas been enhanced to support both single-ended and mixed-mode S-parameter datasets. This, combined with HSPICE’s trust-worthy device and IBIS models, provides acomprehensive signal integrity simulationand modeling solution.

For more information about the latestcapabilities of HSPICE and the integrationof HSPICE into overall design processes,visit the HSPICE Update page atwww.hspice.com.

Summer 2004 Xcell Journal 27

Use the Following Command: To Specify Trace:

.MATERIALConductor and dielectric properties

.SHAPE Conductor geometries

.LAYERSTACKGround planes and dielectric thicknesses

.MODELW-element model derived from the field solver analysis

Table 1 – Use HSPICE’s built-in EM solver to turn materialproperties and trace geometry specifications into accurate lossy,

coupled transmission line models.

HSPICE provides single-ended and mixed-

mode S-parameter modeling capability

through the S-element.

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Eyes Wide Open

28 Xcell Journal Summer 2004

The RocketIO Design Kit for ICX reduces the burden of implementing working multi-gigabit channels.

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by Steve BakerHigh Speed Architect, Systems Design DivisionMentor Graphics [email protected]

If you’re migrating from traditional busstandards such as PCI and ATA to serial-ized asynchronous architectures such asPCI Express™ and ATA-2, you’ve proba-bly discovered that the tools for simulatingthe designs and models for the variousbuffers, connectors, transmission lines,and vias have become more complex.

Although setup and hold, crosstalk andsingle-ended delay are well understood,accurately modeling these new parts andtheir various complex behaviors adds to thejob’s complexity. To reduce the complexityof interacting with model and designparameters, Mentor Graphics and Xilinxhave jointly developed the RocketIO™Design Kit for ICX™ software, producinga design environment that allows you tofully confirm what’s required to satisfy yourdesign specifications.

The Design KitThe RocketIO Design Kit for ICX is a com-panion to the standard Xilinx SignalIntegrity Simulation (SIS) Kit and compris-es a set of designs that match various Xilinx-supplied SPICE transmission lineimplementations. The kit is hierarchical, soall of the different elements – such as docu-mentation, system configuration, simula-tion models, and ICX databases – are storedin different, relative location folders. Thesefolders are located within the ICX kit in thesame parent directory as the Xilinx SIS kit.

The design kit enables easy simulationanalysis through the RocketIO menu andthrough existing features of ICX products,including eye-diagram, jitter, and inter-symbol interference analysis using pre-defined and custom multi-bit stimuli withlossy transmission line modeling.

Additionally, the IBIS 4.1 models,which ICX uses for simulation, referencethe encrypted models supplied by Xilinx.You can progress from design to designthrough the kit’s environment, learningmore about the behavior of the RocketIObuffers with each design or simulation,

the Xilinx Rocket IO Design Kit in eye-diagram form. You can also verify that sim-ulation results match those supplied byXilinx with either the ICX self-containedsimulation environment using ADMS SIor with HSPICE® as an external simulatorcalled from within ICX.

The Example Design The example design has an expanded setof transmission line examples to matchthe 10 examples that Xilinx supplies.Each of the 10 paths comprises aRocketIO transmitter connected to aTeradyne™ HSD five-row connectorthrough two inches of differential boardtraces; 16 inches of differential boardtraces to a second Teradyne HSD five-rowconnector; and finally two inches of dif-ferential board traces from the secondTeradyne HSD five-row connector to aRocketIO receiver.

The custom menu allows direct simu-lation and eye diagram display of any ofthe 10 pairs from a single menu selection.The menu also includes additional con-figuration and pulse train dialogs that youcan use to change the simulation parame-ters, thus allowing investigations ofRocketIO buffer behavior with these dif-ferent settings and stimuli.

In the example design, because thetransmission lines are fixed, you modify thevarious settings of the buffer itself and thenconduct a simulation on whichever differ-

ential channel you want to investigate.The built-in RocketIO configuration

utility allows changes to the temperatureand bit duration settings when using themodels directly from the Xilinx IBIS writerutility. It also gives you additional freedomto set the pre-emphasis level, driver/receivertermination values, and differential volt-age swing when evaluating other possiblesolutions.

such as what is achievable with thesebuffers in a multi-gigabit channel andwhat settings are required to maximizesystem performance.

Standard DesignsThe three standard designs supplied withthe RocketIO Design Kit include:

• Correlation

• Example

• Evaluation.

You can also verify your own design,either in pre- or post-route states, in thekit’s design area.

The Correlation DesignIn a correlation design, the ICX databasereproduces the interconnect scheme(Figure 1) from the Xilinx backplane exam-ple and uses the same drivers and receiverbuffer models and parameters. The ICXdatabase provides virtual “push button”operation so that you can run a signalintegrity simulation and compare theresulting waveform with that provided in

Summer 2004 Xcell Journal 29

Connector ConnectorTX RX

The custom menu is more full-featured,

allowing direct simulation and eye diagram display of any of the 10 pairs

from a single menu selection.

Figure 1 – Generic schematic of the design under simulation

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To enable different bit-patterns andspeeds, you can also change the pulse trainfrom the standard 3.125 GHz to your ownspecified pulse train using the pulse traingenerator. This utility allows you to specifybit patterns that can be used directly inICX or exported as an ASCII file, in eitherSPICE PWL format or VHDL-AMS timevectors, toggling between statetransitions.

The bit-patterns have anunderlying pulse duration overwhich you can add jitter, wherethe peak-to-peak value specifiesthe six sigma points in picosec-onds of this Gaussian randomnumber. The pattern can be auser-defined set of ones and zeros,automatically defined as a randomnumber of user-defined patternlength or as a pre-defined pattern.Pre-defined pattern styles includeseveral pseudo-random bitsequences and Fibre Channelpulse trains (Figure 2).

The Evaluation Design The evaluation design allows youto load a pre-defined cross sec-tion that matches one of the crosssections from the exampledesign. In this virtual prototypeenvironment, you can place actu-al parts, try “what-if” routing,and see the results in an eye dia-gram. As the IBIS part modelsinclude other buffers for Virtex-II Pro™ devices, you can simu-late the whole of the FPGArather than just the RocketIOchannel.

This is where the channel’sdesign is investigated in greaterdetail, as you initially place thedevices to match your expectedend design rather than using a fixed set oftransmission lines. Using the electricaleditor functionality of the IS floorplannertool, you can add additional parts such asconnectors or terminators and evaluatethe impact of these on the resulting eyediagram. When working with these items,you can quickly determine the result of

the different pre-emphasis settings.Additionally, you can see the impact ofdifferent routing strategies, including thefan-out pattern and tightly or looselycoupled differential pairs.

In the evaluation design, you can deter-mine how much pre-emphasis is requiredto create the desired eye, as well as what

level of noise is introduced on adjacent sig-nals, on the board, or through the connec-tor due to that level of pre-emphasis. Theresults of this virtual prototyping, as seenin the eye diagram in Figure 3, can bepassed forward in the flow as constraints todrive the electrical design, as well as place-ment and routing examples.

VerificationThe most advanced part of the kit allowsyou to simulate your design or system. Thevarious parts of the system, backplane andplug-in cards, or just a single card with on-board channel, can be run through verifi-cation using the same complex pulse trainsand model settings as before.

If required, you can modifysettings to improve channelperformance as measured bythe eye. You can also defineadditional corner cases to eval-uate best- and worst-case sce-narios, including the impact ofone pair on the other in termsof crosstalk; its impact on theshape and size of the eye; andthe impact of other signals onthe channel.

ConclusionIteration happens in anydesign process. The quickerdecisions can be made inthose iterations and the small-er the impact on existingdesign implementations, thehappier we all are.

The RocketIO Design Kitfor ICX allows you to makeinitial evaluations of the tech-nology before any of the actu-al design implementation hasoccurred. As the design pro-gresses forward from initialevaluations to the virtual pro-totype environment, you canconfirm, in a pseudo-physicalimplementation, that thespecifications can still beachieved, or use the kit todetermine what changes arerequired to achieve the desiredperformance.

Finally, by verifying the placement, therouting of the multi-gigabit channels, orthe whole design, you can confirm thatyou are within specification. For moreinformation about the RocketIO DesignKit for ICX, visit www.mentor.com/highspeed/resource/design_kits/icx-rocketio_designkit.html.

Figure 2 – Pulse train dialog showing pseudo-random bit pattern

Figure 3 – A 3.125 GHz eye diagram from the evaluation design

30 Xcell Journal Summer 2004

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by Eric Bogatin, Ph.D.President Bogatin [email protected]

The latest generation of Virtex-II Pro™and Virtex-II Pro X™ devices featuresRocketIO™ and RocketIO X transceiversthat can drive high-speed serial links atline rates of up to 10 Gbps. Two impor-tant features of high-speed serial linksmake the behavior of these signals verydifferent from those found on traditionalon-board buses. First are the shorter risetime and associated higher bandwidth sig-nals; this makes the signals more sensitiveto small imperfections. Second are thelonger interconnect lengths; this makesthe signals more sensitive to attenuationeffects. Both effects contribute to rise time

degradation, inter-symbol interference(ISI), and collapse of the eye diagram.

Although it is possible (and important)to model and simulate these two physicalfeatures, it is difficult to do so accurately.We are still low on the learning curve,where feedback from measurements onreal systems is critically important toimprove models and optimize the designfor performance.

When first article hardware is avail-able, measurements on the passive inter-connects can provide valuable insight onthe expected system-level performanceindependent of your choice of silicondrivers and receivers. With accuratemeasurement-based models, you canoptimize the cost/performance tradeoffsof silicon selection.

High-bandwidth measurements of backplane differential channels are critically important for all high-speed serial links.Four-port VNA measurements can identify important electricalfeatures and predict backplane performance.

Backplane Characterization TechniquesBackplane Characterization Techniques

Summer 2004 Xcell Journal 31

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The Bandwidth of the Measurement Bandwidth is the highest sine wave fre-quency component that is significant.“Significant” means the frequency atwhich a harmonic of the signal is greaterthan -3 dB of the amplitude the same har-monic an ideal square wave at the sameclock frequency would have.

If the signal edge is roughly Gaussianwith a 10-90% rise time (RT), the band-width (BW) is approximately:

BW = 0.35RT

For example, a rise time of 0.1 ns has abandwidth of about 0.35/0.1 ~ 3.5 GHz.

Usually, the bit rate is specified in a high-speed serial link. To estimate the bandwidthof the signal, we need to have an estimate ofthe rise time. Assuming that the rise time is25% of the bit period, then the bandwidthof the signal is approximately:

BWsignal = 0.35 BR~1.4 x BR0.25

As a general rule of thumb, the highestsine wave frequency component in a high-speed serial link is about 1.4 times the bitrate. For a 2.5 Gbps signal, the bandwidthis about 3.5 GHz. If it is important toknow whether the bandwidth is really 3.5GHz or 4 GHz, the term “bandwidth” ismisused, as it is not accurate enough tomake this fine a distinction. Rather, youshould use the entire spectrum.

To have confidence in the accuracy of amodel, the bandwidth of that model – thehighest sine wave frequency at which thesimulated electrical performance stillmatches the measured performance of thereal structure – should be at least twice thebandwidth of the signal to allow for a rea-sonable margin. Likewise, the bandwidthof the measurement should be at least twicethe bandwidth of the signal. This rule ofthumb suggests that the bandwidth of themeasurement should be at least:

BWmeasurement = 3 x BR

If the bit rate is 10 Gbps, the bandwidthof any model used (or the bandwidth of themeasurement of the interconnect) should beat least 30 GHz. Of course, if the rise time

from the instrument to the device undertest. However, the interface from the cableto the board traces under test can introduceimpedance discontinuities which degradethe signal getting onto the trace.

The larger the discontinuity, the morehigh-frequency components reflect backto the source, and the fewer that getlaunched into the transmission line. Ifcharacterizing a path for 5 Gbps signals,the connection method may limit themeasured system performance. To increasethe bandwidth of the characterization,you must consider the launch beforedesigning and building the board.

A key ingredient in the design for testfor high-bandwidth characterization is touse a pad and via design transparent to thesignal. This typically means using a smalldiameter via with a surface-mount connec-tor and optimizing the clearance holes inthe planes. Alternatively, you could use acopper fill adjacent to the signal via beingprobed, with the copper fill connected toreturn path vias adjacent to the signal via soyou could use microprobes.

Figure 1 shows the TDR response fordifferent connection designs. The top curveis the TDR response (with a roughly 35 psrise time) for a conventional through-holeSub Miniature version A (SMA) connec-

of the bit pattern is longer than 25% of thebit period, the measurement bandwidthmight be reduced from this rule of thumb.

Unfortunately, the higher the band-width required, the more expensive it is(both in resources, time, and money) toperform a measurement or create a modelof an interconnect. That is why it is soimportant to have a rough idea of thebandwidth requirements so as to minimizethe cost. As high-speed serial linksapproach the 10 Gbps rate, measurementbandwidths need to be at least 30 GHz.Accurate measurements in this regime getincreasingly more difficult with each gener-ation of bit rate.

No Such Thing as a Free LaunchCredit that clever turn of phrase to ScottMcMorrow, president of TeraspeedConsulting. Probing a channel on a boardor a backplane introduces errors that mightnot be there, or be of a different magni-tude, than in the actual product when sig-nals are launched from chips in packages.

All high-performance measurementinstruments, such as a time domain reflec-tometer (TDR) or a vector network analyz-er (VNA), have a standard connector onthe front face, typically APC-7 or 3.5 mm.High-performance cables are used to get

32 Xcell Journal Summer 2004

Figure 1 – TDR curves for different connections to a 50Ohm board trace, measured with an Agilent 86100 DCA,Gigatest probe station, and TDA Systems IConnect soft-ware. The vertical scale is 10% reflection per div, roughly10 Ohms. The horizontal scale is 200 ps per div.

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tion to a bottom trace. On this scale, onedivision is a reflection coefficient of 10%and corresponds to an impedance changeof about 10 Ohms. At this rise time, theimpedance discontinuity is more than 18Ohms, and is predominately capacitive.

You might think that avoiding the viaswill prevent the impedance discontinuity,but just as many problems can be generatedby an edge-coupled SMA attached directlyto a surface trace. The second curve inFigure 1 shows the measured TDR responseof an edge-coupled launch using an SMA.The impedance discontinuity is more than18 Ohms at this rise time and is inductive.

One way to avoid this problem is to usemicroprobes and design the surface padsfor probing. The key feature is to use a cop-per fill shorted to all adjacent ground vias.In Figure 1, the gray vias have been short-ed to the copper fill. With this configura-tion, you can probe every signal.

The third TDR curve in Figure 1 showsthe response of a microprobe launch intoan optimized 50 Ohm stripline. Theimpedance discontinuity at this rise time isless than 5 Ohms and is inductive.

Finally, it is possible to use an SMA con-nection to a circuit board trace if it is opti-mized. The bottom curve in Figure 1 showssuch a connection. Its impedance disconti-nuity, less than 5 Ohms, compares to amicroprobe launch.

High-Bandwidth Measurements All high-bandwidth measurements takeadvantage of what is normally a problemencountered by high-bandwidth signals:reflections from impedance discontinuities.As a signal propagates down an intercon-nect, if the instantaneous impedance the sig-nal sees ever changes, a reflection will occurand the transmitted signal will be distorted.The magnitude of the reflected signal willdepend on the change in impedance.

By using a calibrated reference signal –a sine wave in the frequency domain and a

Gaussian step edge in the time domain –and measuring the amount of signalreflected back from an interconnect as wellas transmitted through it, you can extractthe electrical properties of the intercon-nect. All of the electrical properties of theinterconnect path are contained in thesetwo basic measurements.

When displaying data in the frequencydomain, the reflected signal is called thereturn loss and the transmitted signal iscalled the insertion loss. These two metricshave become the universal standard to char-acterize the fundamental properties of aninterconnect, such as a channel path in abackplane. Many of the important physicallayer properties of a backplane can be readdirectly from the return and insertion loss ofboth single-ended and differential channels.

When displaying data in the timedomain, the reflected signal gives directinsight into how the physical structurecontributes to electrical impedance dis-continuities. The transmitted signal in thetime domain gives a direct measure of thepropagation delay and rise time degrada-tion. From this result, an eye diagram canbe synthesized.

Whether you’ve measured the data inthe time or frequency domain, it can betransformed into either one. A VNA willmeasure the response in the frequencydomain, while a TDR will measure theresponse in the time domain. With appro-priate software, you can convert the datafrom either instrument into both domains.

All high-speed serial links today usedifferential signaling and backplane chan-nels routed on differential pairs. For thesestructures, the same metrics of return andinsertion loss are used, but there are addi-tional terms. Both differential and com-mon signals will have a return andinsertion loss, with mode conversionterms of differential signal in, commonsignal out and common signal in, and dif-ferential signal out.

Differential S-ParametersThe description of return and insertion lossmeasurements borrows from a formalismheavily used in the RF world based on scat-tering or S-parameters. It’s just a shorthandway of keeping track of all the differentmeasurements.

In a differential channel, the interconnectis a single, differential pair, with the two endslabeled port 1 and port 2. The ratio of thereflected sine wave signal coming out of port1 to the incident sine wave signal going intoport 1 is labeled S11. This is the return loss.

The ratio of the transmitted sine wavesignal coming out of port 2 to the incidentsine wave signal going into port 1 is labeledS21. This is the insertion loss.

A complication arises in a differentialpair, where you must consider not only theport at which signals appear but also thenature of the signal (differential or com-mon). There are four choices:

• A differential signal going in and com-ing out, which would be the differen-tial return and insertion loss, SDD11and SDD21

• A common signal going in and comingout, which would be the commonreturn and insertion loss, SCC11 andSCC21

• A differential signal going in and acommon signal coming out, a type ofmode conversion, SCD11 and SCD21

• A common signal going in and a dif-ferential signal coming out, a type ofmode conversion, SDC11 and SDC21.

Don’t forget the case of the signal goingin from port 2 rather than port 1. All ofthese combinations result in 16 differentialS-parameters, which are arrayed in amatrix. Each set of terms has significance,but the most important are the differentialreturn and insertion loss and the differen-tial to common mode conversion.

Summer 2004 Xcell Journal 33

You might think that avoiding the vias will prevent the impedance discontinuity, but just as many problems can be generated by an

edge-coupled SMA attached directly to a surface trace.

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Differential Return LossSDD11 is a direct measure of the imped-ance discontinuities encountered by thedifferential signal propagating throughthe channel. Figure 2 is an example of themeasured differential return loss of abackplane trace in the frequency domain

up to 20 GHz. The more negative thedecibel value, the less reflected signal andthe better the impedance match.

It’s a little difficult to interpret the meas-urement in the frequency domain. This is acase where transforming the data to thetime domain gives immediate insight.

Figure 3 is the same data displayed inthe time domain. In this display, you canidentify the discontinuity from the SMAlaunch, the high impedance of the daugh-tercard, and the capacitive discontinuity ofthe vias in the backplane.

Differential Insertion LossSDD21 is a direct measure of the qualityof the transmitted differential signalthrough the channel. In the frequencydomain we can read the bandwidth of theinterconnect directly off the screen. Themaximum useable bandwidth of the chan-nel is set by the frequency at which theattenuation is below the usable value, typ-ically about -15 dB of loss, depending onthe SerDes. The more discontinuities andlosses, the higher the attenuation, and thelower the bandwidth.

Figure 4 shows the measured SDD21for two different length channels, includ-ing the higher bandwidth of the shorterchannel.

Using the limiting attenuation as -15dB, the short channel has a usable band-width of about 4 GHz, and the long chan-nel has a usable bandwidth of about 3 GHz.This would correspond to a usable bit rateof roughly 2.5 Gbps and 2 Gbps. However,

it is more than just the attenuation thatdetermines the maximum usable bit rate.

A better estimator for the maximumusable bit rate is the eye diagram. Eventhough this differential insertion loss wasmeasured in the frequency domain, it canbe translated into the time domain, and asa response function can be used to calculatean eye diagram.

Figure 5 shows the calculated eye dia-gram for a 25-inch channel with 2.5 Gbpsand 5 Gbps signals. Based on this meas-ured response, this channel might be use-ful for even 5 Gbps data rates, with anappropriate receiver.

Mode ConversionAny asymmetry between the two lines thatmake up the differential pair will convertsome of the transmitted differential signalinto common signal. This will create twoproblems. If any of this created commonsignal gets out of the channel onto externaltwisted pairs, it will potentially contributeto electromagnetic interference. Of course,every good design should have integratedcommon signal chokes in all external twist-ed pair connectors. However, it is alwaysgood practice to try to reduce the source ofthe noise before filtering.

The second problem isn’t so much fromthe common signal created but from theimpact on the differential signal from whatcaused the conversion. One of the mostcommon sources of mode conversion is adifference in the time delay of each chan-nel. This line-to-line skew within a channel

34 Xcell Journal Summer 2004

Figure 2 – SDD11 in the frequency domain for abackplane channel, measured with an AgilentPNA N4421b four-port VNA and PLTS software.

Figure 3 – SDD11 in the time domain for a back-plane channel, measured with an Agilent PNAN4421b four-port VNA and PLTS software.

Figure 4 – SDD21 in the frequency domain for two different length backplane channels,measured with an Agilent PNA N4421b four-port VNA and PLTS software. The red line isabout 26 inches and the green is about 40 inches.

Figure 5 – Eye diagram calculated from SDD21 in the frequency domain for a backplane differential channel, measured with an Agilent PNA N4421b four-port VNA and PLTS software.Left is 2.5 Gbps and right is 5 Gbps.

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Summer 2004 Xcell Journal 35

will convert differential signals to commonsignals and result in increased rise timedegradation of the differential signal andlarger deterministic jitter.

The total amount of common signalcoming out of port 2, based on a pure dif-ferential signal going into port 1, isdescribed by the SCD21 term. Figure 6shows the response for this channel.

Looking at the time evolution of thecreation of the converted common signalcoming out of port 1, we can gain insightinto where the conversion might beoccurring. Figure 7 shows the SCD11term, displayed in the time domain, com-pared with the SDD11 term, which hasinformation about the physical features ofthe channel.

It appears as though most of the modeconversion occurs in the via field of thebackplane side of the connector to thedaughtercard. Additional mode conversionexists at each of the connector locations inthe backplane. This might be caused by thevia fields or an asymmetry between the twolines in the differential pair, such as a spa-tial difference in the dielectric constanteach trace sees.

ConclusionEverything you ever wanted to know aboutthe electrical characteristics of a differentialchannel is contained in the differential S-parameters. They can be measured in thetime domain or the frequency domain anddisplayed in either, and each one offers adifferent insight.

Measurements play an important role inrisk reduction when designing systemsincorporating Rocket IO or RocketIO Xtransceivers. Although it is important tointegrate simulation tools into the designprocess to perform cost/benefit analyses oftechnology and design tradeoffs, it is alsoimportant to use measurements to verifythe accuracy of the simulation process.

Measurements can also offer immediateinsight into the behavior of first articlehardware to evaluate whether they meetspecifications, and how well the intercon-nects will interact with the silicon.

Additional ResourcesFor more information about this and other signal integrity topics, visit www.BogEnt.com.

Acknowledgments The data in this paper was graciously provided by Maria Brown of AgilentTechnologies and Al Neves and DimaSmolyansky of TDA Systems Inc.

Figure 6 – SCD21 displayed in the time domain,showing the converted common signal when the incident differential signal is 400 mV. The conversion is about 2.5%.

Figure 7 – Comparing SCD11 (top) withSDD11 (bottom) displayed in the time domain,showing the converted common signal comingout of port 1 coincident with the reflected differential signal out of port 1. This helps identify the location of the mode conversion.

Xilinx Events and Tradeshows

Xilinx participates in numerous trade shows and events throughout the year.

This is a perfect opportunity to meet our silicon and software

experts, ask questions, see demonstrations of

new products and technologies, and hear other customers’ success

stories with Xilinx products.

For more information and the most up-to-date schedule,

visit: www.xilinx.com/events/.

Worldwide Events Schedule

May 5Mentor Graphics EDA TechForumPrague, Czech Republic

May 17-20ICASSPMontreal, Canada

June 20-23ASEE Annual Conference & ExpositionSalt Lake City, UT

July 7Mentor Graphics EDA TechForumMunich, Germany

September 14-15Embedded Systems ConferenceBoston, MA

September 27-30Global Signal Processing ExpoSanta Clara, CA

Xilinx Events and Tradeshows

Xilinx participates in numerous trade shows and events throughout the year.

This is a perfect opportunity to meet our silicon and software

experts, ask questions, see demonstrations of

new products and technologies, and hear other customers’ success

stories with Xilinx products.

For more information and the most up-to-date schedule,

visit: www.xilinx.com/events/.

Worldwide Events Schedule

May 5Mentor Graphics EDA TechForumPrague, Czech Republic

May 17-20ICASSPMontreal, Canada

June 20-23ASEE Annual Conference & ExpositionSalt Lake City, UT

July 7Mentor Graphics EDA TechForumMunich, Germany

September 14-15Embedded Systems ConferenceBoston, MA

September 27-30Global Signal Processing ExpoSanta Clara, CA

www.xilinx.com/si_xcell.htm S I G N A L I N T E G R I T Y

Page 36: Xcell Journal Issue 49

by Joel TanApplications EngineerXilinx Global Services Division – Asia [email protected]

Xilinx Virtex-II Pro X™ devices containRocketIO™ X multi-gigabit transceivers(MGTs) capable of 10 Gbps line rates, rep-resenting the leading edge of serial I/O per-formance. In Virtex-II Pro™ devices, up to3.125 Gbps are available from eachRocketIO transceiver, with the largestdevice in the family possessing 20 MGTs.When channel bonded together, they yielda single aggregated data channel with 62.5Gbps of bandwidth.

At line rates as much as two orders ofmagnitude higher than single-ended I/O, laband test equipment used in the developmentenvironment must keep up. Unfortunately,equipment designed for use with high-speedserial I/O systems may consume a large por-tion of program budgets.

Should limited access to high-speedequipment stop you from reaping the bene-fits of serial I/O? In this article, we’ll presenta solution that can lift this barrier to entryand make serial technology more accessible.It can also maximize the availability ofexpensive lab equipment for other projects.

The solution comprises a bit-error rate(BER) testing module connected to a flex-ible on-chip logic analyzer core, bothimplemented in FPGA fabric. Togetherwith ChipScope™ Pro software tools,these two components can replace thediagnostic functions of a high-speed BERtester and logic analyzer, which togethercould cost more than $50,000.

RocketIO Design Flow OverviewDesigning a RocketIO system requires youto simulate the system’s digital and analogportions. Figure 1 shows the typical flowfor an MGT design.

To ensure a reliable link, SPICE simu-lation of the analog system is mandatory.

An accurate setup must include all of thephysical connections between transmitter toreceiver, using accurate models for each ofthe vias, traces, connectors, and transmis-sion media. (The importance of SPICEsimulation is highlighted elsewhere withinthis series of signal integrity articles.)

At the same time, you must also simu-late MGT functionality together with userlogic; Xilinx provides MGT SmartModelsfor this purpose. Please refer to AnswerRecord #14596 in the Xilinx AnswersDatabase for HDL simulator requirements.

Using the simulation results, youcan then design and build the proto-type board for further testing. It is dur-ing this hardware test, debug, anddevelopment phase that you can realizethe benefits of this complete, low-costdebugging solution.

Debugging Challenges The RocketIO MGT functional blockdiagram shown in Figure 2 is dividedinto two layers. Functions in the phys-ical media attachment (PMA) layer areimplemented digitally, while those inthe physical coding sublayer (PCS) arepredominantly analog.

Diagnosing a serial link issue is alsosplit along the same divide: analog anddigital.

Locating errors in digital logic is afamiliar process because symptoms areeasily reproducible and isolated. Youcan detect and fix deterministic errorsin hardware by comparing captureddata from a logic analyzer againstexpected data from simulation.

Problems are more difficult to diag-nose for the analog portion, especiallyif errors seem to occur infrequently andrandomly. Results vary from trial to

Choose serial I/O technology for yourdesigns without relying on expensivehigh-speed lab equipment.

A Low-Cost Solution forDebugging MGT DesignsA Low-Cost Solution forDebugging MGT Designs

36 Xcell Journal Summer 2004

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trial because of the random nature inwhich errors occur. However, over a num-ber of repeated trials, it is possible toreproduce them reliably. The BER testdoes just this, and provides a useful met-ric for link performance.

Why Use BER Measurements? BER equals the number of bit errors divid-ed by the total number of bits transmitted.To measure the BER, test patterns are sentover the serial link and then compared tothe original pattern at the receiver. Becausethe occurrence of errors is modeled as a sto-chastic process, a calculated minimumnumber of bits are transmitted before theBER is statistically valid. Xilinx ApplicationNote XAPP661 discusses the method forcalculating the confidence and precision ofthe BER measurement in detail.

Although many factors affect link per-formance, the final figure of merit for linkreliability is the BER. These factors includesignal trace design, clock quality, powerintegrity, and even impedance mismatchesdue to loose manufacturing tolerances. TheBER metric has a systemic scope that coversall these factors, such that an anomaly in anypart of the link (or its associated subsystem)will manifest as a higher than expected BER.

One assumption inherent to the BERmeasure is that the errors follow a Gaussiandistribution. You should always test this byexamining the distribution of errors in thedata stream. If you observe bursts of errors,then the errors are non-random. Thisshould prompt you to check if they arerelated to any noise sources, or even to thedata pattern itself.

To simplify MGT designs, Xilinx pro-vides a comprehensive list of power supplyand oscillator recommendations within theRocketIO User’s Guide. Power integrity isvirtually eliminated as a potential cause fora high BER if these recommendations arestrictly followed. Similarly, clock quality isaddressed by the oscillator recommenda-tions. To date, the majority of signalintegrity issues have been traced to non-recommended power supply and oscillatorconfigurations.

BER testing also verifies that your SPICEsimulations resulted in a physical connec-

ing BERs before and after each change. This is useful for quick what-if scenario

testing of changes made to any part of thelink, such as the PCB, power supply, clocksource, connectors, and cables. An exampleof this is during a cost-down effort, wherecost reductions are traded off with perform-ance based on how each component changeinfluences BER.

XBERT – The “Soft” BER TesterThe XBERT module pictured in Figure 4measures BER and is delivered as a refer-ence design with XAPP661. It uses anMGT to transmit serial data constructed

tion that delivers all the performance ofwhich the silicon is capable. With power andclock quality taken care of, any differencebetween measured and simulated resultscomes down to the accuracy of the modelsand manufacturing processes. To differenti-ate between these, use time-domain reflec-tometry (TDR) measurements of thehigh-speed traces to check impedance devia-tions from the PCB specification.

Determining the root cause of poor BERis not straightforward, since multiple factorsinteract to produce the measured effect.However, you can observe how incrementalchanges affect link performance by compar-

Summer 2004 Xcell Journal 37

Run SPICE Simulation

Eye QualityAcceptance?

Prototype

Production

Simulate in ModelSim

Serial LinkCharacterization

XBERT withChipScope Used

Here

ChipScope UsedHere

XBERT UsedHere

Verify LogicFunctionality

Hardware Test and Verification

Are ResultsExpected?

Design GoalMet?

No LogicErrors?

NN

NN

YY

YY

Channel Bondingand

Clock Correction

TX Clock Generator

RX Clock Generator

ReceiveBuffer

TransmitBuffer

8B / 10BDecode

ElasticBuffer

20X Multiplier

Loop

back

PMAPCS

FIFO Serializer8B / 10BEncode

(Analog)(Digital)

CRC

CRC

Deserializer

TX+

TX-

RX+

RX-

REFCLK

From FPGAFabric

To FPGA

Fabric RX DATA

TX DATA

Figure 1 – Typical RocketIO design flow

Figure 2 – MGT block diagram

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by a pattern generator, whilea pattern follower and com-pare logic detects bit errors atthe receiver.

Control signals into themodule toggle resets and selectbetween various pseudo-ran-dom bit sequence (PRBS) andclock patterns, while the out-puts provide statistics for BERcalculation.

An idle MGT, placed closeto the active MGT, provides asimulated noise source that isuseful when diagnosing inter-ference from nearby MGTs.Such active noise is often cou-pled to other MGTs throughthe power supply or throughpoorly designed traces.

An appropriate test patternmust stress the link sufficient-ly to accurately simulate thedata-dependent stresses that itwill encounter with real traf-fic. The patterns in XBERTare International TelecommunicationUnion (ITU) recommended test patternsused in standards such as SONET and 10Gigabit Ethernet.

By stepping through the various stress lev-els and running each for a short time, youcan obtain a coarse measure of link perform-ance quickly. As the link reliability improves,patterns should get harder and you will needto run tests for longer periods.

On its own, XBERT is by no means acomplete replacement. (For example, jittertolerance testing is required by some stan-dards, which XBERT cannot perform.) Butit can perform many of the more time- andresource-intensive measurements thanBERT test equipment can. XBERT frees uplab equipment for other measurements andmakes more lab resources available.

Solution Overview When implemented in Virtex-II Pro devices,the combination of XBERT and ChipScopesoftware takes a form similar to the blockdiagram in Figure 3. In this particular testsetup, the data is looped back at the far endso that both links are tested in the same trial.

Alternatively, you can have another XBERTat the far end to test each link independently.

The inputs to XBERT are connected toChipScope virtual I/Os (as shown) or to userlogic. XBERT outputs such as the frameerror count and bit error count are read bythe ChipScope integrated logic analyzer(ILA) core and used as trigger conditions.

Together, the pair provides powerful diag-nostic functionality as a data analyzer. Youcan trigger on a bit error or a combination ofconditions to isolate certain types of errors.At the same time, you can sample thereceived data to examine the data patternaround an error condition.

This provides useful clues to identify theroot cause of a bit error, especially if it is data-dependent. For example, if DC balance isdisrupted, then bit errors will probably occurafter long run lengths.

The ChipScope Pro tool implements alogic analyzer within the FPGA withoutadditional hardware. It is a real-timedebugging solution that lets you look atsignals in a design as it is running. You canexamine more ports simultaneously withChipScope Pro software than with any

other logic analyzer equip-ment available today.

Each FPGA requires aChipScope ICON core toenable this JTAG connectionto the host PC. In turn, theICON core supports as manyas 15 ILA, ILA/ATC,IBA/OPB, IBA/PLB, andVIO cores. The maximumnumber of signals possible perILA core is limited by theamount of logic resourcesavailable up to a maximum of16 trigger ports, each with amaximum width of 256 bits.

The ChipScope Pro analyz-er GUI has a convenient wave-form viewer that formats thesampled data in the same wayas common HDL simulators.You can view MGT data andstatus signals as they appear insimulation, thus speeding upthe verification process.

Typical Debugging FlowLet’s consider a scenario where you aredebugging a new prototype board and biterrors are reported by the user logic.

ChipScope software can monitor any busor signal in the design. By manipulating theChipScope probe locations in the designhierarchy, you can narrow in on the problemby comparing the data in hardware againstsimulation results at various checkpoints.When the digital logic has been eliminated asa possible cause, you can then proceed todebug the analog portion.

Here are some debugging steps to takewhen using the solution:

1. Double-check the power supply andoscillator choices against Xilinx recom-mendations.

2. Using ChipScope software, examine thereceived data and status signals directlyfrom the MGT outputs before any userlogic. If all is as expected, then the userlogic is at fault.

3. Use parallel and serial loopback modesto check transceiver settings and verifycorrect MGT operation.

38 Xcell Journal Summer 2004

JTAG or Agilent TPAConnection

Host PC

ChipScopeICONCore

MGT

XBERT Module

Downstream Transceiverin Data Loopback

MGT

ChipScopeVirtual I/O(VIO) Core

FPGA

ChipScope ILA Core

CapturedSamples

GigabitBER_TX GigabitBER_RXMGT_BER_4

InitSequence(Comma)

PatternGenerator

TX FSM

ProgDelay

IdleMGT

ActiveMGT

CommaDetect

RX FSM

PatternFollower

PatternCompare

Frame Counters

Figure 3 – XBERT with ChipScope software

Figure 4 – Single-channel XBERT block diagram

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4. Use ChipScope software to check theassociated status signals for each of theMGT functions in the following order:

a) Clock and Data Recovery

b) Comma alignment

c) 8b/10b

d) Clock correction

e) Channel bonding

f) Cyclic redundancy check (CRC).

5. Run BER tests on the PCB traces to seeif the physical link itself can operatereliably at the target line rate. Try pro-gressively more challenging patterns ifno errors are detected with easier testpatterns.

6. Using XBERT with ChipScope soft-ware as a data analyzer, examine the dis-tribution of bit errors and check if theseerrors are related to any noise sources.

7. Measure TDR and analyze trace and viaconstruction.

8. If possible, gather more informationusing other lab equipment.

Debug FasterThe ChipScope tool speeds up debug-ging. When using ChipScope software,changing the trigger signal or data signalsource does not require changes to theHDL code or re-synthesis, so you canchange probe points to any signal withinthe same clock domain very quickly. Toeffect these changes, you need only rerunpost-synthesis implementation, resultingin significantly shorter implementationiterations.

The ChipScope cores can be quicklyand easily removed and inserted via thecore inserter GUI. You can also place signalprobes much faster than with a conven-tional logic analyzer, especially with widesignal buses.

The XBERT with ChipScope solutionoperates independently of user logic, soft-ware, and system-level control. Beforemeasuring BER, the FPGA is simply con-figured using an image containingXBERT and ChipScope software. You canmodify that same image to fit differentdevices and easily reuse the same designand techniques.

Crowded Boards and Remote ControlWith increasing FPGA device densities,high pin counts make attaching test equip-ment probes a real challenge. Given the buswidths common today, numerous externaltest points are necessary; this greatly reducesthe number of remaining I/Os.

In applications where board space is aconcern, connectors for these test pointsconsume precious real estate. The problemis further complicated by having to routethese bus traces in tight places.

ChipScope software addresses this byrequiring only a four-pin JTAG connec-tion to the host PC. Because this connec-tion is often provided for Boundary Scantesting during production, in most casesno additional pins are needed for theChipScope tool.

Another advantage of the solution isthat ChipScope virtual I/Os are used totoggle ports on the MGT and other con-trol signals, when board space restrictionsdo not allow push buttons or DIP switch-es. In addition, they can also replace man-ual controls in an environmental testingcontext, giving full control over any net inthe design.

If the selected device is too fully uti-lized for ChipScope software, try using thenext larger footprint-compatible deviceduring development. You can keep costslow by switching back to the smallerdevice for production.

The additional logic resources availablethrough the use of footprint compatibilityare freed up when ChipScope software andXBERT are not in use. Should the needarise, these resources can accommodate newfeatures and design revisions that outgrowthe original device. This eliminates the needfor a board redesign, as the footprint can fita range of FPGA densities.

Even without the option of a footprint-compatible device, you can employ a divide-and-conquer strategy to debug parts of userlogic at a time, leaving sufficient resourcesto implement the two solution components.

ConclusionThe Xilinx XBERT with ChipScope solu-tion enables faster diagnostic testing, debug-ging, and development of an MGT system

without the use of expensive lab equipmentsuch as logic analyzers and BERT testers.These significant cost savings reduce totalserial system development costs, allowingeven more budgets to benefit from multi-gigabit serial technology.

Xilinx will be offering a signal integritycourse in the coming months. In themeantime, to find out more about thecomplete serial connectivity solution fromXilinx, please contact your local FAE formore information, or visit the followingweb resources:

• XAPP661 –http://direct.xilinx.com/bvdocs/appnotes/xapp660.pdf

• ChipScope Pro –www.xilinx.com/ise/verification/chipscope_pro.htm

• “Designing with Multi-Gigabit SerialI/O” Course – www.xilinx.com/support/training/abstracts/rocketio.htm

• Serial Tsunami Solutions – www.xilinx.com/xlnx/xil_prodcat_product.jsp?title=hsd_high_speed.

Summer 2004 Xcell Journal 39

"My application uses four channel-bonded MGTs to

communicate between processor boards in a universal

mobile telecommunications system. The 128-bit wide chan-

nel-bonded data and numerous status signals made it very

difficult to debug using a traditional logic analyzer.

ChipScope Pro™ enabled me to easily and accurately

examine even the widest data paths and internal signals.

XBERT also proved useful in verifying my PCB and back-

plane design. This solution enabled me to locate and fix a

particularly elusive bug and is a great debugging tool.

With the assistance of a Xilinx Engineer on-site via

the Xilinx Titanium Technical Service program, we very

quickly started debugging using the advanced capabili-

ties of ChipScope Pro. The Xilinx AE also introducted us

to the use of XBERT as described in this article. The use

of Xilinx Titanium Technical Service saved us many

weeks of debug time!”

Hyung-Rak KimHardware Engineer, UMTS Wireless SystemsLG Electronics

A Success Story

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by Istvan Novak, Ph.D.Senior Signal Integrity Staff EngineerSun [email protected]

More designers are determining the requirementsand completing the design of power distributionnetworks (PDN) for FPGAs and CPUs in the fre-quency domain. Although the ultimate goal is tokeep the time-domain voltage fluctuation (noise)on the PDN under a pre-determined maximumlevel, the transient noise current that creates thenoise fluctuations may have many independent andhighly uncertain components, which in a complexsystem are hard to predict or measure.

The impedance gradient of power planes around bypass capacitors depends on the impedance of planes and the loss of bypass capacitor.

Tolerance Calculations in Power Distribution Networks

40 Xcell Journal Summer 2004

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Figure 1 is a simple sketch of a PDN [1]with two test points. In the frequencydomain, you can describe this networkwith a two-by-two impedance matrix,where the indices refer to the test points.Z11 and Z22 are the self impedances at testpoints 1 and 2, respectively, and Z12 andZ21 are the transfer impedances betweentest points 1 and 2.

With very few exceptions, the PDNcomponents are electrically reciprocal;therefore the two transfer impedances areidentical, and can be replaced with a mutu-al impedance term:

Z12 = Z21 = ZM.

You cannot assume electrical symme-try, however, so Z11 and Z22 are, in gen-eral, different. You can calculate the noisevoltages at test points 1 and 2 generatedby the noise currents of I1(t) and I2(t) ofthe two active devices with the followingformula:

V1(t) = Z11I1(t) + ZMI2(t)V2(t) = ZMI1(t) + Z22I2(t)

A PDN comprises power sources(DC/DC, AC/DC converters, batteries);low- and medium-frequency bypass capac-itors; PCB planes or other metal structures(a collection of traces or patches); packageswith their PDN components; and thePDN elements of the silicon [2]. Whendealing with board-level PDN, its imped-ance contributions to the overall PDN per-formance are much more stable and

could use in a PDN. Each curve has a label,giving the C, ESR, and ESL valuesassumed for the part. The SRF and Q val-ues are also shown for each part. With thesenumbers, the 100 uF part could be a tanta-lum brick; the 1 uF and 0.1 uF parts couldbe multi-layer ceramic capacitors (MLCC).

When connecting capacitors with dif-ferent SRFs in parallel, they may createanti-resonance peaks where the impedancemagnitude exceeds the lower boundary ofthe composing capacitors’ impedance mag-nitude values [4] [5]. The impedancepenalty gets bigger as the Q of capacitorsgets bigger, or as their SRFs are fartherapart in frequency.

The anti-resonance peaks get even big-ger when you consider the possible toler-ances associated with the capacitorparameters. We illustrate this in Figure 4,which shows what happens in typical, best,and worst cases when you connect the threecapacitors from Figure 3 in parallel. Theplot assumes no connection impedance ordelay between the capacitors. You can usethis assumption as long as the distancebetween the capacitors is much less thanthe wavelength of higher frequency ofinterest, and the connecting series planeimpedance is much less than the imped-ance of capacitors.

The frequency plot extends up to 100

predictable, so much so that weoften forget to analyze our PDNdesigns against component toler-ances. In this article, we’ll showhow tolerances of bypass-capacitorparameters, such as capacitance(C), effective series resistance(ESR), effective series inductance(ESL), and capacitor locationimpact the impedance of PDNs.

C, ESR, and ESL Tolerance EffectsFigure 2 shows the simple equivalent cir-cuit of a bypass capacitor when neglectingthe parallel leakage of the capacitor. Theseries capacitor-resistor-inductor circuitshows a resonance frequency with a givenquality factor (Q). You can calculate theseries resonance frequency (SRF) and Qfrom the equations below:

Although in a general case all three ele-ments in the equivalent circuit are frequen-cy-dependent [3], for the sake of simplicity,and because it would not change the con-clusions of this article, we’ll use frequency-independent constant parameters.

Figure 3 shows the impedance magni-tudes of three different capacitors you

Summer 2004 Xcell Journal 41

PCB

Bypass Capacitor

Active DevicePower Planes

Test Point 1 Test Point 2

C ESR ESL

Impedance Magnitudes of Capacitors [Ohm]

1.E-02

1.E-01

1.E+00

1.E-02 1.E-01 1.E+00 1.E+01 1.E+02

Frequency [MHz]

100 uF

0.1 Ohm

10 nH

SRF = 0.16 MHz

Q = 0.1

1 uF

0.02 Ohm

3 nH

SRF = 2.91 MHz

Q = 2.7

0.1 uF

0.05 Ohm

0.8 nH

SRF = 17.8 MHz

Q = 1.8

Figure 1 – Simple sketch of a PDN with two active devices,three capacitors, and one pair of power planes

ESRC

ESL

QESLC

SRF == ;*2

Figure 2 – Three-element equivalent circuit of bypass capacitors

Figure 3 – Impedance magnitudes of three stand-alone bypass capacitors

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MHz, which represents a wavelength of 15meters in FR4 PCB dielectrics. This tells usthat the lumped approximation is valid inthis entire frequency range, no matterwhere we place these capacitors on a typi-cal-size PCB.

Table 1 lists the percentage toleranceranges for the C, ESR, and ESL valuesused in Figure 3. We calculated theimpedance curves and tolerance analysiswith a simple spreadsheet [6]. The spread-sheet calculates the complex impedanceresulting from the three parallel connectedimpedances. During tolerance analysis,the spreadsheet steps each parameter sys-tematically though their minimum andmaximum values – specified by the toler-ance percentage entered – and accumu-lates the lowest and highest magnitudes ateach frequency point.

For Figure 4, we assume acapacitance tolerance of +-20%for all three capacitors. For ESR,datasheets usually state the max-imum value but no minimum,so we can assume a +0 to -50%tolerance around the nominalvalue. ESL strongly depends onboth the capacitor’s construc-tion and its mounting geometry.For this example, we assume +-25% inductance variation.

Figure 4 also shows the impedance mag-nitudes of the individual capacitors withthin lines. The three heavy lines in the fig-ure represent the maximum, typical, andminimum values from all possible tolerancepermutations. All three curves exhibit twopeaks: the first around 1 MHz and a sec-ond around 10 MHz.

The trace representing the typical casehas an impedance magnitude of 0.11Ohms and 0.24 Ohms at these peak fre-quencies, respectively. Impedance at andaround the first peak is mostly below theimpedance curves of the 100 uF and 1 uFcapacitors. The second peak, however,exceeds the lower boundary of the imped-ance curves of the 1 uF and 0.1 uF capaci-tors by about a factor of two. This is atypical anti-resonance scenario.

In a worst-case combination of compo-

nent tolerances, the second anti-resonancepeak increases from 0.24 Ohms to 0.77Ohms, a 220% increase. The contributorsto the second anti-resonance peak are theESR and ESL of the 1 uF capacitor, and theC and ESR of the 0.1 uF capacitor. The sumof the tolerances of these four parameters is145%, but they increase the impedance atthe peak by 220%. This illustrates that theresonance magnifies the tolerance window.

Bypass Capacitor RangeBypass capacitors are considered to becharge reservoir components, and commonwisdom tells you to put them close to theactive device they need to feed. We willshow here that when the capacitor and theactive device are connected with planes, theratio of plane impedance and ESR ofcapacitor will determine the spatial gradi-ent of impedance around the capacitor.Even at low frequencies, the impedancegradient can be significant.

Let’s look at the self-impedance distri-bution over a 2” x 2” plane pair with 50 milplane separation. You will get this planeseparation if you have just a few layers inthe board and if they are not placed next toeach other in the stack-up. The characteris-tic impedance of these planes is approxi-mately 1.7 Ohms. You can calculate theapproximate plane impedance from ourthird equation [7]:

where Zp is the approximate plane imped-ance in Ohms and h and P are the planeseparation and plane periphery, respec-tively, in the same but arbitrary units.

We assume one piece of capacitor locatedin the middle of theplanes. MLCC capacitorsare available with as muchas a few hundred uFcapacitance in the 1210case style, and their ESRcan be as low as one mil-liohm. For this example,we use C = 100 uF, ESR =0.001 Ohm, ESL = 1 nH.The SRF of this part is0.5 MHz.

42 Xcell Journal Summer 2004

Impedance of Three Parallel Capacitors [Ohm]

1.E-02

1.E-01

1.E+00

1.E-02 1.E-01 1.E+00 1.E+01 1.E+02

Frequency [MHz]

Max: 0.22Typ: 0.11Min: 0.079

Max: 0.77Typ: 0.24Min: 0.13

C1 tol. [%] C2 tol. [%] C3 tol. [%]

Capacitance [uF]: 100 20 1 20 0.1 20-20 -20 -20

ESR [Ohms]: 0.1 0 0.02 0 0.05 0-50 -50 -50

ESL [nH]: 10 25 3 25 0.8 25-25 -25 -25

Figure 4 – Typical, highest, and lowest impedance curves of the three parallel connected capacitors shown in Figure 3

Table 1 – Parameters used for Figure 4

Ph

Zr

532=

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The surface plot of Figure 5 shows thevariation of self-impedance magnitudeover the plane at 0.5 MHz. The gray bot-tom area of the graph represents the topview of the planes. The grid on the bot-tom area shows the locations where theimpedance was calculated: the granularitywas 0.2 inches. The logarithmic verticalscale shows the impedance magnitudebetween 1 and 10 milliohms.

We calculated the surface imped-ance with a spreadsheet [8]. Themacro in the spreadsheet calculatesthe impedance matrix by evaluatingthe double series of cavity reso-nances. It then combines the com-plex impedance of plane pair withthe complex impedance of thebypass capacitor.

The impedance surface at 0.5MHz has a sharp minimum in themiddle; here the capacitor forces itsESR value over the plane imped-ance. However, as we move awayfrom the capacitor, the impedancerises very sharply. At 0.2 inches away,the impedance is approximately50% higher; 0.4 inches away, theimpedance magnitude doubles. Atthe corners of the 2” x 2” plane pair,the impedance magnitude is almost10 milliohms.

When changing either the planeimpedance or the ESR of capacitorso that their values are closer, thevariation of impedance over theplane shape gets smaller. Figure 6shows the impedance surface of thesame plane shape and same capaci-tor in the middle, except weincreased ESR from 1 to 7 mil-liohms and decreased the plane sep-aration from 50 to 20 mils. Nowthe impedance surface at SRF variesonly about 10% over the plane area.

For Figures 5 and 6, you can seethe same characteristic behavior ifyou sweep the frequency over a widerfrequency range in the spreadsheet.The impedance surface of Figure 5changes and fluctuates significantly,while the impedance surface ofFigure 6 changes less with frequency.

Note that this trend does not change ifwe have more capacitors on the board. Ifwe have significantly different planeimpedance and cumulative ESR of capac-itors, the impedance gradient will be big,and we must use many capacitors to holdthe impedance uniformly down over abigger area even at low frequencies.

ConclusionThe impedance tolerance window at theanti-resonance peak of paralleled discretebypass capacitors widens with higher Qcapacitors. To keep the impedance windowdue to tolerances small, you need eithermany different SRF values tightly spacedon the frequency axis, or the Qs of capaci-tors must be low.

Contrary to popular belief, the serv-ice range of low-ESR capacitors isseverely limited when connected toplanes of much higher impedance. Butyou can achieve the lowest spatialimpedance gradient if the cumulativeESR of bypass capacitors is close to thecharacteristic impedance of planes.

References

[1] Novak, I. “Frequency-Domain Power-

Distribution Measurements – An Overview,

Part I” in HP-TF2, Measurement of Power

Distribution Networks and their Elements.

DesignCon East, June 23, 2003, Boston.

[2] Smith, L.D., R.E. Anderson, D.W.

Forehand, T.J. Pelc, and T. Roy. 1999. Power

Distribution System Methodology and

Capacitor Selection for Modern CMOS

Technology. IEEE Transactions on Advanced

Packaging 22(3): 284-290.

[3] Novak, I., and J. R. Miller. “Frequency-

Dependent Characterization of Bulk and

Ceramic Bypass Capacitors” in Proceedings of

EPEP, October 2003, Princeton, NJ.

[4] Brooks, Douglas. 2003. Signal Integrity

Issues and Printed Circuit Board Design.

Upper Saddle River: Prentice Hall.

[5] Ritchey, Lee W. 2003. Right the First Time,

A Practical Handbook on High Speed PCB

and System Design, Volume 1. Glen Ellen:

Speeding Edge.

[6] Download Microsoft™ Excel spreadsheet

at http://home.att.net/~istvan.novak/tools/

bypass49.xls

[7] Novak, I., L. Noujeim, V. St. Cyr, N.

Biunno, A. Patel, G. Korony, and A. Ritter.

2002. Distributed Matched Bypasssing for

Board-Level Power Distribution Networks.

IEEE Transactions on Advanced Packaging

25(2):230-243.

[8] Download Microsoft Excel spreadsheet at

http://home.att.net/~istvan.novak/tools/

Caprange_rev10.xls

Summer 2004 Xcell Journal 43

1.E-03

1.E-02

Self-Impedance Magnitude [Ohm]

1.E-03

1.E-02

Self-Impedance Magnitude [Ohm]

Figure 5 – Self-impedance at 0.5 MHz on a 2” x 2” plane pair with 50 mils dielectric separation, with a 100 uF,

0.001 Ohm, 1 nH capacitor located in the middle

Figure 6 – Self-impedance at 0.5 MHz on a 2” x 2” plane pair with 20 mils dielectric separation, and a 100 uF,

0.007 Ohm, 1 nH capacitor located in the middle

www.xilinx.com/si_xcell.htm S I G N A L I N T E G R I T Y

Page 44: Xcell Journal Issue 49

by Suresh Sivasubramaniam Senior Design EngineerXilinx, [email protected]

Philippe GarraultTechnical Marketing EngineerXilinx, [email protected]

Xilinx Website ResourcesSignal Integrity Central

www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=Signal+Integrity

This Xilinx portal has everything you need toachieve reliable PCB designs on the first pass.It covers signal integrity fundamentals, powersupply and bypassing, simulation tools, PCBdesign and thermal considerations, andmulti-gigabit signaling, with a variety of doc-uments, FAQs, and links.

White Papers and Application Notes

http://direct.xilinx.com/bvdocs/whitepapers/wp174.pdf

White Paper WP174, “Methodologies forEfficient FPGA Integration into PCBs,”describes how PCB design considerations playa major role in obtaining the expected per-formance from FPGAs. It then focuses onearly analysis and simulation methodologies asa way of performing a guided implementation.

www.xilinx.com/bvdocs/appnotes/xapp623.pdf

Application Note XAPP623, “PowerDistribution System (PDS) Design: UsingBypass/Decoupling Capacitors,” detailsVirtex™ power supply requirements andtechniques for designing power distributionsystems using bypass/decoupling capacitors.

www.xilinx.com/bvdocs/appnotes/xapp689.pdf

Application Note XAPP689, “ManagingGround Bounce in Large FPGAs,” explainsthe ground bounce effect, with calculationsto help you derive an FPGA pinout thatmeets input undershoot and logic-low volt-age requirements for devices receiving signalsfrom an FPGA.

www.xilinx.com/bvdocs/appnotes/xapp609.pdf

Application Note XAPP609, “LocalClocking Resources in Virtex-II™ Devices,”describes the different local clockingresources available in the Virtex-II architec-ture. Along with a reference design, thisapplication note explores local clockingresources in source-synchronous applications.

If you’ve read up to this point in the series, you’re probably thirstyfor additional information about the tools and methods discussed.Thus, we’ve compiled different sources of information availablefrom the Xilinx website and design and education services. We’ve also included references to partner software developmenttools, hardware development platforms, and literature fromrenowned personalities.

High-Speed PCB Design Resources

44 Xcell Journal Summer 2004

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Page 45: Xcell Journal Issue 49

Xilinx and Partner Software Resources

www.support.xilinx.com/support/software_manuals.htm

The ISE software tool suite includes helpfultools like the pin assignment constraintseditor (PACE) to help you during the I/Oplanning and pinout assignment phases.Another helpful tool is Xpower, whichallows you to plan and estimate your FPGApower requirements.

AllianceEDA

www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=Alliance+EDA+Program

Visit this website to learn more about the toolsmentioned in the Xcell SI series. This pageprovides information on all third-party toolsinterfacing with Xilinx software.

Education Courses

www.xilinx.com/support/education-home.htm

Xilinx offers courses about PCB considerationswhen designing with high-performanceFPGAs. The “High-Speed Signal IntegrityDesign” course, for example, teaches how sig-nal integrity techniques are applicable to high-speed interfaces between Xilinx FPGAs andsemiconductor memories.

The course covers high-speed bus and clockdesign, including transmission line termina-tion, loading, and jitter. For additional details,visit the education services website.

Design Services

www.xilinx.com/xds/

Xilinx provides a comprehensive serviceoffering that includes education services,support services, and design services to accel-erate time to knowledge and time to market.To effectively design new multi-gigabit serialsystems, it is imperative to understand thecomplete channel. Xilinx services leveragenew techniques, relying on in-house expert-ise and state-of-the-art tools to create accu-rate models, evaluation platforms, andproduction backplanes. Xilinx helps compa-nies to design, simulate, and characterizeevery aspect of the channel from 1 Gbps tomore than 10 Gbps.

Reference Books

“Computer Circuits Electrical Design” by Ron K. Poon

“Digital Systems Engineering” by William J. Daly and John W. Poulton

“High-Frequency Characterization ofElectronic Packaging” by Luc Martens

“Signal Integrity – Simplified” by Eric Bogatin

“High-Speed Digital Design: A Handbookof Black Magic” by Howard Johnson

“High Speed Signal Propagation: AdvancedBlack Magic” by Howard W. Johnson

“Digital Signal Integrity: Modeling andSimulation with Interconnects andPackages” by Brian Young

“MECL System Design Handbook,”Motorola Semiconductor Products, Inc.

“High-Speed Digital System Design: A Handbook of Interconnect Theory and Design Practices” by Stephen H. Hall,Garrett W. Hall, and James A. McCall

Other Resources

www.signalintegrity.com

www.speedingedge.com

www.gigatest.com

www.nesa.com

www.qsl.net/wb6tpu/si_documents/docs.html

www.ultracad.com

www.teraspeed.com

www.tdasystems.com

ConclusionWe hope that you enjoyed reading this spe-cial SI series and that you feel betterinformed in dealing with signal and powerintegrity issues in your current and futurehigh-speed PCB designs.

If you have any comments or feedbackabout the topics discussed, please e-mail usat [email protected].

RocketIO Multi-Gigabit Serial Transceivers

RocketIO Resources

www.xilinx.com/serialsolution/

The Serial Tsunami Solutions portalprovides you with a wealth of informa-tion on RocketIO™ transceivers, withaccess to transceiver data sheets, charac-terization data, protocols, articles, whitepapers, and a gateway to the SerialBackplane Simulator tool.

The Serial Backplane Simulator

www.xilinx.com/products/xaw/hsd/simulator.htm

The Serial Backplane Simulator providessignal integrity simulations for morethan 300 situations when using Virtex-II Pro™ devices to drive signals acrossbackplanes and line cards. The analyzercovers several different backplane mate-rials, speed, pre-emphasis, lengths, peak-to-peak differential swings, number ofconnectors, and connector types.

RocketLabs

www.xilinx.com/rocketlabs/

With 15 locations around the world,RocketLabs is the first network of labs toprovide system designers with free accessto high-speed equipment, multiple hard-ware evaluation boards, applicationexpertise, signal integrity simulation tools,and presentations and specialized training.

RocketIO Design Kits

www.xilinx.com/support/software/spice/spice-request.htm

From the SPICE suite, you can down-load RocketIO SPICE models anddesign kits. The kits have comprehensivedocumentation and examples that willjumpstart the simulations process andget you to the simulation results analysisphase faster and easier.

Summer 2004 Xcell Journal 45

www.xilinx.com/si_xcell.htm S I G N A L I N T E G R I T Y

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Page 47: Xcell Journal Issue 49

by Joel WoodwardLogic Analysis Project ManagerAgilent [email protected]

FPGAs play an increasingly important rolein project development, where the need forhigh-performance designs with flexiblearchitectures collides with lean engineeringteams, constrained budgets, and rapid devel-opment schedules. Yet traditional in-circuitdebug methodologies limit how quicklydesigners can uncover design problems.

Often, design defects in increasinglycomplex systems may occur exclusively in

real time, when multiple subsystems andsoftware interact. Using FPGAs, designteams can move quickly to system integra-tion, increasing the importance of effectivedebug and validation. With sufficient visi-bility, in-circuit debug of FPGA designscan uncover in just a few minutes prob-lems that might have required hours, days,or weeks to simulate.

Logic analyzer measurements are par-ticularly effective in the debug of FPGAsand surrounding systems. A typical meas-urement approach is to take advantage ofthe programmability of the FPGA to routeinternal signals to a small number of pins.

Although this is a very useful approach, ithas limitations that inhibit productivity.

Because pins on the FPGA are typicallyan expensive resource, there are a relativelysmall number available for debug. One pinis required for each internal signal to beprobed, thereby limiting the visibility ofinternal nodes to the same small number ofsignals. Design teams rarely find this widthof visibility adequate.

When different internal signals aremeasured, new signals are routed out topins; sometimes, a recompile of the designis required. In either case, the change con-sumes valuable engineering resources and

The FPGA Dynamic Probe

Summer 2004 Xcell Journal 47

Innovative technology significantly increases in-circuit debug productivity.

Page 48: Xcell Journal Issue 49

can change the timing of the FPGA. Tomake sense of the measuring, engineersmust manually update logic analyzer labelnames and probe locations to match thenew configuration of the measurementevery time new signals are routed to pins.

New technology from AgilentTechnologies and Xilinx mitigates theissues described above by combiningChipScope™ Pro technology withAgilent’s FPGA dynamic probe logicanalysis application. Figure 1 shows thekey components of the application.

You can use the Xilinx Core Inserter orCORE Generator™ tool to insert anAgilent Trace Core 2 (ATC2) into anFPGA, thus facilitating a more productivedebug session. The core is controlled byAgilent’s FPGA dynamic probe logic analy-sis application software. The applicationruns on Agilent’s 1680, 1690, or 16900series logic analyzers.

Time-to-Market AdvantagesThe FPGA dynamic probe delivers fourprimary benefits:

1. The ATC2 core allows a dynamicapproach to choose internal signals forlogic analysis – without incurring thelimitations (such as potential recom-piles and the associated timingimpact) of the traditional “route outsignals to pins” approach.

Using Core Inserter, you can specifygroups of internal FPGA signals thatmight need measurement. Each groupof signals represents an input to theATC2 core. The core allows onegroup of input signals to be routed topins. With a mouse-click in the logicanalysis application software, the ana-lyzer changes which group of internalFPGA signals are routed through thecore. This capability eliminates theneed to recompile to change signalprobing, saving days of developmenttime per FPGA design. In addition,this method keeps timing constant.

2. Although a 1:1 internal signal-to-pinratio normally exists for debug, theFPGA dynamic probe increases thisvisibility ratio to 64:1. With 32 input

tain types of validation requirements,you can bypass the time-consumingprocess of creating test benches andperform the validation more quicklyin-circuit.

3. The FPGA dynamic probe automatesthe process of label naming when anew set of internal signals is selected.Logic analyzers with this applicationread a file from a .cdc file that theCore Inserter generates. This file con-

groups into the ATC2 core, a singlepin can sequentially gain access to 32internal signals. With an optional2X compression mode, each pinaccesses two signals on each of the32 input groups, for a total visibilityof 64 signals per pin.

This means that for each pin dedicatedto debug, you can access as many as64 internal signals (Figure 2). Withthis increased visibility width for cer-

Agilent Trace Core 2

to FPGA Pins

Change Input BankSelection via JTAGS

elec

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Figure 1 – The FPGA dynamic probe application software can change virtual probe points inside XilinxFPGAs in less than a second. The logic analysis application communicates to a debug core via JTAG.

Figure 2 – Agilent’s second-generation configurable trace core provides visibility to as many as 64 internal FPGA signals for each pin dedicated to debug.

48 Xcell Journal Summer 2004

Page 49: Xcell Journal Issue 49

Summer 2004 Xcell Journal 49

tains all node names of signals thatmay be eventually selected.

Because the tool tracks which signalsare currently routed through theATC2 core, the software applicationrunning on the logic analyzer auto-matically enters signal names andchannel locations on the logic analysissetup menu each time a new set ofinternal signals is probed (Figure 3).This additionally saves time and eliminates errors.

4. The FPGA dynamic probe helps youmake more accurate state measure-ments. The core invokes test stimulusthat is acquired by the logic analyzer.The logic analyzer samples the testpattern and automatically determineswhen to best sample each signal rela-tive to the clock. This calibrationcapability compensates for path lengthvariances, ensuring accurate statemeasurements. This is particularlybeneficial on high-speed circuits withnarrow data valid windows.

Configure the Core to Match Debug NeedsThe ATC2 core is configurable to matchyour design requirements. Number of pins,number of input banks, and sampling mode(timing or state) are some of the configurableparameters. The ATC2 core has been craftedto take minimal space inside the FPGA.

As an example, an ATC2 core with eightbits of visibility on each of 32 input banksconsumes only about 2% of the slices in aXC2V3000 device. This core offers accessto 256 signals using just eight pins.

A smaller number of input banks andfewer pins allows the core to consume fewerFPGA resources. A higher number of inputbanks and more pins increases visibility. Youcan make tradeoffs depending on the spe-cific device and visibility requirements.

The ATC2 core runs as fast as the deviceruns, so measurement speeds are limitedonly by the acquisition capabilities of thelogic analyzer. With state speeds well inexcess of 200 MHz and timing speeds of 4GHz, most new logic analyzers containenough headroom to make accurate FPGAmeasurements for the next several years.

When you have significant debug issues,you can create multiple ATC2 cores thatcoexist peacefully within a single device.The FPGA dynamic probe applicationsoftware can also control ATC2 cores inmultiple FPGAs, as long as the FPGAs areon the same scan chain.

The new technology allows you to moreeasily correlate internal FPGAs to externalevents, thus isolating problems morequickly. When the ATC2 core facilitatesmeasurements internal to the FPGA, thelogic analyzer can time-correlate thesemeasurements with measurements else-where on the target system. This capabilityallows you to gain insight into your systemdesigns more quickly.

The FPGA dynamic probe virtualprobing technology, combined with a logicanalyzer, blurs the boundary betweeninternal FPGA measurements and externalmeasurements.

ConclusionThe joint collaboration between Xilinx andAgilent in producing the royalty-free ATC2core and the FPGA dynamic probe willenable more productive in-circuit debug.Agilent has already used this technologyinternally to shave weeks of developmenttime from a critical project that used mul-tiple Xilinx FPGAs. The lead hardware

engineer found that the solution allowedhim to uncover in a few minutes problemsthat would have traditionally requiredhours or days to reveal.

As FPGA sizes increase and biggerdesigns take advantage of increased densi-ties, successful design teams will adapt byemploying innovative debug methodolo-gies. The FPGA dynamic probe and ATC2core provide critical capabilities for effectivedebugging. With these new tools, you canplan for debug early in the developmentprocess. Employing a design-for-debugmethodology will allow you to keep pacewith ever-increasing design sophistication.

ChipScope Pro software makes it possi-ble for Xilinx FPGA users to easily debugdesigns. ChipScope Pro cores are integrat-ed into the FPGA to provide real-timedebug and verification capabilities via astandard JTAG port. ChipScope Pro isavailable from Xilinx for $695. A 30-daydownloadable evaluation version is avail-able for free. For more information, visitwww.xilinx.com/chipscopepro/.

You can purchase Agilent’s FPGAdynamic probe logic analysis applicationfor an introductory price of $995 throughthe end of 2004. For more information onthe Agilent FPGA dynamic probe, theATC2 core, and supported logic analyzers,visit www.agilent.com/find/FPGA/.

Figure 3 – The FPGA dynamic probe automatically extracts internal signal names and updates the logic analyzer each time new probe points are selected.

Time Correlationwith External Events

New Internal FPGA Probe Points and Associated Signal Names

Page 50: Xcell Journal Issue 49

by Lee HansenSr. Product Marketing Manager, Product Solutions MarketingXilinx, [email protected]

Xilinx Integrated Software Environment(ISE) 6.2i, the newest version of industry-leading Xilinx logic design tools, is focusedon delivering you the highest performanceavailable in PLD design. With ISE 6.2i,Virtex-II Pro™ FPGAs are now on average40% faster than the nearest delivering com-petitive FPGA offering. That’s up to threespeed grades faster, and on silicon and soft-ware delivering today.

Spartan-3™ designers will also benefitsignificantly from using ISE 6.2i. You canimprove performance by as much as 50%when using ISE 6.2i over our last releasethrough a series of Spartan-3 enhancements:

• The Spartan-3 -4 speed grade hasbeen enhanced to deliver higher performance

• The new, faster Spartan-3 -5 speed grade

• The clock-to-output performance hasimproved by 35-40%

• Embedded multiplier performance isas much as 50% faster – greater than225 MHz

• ISE 6.2i now supports automaticlocal clock placement for Spartan-3designs, delivering quicker and moreaccurate off-chip memory interfacedesigns.

ISE 6.2i also continues to deliver 15%better logic utilization over competingsolutions; you can get more design into aXilinx FPGA using ISE. These perform-ance improvements, combined with indus-try-leading cost advantages, are fueling therapid replacement of ASICs and ASSPswith Spartan-3 FPGAs in numerous high-volume applications.

But faster performance has implicationsto all Xilinx customers, whether or notyou’re currently attacking a high-speedproject. High performance means that ISEwill hit your design targets first, with fewercostly design iterations requiring you totweak your code to meet timing.

The latest releases of ISE and ChipScope Pro design tools slash design and verification times while delivering the fastest performance available in PLD-based designs.

The latest releases of ISE and ChipScope Pro design tools slash design and verification times while delivering the fastest performance available in PLD-based designs.

Xilinx 6.2i Design ToolsXilinx 6.2i Design Tools

50 Xcell Journal Summer 2004

Page 51: Xcell Journal Issue 49

Nearly Optimal Place and Route Results Many design tools claim leadership, butISE place and route (PAR) algorithmswere recently tested by researchers fromthe University of California, Los Angeles(UCLA). These independent benchmarktests presented at the InternationalConference on Computer-Aided Design(ICCAD) showed that ISE PAR tools pro-duce near-optimal timing-driven results.In an ICCAD paper titled “Optimalityand Stability in Timing-Driven PlacementAlgorithms,” Microelectronics Center ofNorth Carolina (MCNC) benchmarksdemonstrated that ISE came between 8.3and 4.1% of the optimal PAR solution.

“As part of our placement optimalitystudy, we generated a set of placementbenchmark examples with known optimalsolutions. Our study showed the Xilinxplace and route tools produced consistentlynear-optimal timing results on Virtex-II™series devices,” said Dr. Jason Cong, a pro-fessor at the UCLA Computer Science

ChipScope Pro software lets you insertlow-profile logic analyzer (ILA), bus analyz-er (IBA), and Virtual I/O (VIO) softwarecores into your design or post-synthesisnetlist. These cores allow you to view anyinternal signal or node within your FPGA,including the IBM™ CoreConnect proces-sor local bus, on-chip peripheral bus for theIBM PowerPC™ 405 inside Virtex-II ProPlatform FGPAs, or the MicroBlaze™ softprocessor core. Signals are captured at ornear operating system speed, and broughtout through the programming interface,freeing up pin assignments for your design.The ChipScope Pro logic analyzer can thenanalyze the captured signals (Figure 1).

ChipScope Pro and FPGA Dynamic ProbeChipScope Pro software also links internalFPGA debug to your Agilent™ 16900,1690, or 1680 series logic analyzer throughthe new ATC2 core. ATC2 synchronizesChipScope Pro software to Agilent’s newFPGA Dynamic Probe technology, deliver-ing the first integrated application forFPGA debug with logic analyzers.

This unique partnership between Xilinxand Agilent gives you deeper trace memo-ry, faster clock speeds, and more triggeroptions, all using fewer pins on the FPGA.For more details on ATC2 and the FPGADynamic Probe, see Joel Woodward’s arti-cle, “The FPGA Dynamic Probe,” also inthis issue of Xcell.

ConclusionISE 6.2i and ChipScope Pro 6.2i tools canhelp you realize lower project costs immedi-ately. Release to release, Xilinx is committedto delivering higher performance and short-er implementation and verification cycles,helping you slash design times and loweryour costs. With a performance advantageof as many as three speed grades, the slow-est Virtex-II Pro device is still faster than thefastest competing FPGA in production,helping you save in device costs with theadded potential to get more design intoyour target device.

Download the free 60-day ISE 6.2i eval-uation at www.xilinx.com/ise_eval or thefree 60-day ChipScope Pro 6.2i evaluationat www.xilinx.com/chipscope today.

Department and the faculty member direct-ing the research. “We believe the excellentplacement timing results were achieved byemploying advanced timing-driven place-ment algorithms with efficient exploitationof the segmented routing architecture usedin the Virtex-II series FPGAs.” This is thefirst time a quantitative timing optimalitystudy has been reported on any FPGAplacement and routing tools.

A Unique New Approach to Logic DebugIf you’re looking for a way to slash yourverification cycle, you’ll want to seewhat’s new in the ChipScope™ Pro 6.2irelease. The industry standard for real-time debug, the ChipScope Pro tool(along with Agilent Technologies’ newFPGA Dynamic Probe) combines to cre-ate a logic debug solution that can’t bematched by ASICs or competing FPGAsolutions. ChipScope Pro can slash yourverification cycle by as much as 50%, sav-ing you significant time and money.

Summer 2004 Xcell Journal 51

Figure 1 – ChipScope Pro logic analyzer

This is the first time a quantitative timing optimality studyhas been reported on any FPGA placement and routing tools.

Page 52: Xcell Journal Issue 49

At your Service.From start

to finish.

www.xilinx.com/services Xilinx offers the industry’s broadest portfolio of education, supportand design services to extend your technical capabilities, accelerateyour time to market, and build a competitive advantage.

• Reduce the learning curve

• Speed your design time

• Jump-start your product development cycle

• Lower your overall development costs

Finish FasterXilinx delivers industry-leading service and support through everystep of the design process—around the clock and around the world—to help you get to market faster. From technical support, consultativeservices, and dedicated design assistance to online support and train-ing, you can find it all at www.xilinx.com/services.

The Programmable Logic CompanySM

© 2004 Xilinx, Inc. 2100 Logic Drive, San Jose, CA 95124. Europe +44-870-7350-7722; Japan +81-3-5321-7711; Asia Pacific +852-2-424-5200;Xilinx is a registered trademark and The Programmable Logic Company is a service mark of Xilinx, Inc.

Page 53: Xcell Journal Issue 49

by Hitesh PatelSr. Manager, Software Product Marketing Xilinx, [email protected]

As programmable logic devices increase indensity and complexity, the combinationof a feature-rich fabric and sophisticateddesign tools enables users to realize theirperformance goals faster. Shorter designcycle times also enable users to lower over-all design costs and meet time-to-marketrequirements.

From analyzing 50 customer designs,we determined that Xilinx Virtex-II Pro™FPGAs enjoy a 40% performance advan-tage over their nearest competitor,Altera™ Stratix™ FPGAs, to further real-ize the advantages of FPGAs. With densi-ties ranging from 200,000 to 6 millionsystem gates, the Virtex-II Pro device wasas much as 123% faster than the Stratixdevice. Figure 1 shows the performanceadvantage distribution.

This article highlights how Virtex-IIPro FPGAs, along with ISE 6 designtools, provide a 40% performance advan-tage when compared to Stratix FPGAs.

Virtex-II Pro FPGAs offer marked performance advantages over a competing device.Virtex-II Pro FPGAs offer marked performance advantages over a competing device.

Better... Stronger... FasterBetter... Stronger... Faster

Summer 2004 Xcell Journal 53

Page 54: Xcell Journal Issue 49

Architectural FeaturesThe basic building block in the Stratixarchitecture is called a logic element (LE).An LE contains three functional structures:a four-input look-up table (LUT), a regis-ter, and a carry chain.

Virtex-II Pro architecture not onlyincludes the structures found in an LE, butalso additional functionality, such as afunction expander (MUXF), aMULT_AND arithmetic cell, and a morelogic-rich carry structure.

Furthermore, the Virtex LUT can beused as a 16-bit shift register or as a single-or dual-port RAM element. These addi-tional features in the Virtex-II Pro archi-tecture enable users to realize higherdesign performance, as we’ll describe inthe next section.

MUXF Function ExpanderOne of the primary factors impacting cir-cuit performance in FPGAs are logic levelsin the signal path. The function expandercell represents a 2:1 MUX, which can beused to build functions wider than fourinputs without the need for additionalLUT logic levels.

For example, using the MUXF, onlyfour LUTs are required to implement an8:1 mux in a single LUT logic level. Thatsame 8:1 mux in the Stratix PLD is imple-mented using five LUTs – and the imple-mentation is two LUT logic levels. Theadditional LUT logic level adds delay tothe signal path.

logic levels and also far fewer LUTs con-sumed (10% on average) than for the samefunction in Stratix FPGAs. This results inhigher performance for Virtex-II Pro designsbecause fewer logic levels are generallyrequired for critical paths. At the same time,less placement and routing congestion occursbecause 10% fewer resources (LUTs) are nec-essary to build the same functionality.

Shift Register LUTA LUT in shift register mode (SRL) canimplement a selectable 16-bit shift registerin a single LUT. The same shift register in aStratix device would be implemented using16 flip-flops and as many as 10 LUTs or amemory block, a much less flexible manner.

In a Stratix PLD, if the shift register can-not be implemented in a memory block, a16-bit shift register implemented using 16LEs creates added routing congestion thatmay impact design performance. If the shiftregister requires variable tap selection, thiswill add logic levels on the output path,resulting in much slower operation.

MULT_ANDThe MULT_AND arithmetic cell is com-monly used in soft multiplication applica-tions. However, the flexibility of the FPGAfabric allows some five-input functions tobe mapped onto a single LUT. For exam-ple, loadable up and down counters imple-mented using the MULT_AND functionutilize only one LUT per bit instead of twoLUTs per bit, as in Stratix PLDs. This

The function expander is not limited tomultiplexers; it can be used for many otherlogic functions. For example, a MUXFcombined with two LUTs can implementany function of five inputs, thereby imple-menting a full five-input LUT in a singleLUT logic level. A Stratix implementationwould require two or three LUTs, depend-ing on the function, and would be imple-mented in two LUT logic levels.

Figure 2 shows a nine-input functionmapped onto two LUTs (plus one functionexpander for the Virtex-II Pro architec-ture). The same function requires threeLUTs for the Stratix device and two LUTlogic levels, as opposed to a single LUTlogic level for a Virtex-II Pro device.

The MUXFx component is like having afive- or six-input LUT. This leads to fewer

54 Xcell Journal Summer 2004

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One Logic Level Two Logic Levels

Figure 1 – Virtex-II Pro performance advantage versus Stratix FPGAs for 50 customer designs

Figure 2 – Nine-input function mapped to Virtex-II Pro and Stratix devices

Page 55: Xcell Journal Issue 49

implementation can result in as much as30% faster performance in Virtex-II ProFPGAs because of the fewer logic levelsand fewer required LUTs.

LUT-based RAMsA LUT may also be configured as a single-or dual-port RAM, resulting in very fastread and write access for smaller data stor-ing and buffering applications. In Stratixdevices, the smallest RAM configuration(the M512 blocks) offers much slowerRAM operation and less flexible dual-portaccess, while at the same time requiringgreater latency for reads.

The maximum read speeds for theM512 RAMs are 266 MHz for one-clockcycle reads and 320 MHz for two-clockcycle latency, while the Virtex-II ProSelectRAM™ memory allows 360 MHzread operation with a single clock latency,as well as asynchronous read capability forlow-latency design requirements.

Because small RAMs are often used asdata storage for small FIFOs, coefficientstorage for DSP filters, buffers for packetprocessing, and other applications, havingmaximum performance in this structurecan often enable designers to meet theirsystem performance requirements.

Block RAMsAs most designs typically use a majority ofthe RAM memory available on the device,Stratix users are forced to use the MegaRAMmemory blocks to create their desired func-tionality. For the wide (4k x 144) and deep(64k x 8) configuration of the MegaRAM,we evaluated the read/write performance ofVirtex-II Pro block RAM configured to thesame width and depths as the StratixMegaRAM memory. The results, as present-ed in Table 1, show that for the deep andwide configuration with one clock delay, thememory read time performance in Virtex-IIPro FPGAs is approximately 40% and 95%faster than Stratix FPGAs, respectively.

The wide MegaRAM configuration hasapproximately 300 signals that need to beconnected to the relatively small footprintof the memory block. This leads to regis-ters and logic competing for optimalplacement locations of a few sites in the

array closest to these memory pins. Theadditional routing congestion of these sig-nals impacts overall memory performance.

Because the Virtex-II Pro configurationwas created using smaller RAMs spread outover a greater area of the chip, a more opti-mal placement and routing could be real-ized, resulting in higher performance.

Multiply and AccumulateStratix devices contain a dedicated DSPblock; it is often assumed that it can outper-form that same function created in a Virtex-

II Pro device. Figure 3 highlights themaximum performance, with latency, forthe two popular sizes of implementation fora multiply and accumulate (MAC): 9 x 9and 18 x 18. This analysis shows that Virtex-II Pro devices have faster performance thanStratix devices for the MAC function.

Software FeaturesThe FPGA fabric feature set continues tooffer capabilities that improve design per-formance and reduce area. For users torealize these benefits, the software tools –both synthesis and place and route – needto use these architecture capabilities.

SynthesisFPGA-centric synthesis tools constantlylook for new optimization techniques thatgo beyond mere LUT mapping. Thesesynthesis tools can extract known func-

tions such as arithmetic functions, memo-ries, and multiplexers by parsing the RTLcode, automatically mapping these func-tions to features on the target architecture.

Synthesis mapping to the MUXF,MULT_AND, and SRL are examples of syn-thesis tools providing architecture-specific

Summer 2004 Xcell Journal 55

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Figure 3 – Virtex-II Pro(-7) and Stratix(-5) MAC performance

Figure 4 – Logic versus route delay on the critical path for “blowfish” design

Page 56: Xcell Journal Issue 49

mapping to reduce logic levels on the criti-cal paths, as well as reducing placementand routing congestion, thereby improvingoverall design performance. Synthesis toolswill also automatically infer either the LUTRAM or block RAM based on the codingstyle and the size of memory being used.For example, the Synplicity® Synplify®

software tool may infer fast LUT RAMs foras much as 2k of memory.

As FPGAs go deeper into sub-microntechnologies, routing delays become morepredominant, and design performance ishighly influenced by cell placement. Thus,Xilinx provides detailed timing estimates

to enable synthesis tools to not only selectthe best architecture element for theimplementation, but also to improve tim-ing predictability between post-synthesisand post-layout. This close technical col-laboration ensures that synthesis optimiza-

tion is focused on the path that is criticalto place and route.

Place and RouteA study done by researchers at UCLAshowed that timing-driven placementalgorithms for FPGAs can average 30% offfrom optimal results. The study also foundthat Xilinx tools do much better thanother tools in the industry. For instance,the delay generated by the Xilinx ISE plac-er was only 8.3% worse than optimal andonly 4.1% worse after routing.

To illustrate this advantage, we com-piled the “blowfish” encryption algorithm,an open source design, using ISE 6.2i andAltera Quartus™ 3.0 targeting Virtex-IIPro(-7) and Stratix(-5) devices, respective-ly. Figure 4 represents the breakdown oflogic and route delay for the critical path.

This analysis shows that ISE place-ment technology is able to provide near-optimal placement, resulting in a 80:20logic:route delay ratio for Virtex-II ProFPGAs, whereas the Stratix implementa-tion using Quartus leads to a 50:50logic:route delay ratio. As a result, thedesign is two times faster when imple-mented in a Virtex-II Pro device.

Timing-driven map technology, newin ISE 6 software, is just one example ofyears of Xilinx expertise in place and

route for segmented architectures. Thistechnology enables the mapper to iteratebetween map and place, as shown inFigure 5, such that the placer can providethe mapper with suggested slice-levelprimitive mapping. This iterative loop

leads to near-optimal slice mapping andplacement, resulting in improved timing,because the router can now pick the bestroute with fewer conflicts for the samerouting resources.

Critical SettingsThe performance graphs in Figure 1 showthat the Stratix device outperformed theVirtex-II Pro device in one design. This isbecause our analysis uses default settingsin synthesis, with pipelining “off.”Because the design had a multiply func-tion on the critical path, the Stratix designhad an instantiated pipelined lpm (libraryof parameterized modules) multiplier, ablack-box function generated by theQuartus MegaWizard. For the Virtex-IIPro design, synthesis inferred theMULT18x18 primitive.

By changing pipelining to “on,” thesynthesis tool inferred a MULT18x18Sprimitive for Virtex-II Pro FPGAs,resulting in an implementation withfaster performance compared to StratixFPGAs. So, in real-world designs, you’llsee that Virtex-II Pro devices almostalways outperform Stratix devices.

ConclusionAdvanced architecture features, such asMUXFs, SRLs, MULT_ANDs, fastSelectRAM and block RAM solutions, andfast dedicated multipliers contribute sig-nificantly to the performance advantage ofVirtex-II Pro devices over Stratix devices.

The combination of an advancedarchitecture, the synthesis tool’s capabili-ty to access architecture-specific features,and the place and route software’s abilityto deliver near optimal placement for asegmented architecture result in Virtex-IIPro FPGAs having a 40% average per-formance advantage over Stratix PLDs.

In most cases, the fastest Stratix speedgrade must be used to realize the per-formance of the slowest Virtex-II Prospeed grade. A Stratix device in any speedgrade cannot match the performance seenin the faster speed grades of Virtex-II Prodevices. Virtex-II Pro FPGAs reach a newlevel of performance not matched by anyother FPGA in the industry today.

56 Xcell Journal Summer 2004

MAP MAP

PLACE PLACE

ROUTE ROUTE

Flow withoutTiming-Driven Map

ISE 6.2i Flow withTiming-Driven Map

Write Speed Read Speed

Configuration Clock Delays Stratix [MHz] Virtex-II Pro [MHz] Stratix [MHz] Virtex-II Pro [MHz]

Deep Single-Port 1 287 282 199 282Memory 64k x 8

2 287 282 287 282

Wide Single-Port 1 255 284 145 282Memory 4k x 144

2 255 287 255 287

Figure 5 – ISE 6.2i timing-driven map flow

Table 1 – Virtex-II Pro(-7) and Stratix(-5) block RAM performance

Page 57: Xcell Journal Issue 49

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• Key enabling technologies• Standards• Delivery and reception systems• Applications• Networking systems

Order your copy of The Digital Consumer Technology Handbook todayat www.xilinx.com/esp or www.amazon.com.

©2004 Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124. Europe +44-870-7350-600; Japan +81-3-5321-7711; Asia Pacific +852-2-424-5200; Xilinx is a registered trademark, and The Programmable Logic Company is a service mark of Xilinx, Inc.

Page 58: Xcell Journal Issue 49

by Robert BielbySr. Director of Strategic Solutions MarketingXilinx, [email protected]

Technology developments and trafficdemands are transforming the dynamicsof the telecom market. The virtual explo-sion of bandwidth in local area networks(LANs), the deployment of GigabitEthernet, and the growth of dense wavedivision multiplexing (DWDM) in long-haul wide area networks (WAN) have allfueled the demand for servicing greateramounts of data traffic.

Today, it is believed that 80% of alltelecommunications traffic is data traffic.Although this percentage is expected torise, service providers continue to remainmotivated to support legacy voice services,as this fundamental revenue-bearing serv-ice provides a significant base for carriers tobuild out their new service models. At thesame time, service providers are deployinga wide range of new technologies to capi-talize on new revenue opportunities.

Despite the focus on new or modifiedLayer 2 technologies (such as Ethernetover SONET [EOS], Resilient PacketRing [RPR], Metro Ethernet Forum[MEF], and a host of others) that addresslegacy voice support as well as up-and-coming data services, challenges arise inthe development of the platforms them-selves. Aggressive business models contin-ue to push for a continued model oflower-cost-per-megabit bandwidth.

The Advanced Telecom Compute Architecture standard has great potential for widespread adoption in next-generation infrastructure applications.The Advanced Telecom Compute Architecture standard has great potential for widespread adoption in next-generation infrastructure applications.

The Next Gold Standard?The Next Gold Standard?

58 Xcell Journal Summer 2004

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The “data-friendly” Layer 2 technolo-gies have come a long way in reducing datatransport costs in some of the existinginfrastructures. However, beyond thosesavings, achieving additional cost reduc-tions has forced equipment providers torethink their basic platform architectures.

A clear trend in the industry is theadoption of standard technologies over cus-tom wherever possible. This trend is fur-ther exacerbated by the recent economicdownturn – not only in the telecom mar-ket, but across almost every infrastructuremarket, forcing top-tier equipmentproviders to downsize and employ out-sourced technologies. Furthermore, issuessuch as reduced margins, increased tech-nology costs, rapid hardware obsolescence,and high competition have given evengreater weight to a standards-based model.

Next-generation platform productdevelopment has been limited in the area ofI/O signaling performance, more specifi-cally at the point where the majority oftraffic is aggregated in the backplane. Thecontinuous scaling of system bandwidth isexceeding the capabilities of traditionalbackplane signaling technologies and archi-tectures, in addition to challenging currentpower technologies and cooling systems.

The combination of these technical andeconomic factors has given rise to the defi-nition of an industry standard for boardand shelf, optimized to address the needs ofnext-generation infrastructure applications.

ATCAIn 2001, experts from more than 600industries and companies collaborated todefine a standardized platform that couldaddress the challenges of future applica-tions. This lead to the formation of a con-sortium under the PCI Industrial ComputerManufacturers Group (PICMG™).Previously, the consortium was responsiblefor the definition of PICMG 2, also knownas the CompactPCI standard.

From the PICMG 3 specification, thenext-generation platform dubbed ATCA™(Advanced Telecom Compute Architecture)addresses the requirements of applicationsthat could not be served by the CompactPCI(CPCI) standard or proprietary solutions.

that addresses a range of standard and pro-prietary fabric interfaces, primarily basedon serial signaling technologies, robustsystem management, and support forhigher performance power and cooling.Table 1 compares the key characteristics ofthe CPCI (PICMG 2) standard versus theATCA (PICMG 3) standard.

The consortium employed a layeredapproach in the definition of the ATCAspecification to accommodate support fornew fabric technologies as they evolve. Theselayers are specified under the guidelines ofthe PICMG, and to date a number of themhave already been defined. They include:

• PICMG 3.0 – the core specificationdefining architecture, mechanicals,power system management, and fabricconnectors

• PICMG 3.1 – specification forEthernet and Fibre Channel fabricinterconnects

• PICMG 3.2 – specification forInfiniBand™ fabric interconnects

• PICMG 3.3 – specification forStarFabric™ interconnects

• PICMG 3.4 – specification for PCIExpress™ fabric interconnects.

Finalized in January 2003, the ATCAstandard has become one of the most rapid-ly adopted open specifications in the histo-ry of PICMG. ATCA’s prime objective is toprovide the benefits of a standardized yetscalable platform to address the key chal-lenges of next-generation systems, with suf-ficient flexibility to be used across a broadclass of applications without imposing con-straints that might impact product differen-tiation. A key objective was that theplatform could be employed in carrier-grade telecommunication applications,with support for such features as NetworkEquipment Building Specification (NEBS),European Telecommunications StandardsInstitute (ETSI), and 99.999% availability.

The ATCA platform was designed to bescalable to 2.5 Tbps; provide support formulti-protocol interfaces at rates as high as40 Gbps; and provide high levels of mod-ularity and configurability, allowing arange of vendors to drive competitive solu-tions to market.

ATCA architecture is optimizedaround connectivity requirements formedia gateways, while providing scalabili-ty to address higher performance comput-ing elements. ATCA was defined tosupport a scalable backplane environment

Summer 2004 Xcell Journal 59

Attribute PICMG2 CPCI PICMG3 ATCA

Board Size 57" sqr. + 2 Mez 140" sqr. + 4 Mez

Board Power 35-50W 150-200W

Backplane Bandwidth ~ 4 Gbps ~ 2.4 Tbps

Number of Active Boards 21 16

Power System Central Converter 5,12, Distributed Converter 3.3V Backplane Dual 48V Backplane

Management OK Advanced

I/O Limited Extensive

Clock, Update, Test Bus No Yes

Regulatory Conformance Vendor-Specific In Standard

Multi-Vendor Support Extensive Currently Limited

Base Cost of Shelf Low Moderate

Functional Shelf Density Low High

Lifecycle Cost Per Function High Low

Table 1 – PICMG2 versus PICMG3 features comparison

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Many new layers are currently underproposal or in the process of being ratified.

In addition to supporting several fabrictechnologies, the backplane supports bothstar and full-mesh connectivity betweenboards in the system. System managementis built on the Intelligent PlatformManagement Interface (IPMI) 1.5 specifi-cation. Each ATCA board supports up to200W in a single slot, with power suppliedvia redundant 48V DC feeds. The result isa standard that enables solution providersto deliver products rapidly to market thatsupport high availability and high perform-ance, and at significantly lower costs thancustom-developed or proprietary solutions.

The Market for ATCAThe confluence of a significant downturn inthe infrastructure markets, competitive mar-ket pressures, and the need to address thecomplex and costly challenges associatedwith next-generation equipment platformdevelopment has caused many industries –including the telecom industry – to recon-sider traditional business models. Thus,industry analysts expect the ATCA standardto achieve far greater adoption in the mar-ketplace than previously introduced stan-dards such as PICMG 2. A report fromCrystal Cube Consulting Inc. suggests thatthe ATCA equipment market will exceed$250 billion by 2007.

The key benefits of the ATCA platforminclude lower materials costs, faster time tomarket, and lower development costs.Because the specification is modular in itsdefinition, it is expected (and has alreadybeen seen through product introductions)to spawn an ecosystem of building blocksranging from silicon solutions, boards,chassis, middleware, operating systems,and applications, among others.

The benefits to equipment manufactur-ers are many, as this standards-basedecosystem will allow for a lower cost ofmarket entry/investment costs, more effi-cient inventory management, and a focus

on higher value-added differential serviceswhile delivering cost-competitive products.

Industry analyst RHK expects ship-ments of more than 600,000 shelves basedon the ATCA standard by the year 2007.Assuming that a shelf contains 16 cards,this translates to shipments of more than9.6 million ATCA-based line cards.

Considering that this growth stems froman effective base of zero in January 2003,when the ATCA specification was first rati-fied, it’s no surprise that ATCA has received aphenomenal amount of attention and press.

Industry analysts expect that the adop-tion of this standard will occur across vari-ous network segments at different rates –understandably so, as it provides differentlevels of benefits relative to where it isemployed within the network. Table 2 liststhe expected adoption of ATCA across var-ious markets by 2007.

ConclusionNew business and technology paradigmscontinue to challenge existing businessand product development models. Themost recent downturn in the infrastruc-ture markets and the introduction ofmany flawed business models have causedequipment suppliers to re-think their

approaches to product development.A new outsourced model based on

industry standards that comprehends therequirements of specific needs for multiplemarkets appears to be the next major para-digm shift. Equipment suppliers need toembrace this shift to remain competitive forthe next generation of platform solutions.

ATCA, which was developed, defined,and endorsed by experts from many indus-tries, holds great promise in serving as thenew disruptive technology to continue todrive down costs while increasing perform-ance and features across a range of marketsand applications.

The platform’s inherent scalability andits sweeping applicability versus the signifi-cant investment costs required to developproprietary platforms – further aggravatedby the need to employ technically challeng-ing serial signaling technologies to supportnext-generation backplanes – are causingequipment suppliers to seriously considerthis new platform.

Once these suppliers begin to signaltheir intent to build products based on theATCA standard, an entire ecosystem ofmodular component suppliers is expectedto emerge to help further fuel the growth ofthis new outsourced model.

Segment Equipment Types ATCA System Units 2007

Wireless Access BTS/Node B, BSC/RND, Transcoder 38%

Wireless Edge MSC, HLR, GGSN, SGSN/PDSN, 50%Billing Server, Multimedia Server

Wireline Access DSLAM, CMTS, MxU 1%

Edge Edge Router, Multiservice Switch, 3%Optical Edge Device

New Access Edge Media Gateway, Softswitch, Media Server 21%

Core Transport Core Router, SONET/SDH, ADM, WDM <1%

Signaling Signaling Server, STP, SCP 5%

A report from Crystal Cube Consulting Inc. suggests that the ATCA equipment market will exceed $250 billion by 2007.

Table 2 – Estimated 2007 ATCA system unit shipments by equipment type (Source: RHK)

60 Xcell Journal Summer 2004

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End-to-end Programmable Solutions—From the Line Card

to the Backplane.

Pb-free devicesavailable now

The Programmable Logic CompanySM

Xilinx delivers the complete, open standards-based,modular platform you need to develop designs forthe line card, control plane, and high-speed serialbackplane. Superior density, features, and perform-ance make these solutions ideal for networking,telecom, data storage, and computing.

Unbeatable programmable solutionsThe Xilinx Virtex-II Pro™ FPGA family offers advancedembedded features — including multi-gigabit trans-ceivers and microprocessors — at prices that make afully programmable line card practical, from thephysical layer to the network layer.

Reduced latency, cost, and design timeXilinx provides a proven framework for product devel-opment and deployment with the PICMG 3.0-compliantATCA Development Platform — a 15-channel, 3.125 Gbpsfull mesh fabric interface, with headers for application-specific personality modules.

In addition, Xilinx offers comprehensive referencedesigns, IP cores and design services, makinghigh-speed serial designs easy.

Visit www.xilinx.com/esp/backplanes for moreinformation.

©2004 Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124. Europe +44-870-7350-600; Japan +81-3-5321-7711; Asia Pacific +852-2-424-5200; Xilinx is a registered trademark, Virtex-II Pro is a trademark, and The Programmable Logic Company is a service mark of Xilinx, Inc.

Page 62: Xcell Journal Issue 49

by Amit Dhir Sr. Manager, Networking & Telecom Markets, Strategic SolutionsXilinx, [email protected]

Delfin Rodillas Manager, Networking & Telecom Markets, Strategic SolutionsXilinx, [email protected]

Historically, designers improved band-width performance in telecom, datacom,and computing systems backplanes bywidening buses and increasing signal clockrates. Now, with data rates exceeding 622Mbps and reaching the 1 to 10 Gbps rangeacross 20 inches or more of backplanetrace, passing data reliably over parallelbuses is a challenge. Characteristics such assignal skew and loading – non-issues before– are suddenly problematic. Consequently,designers have shifted from parallel busesto more advanced serial interconnects.

However, even serial technologies havelimitations, especially at data rates beyondthe 1 Gbps level, where new problemsarise. These limitations include reflectionsdue to impedance mismatches along thesignal path; signal attenuation from back-plane materials; and added noise due tocrosstalk and inter-symbol interference.

Backplane designers should be aware ofthese issues and compensate accordingly toensure that the bit error rate (BER), whichis a measure of backplane robustness, is lessthan 10-12. This challenging task becomeseven more critical as system throughputrequirements approach 40 Gbps.

Fortunately, you can reduce the effectsof the signal degradation phenomena byseveral means, including:

• Using better backplane material (FR4, Rogers)

• Using better connector types

• Improving layout trace to reduce thenumber of PCB layers and crosstalk

• Implementing different signalingschemes

• Using signal conditioning techniques.

Programmable Logic Solutions for Next-Generation Serial Backplanes

Programmable Logic Solutions for Next-Generation Serial Backplanes

62 Xcell Journal Summer 2004

Virtex-II Pro and Virtex-II Pro X FPGAs enable rapid development of flexible, serial backplane designs.Virtex-II Pro and Virtex-II Pro X FPGAs enable rapid development of flexible, serial backplane designs.

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In addition, you can improve the signalintegrity of a multi-gigabit serial link byselecting the appropriate serializer/deserializ-er (SerDes) device, comprising a transmitter,receiver, clock/data recovery (CDR),SerDes, integrated termination resistors,programmable output swing, transmit pre-emphasis, and receive equalization.

Standards for Serial BackplanesThe large investment required to develop aproprietary serial backplane subsystem ledto the organization of the PCI IndustrialComputer Manufacturers Group(PICMG™), which develops open specifi-cations for high-performance telecommu-nications and industrial computingbackplane architectures.

PICMG recently produced a series ofspecifications (PICMG 3.x) called theAdvanced Telecom Computing Architecture(ATCA™) for next-generation carrier-gradetelecommunications equipment. ATCA fea-tures a new form factor and is based onswitched fabric architectures, including dualstar, dual-dual star, and mesh topologies.The base specification, PICMG 3.0, wasadopted at the end of 2002. Additionalspecifications in the series include PICMG3.1 for Ethernet fabric, PICMG 3.2 forInfiniband™, PICMG 3.3 for StarFabric™Interconnect, and PICMG 3.4 for the PCIExpress™ architecture.

Xilinx Solutions for Serial BackplanesXilinx has made significant strides in mak-ing serial technology available in our FPGAsand developing solutions such as IP cores,reference designs, and tools to help our cus-tomers gain the benefits of serial technologyeasily and quickly. Let’s take a look at theserial backplane solutions we offer.

Virtex-II Pro and Virtex-II Pro XThe Virtex-II Pro™ and Virtex-II Pro Xfamily of FPGAs represent a high-end lineof Xilinx FPGAs built on 130 nm, nine-layer copper and featuring an advancedfabric, embedded processors, and multi-gigabit SerDes devices. Both families arebased on the same FPGA fabric, whichprovides abundant logic (as many as125,000 logic cells), embedded memory

integrity, such as receive equalization. With10 Gbps capability, you can implementnext-generation standard interfaces requir-ing serial 10 Gbps interfaces such as10GBase-R Ethernet or SXI-5, or imple-ment your own proprietary 10G interface.

AuroraAurora is a scalable, lightweight, link-layerprotocol that you can use to move dataacross point-to-point serial links at baudrates as high as 75 Gbps. It is an open pro-tocol that you can implement in any silicondevice/technology. Aurora provides a trans-parent interface to the upper layers of pro-prietary or industry-standard protocols suchas Ethernet or TCP/IP. This allows next-gen-eration communication and computing sys-tem designers to achieve higher connectivityperformance while preserving softwareinfrastructure investments.

Mesh Technology on XilinxMesh Technology on Xilinx (MTX)includes hardware and software referencedesigns and a bit error rate test (BERT)toolkit to enable rapid development of full-mesh serial backplane systems.

The PICMG 3.0 2.5G ATCADevelopment Platform is a reference boardfor PICMG 3.x line cards supporting portrates to 2.5 Gbps. The heart of the devel-opment platform is the Virtex-II Prodevice, which serves as the interface to thefull-mesh backplane.

Virtex-II Pro’s on-chip RocketIO MGTsallow all mesh cards on a full-mesh back-plane to have direct, high-speed serial linksto each other. The full-mesh card alsoallows application flexibility by reservingan area of the board for a pluggable “per-sonality module” (PM). You can use thePM to implement any application-specificline card and easily connect to the full-mesh card through the included headers.

(as much as 10 Mb block RAM), clockmanagement, and DSP resources.

Standard SelectIO™ resources are alsocommon, with as many as 1,200 userI/Os, 840 Mbps LVDS for interfaces suchas 10 Gigabit Sixteen-Bit Interface(XSBI) and SerDes Framer InterfaceLevel (SFI)-4, as well as XCITE (XilinxControlled Impedance Technology) on-chip termination.

Both devices also use the same embed-ded IBM™ PowerPC™ supporting 300Mhz+ operation. The main difference isthat the Virtex-II Pro FPGA has embeddedRocketIO™ transceivers supportingspeeds as high as 3.125 Gbps per channel,while the Virtex-II Pro X FPGA hasembedded RocketIO X transceivers, pro-viding up to 10.3125 Gbps per channel.

The largest of the 10-member Virtex-IIPro family of devices supports as many as24 RocketIO transceivers. Each device cansupport operation from 622 Mbps to 3.125Gbps, allowing up to 75 Gbps aggregatebaud rate. Moreover, features such as pro-grammable transmit pre-emphasis and out-put voltage enable the RocketIO transceiverto drive signals over 40" of FR4 material at3.125 Gbps.

You can thus use RocketIO devices toaddress a number of emerging high-speedserial standards that fall within its range ofoperation, such as 1 Gigabit Ethernet, 10Gigabit Ethernet (XAUI), PCI Express,Serial RapidIO, and Serial ATA.

RocketIO X transceivers found onVirtex-II Pro X FPGAs are capable of oper-ating from 2.488 Gbps to 10.3125 Gbps.The larger of the two Virtex-II Pro Xdevices supports as many as 20 RocketIO Xtransceivers, providing an aggregate baudrate of more than 206 Gbps.

RocketIO X devices have the same fea-tures as RocketIO devices, as well as someadditional features to improve signal

Summer 2004 Xcell Journal 63

Virtex-II Pro’s on-chip RocketIO MGTs allow allmesh cards on a full-mesh backplane to havedirect, high-speed serial links to each other.

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PICMG 3.0 also specifies card and shelfmanagement functionalities that are imple-mented in the development platform.

The Mesh Fabric Reference Design(MFRD) is a fully functional IP referencedesign that provides a building block for cre-ating Virtex-II Pro-based mesh switch fabricinterfaces. You can use the fabric referencedesign in a single Virtex-II Pro device or inseveral daisy-chained Virtex-II Pro devices,allowing up to 256 RocketIO serial channels.Figure 1 shows the concept of the mesh fab-ric interface and the daisy-chain scheme.

By having the flexibility to daisy-chaindevices of different densities, you can choosean appropriate logic-to-RocketIO ratio. Forexample, more logic may be useful in adesign where additional network processingfunctions are needed beyond those providedby an ASSP or ASIC. Flexible traffic sched-

uling is also possible with the support of asmany as 16 priority levels and multiplescheduling algorithms on egress.

Figure 2 illustrates an example systemwith line cards that use the Virtex-II ProFPGA and the full-mesh IP as the back-plane interface.

GigaBERT is an IP toolkit that enableseasy and comprehensive BERT of Virtex-IIPro-based, full-mesh fabric channels. UsingGigaBERT, you can configure eachRocketIO transceiver on each mesh fabricinterface FPGA connected to a backplane aseither a BERT tester or a far-end loopback.In effect, you can accomplish a scheme forsimultaneous BERT testing of all links in afull-mesh fabric. Furthermore, GigaBERT’sflexibility enables you to quickly and easilycreate a BERT stress test to check for signalintegrity in specific configurations.

Legacy Backplanes Support Xilinx FPGAs are also ideal for cus-tomers who still need to support theirdifferential or single-ended legacy busarchitectures as they transition to serialarchitectures. For the highest perform-ance differential solution, you can usethe Virtex-II Pro or Virtex-II Pro XFPGAs to achieve LVDS rates as high as840 Mbps. For low-cost LVDS,Spartan™-3 FPGAs support rates ashigh as 622 Mbps. Together, thesedevices provide a complete differentialI/O solution with coverage of popularstandards such as LVDS, ExtendedLVDS, Bus LVDS, Ultra LVDS,LVPECL, LDT, and RSDS.

For legacy designs using older single-ended signaling standards, the XilinxSelectIO technology available in Virtex-IIPro, Virtex-II Pro X, and Spartan-3FPGAs allows the most comprehensivesupport for LVTTL, LVCMOS, PCI/PCI-X, GTL, HSTL, and SSTL signaling stan-dards. As a result, Virtex-II Pro, Virtex-IIPro X, and Spartan-3 FPGAs provide youwith everything you need to support lega-cy backplane interfaces.

ConclusionDesigners of high-end telecom, datacom,and computing platforms have lookedtowards serial I/O technologies to addressthe increasing performance requirementsof next-generation systems. Additionally,consortia such as the PICMG havestepped up to the plate to define serialbackplane standards.

Whether proprietary or standards-based, Virtex-II Pro and Virtex-II Pro XFPGAs with embedded multi-gigabitserial transceivers provide the technologyto enable serial backplanes – includingadvanced, full-mesh architectures. Ourgrowing portfolio of IP cores, referencedesigns, and toolkits for serial backplanessuch as Aurora, Mesh Fabric IP, thePICMG ATCA Development Platform,and GigaBERT lead to shorter time toknowledge and ultimately shorter time tomarket. For more details about Xilinxsolutions for serial backplanes, visitwww.xilinx.com/esp/backplanes/.

Virtex-II ProFabricFPGA

4 to 24RocketIO

Virtex-II ProFabricFPGA

4 to 24RocketIO

Virtex-II ProFabricFPGA

4 to 24RocketIO

CascadeInterface

CascadeInterface

CascadeInterface

CascadeInterface

CascadeInterface

CascadeInterfaceFrom Ingress

Traffic Manager

From IngressTraffic Manager

Backplane-Fabric Interface

Arbitrary Mix of

Virtex-II Pro Devices

Ingress TM

Egress TM

Physical Ports

Line Card 1

Ingress TM

Egress TM

Physical Ports

Line Card 3

Ingress TM

Egress TM

Physical Ports

Line Card 5

Ingress TM

Egress TM

Physical Ports

Line Card 2

Ingress TM

Egress TM

Physical Ports

Line Card 4

Ingress TM

Egress TM

Physical Ports

Line Card 6

Figure 2 – In a Virtex-II Pro-based full-mesh backplane, you can implement serial channels and distributedswitch functions using RocketIO transceivers and logic resources with the Mesh Fabric Reference Design.

Figure 1 – You can implement the Mesh Fabric Reference Design in a single FPGA or in multiple, daisy-chained FPGAs.

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by Warren MillerVP of Marketing, Avnet Design [email protected]

Traditionally, designs for a varietyof applications used high-speedbackplanes to provide high-band-width communications betweensubsystem cards. Parallel busimplementations like PCI werepopular because they offered thehighest bandwidth in an industry-standard form factor.

However, for applications requiring veryhigh bandwidth connectivity (such as tele-com and networking), these parallel imple-mentations ran into bandwidth and costproblems. Non-standard implementationswere sometimes needed; these custom effortsslowed development and increased costs.

Technological advances now allow youto use high-speed serial interfaces cost-effectively in chassis-based, industry-stan-dard designs. The new Advanced Telecom

Compute Architecture (ATCA™)PICMG™ 3.1 specification creates a flex-ible, industry-standard platform that letsyou cut-and-paste previously complex andexpensive high-speed serial portions ofyour design. This improves time to marketand significantly reduces the cost normallyassociated with creating high-speed back-plane designs.

We expect that this change willopen the market to a wide range ofnew applications and companiesthat were historically shut out ofthese designs. Xilinx and Avnethave partnered to create a completeATCA PICMG 3.1 Design Kit thatcan be used to quickly and easilyimplement the high-speed serialbackplane portion of the ATCAPICMG 3.1 specification; it canalso be used as a platform for acomplete design.

PICMG 3.1 Design KitThe card cage, shown in Figure 1, is aPICMG-standard 12U form factor sizedfor 16 slots in a 600 mm frame, withroom for both front and rear fiber bend.The boards measure 8U x 280 mm x 1.2in (140 in2 + 4 mezzanine connectors),can run 150-200W of power, and canprovide 2.4 Tbps of bandwidth. There areas many as 16 active boards per chassis.

Xilinx and Avnet have released a new design kit that reduces time to market for a wide range of serial backplane applications.

Xilinx and Avnet have released a new design kit that reduces time to market for a wide range of serial backplane applications.

Create ATCA-Compliant DesignsCreate ATCA-Compliant Designs

Summer 2004 Xcell Journal 65

Figure 1 – ATCA card cage

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The power is at 48V and sourced fromthe backplane.

The main component of the ATCAPICMG 3.1 Design Kit is the line card,which is a complete development platformfor creating PICMG 3.1-compliant designs.Some of the key features are:

• 15-channel, one-port full mesh fabricinterface

• Intelligent Platform ManagementInterface (IPMI)

• Base interface ShMC port

• Headers for an application-specific personality module

• Fully distributed system management

• Management firmware running on aPowerPC™ processor

• Linux™-based control plane software.

Line CardThe Xilinx ATCA PICMG 3.1 full mesh linecard (Figure 2) provides a baseline imple-mentation of a PICMG 3.1 line card. Itincludes a Virtex-II Pro™ FPGA that imple-ments both a full mesh fabric interface and amanagement subsystem.

The full mesh line card can serve as adevelopment platform for PICMG 3.xline cards supporting port rates to 2.5Gbps. It includes a Virtex-II Pro-basedfabric interface that also includes allPICMG 3.0-defined card and shelf man-

Fabric Interface FPGAThe fabric interface FPGA implements notonly the data plane functions needed totransfer data across the distributed fabric, butalso all management functions defined in thePICMG 3.1 specification. When placed inslots one or two, the card is capable of actingas a shelf manager.

The control plane section of the fabricinterface FPGA implements managementfunctions for the card; a block diagram forthe control plane implementation is shownin Figure 3. All of these functions are imple-

agement functionalities. Managementfirmware executes on one of the Virtex-IIPro’s PowerPC processors running anembedded Linux operating system.

The card also includes headers to inter-face to a user-defined personality module.This module is used to implement appli-cation-specific line card processing andexternal interfaces. I/O access for thismodule can be reached through the frontpanel or rear transition modules. The per-sonality module also has full access to thePICMG 3.1 update channel interface.

128MBExternal DDR

Memory

Address MappingLogic in Data Plane

32 KBBlock RAM

PLBARB

OPBARB

IPIF

IPIF

IPIF

IPIF

IPIF

IPIF

IPIF

IPIF

PLB2OPBBridge

DSPLB

ISPLB

INT

DDR MemoryController

Block RAM Memory Controller

ChipScope ProPPC405Processor Block

Non-Crit.INTC

Crit.INTC

System ACEMPU

Ethernet

IIC

IIC

IIC

GPIOGPIO

UART16450

DCRBridge

MicroDrive Interface

ShMC Interface

IPMB Port A

IPMB Port B

System Monitoring

HA Interface &Front Panel Status Interface

RTM Serial Port

Memory MappedDCR Bus

FabricMGT

Interface

AuroraInterface

Logic

AddressMapping

Logic

PLB Bus FromControl Plane Section

FIFO

FIFO

FIFO

FIFO

ChannelInterface

15

ChannelInterface

1

FabricChannel 1

FabricChannel 15

Figure 2 – PICMG 3.1 line card

Figure 3 – Fabric FPGA control plane block diagram

Figure 4 – Fabric FPGA data plane block diagram

66 Xcell Journal Summer 2004

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Summer 2004 Xcell Journal 67

mented as firmware running on an embed-ded Linux operating system. The func-tions provided include an IPMI agent,shelf manager, and hardware and soft-ware updates via an ShMC interface.

The Virtex-II Pro FPGA includes two400 MHz PowerPC 405 processors. Oneprocessor is used to implement manage-ment functions. It interfaces to the rest ofthe management subsystem by way of a64-bit CoreConnect processor local busand a 32-bit on-chip peripheral bus. Thesecond PowerPC processor is availablefor application-specific functions.

The data plane section implements acomplete 15-channel distributed switchfabric interface. The configurationshipped with the card implements aPICMG 3.1 Ethernet transport, but itcan also be customized to support otherPICMG 3.x transports. Figure 4 shows ablock diagram of the data plane sectionof the fabric interface FPGA.

The Aurora interface is used to trans-fer packets between user-defined logicon the prototyping module and thePICMG 3.x fabric. The Aurora interfaceuses the fabric interface multi-gigabittransceiver signals for connectivity, butyou can substitute other interfaces. Forexample, if you used an alternative inter-face such as POS-PHY Level 3, the fab-ric interface GPIO signals would be usedfor connectivity.

Conclusion Xilinx has certified Avnet Cilicon, viathe Avnet Design Services DesignCenters, to sell and support the ATCAPICMG 3.1 Design Kit. The kitincludes detailed design files, a compre-hensive board support package, andexample designs, along with test results.Design Services can be bundled alongwith the Design Kit to help port a cus-tom design to the line card FPGA.

To get the most up-to-date informa-tion on the ATCA PICMG 3.1 DesignKit, visit www.avnetavenue.com and select“ATCA Design Kit.” To obtain pricing,delivery information, and a more com-plete description from an Avnet Ciliconrepresentative, click on “To Register.”

Typical application areas include:

• Narrowband line units

• Narrowband local switch line or trunk unit

• Digital loop carrier localterminal/ONU

• PBX line unit

• Broadband line units

• DSLAM

• Cable modem termination system/head end

• FTTx line unit

• Wireless elements

• Base transceiver station

• Base station controller

• Wireless access gateway

• Radio network controller

• SGSN/GGSN

• Home location regulator

• Integrated mobile switching center

• Service nodes

• Echo canceller

• Network resource server/intelligentperipheral

• Remote access server/modem pool

• IVR/voicemail system

• Core data network elements

• Switched LAN hub

• IP switch/router

• ATM switch

• Optical transport terminal (DACS, WDM)

• Metro optical system

• Data network elements

• ASP server

• Storage area network element

• Compute server (thin client host, game host)

• Web server (e-commerce, web cache,firewall, filter)

• Database engine (RADIUS, LNP,billing)

• Video server

• Converged switch elements

• Softswitch

• Line access gateway

• Trunk access gateway

• Signaling gateway

• Internet telephony host

• Compression/vocoding/encryptiongateway

• PSTN elements

• Universal AIN element (SCP, SCC,NCP, STP)

• DLC/GR-303 host terminal

• TDM switch core replacement

• PBX

• E.911, CALEA host

• Industrial applications

• Factory automation/robotics

• Multimedia studios

• Traffic control

• Military/avionics/shipboard

The ATCA PICMG 3.1 specification defines a flexible serial backplane developmentplatform that is applicable to a wide variety of applications. In general, the specificationtargets Telco carrier-grade applications, but it is also applicable to data centers and othermore computationally intensive applications.

APPLICATIONS

B A C K P L A N E S

Page 68: Xcell Journal Issue 49

by Bruce OakleyDirector of Embedded Systems DesignAMIRIX [email protected]

Although the existing transport networkinfrastructure was built for carrying voice,it now carries other types of traffic, such asvideo, data, and storage. Network serviceslike asynchronous transfer mode (ATM)carry this traffic with varying degrees ofoverhead and impact on performance.

The Generic Framing Procedure (GFP)– as defined by the InternationalTelecommunication Union (ITU)Telecommunication Standardization Sector(ITU-T) Recommendation G.7041 –offers another solution. GFP defines fram-ing methods for mapping different traffic

types directly to the octet-synchronousoptical network (SONET) infrastructure.

GFP comprises two stages: client-spe-cific mapping of different protocols intoframes, and common procedures to adaptframes to an octet stream. The flexibility ofFPGAs makes them a natural solution forthe first stage, in which supporting a vari-ety of different interfaces is necessary. Amultiplexer can then aggregate the result-ing GFP frames and send them to a framerfor adaptation to SONET. Framing andaggregation of Gigabit Ethernet frames toa SPI-4.2 interface, as shown in Figure 1,will be a very common building block.

The Xilinx Virtex-II Pro™ FPGA offersa very powerful platform on which to buildsuch a system. The Gigabit Ethernet andSPI-4.2 interfaces can be driven directly by

MGT and LVDS I/O, respectively, andproven IP cores for these functions exist.

Using the programmable array for fram-ing and multiplexing allows a great deal offlexibility, which you can use to support dif-ferent algorithms for application-specificfunctions such as mapping, scheduling, andflow control. You can also include a controlplane subsystem in the same device using theembedded PowerPC™. Such a solution hasbeen developed and tested by AMIRIX™Systems, which Xilinx now offers as a freereference design.

Architecture and Data FlowThe basic architecture of the EthernetAggregation Reference Design (EARD) isshown in Figure 2. Although the architec-ture shown in the figure is for a four-port

A new reference design from AMIRIX Systems and Xilinx allows aggregation of multiple Gigabit Ethernet ports to SPI-4.2, with frame-mapped GFP.

A new reference design from AMIRIX Systems and Xilinx allows aggregation of multiple Gigabit Ethernet ports to SPI-4.2, with frame-mapped GFP.

Ethernet Aggregation with GFP Framing in Virtex-II ProEthernet Aggregation with GFP Framing in Virtex-II Pro

68 Xcell Journal Summer 2004

B A C K P L A N E S

Page 69: Xcell Journal Issue 49

system, the EARD can also be configuredfor eight ports. In the egress direction,frames arriving at the Ethernet ports aremultiplexed and segmented into the SPI-4.2 interface. Segments are de-multiplexedand reassembled in the ingress direction.

Egress access to the SPI-4.2 interface is

GFP/Pass-Through/Loopback ModesWhen in GFP mode, the EARD sup-ports frame-mapped GFP for Ethernetmedium access control (MAC) pay-loads, as defined in Section 7.1 of theGFP standard. The EARD adds headersin the egress path and strips them in theingress path; header contents are setusing compile parameters. To correctlyencode the length during GFP encapsu-lation, an entire frame must be bufferedbefore forwarding. This store-and-for-ward approach is used in both egress andingress directions when GFP framing isenabled.

When GFP framing is disabled (pass-through mode), a lower latency approachis used. Forwarding begins upon receiptof an entire SPI-4.2 segment duringegress, or when reaching a programmablethreshold during ingress.

The EARD can also be configured inloopback mode, in which traffic at eachport is fed back to itself. The SPI-4.2 sinkclient interface is connected directly tothe SPI-4.2 source, and Gigabit Ethernettraffic is looped back through the egressand ingress FIFOs.

InterfacesBoth the Gigabit Ethernet and SPI-4.2interfaces are implemented using Xilinx IPcores. Features of these interfaces include:

Gigabit Ethernet

• Core – Xilinx Gigabit Ethernet MACrevision 3.0

• Physical Interface – Built-in physicallayer device (physical coding sublayer[PCS]/physical medium attachment[PMA]) using MGT

• Frame Size – Support for jumbo frames

• Flow Control – Support for incomingand outgoing pause frames; pauseframes have fixed delay (compileparameters) triggered by a program-mable egress FIFO threshold

• Statistics – Traffic statistics main-tained by the MACs, accessiblethrough the management interface.

scheduled according to a simple round-robinalgorithm, with a one-to-one mapping ofGigabit Ethernet ports to SPI-4.2 channels.

We should note that EARD traffic direc-tions (ingress and egress) are defined fromthe point of view of a SONET framer. Theopposite sense is used in the GFP standard.

Summer 2004 Xcell Journal 69

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Figure 2 – EARD block diagram

B A C K P L A N E S

Page 70: Xcell Journal Issue 49

SPI-4.2

• Core – Xilinx SPI-4.2 revision 6.0

• Phase Alignment – Dynamic phasealignment

• Flow Control – Sink status (ingresspath) is reported based on programma-ble ingress FIFO thresholds; source sta-tus is not used.

Control PlaneEARD control plane software runs on anembedded PowerPC, clocked at 250 MHz.It manages system initialization and pro-vides an external management interface.This management interface is based on asimple serial port, which is useful fordemonstration purposes. In an actual appli-cation, a more sophisticated interface suchas PCI or RapidIO would be more useful.

To facilitate porting to different physicalinterfaces, the management interface soft-ware is based on a generic message passing

protocol. You can support changes to thephysical interface by modifying a few low-level routines.

Because the control plane is a relativelysmall part of the system, we preferred anISE-centric design flow. Thus, the controlplane was built using EDK, but is exportedas a sub-module and integrated into theEARD as a core.

ValidationWe performed all EARD validation in aXilinx XC2VP50 device. The four-portversion should fit in an XC2VP30, andwith some customization (such as runningcontrol plane software directly from cache),we expect that the eight-port version can fitin an XC2VP40. Table 1 shows the approx-imate resource usage.

The EARD was tested through a combi-nation of simulation and hardware valida-tion. The various configurations weresubjected to extended heavy traffic, as well as

tests focused on exercising segmentation andreassembly, scheduling, and error handling.

We performed hardware validation usinga Xilinx ML324 board, as shown in Figure 3.LVDS headers were used to loop back theSPI-4.2 interface, and the Gigabit Ethernetports were daisy-chained. We used an opticalnetwork interface card (NIC) in a Linux™host computer, as well as laboratory networkanalysis equipment, to generate and checktraffic. The EARD carried hundreds of mil-lions of Ethernet frames of varying sizes atdata rates well over 900 Mbps on all ports.

ConclusionThe Ethernet Aggregation Reference Designmakes an excellent starting point for designsrequiring Gigabit Ethernet aggregation, par-ticularly those involving GFP framing. Thisreference design is described in XilinxApplication Note XAPP695 and can bedownloaded from the Xilinx website atwww.xilinx.com/esp/networks_telecom/opti-cal/xlnx_net/eard_download.htm.

Using the EARD in real applications willlikely involve some degree of customizationto meet system needs. Examples include:

• Changing SPI-4.2 configurationoptions to comply with PCB require-ments and SONET framer specifics

• Replacing the management interfacewith something more suitable for anembedded system, such as PCI orRapidIO

• Modifying the algorithms used forscheduling, mapping, and flow control.

Of course, you can make more extensivearchitectural changes as well, such asadding queue management or replacing theEthernet ports with different interfaces.You can make changes yourself using thefreely available source code, or leverageAMIRIX Systems’ extensive experiencewith FPGA design and the EARD. Wehave applied our FPGA design capabilitiesto a number of communication systemsinvolving queueing, classification, segmen-tation and assembly, and a variety of cus-tomized packet processing functions. Formore information, visit www.amirix.com,or e-mail [email protected].

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Eight-Port 215 29800 27300 5 11 8 96

Figure 3 – EARD validation environment

Table 1 – EARD resource usage

70 Xcell Journal Summer 2004

B A C K P L A N E S

Page 71: Xcell Journal Issue 49

by Mike NelsonSr. Manager, Strategic SolutionsXilinx, [email protected]

The introduction of the Virtex-II Pro™Platform FPGA with integrated multi-gigabit transceivers (MGTs) enabled a newera of system design. Specifically, Virtex-IIPro devices now enable designers to imple-ment switched fabric system architecturesefficiently, affordably, and entirely in pro-grammable logic.

To illustrate this point and enable itsrapid exploitation by our customers,Xilinx developed the Mesh FabricReference Design (MFRD), a modular,highly scalable, and configurable resourcefor building switched fabric system solu-tions, and the Advanced Telecom ComputeArchitecture (ATCA) DevelopmentPlatform. In this article, we’ll take a closelook at both tools.

Switched Fabric TopologiesThe classic switched fabric configuration isa star in which each node communicateswith all of the other nodes through a cen-tral switch (Figure 1A). The obvious limi-tation of a star is that it is not fault tolerant.To address this limitation, you need a dualstar (Figure 1B).

In a mesh fabric, the switching functionis distributed across the system; every nodeconnects directly to each and every othernode. This configuration is inherentlyresilient, as shown in Figure 1C.

To compare the performance of thesealternatives, let’s consider two atypical 16-slot configurations: a dual star with 10 Gblinks, and a mesh with 2.5 Gb links.Because these configurations requireapproximately the same number of MGTresources for implementation (224 for thestar versus 240 for the mesh), they areessentially equal from a power and systemcost perspective (i.e., connector and back-plane routing resources).

The maximum theoretical systembandwidth for a dual star is equal to thenumber of nodes times the link rate timestwo (as all links are full duplex). In our 16-slot example, this works out to 14 nodes(two slots are required for the switches) x10 Gb x 2 = 280 Gb.

The maximum theoretical system band-width for a mesh is equal to the number ofnodes times the number of links per node(nodes minus 1) times the link rate. In our

example, this works out to 16 (all slots arenodes in a mesh) x 15 x 2.5 Gb = 600 Gb.

The mesh configuration is able toachieve more than twice the system per-formance with essentially equal resourcesbecause half of the star is required simplyfor fault tolerance. Additionally, the starincurs a fractional performance hit becausetwo slots must be dedicated to switchingin its chassis, thus limiting the node count.

In fairness, we should note that a dualstar can double its theoretical bandwidth to560 Gb if it uses active-active load balanc-ing, but not with fault tolerance. Thatwould require the addition of a thirdswitch for failover, increase the MGTcount to 312, and reduce performance to520 Gb in a 16-slot chassis, as the nodecount decreases to 13. Table 1 comparesthe performance of these configurations,along with additional examples.

Implementing mesh fabric architectures has just gotten easier with the Xilinx Mesh Fabric Reference Design and ATCA Development Platform. Implementing mesh fabric architectures has just gotten easier with the Xilinx Mesh Fabric Reference Design and ATCA Development Platform.

Mesh Fabric Switching with Virtex-II Pro FPGAsMesh Fabric Switching with Virtex-II Pro FPGAs

Summer 2004 Xcell Journal 71

16-Slot Chassis ConfigurationFabric Topology MGT BW Link BW Aggregate System BW MGTs Required

4X Star 2.5 Gb 10 Gb 300 Gb 1204X Dual Star 2.5 Gb 10 Gb 280 Gb 224

Active-Active 4X Dual Star 2.5 Gb 10 Gb 560 Gb 224A-A 4X Dual Star with HA* 2.5 Gb 10 Gb 520 Gb 312

1X Full Mesh 2.5 Gb 2.5 Gb 600 Gb 2402X Full Mesh 2.5 Gb 5 Gb 1.2 Tb 4804X Full Mesh 2.5 Gb 10 Gb 2.4 Tb 960

* Requires three switches

Table 1 – Performance comparison of various star and mesh fabric configurations

B A C K P L A N E S

Page 72: Xcell Journal Issue 49

Mesh Fabrics Fit Virtex-II Pro FPGAsBefore the advent of abundant and afford-able MGT resources, mesh fabrics werechallenging to implement. Now, they’re anemerging segment – historically an excel-lent home for programmable logic.

The distributed nature of switching in amesh fabric enables a mesh to map extreme-ly well to the resources available in Virtex-IIPro Platform FPGAs. These products haveeverything you need to build exceptionalmesh fabric interconnects:

• Four to 24 MGTs per device for imple-menting serial links

• Block RAM for implementing queues

• Logic for implementing control andtraffic management functions

• Embedded PowerPC™ processors thatcan be used to implement managementfunctions.

Mesh fabrics will also scale well in next-generation Virtex-II Pro X™ PlatformFPGAs. The Pro X family introduces 10Gb MGTs that can quadruple the perform-ance for our 16-slot mesh example to anincredible 2.4 Tb.

The Xilinx Mesh Fabric Reference DesignTo enable Virtex-II Pro applications inmesh fabrics, Xilinx developed the MeshFabric Reference Design. The MFRDenables an extremely broad range of systemconfigurations.

When designing the MFRD, Xilinx setout to address a number of key objectives:

1. Support system configura-tions from a few to hun-dreds of ports

2. Enable flexibility for imple-menting a chosen configura-tion and thus the ability tocost-optimize the solution

3. Provide configurable andcompetent queue manage-ment functionality

4. Enable efficient use of fabric bandwidth

5. Support standard Xilinx interfaces onmodular boundaries

6. Enable processor-based switch management.

72 Xcell Journal Summer 2004

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Figure 2 – MFRD architecture

Figure 3 – MFRD block diagram

B A C K P L A N E S

Page 73: Xcell Journal Issue 49

To achieve these goals, the MFRDimplements a mesh switching architecture,as illustrated in Figure 2. The MFRDspecifically implements a “mesh switch IP”element illustrated in each device in the fig-ure. We will review the details of this IP, butfor now let’s focus on the bigger picture.

The MFRD implements a modulararchitecture that can be realized in one ormore components. This enables configu-rations from four to 256 ports in any mixof Virtex-II Pro FPGAs and providesdesigners with exceptional flexibility inconfiguring their systems. For instance,

you could implement a 16-port switch ina single 2VP50, in a combination of a2VP20 and 2VP7, or in two 2VP7s. Thisflexibility is ideal for optimizing theprice/performance of the solution to yourspecific needs.

Other aspects to note in Figure 2 are:

• The use of the standard LocalLinkinterface for switch ingress and egress

• The use of the device control register(DCR) bus for switch management bythe Virtex-II Pro embedded PowerPCRISC processor

• The traffic management gasket: While akey element of any design, it is impor-tant to note that this interface will differfor every application and is thereforebeyond the scope of the MFRD.

Internally, the MFRD is a cell-basedswitch architecture supporting 40 to 128byte payloads. To understand its operation,let’s look at a block diagram and follow thecourse of traffic from ingress through egress;in this way we can easily understand its fea-tures and capabilities. The basic structure ofthe MFRD is illustrated in Figure 3.

Summer 2004 Xcell Journal 73

Figure 4A Figure 4B

Figure 4C Figure 4D

Figure 4E Figure 4F

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B A C K P L A N E S

Page 74: Xcell Journal Issue 49

The switch comprises four basic elements:

• The ingress datapath illustrated in thetop half of the diagram

• The switch ports illustrated on theright side

• The egress datapath along the bottom

• The management interface on the left.

Also clearly visible is the use ofLocalLink and the DCR bus as the interfacestandards in the architecture, as well as side-band signaling for flow control status onthe cascade interfaces.

Figure 4 illustrates how data flowsthrough the ingress datapath. Dataflowthrough the MFRD begins at theLocalLink ingress port at the top right sideof Figure 4A. Incoming cells are simultane-ously vectored to destination lookup andcascaded through the switch to any down-stream devices in the configuration. Thisapproach ensures efficient handling ofbroadcast and multicast traffic which tra-verse multiple devices.

In Figure 4B, destination lookup for-wards the cell to the appropriate port (ormultiple ports in the case of multicast or

broadcast). On this path we first enter aFIFO depth control block, which isresponsible for ingress flow control for thisport. If this cell triggers a FIFO evententering the buffer immediately down-stream, the logic generates port-specificbackpressure to the ingress traffic managerover the cascade interface (Figure 4C). Thislogic does not exercise flow control. Itmerely signals the need for flow control asthe packet is forwarded to the port, illus-trated in Figure 4D.

Figure 4E shows how the cascade inter-face also aggregates port-specific backpres-

74 Xcell Journal Summer 2004

Figure 5A Figure 5B

Figure 5C Figure 5D

Figure 5E Figure 5F

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Figure 5 – MFRD egress datapath

B A C K P L A N E S

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Summer 2004 Xcell Journal 75

sure from downstream devices in the cas-cade chain, communicating flow controlrequirements for all ports to the ingress traf-fic manager. Figure 4F indicates that thearchitecture also supports the communica-tion of flow control from the egress side ofthe switch across the serial links. Thismechanism is able to refine backpressureto the ingress traffic manager with priority-specific information per port.

The egress datapath of MFRD is illustrat-ed in Figure 5. Egress begins with the arrivalof a cell at the switch port (Figure 5A).Immediately upon arrival, it is fed into amemory access multiplexer that places it intothe appropriate priority queue. As shown inFigure 5B, this activity includes the genera-tion of flow control messaging back to alllink partners on the ingress side of the switchshould this action trigger a buffer event inthe target queue. This action communicatesport- and priority-specific backpressure to allingress traffic managers.

Egress from the priority queues is con-trolled by the priority scheduler (Figure 5C).This block can be configured using either astrict priority or weighted round robin sched-uling algorithm. The scheduler is tied intobackpressure from the egress cascade inter-face, enabling the egress traffic manager toassert priority-based flow control on thescheduling algorithm. This ensures that thescheduler will not select a priority candidatethat the egress traffic manager is not preparedto accept.

Once the scheduler selects a candidatecell for egress, it is forwarded to an egressmultiplexer on the egress cascade interface(Figure 5D). This block is also responsiblefor forwarding traffic from downstream cas-cade devices and must therefore ensure fairaccess to egress bandwidth. This is achieved

using weighted round robin schedulingthrough the egress multiplexer. Figures 5Eand 5F illustrate how competing traffic isserialized through this mechanism.

Use ModelsWe have shown that the MFRD enables agreat deal of flexibility to optimize themesh switch implementation when design-ing your system. To illustrate this, considerthe three configurations in Figure 6.

All three configurations support a 16-slotfull mesh fabric. Figure 6A shows a fullyintegrated single-chip mesh fabric controllerimplementing a 10 Gb SPI4.2 interface tothe application logic, a 15-port MFRD con-figuration, as well as processor IP suitable forimplementing blade and even fully distrib-uted shelf system management.

Figure 6B is a reduced-cost configurationof two devices that might be more suitablefor supporting a 2.5 Gb SPI3-based applica-tion. Figure 6C illustrates a very low-cost

solution for applica-tions that would usethe LocalLink cas-cade interface fromanother FPGA inthe Virtex-II™ andVirtex-II Pro fami-lies – a very effectiveway to enhance anexisting systemarchitecture.

The Xilinx ATCA Development PlatformTo facilitate mesh fabric development,Xilinx has also created a full mesh referenceboard for ATCA, a serial backplane stan-dard developed by the PCI IndustrialComputer Manufacturers Group(PICMG™). The ATCA DevelopmentPlatform is an ideal prototyping ecosystemfor mesh fabric systems (Figure 7).

The ATCA Development Platform fea-tures a Virtex-II Pro FPGA with 16 integrat-ed MGTs, 4.2 Mb of block RAM, 53,000cells of programmable logic, and embeddedPowerPC 405 microprocessors. The card isrouted as a 1X full mesh and includes IP forinstantiating an MFRD demo configura-tion. IP for instantiating a PowerPC man-agement complex and Linux board support

package (BSP) is also available.Programmable I/O suitable for SPI4.2,

CSIX, or other interfaces is routed to per-sonality module headers where you canintegrate application-specific designs. Theboard also provides access to the ATCAupdate port and a rear transition moduleshould your design require them.

Finally, the board features a NetworkEquipment Builders Specification (NEBS)-quality, dual feed, ATCA power subsystemdelivering 30W to the base board and170W to the personality module and reartransition module.

ConclusionSwitch fabrics are the backbone of modernhigh-performance system architectures;MGT-based serial communications technol-ogy makes the benefits of mesh fabric con-figurations extremely accessible. With theintroduction of the Virtex-II Pro PlatformFPGA, Xilinx created a foundation for build-ing such systems entirely with programmablelogic. Now, with the availability of the MeshFabric Reference Design and ATCADevelopment Platform, Xilinx is making iteven easier to exploit these developments andturbocharge your architectures.

2VP502VP20

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MeshSwitch IP

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Figure 6A Figure 6B Figure 6C

Figure 6 – Design flexibility with the MFRD

Figure 7 – The Xilinx ATCA Development Platform

For more information on these topics, please refer to the following resources:

• www.xilinx.com/esp/networks_telecom/optical/xlnx_net/mfrd.htm

• www.xilinx.com/esp/networks_telecom/optical/xlnx_net/atca_dev.htm

• www.picmg.org/newinitiative.stm

B A C K P L A N E S

Page 76: Xcell Journal Issue 49

The hard work is done! Now ASIC and FPGA designers can prototypelogic designs for a fraction of the cost of existing solutions. Here are 6+ million gates(measured the ASIC way) on an easy to use, stand-alone, USB2.0-hosted board (a PCI/PCI-X interface is coming soon). The DN6000k10 supports up to 9, 2vp100 VirtexII-Pro FPGA’s,with an incredible amount of FPGA to FPGA interconnect for easy logic partitioning. FPGA’sare interconnected with rocket I/O’s, enabling the movement of data between them at100’s of GB/s. In addition to 6M+ gates, the DN6000k10 also packs on-board:

• 2 PowerPC cores per FPGA (400MHz)

• Up to 8MB embedded RAM, 444, 18x18 multipliers — per FPGA

• 12 external 133MHz 32M x 16 DDR SDRAM’s, 5 4Mx16 FLASH

• 480+ connections for daughter card and logic analyzer interfaces

Configuration is fast, easy, and robust using a SmartMedia-based FLASH card or, via theUSB interface. Every tool, utility, driver, and support application that The Dini Group couldimagine you might need is included. Please contact us for complete specifications, we areeager to show you how our hard work can make you job easier.

1010 Pearl Street, Suite 6 • La Jolla, CA 92037 • (858) 454-3419 • Email: [email protected]

So Many GatesSo Many Gates

So Few Dollars

Page 77: Xcell Journal Issue 49

by Rick Folea CTORicreations, [email protected]

The first prototype of a processor boardwith Flash memory on it always poses a bitof a problem: How do you get the firstchunk of code/boot loader/RTOS into thePROM? You could pre-program thePROM before populating the board, butthat assumes the code is ready in time andwon’t require any changes.

Most designers and lab technicians don’thave access to or can’t afford the high-endJTAG tools available today. Furthermore,they usually don’t want to take the time tobuild the tests required to do the scan test-ing and Flash programming anyway. So,what do you do?

We have added a new tool to the popu-lar Universal Scan™ JTAG test suite that

makes Flash programming from yourXilinx FPGA or CPLD a snap. You justtell the Universal Scan tool which Xilinxpins are connected to the PROM, selectthe data file to put in the PROM, andthen press PROGRAM.

That’s it. What’s more, the UniversalScan tool is compatible with your Xilinxparallel port download cable, so you don’teven need special hardware to do it.

JTAG Background: How Does it Work?The I/Os on all Xilinx FPGAs andCPLDs are connected to a giant shiftregister around the boundary of thedevice. From the JTAG port, you canshift test vectors into this boundary reg-ister using the TDI pin and then applythose vectors to the I/Os, independent ofthe logic inside the part. In fact, the partdoesn’t even have to be configured forthis to work.

You can also unobtrusively monitor theI/O cells while your device is running byinstructing the Boundary Scan chain tocapture the state of the I/O cells, and thenshift the result out on the TDO pin.

Simply stated, you would follow thesesteps to program your PROM:

1. Shift a vector into the JTAG chain tosetup the address, data, and chip-enables (CEs) and apply it to the pins.

2. Shift the same vector into the JTAGchain to enable the write-enable (WE)signal to the PROM and apply it tothe pins.

3. Shift the same vector into the JTAGchain with WE disabled and applythat to the pins.

Repeat these steps a few million times,throw in an occasional command or two tothe PROM, and you’re done. Sounds easy,

A new, inexpensive tool from Ricreations makes it simple and easy to program small data files into Flash memory using Boundary Scan.

A new, inexpensive tool from Ricreations makes it simple and easy to program small data files into Flash memory using Boundary Scan.

Programming Flash Memory from FPGAs and CPLDs Using the JTAG Port

Programming Flash Memory from FPGAs and CPLDs Using the JTAG Port

Summer 2004 Xcell Journal 77

Page 78: Xcell Journal Issue 49

right? Unfortunately, dealing with the low-level details of the JTAG state machine istedious and difficult.

Fortunately, Universal Scan takes care ofthese details for you, and knocks the PROMprogramming effort down to the absolutesimplest model possible. You don’t need anynetlists, test executives, test vectors, specialhardware, or anything else normally associ-ated with JTAG test development.

A Simple SolutionUniversal Scan supports any bus configu-ration: 8-, 16-, and 32-bit PROM databuses built from 8-, 16-, or 32-bitPROMs. For example, you can have a 32-bit bus that comprises four 8-bit PROMsin parallel, and Universal Scan will pro-gram all four in parallel.

Figure 1 shows example PROM configu-rations supported by Universal Scan.Universal Scan also supports direct connec-tions between the Xilinx part and thePROM enables, or indirect enables throughmemory-mapped I/O. (Perhaps yourPROM CEs are derived from address linesin a PLD that is not in the JTAG chain, asshown in Figure 2.)

As Figure 2 also illustrates, PROM sig-nals don’t have to come from a singledevice; they can be spread out among anyof the devices in the chain.

Limitations and Design ConsiderationsAll this shifting of data around the JTAGchain mentioned previously is very timeconsuming. To demonstrate this point,

with a command, which doubles the over-head. Thus, a total of 7,200 bits must shiftaround the JTAG chain just to write onebyte/word, as shown in Figure 3. And thatdoesn’t include adding a command tocheck the results of the operation.

Now, if we assume we have a small 20KB boot loader we want to put in the Flashmemory, then we would need to repeat this7,200 bit shift operation 20,000 times.

Because you typically get only a fewhundred kilohertz bit rate out of a standardparallel port, that little 20 KB chunk ofdata takes about 10 minutes to program. Ifyou happen to have a larger FPGA or alarger data file, it will take even longer. It alldepends on the total length of the JTAGchain and the size of the data file.

Because all of the data is shifted in seri-ally and then applied to a giant latch inparallel, there is no penalty for bus width.An 8-bit data bus programs at the same rateas a 16- or 32-bit bus. So if you are using aPROM that supports an 8- or 16-bit widedata bus as an 8-bit device, go ahead andconnect the unused data lines and theBYTE control line to the FPGA. Eventhough they aren’t used in the final design,you can use them to program the PROMthrough JTAG and cut the programmingtime in half. This works with 16- and 32-bit devices as well.

Other ways you can minimize program-ming time include:

• Connecting the PROM to the smallestJTAG device you can (the one with theshortest boundary register)

let’s take a simple example of a XilinxSpartan-IIE™ device in a 456-pin FBGApackage (XC2S300E-FG456). Assume allof the PROM pins are connected directlyto this part.

This device has roughly 1,200Boundary Scan cells in the giant shift regis-ter around the boundary of the device. Ifwe take the worst-case scenario of writingone byte at a time to the PROM (nobuffered writes), then we need to:

1. Shift the 1,200 bits into the chain tosetup data, address, and CEs.

2. Shift the 1,200 bits into the chain toenable the WE signal.

3. Shift the 1,200 bits into the chain todisable the WE signal.

If we use an Intel® algorithm for writinga single byte, the example must be preceded

78 Xcell Journal Summer 2004

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Figure 1 – Examples ofsome of the supportedPROM configurations.Because no penalty exists forbus width, be sure to setupprogramming on the widestbus possible, even if it is notused in the actual design.

Figure 2 – Although it simplifies things to have all PROM pins connected to a single JTAG part, it is not a requirement. With Universal Scan you can program both memory-mapped PROMs andPROMs with signals from multiple JTAG devices.

Page 79: Xcell Journal Issue 49

• Putting any JTAG parts not connectedto the PROM into BYPASS mode to shorten the overall length of theJTAG chain

• Trying to connect all PROM signalsto only one of the devices in theJTAG chain (maximizes the numberof devices you can put into BYPASS)

• Choosing a Flash memory that sup-ports buffered writes – these don’trequire that you write a commandbefore every byte/word write-cycle andnearly doubles the throughput rate ofthe programming operation.

Also, be sure to connect all PROMsignals to the JTAG chain so that you cancontrol every aspect of the PROM’sfunctionality through Boundary Scan –and don’t forget to connect the VPENsignal to a pin under JTAG control.

Although this article focuses on XilinxFPGAs and CPLDs, this method willwork exactly the same way with anyJTAG-enabled device: processors, DSPs,Ethernet switches, microcontrollers, andothers.

If things don’t go according to plan,it’s easy to debug any issues you might behaving with the JTAG chain or Flashprogramming, as the Flash programmeris part of the Universal Scan JTAGdebugging tool. You can use UniversalScan to manually toggle signals betweenthe PROM and your Xilinx device to iso-late the issue quickly and efficiently.

ConclusionThe Universal Scan tool enables you toeasily program small data files into Flashmemory using Boundary Scan. UniversalScan does not replace high-end JTAGtools, which are great if you need to pro-gram large data files quickly or in largequantities. But if you want an inexpen-sive, simple, and flexible JTAG Flashmemory programming tool for prototypeand general lab development using smalldata files, then Universal Scan may be theperfect solution.

Universal Scan is available now as a free

upgrade to Universal Scan 6.0 users withactive registrations. A free, fully functionaltrial is also available on the Web atwww.UniversalScan.com. Download it andstart programming Flash from your Xilinxdevices today.

You’ll find more information on this toolon the Xilinx website at www.xilinx.com,under Products & Services > SystemResources > Configuration Solutions >Automatic Test Equipment (ATE) andBoundary Scan Tools. You can also call yourlocal Xilinx distributor for information orarrange a live demo at your business.

Command Data User Data

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Check out these Xilinx approved suppliersif you are interested in full high-end orhigh-speed JTAG testing tools:

• JTAG Technologies www.jtag.com

• Acculogic www.acculogic.com

• Corelis www.corelis.com

• Goepel www.goepel.com

• Assett-Intertech www.assett-intertech.com

• Intellitech www.intellitech.com

• Flynn www.flynn.comFigure 3 – Programming Flash memories is slow because each and every bus transition requires shiftingthe data through the entire JTAG chain. This shows the un-optimized example described in the text.

For more information about Boundary Scan, please consult these resources:

Intel (www.intel.com)

Intel, “Designing for On-Board Programming Using the IEEE 1149.1 (JTAG) Access Port” Application Note #AP-630.

Intel, “Introduction to On-Board Programming with Intel Flash Memory”Application Note #AP-624.

Xilinx (www.xilinx.com)

Folea, Rick. “Got the BGA Blues?” Xcell Journal – Issue 46, Summer 2003.

Xilinx, “A Quick JTAG ISP Checklist” Application Note XAPP104.

Xilinx, “Using BSDL Files for Spartan-3 FPGAs” Application Note XAPP476.

Xilinx, “Using the XC9500/XL/XV JTAG Boundary Scan Interface” Application Note XAPP069.

Amazon (www.amazon.com)

Parker, Kenneth. 2003. The Boundary-Scan Handbook. Kluwer Academic Publishers: 3rd edition.

Summer 2004 Xcell Journal 79

Page 80: Xcell Journal Issue 49

by Anthony Le Marketing Manager, Configuration Memory Products Xilinx, [email protected]

Frank TothMarketing Manager, EasyPath ProductsXilinx, [email protected]

When Xilinx set out to design a high-performance and dense PROM thatcould configure a wide variety of FPGAsat a low cost, they needed to think “outof the box” to meet the monetary, devicecomplexity, and schedule requirements.They also had several important require-ments for a partner: world-class FlashMemory technology, system-level andsilicon design expertise, and worldwidehigh-volume production.

After evaluating potential partners,Xilinx chose to collaborate with STMicroelectronics™ to design a newseries of feature-rich, high-performancePlatform Flash configuration PROMs(Table 1).

The Benefits of PartnershipThe advantages of designing a complexdevice with a knowledgeable partnerinclude:

• Reducing schedule timeframes andrisk. Platform Flash PROMs use STMicroelectronics’ state-of-the-art 0.15micron flash technology. They weredeveloped by a seasoned team of sys-tem-on-chip system and IC designers.

• Taking advantage of the core competen-cies and experience of each partner.Xilinx brought more than 20 years ofFPGA configuration managementexpertise to the challenge of designingthe Platform Flash configuration PROM.The new device includes multiple modesof configuration (serial, JTAG, and paral-lel) as well as the ability to easily managemultiple bitstreams and unique featureslike bitstream compression.

Xilinx and ST Microelectronics have produced a “no compromise” PROM with extensive features at a reasonable cost.

Xilinx and ST Microelectronics have produced a “no compromise” PROM with extensive features at a reasonable cost.

Developing the NewPlatform Flash PROMDeveloping the NewPlatform Flash PROM

XCF01S XCF02S XCF04S XCF08P XCF16P XCF32P

1 Mb 2 Mb 4 Mb 8 Mb 16 Mb 32 Mb• • • • • •

• • •• • •• • •

3.3 3.3 3.3 1.8 1.8 1.81.8 - 3.3 1.8 - 3.3 1.8 - 3.3 1.5 - 3.3 1.5 - 3.3 1.5 - 3.3

33 33 33 40 40 40VO20 VO20 VO20 FS48 FS48 FS48

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80 Xcell Journal Summer 2004

Table 1 – Platform Flash PROM family

Page 81: Xcell Journal Issue 49

• Designing and producing the rightproduct for the market. With itsextensive worldwide FAE force anddesign centers, Xilinx worked closelywith FPGA users to define a PROMthat meets the needs of sophisticatedsystem designers.

Platform Flash PROMs are cost-com-petitive products that have both therequired baseline features as well as newcapabilities to make FPGA systemsmore attractive and flexible.

• Taking advantage of sophisticated flexi-ble worldwide manufacturing expertise.ST Microelectronics has the manufactur-ing capacity to produce PROMs in highvolumes, along with extensive experiencein very small form factor packages.

The Platform Flash PROM offersdesigners the smallest package board spacearea per megabit in the industry, such asthe VO20 TSSOP (6.4 mm x 6.5 mm) for1, 2, and 4 Mb density PROMs. Becauseboard space (horizontal as well as verticalspacing) is always at a premium, largerPlatform Flash devices with 8, 16, and 32Mb densities come in small (8 mm x 9mm) thin flat ball grid array packages.

During the product definition processfor Platform Flash PROMs, several multi-ple chip packaging and stacked dieapproaches were carefully examined. Noneappeared to be competitive because thegoal was to produce a configurationPROM with the highest reliability, lowestcost, and minimum board space. The resultis among the world’s most flexible, cost-effective configuration PROMs.

CompressionHigher density Platform Flash PROMs(Figure 1) employ an advanced bitstreamcompression technology from Xilinx.Compression allows you to store moreinformation in the same memory space,thus reducing cost and board space.

Bitstream file(s) are compressed usingXilinx’s ISE design software. The com-pressed file(s) are then programmed intothe Platform Flash PROM, just like anyother bitstream file.

(Figure 2). A microprocessor or other con-figuration engine can then activate a bit-stream at any time, allowing systemadministrators to access previous versionsof system configuration in the event that aproblem with a newly transmitted config-uration arises.

Safe updates can be achieved with theability to store multiple bitstreams.Updated bitstreams can be programmedinto the free memory blocks of thePlatform Flash PROM without losing theoriginal bitstream.

ConclusionDeveloped jointly with ST Microelectronics,the Platform Flash family of configurationPROMs offers users the ultimate in low-cost, feature-rich system options, includ-ing compression and bitstream upgrademanagement.

For more information about the new Platform Flash PROMs, visitwww.x i l inx . c om/x l n x / x i l _ p r o d c a t _product.jsp?title=PFP.

The Platform Flash PROM has a built-in decompressor that automatically senseswhen a compressed file is stored, anddecompresses compressed bitstream infor-mation on the fly.

Typically, you can get 50% more bitsusing this advanced compression technology,fitting, for example, a 48 Mb FPGA design(such as a Virtex-II™ 2VP100 design) intoa 32 Mb Platform Flash PROM.

Upgrade ManagementYou can accomplish in-system program-ming and upgrades via the JTAG portusing the industry-standard four-wire TestAccess Port interface (IEEE 1149.1).Platform Flash PROMs are IEEE 1532-compliant, adding to the flexibility andtotal system integration that allows them tobe used with other Xilinx IEEE 1532-com-pliant devices such as CoolRunner™-IICPLDs and Virtex-II Pro™ FPGAs.

The Platform Flash PROM architec-ture integrates unique controls that give itthe ability to store multiple bitstreams

Summer 2004 Xcell Journal 81

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Figure 1 – Platform Flash block diagram

Figure 2 – Platform Flash block design revisions

Page 82: Xcell Journal Issue 49

by Daniel DenningResearch EngineerNallatech [email protected]

The XtremeDSP™ Development Kit-II,developed by Nallatech in partnershipwith Xilinx, provides an ideal develop-ment platform for high-performance sig-nal processing applications such assoftware defined radio, networking,HDTV, 3G wireless, and video imagery.The kit provides entry into scalableDIME-II systems from Nallatech.

The combination of the XtremeDSP kit,Simulink™ environment in MATLAB™,and Xilinx System Generator 6.1i softwareoffers a complete design framework forFPGA and DSP designers to get partial orentire systems running on hardware quicklyand efficiently. This approach is redefiningtime to market by rapidly producing high-performance systems with design flexibility,as well as the possibility of reconfiguringand upgrading the system without changingthe physical hardware.

FeaturesThe XtremeDSP kit includes an on-boarduser-programmable Xilinx XC2V3000FPGA, two 14-bit ADC channels with asmany as 65 mega samples per second(MSPS) per channel, and two 14-bitDACs with as many as 160 MSPS perchannel. A Spartan-II™ FPGA is pre-configured with 32 bit/33 MHz PCI orUSB 1.1 firmware. One bank of 1 MbZBT SRAM, configured as 512K x 16, isalso available. An external power supplyallows you to power the kit on its own;JTAG configuration headers and statusLEDs provide feedback. Figure 1 showsthe XtremeDSP kit. Figure 2 shows ablock diagram of the kit.

The XtremeDSP kit comes withNallatech’s Field Upgradeable SystemsEnvironment (FUSE) FPGA managementsoftware. This software provides the abili-ty to control and configure the FPGA andtransfer data between the kit and the hostPC thorough a GUI or C-based API.Additional options allow the use of Java orMATLAB M-code script control.

The XtremeDSP Kit-II is an ideal development platform for DSP design without VHDL programming.The XtremeDSP Kit-II is an ideal development platform for DSP design without VHDL programming.

Accelerate and Verify Algorithms with the XtremeDSP Development Kit-II

Accelerate and Verify Algorithms with the XtremeDSP Development Kit-II

82 Xcell Journal Summer 2004

Page 83: Xcell Journal Issue 49

Designing with System GeneratorThe first step in creating a SystemGenerator model is as follows:

1. Open a Simulink workspace and dropa System Generator token in at thetop level of the model.

2. Open up the token. This allows youto select various options, such asFPGA device, package, system clock,location of the generated VHDL, andtype of synthesis tool required. Youcan also drop the token into a subsec-tion of the System Generator model.

subsystem has its own associated input andoutput ports. Placing low-level blocks intothe Simulink environment creates a bot-tom-up design approach, which allowsfunctional verification of each subsectionbefore it is included in the system model.

During the design process, the Simulinkenvironment allows you to test and verifythe model, providing an array of test facili-ties for this purpose, including scopes,graphs, and displays. For further pre- andpost-processing and verification, you canimport to and extract the data from theMATLAB environment. When extractingdata, MATLAB functions offer extensivepost-processing options, including three-dimensional visualization graphs, plottingimages, and a vast collection of computa-tion algorithms.

Hardware Co-Simulation on the XtremeDSP Kit-IIVerification of the software model meansthat you can then test and verify the modelin hardware by creating a hardware co-sim-ulation block, executed by the SystemGenerator token in the model, which con-trols the design flow. Select the compilationtarget for hardware co-simulation in thisblock and choose the XtremeDSP kit as thehardware target. This will generate anequivalent hardware Simulink co-simula-tion library block.

This block is effectively an FPGA bit-stream, the result of a synthesis tool such as

This functionalityallows you to construct asystem quickly by placingand connecting tradition-al System Generatorblocks. You do not haveto write any VHDL,although a black box pro-vides this capability ifrequired.

Other user-friendlyfeatures include the abili-ty to drop Xilinx efficienthandcrafted IP blocks

into the model, such as fast Fourier trans-forms (FFTs), multipliers, direct digitalsynthesizers (DDSs), linear feedback shiftregisters (LFSRs), and finite impulseresponse (FIR) filters.

Each block within the model has associ-ated options that allow for customization.For example, Figure 3 depicts the differentoptions available for block RAM place-ment, such as size, initial values, writingoptions, and distribution of memory.

Grouping various System Generatorblocks together generates subsystems, cre-ating a hierarchy within the model. Each

Summer 2004 Xcell Journal 83

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2xDAC

(MCX Outputs)

Flying LeadJTAG

Header

Parallel IVJTAG

Header

Spartan-IIInterface FPGA

Configured withAppropriate

Interface ControlFirmware

(i.e., USB/PCI)ProgrammableClock Source B

Virtex-II(XC2V80-4CS44)

User ClockFPGA

Virtex-II(XC2V3000-4FG676)

Main UserFPGA

Local Bus (LBUS)

Adjacent Out Bus (ADJOUT)

Comms P-Link 0

Adjacentin Bus

(ADJIN)

ProgrammableClock Source A

*Clock C :Crystal or Internal

Inter-FPGA clock nets(source clocks, generatedclocks and feedback clocknets)

Connected Bus

*Note that Clock C is NOT initially available in the kit. It is a socket to allow users to populate their own crystals if required.

KEY

Signals predominantly associated with thegeneral kit, i.e., JTAG access

User signals part or in whole associatedwith the FPGAs

Figure 1 – XtremeDSP (DIME-II) kit hardware

Figure 2 – Functional block diagram of the XtremeDSP kit

Figure 3 – Example of System Generatorblock options with block RAMs

Page 84: Xcell Journal Issue 49

XST (Xilinx Synthesis Tool). The blocktakes care of board operations such asdevice configuration, data transfers, andclocking. Each port in the software modelmaps to the relevant hardware co-simula-tion library block.

The co-simulation library block nowoffers options for hardware co-simulationwith the DIME-II XtremeDSP Kit-II.When Simulink simulates the model, ittakes the results from the FPGA on theXtremeDSP kit. You can treat the libraryblock exactly the same as any other in theSimulink library.

TCP/IP Hardware Co-SimulationHaving produced a hardware co-simulationlibrary block, your next step is to selectwhich bus configuration over which co-simulation will take place. The XtremeDSPkit offers the following standard co-simula-tion options: PCI and JTAG. An enhancedoption is available from Nallatech to addsupport for TCP/IP, which allows you toshare the XtremeDSP kit for hardware co-simulation through another workstation.

As the XtremeDSP kit is a derivative ofNallatech’s DIME-II BenONE mother-board and BenADDA module, this combi-nation of hardware makes the connectionto an Ethernet module possible. This pro-vides the capability to power the board onits own without the need for additionalworkstations and their associated licenses.With this module interface connection onthe BenONE motherboard, the board cannow be run on its own anywhere – provid-ing that it has a TCP/IP location.

Therefore, if a design team wants to effi-ciently utilize the FPGA developmentboard, the board no longer needs to beswapped from workstation to workstation,as each designer can change their location,providing that the appropriate softwarelicenses are available.

For an extreme proof-of-concept exam-ple, take a transatlantic hardware co-simu-lation of the AES-128 (AdvancedEncryption Standard). The board runs onits own with a loosely coupled connectionto the Internet, located in a laboratory inSan Jose, California, while the design of theAES-128 encryption core in System

Generator is completed in the UnitedKingdom. Simulation speeds wereincreased by around a factor of two, butmore importantly, the FPGA engineer didnot need a board for functional hardwareverification to occur.

This capability provides significant bene-fits when working with shared hardware inboth the development and debug phases of aproduct’s lifecycle. To have the ability to con-nect to a remote piece of hardware and carryout co-simulation aids the development ofproducts within a team environment, whereindependent and geographically scatteredteam members need access to a singlephysical piece of hardware at a particularsite. A principle example of this could bedevelopment and support work for basestation components.

Hardware Co-Simulation Greater than 32 BitsWhen simulating designs in SystemGenerator without an FPGA co-simula-tion, you can simulate any number of bina-ry widths by using the library blocks inSystem Generator. This is not currentlypossible when converting the model for co-simulation on the FPGA.

Once the I/O bit widths become greaterthan 32 bits, System Generator will indi-cate that an error has occurred. To avoidsuch an error, split the bit widths down to32 bits so that each I/O port on the co-sim-ulation library block has a width of 32 bits.

Incorporating a part-System Generator,part-FPGA wrapper keeps the same bitwidths within the model and the FPGA.Slicing the data path on entry to the co-

simulation block allows concatenationback into the FPGA for the IP core or sys-tem. This data path will split again beforeleaving the FPGA, finally concatenatingback into the Simulink model.

Figure 4 illustrates this technique for co-simulating bit widths of 128 for the AES-128. The gray section in Figure 4 representsthe co-simulated area on the FPGAachieved during the simulation process. Thearea outside the gray region shows the fixedorder in which the bit widths appear in theSystem Generator model. This methodapplies to any number of bit widths: forexample, 64, 128, 256, and 77.

ConclusionThe XtremeDSP Kit-II offers the idealdevelopment platform for DSP designers.Combining the kit with System Generatorprovides the capability to design systemswithout the need for programming inVHDL, although the option exists to addVHDL and even MATLAB M-code forHDL auto generation.

By including a TCP/IP interface, unlessthere is a need to see or connect inputs tothe board, this type of connection is aviable option in hardware co-simulationand offers cost-effective, efficient utiliza-tion and time-saving benefits.

To learn more about DIME-II, pleasevisit www.nallatech.com/solutions/products/embedded_systems/dime2/index.asp, or [email protected]. For more informa-tion about the XtremeDSP DevelopmentKit-II, please visit www.xilinx.com/ipcenter/dsp/development_kit.htm.

84 Xcell Journal Summer 2004

Simulink Environment

FPGA

IP Blockor

System

32 bits32 bits

128 bits 128 bits

Figure 4 – Hardware co-simulating with designs greater than 32 bits

Page 85: Xcell Journal Issue 49

by Richard WilliamsSenior EngineerHunt Engineering (UK) [email protected]

The main goal of image processing is tocreate systems that can scan objects andmake judgments on those objects at ratesmany times faster than human observers.When creating an image processing sys-tem, the first step is to identify the imag-ing functions that allow the computer tobehave like a trained human operator.Once you’ve accomplished that, you canthen concentrate on making that systemrun faster by finding – and removing – thebiggest performance bottleneck.

For most complex imaging systems, thebiggest bottleneck is the time taken toprocess each image captured. As a simplesolution, you could use more advancedprocessors to implement the algorithms –the faster the processor, the faster the pro-duction line. Alternatively, you could use

dedicated hardware built specially for thejob, although that can be very expensive.The most innovative solution is to use pro-grammable electronics in the form of fieldprogrammable gate arrays.

Real-World ApplicationOne of our customers, Visiglas SA, usesDSP-based boards to inspect glass contain-ers. The systems are successfully installed allover the world, inspecting hundreds ofobjects per minute. Figure 1 shows some ofthe image processing used in these systems.

For their next-generation systems,Visiglas would like to:

• Improve fault detection by usinghigher resolution images

• Increase system throughput by processing larger images faster thanthe current systems allow.

Hunt Engineering has been able toachieve these requirements through the useof Virtex-II™ FPGAs.

Increase Image Processing System Performance with FPGAs

Increase Image Processing System Performance with FPGAs

Summer 2004 Xcell Journal 85

Using FPGAs instead of DSPs to perform common image-processing functions can offer a wide range of benefits.

Using FPGAs instead of DSPs to perform common image-processing functions can offer a wide range of benefits.

Page 86: Xcell Journal Issue 49

The Mathematics of Image ProcessingImage processing typically involves apply-ing the same repetitive function to eachpixel in the image to create a new outputimage. We can categorize the techniquesinvolved into three types:

1. Where one fixed-coefficient operationis performed identically on each pixelin the image.

2. Where there are two input imagesrather than one. In this type of opera-tion, the mathematics performed maybe the same as for the fixed coefficients,but now the operation is based on theposition of the pixel in the image.

3. Neighborhood processing, or convolu-tion. There is only one input frame,and the result created for each pixellocation is related to a window of pix-els centered at that location.

So although the exact mathematical oper-ation may vary, all three techniques requirerepetitive functions to be performed acrossthe entire image. Thus, this kind of process-ing is ideally suited to a hardware pipelinethat can perform fixed mathematical opera-tions over and over on a stream of data.

DSPs versus FPGAsDSPs typically must execute severalinstructions to perform an image process-ing function. Because it is a sequentialdevice, these instructions will probablytake several processor clock cycles to com-plete. Add to that the cycles needed tofetch the image data, store the results, andhandle interrupts, and you have a largenumber of clock cycles needed to processeach pixel.

Because the majority of image processingcan be broken down into highly repetitivetasks, FPGAs present a very interesting alter-native to DSPs. Additionally, you can useFPGAs to perform lots of steps in parallel,using dedicated logic for each step.

Through the use of Virtex-II FPGAs, wecan implement image-processing tasks atvery high data rates, reaching hundreds ofmegahertz. These functions can be directlyperformed on a stream of camera data as itarrives without introducing extra processing

reusing multiplier units to complete thematrix multiplication.

FPGAs, however, can implement as manymultipliers as necessary to calculate one pixelat the full input data rate, whether the convo-lution uses a 3x3 kernel or a larger 5x5. Withthe one-million-gate Virtex-II, 40 multipliersare available; in the eight-million-gate ver-sion, this number increases to 168. By map-

ping convolution to FPGAsthat already provide dedi-cated multipliers amongtheir sea of gates, it becomeseasy to build a processingpipeline that can convolveat very high data rates.

A Role for the DSP?Although a large propor-tion of image processingalgorithms are simply high-ly repetitive processes, thereis still a role for the DSP. Ina system that can benefitfrom the performanceadvantages of FPGAs, thereis a point in the data flowwhere a decision has to bemade. This decision willoften take the form of “if,then, else” logic rather thana pixel-by-pixel iteration.

For control loops andcomplex branches in opera-

tion, DSPs can still prove to be highly effec-tive. Implementing equivalent logic inFPGAs can quickly eat up the available gatesand reduce the overall data rate.

A simple solution is to use both types ofresources in a single system: a high-data-rate FPGA as the data-reducing engine,feeding results downstream to a DSP as theaccept/reject, pass/fail decision maker.

Image Acquisition and Processing with HERONThe HERON module range from HuntEngineering provides a flexible, high-per-formance solution to image processing.HERON-FPGA modules, which includethe Virtex-II series of FPGAs, presentresource nodes that are suited to a widerange of tasks, particularly the repetitivetasks of image processing.

delays – significantly reducing and some-times removing performance bottlenecks.

In particular, you can map more com-plex functions such as convolution verysuccessfully to FPGAs. When convolvingan image, a window of pixels is treated witha mask, where individual locations in thewindow are “weighted” according to a setof previously defined coefficients. For each

position of the window, all pixels are mul-tiplied against their respective coefficients.The final result is then scaled to produce asingle output pixel for the center locationof the window.

In essence, the whole convolutionprocess is a matrix-multiplication, and assuch requires several multiplications foreach pixel. The exact number of multipliersrequired is dependent on the size of win-dow used for convolution. For example, a3x3 kernel (window) requires nine multi-pliers; a 5x5 kernel requires 25 multipliers.

Conventional DSPs have a fixed num-ber of multiplication units inside theprocessor core – fewer multiplier units thanwhat are needed to perform the matrixmultiplication in one step. Thus, a DSPwould introduce a performance drop by

86 Xcell Journal Summer 2004

Figure 1 – A real-world application of an imageprocessing system where FPGA processing can

significantly increase performance

Raw image of a bottle with special lighting to highlight problems

Edge detected image with regions of interestmarked for fault detection

▲▲

Page 87: Xcell Journal Issue 49

These FPGA modulescan also be directly con-nected to cameras, accept-ing data in formats suchas Camera Link andRS422. Combine thatwith HERON processormodules based aroundTexas Instruments’™TMS320C6000 DSPseries, and a completeimaging solution becomespossible.

In addition to the hard-ware resources required atthe heart of the system,firmware and software arealso necessary to imple-ment the appropriate algo-rithms in the FPGA andDSP. Hunt Engineering offers imaginglibraries for both DSPs (in C) and FPGAs (inVHDL), downloadable from www.hunteng.co.uk. These libraries enable you to quicklyand easily assemble the key algorithm com-ponents into a working imaging system.

Memory RequirementsIf you use the multi-frame operations pro-vided in our VHDL imaging libraries (suchas the addition of two images), you musthave an area of available memory that canstore an entire frame.

Unless the size of one frame is verysmall, the FPGA’s internal RAM resourceswill be insufficient for this type of opera-tion. In this situation, you could use a mod-ule like the HERON-FPGA5 (Figure 2).The reference image is stored in SDRAMexternal to the FPGA and read into theFPGA as required.

Because separate dedicated logic isused to receive the incoming image,access the stored image, and perform theprocessing, image processing can still beperformed at pixel rates greater than 100megapixels/sec. With a processor-basedapproach, the processor has to access bothimages from memory, and these opera-tions will be slower than pixel-basedoperations when using a DSP.

Neighborhood processing, on the otherhand, requires several lines of image data to

be stored before processing can begin. Theimage size determines the amount of stor-age required per line, and the kernel size ofthe operation determinesthe number of lines. It’spossible to use the FPGA’sinternal block RAM forthis storage, but theamount available dependson the size of the FPGAand the design require-ments.

For example, a one-million-gate Virtex-IIFPGA has 90 Kb ofblock RAM. If nothingelse in the designrequires block RAM,then the convolution can use all 90Kb. With 8-bit monochrome data,you can store 90 Kpixels. If the imageis 2K pixels per line, then 45 lines ofdata is more than enough for a largeconvolution function.

If the FPGA design uses block RAMfor other functions, using hardware likethe HERON-FPGA5 enables you tostore the image in off-chip SDRAM.

ConclusionMany key imaging functions break downinto highly repetitive tasks that are wellsuited to modern FPGAs, especially those

with built-in hardware multipliers and on-chip RAM. The remaining tasks require hard-ware more suited to control flows anddecision making, such as DSPs.

To gain the full benefit of bothapproaches, systems can effectively combineboth FPGAs and DSPs. With the additionof standard imaging functions written ineither VHDL or C, all of the key buildingblocks are available to create an image pro-cessing system. Hunt Engineering hasdeveloped a demonstration framework ofsuch a system, shown in Figure 3.

For our customer Visiglas, a system suchas the one shown in Figure 4 allows themto achieve their performance goals.

The next logical step is an addition to theHERON module range of devices for Virtex-II Pro™ FPGAs. With a PowerPC™processor core, a sea of gates, built-in multi-pliers, and on-chip RAM, a self-containedhigh-performance imaging solution becomespossible in a single chip.

Figure 2 – Hunt Engineering’s HERON-FPGA5 module with a Virtex-II FPGA, 256 Mb of SDRAM, and

digital I/Os for connecting cameras

Figure 3 – Using HERON to combine a DSP and an FPGA for image processing

Figure 4 – The imaging framework provided by Hunt Engineering to demonstrate FPGA

image processing at frame rate

Summer 2004 Xcell Journal 87

Page 88: Xcell Journal Issue 49

by Suhel DhananiSenior Solutions Marketing ManagerXilinx, [email protected]

Steve ZackSignal Processing EngineerXilinx, [email protected]

FPGAs have been used in DSP applicationsfor years as logic aggregators, bus bridges,and peripherals. More recently, FPGAshave gained considerable traction in high-performance DSP applications and havealso emerged as ideal co-processors forstandard DSP devices.

In these latter roles, FPGAs providetremendous computational throughput byusing highly parallel architectures. Becausethe hardware is re-configurable, you candevelop customized architectures for idealimplementation of your algorithms.

The new generation of Spartan-3™low-cost FPGAs, developed using 90 nmprocess technology, not only creates aneffective way to implement high-perform-ance DSP functions but provides an evenmore economical solution. Their low costmeans that you can use them to implementhigh-performance DSP co-processingfunctions in conjunction with a conven-tional DSP device – typically integratingpre- and post-processing functions in acost-effective manner.

Key AdvantagesFPGA architectures are well suited forhighly parallel implementations of DSPfunctions, allowing for very high perform-ance. And user programmability allows youto trade off device area versus performanceby selecting the appropriate level of paral-lelism to implement your functions.

FPGAs are essentially arrays of uncom-mitted logic and signal processingresources. These signal processingresources allow you to implement DSPfunctions using highly scalable, parallelprocessing techniques.

For example, whereas a traditionalDSP solution would implement multiplemultiply accumulate (MAC) functions ina serial manner, an FPGA allows you toimplement these in parallel using dedicat-ed multipliers and registers that are nowavailable in the Spartan-3 family.

As another example, consider a 256-tapfinite impulse response (FIR) filter. By

using resources available in the FPGA fab-ric, you can design a highly parallel imple-mentation and achieve higher performance(Figure 1).

Because FPGAs are completely hard-ware-configurable, you have the flexibilityto only use the necessary resources that thealgorithm demands.

Figure 2 shows the different ways ofimplementing four MAC functions. Byusing four embedded multipliers withinthe FPGA fabric, you can complete theseimplementations at maximum speed.Alternatively, you can opt to conserve areaand implement the same function at alower performance by using only one mul-tiplier, one accumulator, and a register, oruse the semi-parallel approach.

Although FPGAs bring significantbenefits to DSP, it is important to analyzethe effective cost of implementing DSPfunctions within the FPGA fabric. Forthe purpose of this analysis, the newSpartan-3 FPGA family is consideredbecause of its low cost and system featuresfor DSP.

Spartan-3 Devices: Optimized for DSPSpartan-3 FPGAs use 90 nm manufactur-ing technology to achieve low silicon diecosts. These devices are also the only low-cost FPGAs that have all of the featuresrequired for efficiently implementingDSP functions – features that were oncethe exclusive domain of high-end FPGAs(Table 1).

With the Spartan-3 family, you canimplement high-performance, complexDSP functions in a small portion of thetotal device, leaving the rest of the devicefree to implement system logic or interfac-

Enabling Low-Cost DSP Co-Processing with Spartan-3 FPGAs

88 Xcell Journal Summer 2004

Embedding high-performance DSP functions within FPGA fabric is now a genuine low-cost option.

Spartan-3 Silicon Features Customer Benefits

Embedded 18 x 18 Multipliers Area-efficient implementation of multiply function

Distributed RAM Local storage for DSP coefficients, small FIFOs

Shift Register Logic 16-bit shift register ideal for capturing high-speed or burst modedata and to store data in DSP applications

Up to 104 18 Kb Block RAM Video line buffers, cache tag memory, scratch-pad memory, packet buffers, large FIFOs

Table 1 – These Spartan-3 features enable DSP functions in an area-efficient manner.

Page 89: Xcell Journal Issue 49

ing functions – providing both lower costsand higher system integration.

Table 2 demonstrates how the combi-nation of advanced features and low costwork together to provide DSP capabilityat a low cost. The table shows a samplingof available Spartan-3 parts, the numberof million multiply accumulate per sec-ond (MMAC/s), and the cost forMMAC/s in each device.

We calculated the MMAC/scolumn by multiplying the num-ber of multipliers with their oper-ating frequency, which forSpartan-3 FPGAs is 150 MHz inthe slowest speed grade.

Then, looking at the published50,000-unit price for the slowestspeed grade of the appropriatedevice, we calculated the cost forMMAC/s. This is one of the quot-ed industry benchmarks, with thecost per MMAC/s reaching aquarter of a cent.

To calculate the effective cost of a DSPfunction when implemented in an FPGA,we considered the Spartan-3 XC3S1000device, which is a mid-range member of theSpartan-3 family. In many cases, a givenDSP function uses not only the FPGA logicbut also embedded multipliers and blockRAMs. In that case, we included the esti-mated amount of die space taken by theseembedded functions and added that to thedie area used by the logic.

Table 3 shows some of these functionsand the cost of implementing these withinthe Spartan-3 silicon. (We have notincluded the cost for programming thePROM, because in many cases you can usethe existing EPROM on-board to programthe FPGA.)

Some of the most common functions usedin DSP applications are fast Fourier trans-forms (FFTs) and FIR filters. A single channel64-tap MAC FIR filter running at 8.1 megasamples per second (MSPS) can be imple-mented for an effective cost of $0.41. Note

that this filter uses 200 logic slicesand four embedded multipliers –approximately 3% of the die area.

You can also implement simpleforward error correction DSPcores such as Viterbi and ReedSolomon functions at a low costwithin the Spartan-3 device. A 32-channel, parallel mode Viterbidecoder running at 1.9 MSPS perchannel has an effective cost of$5.06, or $0.16 per channel. AReed Solomon G.709 decoderfunction running at 60 MHz

How to Achieve the Lowest DSP Function CostNo standard currently exists to estimate theactual cost of implementing DSP functionsonto FPGAs. For the purposes of thisanalysis, however, let’s theorize that theeffective cost is the cost based on percent-age of silicon area utilized, multiplied bythe unit device cost. This is a fair calcula-tion, since the remainder of the FPGA isavailable for other system functions.

Summer 2004 Xcell Journal 89

Device Embedded Mults MMAC/second Cost for MMAC/s(18 x 18) (Number of Mults x

150 MHz)

XC3S50 4 600 $0.0055

XC3S200 12 1,800 $0.0024

XC3S400 16 2,400 $0.0030

XC3S1000 24 3,600 $0.0037

XC3S1500 32 4,800 $0.0044

AC Unit

Data Out

Reg

Reg

Data In

Coefficients

256 LoopsNeeded

to ProcessSamples

Conventional DSP Processor – Serial Implementation FPGA – Fully Parallel Implementation

C1

Data In

256 Operationsin One Clock Cycle

Data Out

C0

Reg

C2

Reg

C3

Reg

C4

Reg Reg

C5 C255

Device Area: <4A Device Area: <2A Device Area: 1A MMAC/s: 600 MMAC/s: 300 MMAC/s: 150

++

+

+

+

+

+

+

+

+

D

+

+

+

+

DD

Parallel Semi-Parallel Serial

HIGH SPEED OPTIMIZED FOR SMALL AREA

+ ++ +

+

Figure 1 – An FPGA’s parallel approach to DSP enables higher computational throughput.

Figure 2 – You can customize an FPGA to suit your needs.

Table 2 – Calculating the cost per MMAC/s

Page 90: Xcell Journal Issue 49

takes only 6.9% of the same device (withan effective cost of $0.92).

Complex functions such as a digitaldown converter (DDC) or a digital up con-verter (DUC) – commonly used in wirelessbase stations – take less than 20% of theSpartan-3 XC3S1000 device (with aneffective cost of $2.49).

Development Tool FlowWith Xilinx, you can use industry stan-dard development tools for your DSPdesigns. Using MATLAB™ andSimulink™ from The MathWorks, cou-pled with Xilinx System Generator forDSP, you can now model, simulate, andverify your signal processing algorithms

on your target hardware platform with-out leaving the Simulink environment.

The design flow typically involves thefollowing steps:

1. A DSP designer develops and veri-fies the hardware model usingindustry-standard tools from TheMathWorks in conjunction withXilinx System Generator for DSP.

2. With a push of a button, XilinxSystem Generator generates anHDL circuit representation that isbit- and cycle-true, meaning thatthe behavior is guaranteed to matchthe functionality seen in theSimulink/System Generator model.

3. The ISE design tools synthesize thedesign and produce a bitstream thatcan be used to program the FPGA.

The error-prone and time-consumingstep of having an FPGA designer trans-late the system engineer’s design intoHDL is thus eliminated. Figure 3 showsa typical design flow using the XilinxSystem Generator. With recent advancesin this product, DSP designers can nowgenerate an FPGA bitstream directlyusing Simulink/System Generator.

ConclusionWith its combination of low unit costand architecture optimized for DSPfunctions, Spartan-3 FPGAs have theindustry’s lowest price points for high-performance DSP functions. Xilinx fur-ther enables embedded DSP functions byproviding design tools that fit withinyour tool flow and enhance your produc-tivity by automating the FPGA imple-mentation process.

With the availability of Spartan-3devices, associated design tools, and theincreasing number of off-the-shelf DSPfunctions optimized for this fabric, youmust evaluate embedding DSP functionswithin Spartan-3 FPGAs as a viableoption.

For more information, visit www.xilinx.com/spartan3/, www.xilinx.com/dsp/,and www.xilinx.com/ipcenter/.

XILINXBLOCKSET

MATLABSIMULINK

ISE

FPGA Bitstream

ModelSim• Synthesis• Place and Route• Bitstream Generation

+

.mdl

.hdl, .tv, .do

Function/System Modeling

Auto HDL Generation

FPGAImplementation

Functions% of the Effective

Key Specification Other SpecificationsXC3S1000 CostDevice Utilized (50K Units)

1024-point 24.1% $3.23 20 µs transform 20 µs transform, burst I/O,complex FFT 16-bit input and phase factor

Single channel 3.0% $0.41 8.1 MSPS 16-bit data and co-efficient, MAC64-tap FIR filter implementation, 8.1 MSPS

Digital down 18.6% $2.49 Sample rate 100converter per MSPSchannel

Digital up 18.6% $2.49 Sample rate 100converter per MSPSchannel

Viterbi decoder 37.8% $5.06 1.9 MSPS per channel Parallel mode, trace-back 42,constraint length = 7,

32-channel, 1.9 MSPS per channel

Reed Solomon 1.3% $0.17 120 MHzG.709 encoder

Reed Solomon 6.9% $0.92 60 MHzG.709 decoder

Figure 3 – A DSP design methodology that works within an existing tool flow

Table 3 – Effective costs of various DSP functions in a Spartan-3 device

90 Xcell Journal Summer 2004

Page 91: Xcell Journal Issue 49

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Page 92: Xcell Journal Issue 49

by Rob SchreckSenior Marketing ManagerXilinx, [email protected]

Product designs are a major invest-ment. However, if a design is

stolen (known as reverse engi-neering), that unique product

can then be copied and sold for a lower price. Thecompany that originallydesigned the product losesrevenue and market share.Consumers may benefit inthe short term, but in thelong run companies willdecide against major prod-uct designs and consumers

will ultimately pay the price.Xilinx CoolRunner-II™

CPLDs offer a great way to pro-tect consumer designs from reverse

engineering. Of course, Xilinx CPLDsare non-volatile, so it’s not necessary toconfigure the device at start up. But let’sdiscuss more important security measures.

CoolRunner-II CPLDs offer unique features to ensure a more secure design and reduce the risk of reverse engineering.

Secure Your Consumer Design with CoolRunner-II CPLDs

92 Xcell Journal Summer 2004

Page 93: Xcell Journal Issue 49

Bits hidden here,somewhere...

Elusive Security BitsXilinx offers a unique capability inCoolRunner-II CPLDs: multiple securitybits. These security bits are electrically eras-able cells scattered throughout the device.You set the security bits by simply selectingthe action within the Xilinx iMPACT pro-gramming software dialog box when thedesign is finished. Once these bits are pro-grammed, the internal pattern remainsfixed in the device and the program is pro-tected from theft.

Somewhere above the substrate butbeneath the metal are floating gates thathold the nonvolatile memory bit contents(Figure 1). If another company wanted toreverse engineer the design, they wouldhave to de-program the security bits. To dothat, they would first have to look throughfour or five metal layers to find them.

Even if they could see through four orfive metal layers (Figure 2), they still could-n’t “see” the bits because they are inter-spersed among the programming bits. Plus,

a unique CryptoBLAZE processor, based onthe Xilinx PicoBlaze™ soft processor, withits own instruction set, non-volatility, andtricky timing. That would be a particularlydifficult device to reverse engineer.

Additionally, the CoolRunner-IIDataGATE feature can be used as a responseto tampering. DataGATE is designed todynamically and selectively block switchinginput signals that can draw power withinCoolRunner-II devices. To increase designsecurity, you can use the DataGATE featureto lock up the device when someoneattempts to read the program.

For example, you can use a serial passwordfrom an external source, such as a keypad. Ifthe password is correct, the device will run; ifnot, DataGATE will block all inputs anddeny additional password attempts.

ConclusionConsidering how important maintainingdesign security is to your company,CoolRunner-II CPLDs offer an easy-to-implement solution to make reverse engi-neering CPLD designs nearly impossible.See for yourself how you can take advantageof this unique feature for your next project.

For more information about CoolRunner-II devices, visit www.xilinx.com/cr2. For aQuick Start presentation on security issueswith Cool-Runner-II devices, visit www.xilinx.com/products/cpldsolutions/module/cr2_security.pps.

they would have to figure out which onesare the security bits and which ones are theprogram bits. Figure 3 shows the underly-ing configuration cells beneath the archi-tecture of CoolRunner-II devices.

So for someone to read-back the design,they would have to find the security bits (avery difficult task) and then erase them. Ifthey attempted to erase them with a laser,they would have to know where to aimand how to erase each of them withouterasing any other bits. They would alsohave to disconnect key signals for the chipoperation and bit read-back. It would takemany costly, time-consuming experimentsto arrive at a solution.

Additional Protection MeasuresAfter erasing the security bits, reverse engi-neers would still need to issue the correctdemands and reverse the JEDEC file. Theentire project would require a long, costlytrial-and-error process, and would not beeconomically prudent.

Even after reading the JEDEC file,reverse engineers still need to understandthe design. There are various tricks thatyou, as the original product designer, canuse to make such an analysis prohibitivelytime-consuming. For example, double-datarate designs make analysis much more diffi-cult to understand. You can also designusing state machines, which are less pre-dictable than processors. You can even build

Summer 2004 Xcell Journal 93

Figure 1 – CPLD wafer

Figure 2 – Wafer below the top routing layers

Figure 3 – Internal viewof CoolRunner-II CPLD

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by Steve PereiraTechnical Marketing ManagerSynplicity, [email protected]

As system complexities advance, program-mable logic follows suit. High-densityFPGAs now contain millions of gates andoperate at speeds in excess of 200 MHz. Atthis level, schedules, budgets, and FPGAdesign tools all begin to feel the burden.

You can incrementally increase perform-ance or reduce the area of Xilinx devicesusing the Synplicity® Synplify Pro® tool inseveral ways. In this article, we’ll describefour preferred ways to set up your design andfour ways to fine-tune synthesis, all of whichcan be used together or independently.

Design Setup to Improve Timing or AreaSetting up your design correctly can

result in huge performance increases orreductions in chip area. The following

checklist describes the best practices youcan use when setting up your design.

Include CORE Generator EDIFs or Timing Models for Black BoxesIf Xilinx CORE Generator™ EDIF files(*.edn) or black box timing models areprovided during synthesis, the SynplifyPro tool knows the path timing and canalter the logic surrounding the boxes basedon the timing constraints. If the design’scritical path starts or ends in a black box,adding the EDN file usually results in bet-ter performance.

To demonstrate this point, we took anopen-source design that included a black-box FIFO, with the critical path endinginside the FIFO. Without adding theCORE Generator EDN file to the SynplifyPro tool, the post PAR (place and route)results yielded an Fmax of 153 MHz.However, when we added the COREGenerator EDN file to the synthesis

process, the clock frequency jumped to 171MHz because of additional path optimiza-tion performed by Synplify Pro synthesis.

Provide Accurate Clock Constraints Under- or over-constraining your designresults in reduced performance. Do notover-constrain the clocks by more than15%. For maximum performance, makesure that there is 10% negative slack on thecritical clock. This ensures that criticalpaths are squeezed (see the RouteConstraint section for more information).

The Fmax field on the front panel of theSynplify Pro software is fine for a quickrun, but do not use it if you need maxi-mum performance. Instead, you can putunrelated clocks in separate clock groups inthe Synplify Pro synthesis design con-straints file (*.sdc). If your clocks are in thesame group, the Synplify Pro tool worksout the worst-case setup time for the clock-to-clock paths.

Tips for Improving Synplify ProPerformance for FPGA DesignsTips for Improving Synplify ProPerformance for FPGA Designs

94 Xcell Journal Summer 2004

Using simple setup and optimization techniques, the Synplify Pro synthesis tool helps you increase design speed and reduce chip area.Using simple setup and optimization techniques, the Synplify Pro synthesis tool helps you increase design speed and reduce chip area.

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Figure 1 shows a timing diagram for twoclocks that are in the same clock group.Synplify Pro rolls the clocks forward untilthey match up again. The tool then calcu-lates the minimum setup time between theclocks – in this case 10 ns.

If the clocks are very unrelated, severalhundred clock periods may be requiredbefore the clocks match up again. This willprobably result in the worst-case setup timebeing very small, such as 100 ps. You cancheck the setup time in the clock relation-ships table in the log file. If the setup timeis too short, it is best to re-constrain theclocks so that they are more related.

Specify Timing Exceptions You should provide all timing exceptions,such as false and multicycle paths, to theSynplify Pro tool. With this information,the tool can ignore these paths and concen-trate on the actual critical paths.

As an example, in the Synplify Pro 7.3.3tool we have enabled timing-driven, 3-stateto MUX conversion. If a 3-state path iscritical, the Synplify Pro tool automaticallyconverts the logic to multiplexers, thusspeeding up the path. Data on buses is usu-ally not critical and can survive a few clockcycles because the bus master can wait forthe data to become valid. In these situa-tions, applying a multicycle constraint tothe 3-state path causes the Synplify Protool to keep the TBUFs, thus saving area.

Constrain I/OsIf your design has I/O timing constraints,it is likely that the critical path is through

Resource Sharing With this option enabled, the softwareshares hardware resources, thus decreas-ing the area. If you disable this option,hardware resources are not shared, whichwill probably increase the area but yieldhigher performance.

FSM CompilerThis option extracts and optimizes finitestate machines (FSMs) based on the num-ber of states. As a rule, we find the follow-ing guidelines improve performance:

FSM ExplorerIf the previous methods of encoding do notproduce the desired result, you can use tim-ing-driven state encoding. The Synplify Protool automatically selects the best encodingfor the specified timing constraints.

Resource Allocation The use of dedicated macro blocks inXilinx devices usually provides the best syn-thesis solution, but this is not always thecase. A well-pipelined multiplier in logiccan often provide a faster (but larger) solu-tion. You can configure macro blocks with-in the Synplify Pro tool based on the designrequirements. You can also force the tool touse a specific resource implementation byadding any of the following attributes:

These attributes are extremely design-dependent.

the I/O buffer. The Synplify Pro tool rec-ognizes these paths as the most criticaland tries to optimize them. However, I/Opaths cannot usually be physically opti-mized further. Therefore, the Synplify Protool prematurely stops optimizing the restof the design.

A new switch has been added to theSynplify Pro 7.3 release called “Use clockperiod for unconstrained I/O.” Whenenabled, the tool does not include anyunconstrained I/O paths in timing opti-mizations, therefore allowing the optimiza-tion process to continue.

Fine-Tuning Designs to Improve Timing or AreaAfter setting up a design using the meth-ods previously described, you can use addi-tional options after synthesis to improvedesign performance or area utilization.Following these guidelines will usually savea device size or a speed grade, and in manycases, both.

The following optimization techniquesare design-dependent. Not all designs ben-efit from enabling these features. The bestmethod is to analyze the implementationof your design and see if the following opti-mizations improve performance.

Standard Optimization Techniques

Retiming and Pipelining Enabling the retiming and pipeliningoptions can improve your design perform-ance by as much as 50%. Retiming attrib-utes such as syn_allow_retiming let yourefine your constraints by applying retim-ing to a single register.

Summer 2004 Xcell Journal 95

Number of States Suggested Encoding Scheme2-4 Sequential5-40 OnehotOver 40 Gray

0 15

10ns 20ns 30ns

0 20 40 60 80 100 120 140

30

CLK1

CLK2

45 60 75 90 105 120 135

Macro Block Attribute (Options)

Multiplier syn_multstyle {logic |block_mult}

RAM syn_ramstyle {registers |select_ram | block_ram |no_rw_check}

ROM syn_romstyle {logic |select_rom | block_rom}

Shift Register syn_srlstyle {registers |select_srl |noextractff_srl}

Figure 1 – Clock relationships when in the same group

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Optimization ControlsThe Synplify Pro tool provides user con-straints to let you shape and control logicaccording to your design requirements.The following attributes and directives arethe most commonly used.

• syn_keep (in the source code).Preserves an RTL net throughout synthesis and prevents LUT packingand replication. It is also useful fortiming exceptions because you canapply a -thru constraint to it.

• syn_preserve. Disables sequential opti-mizations on registers, preventingremoval, merging, inverter push-through, and FSM extraction.

• syn_replicate (in the constraint file).Prevents replication of registers.

• syn_maxfan (in the constraint file).Controls the maximum fanout limit,triggering register replication andbuffering. This control is a hard limiton modules and instances but a softlimit when set globally.

• syn_direct_enable (in the constraintfile). Forces a connection to the enablepin of the register; additional logic ismoved to the D input path.

Route ConstraintThe -route constraint is probably the mostimportant but least known timing con-straint. It can provide a 10% performanceimprovement with minimal effort, as wellas drastically reduce area.

The -route constraint adds a specifieddelay to Synplify Pro’s routing estimates. Apositive value adds to the routing delayestimate and increases criticality. A negativevalue reduces the routing delay estimateand decreases criticality.

If the Synplify Pro timing estimate isdifferent from the PAR value, the differ-ence will prevent the Synplify Pro toolfrom optimizing the actual critical paths.The -route switch allows you to align syn-

thesis estimates with the PAR delays.Aligning the routing delays almost alwayscreates significantly better results.

Use the -route constraint to perform twofunctions:

• To make synthesis see the same criticalpath as PAR

• To make synthesis estimate the sameslack as PAR.

If many clocks fail PAR timing, apply -route to the clock. If there are only a fewpaths failing PAR timing, apply -route tojust those paths.

ConclusionBy setting up your design correctly andusing features and constraints described in

this article, you can meet and often surpassperformance. We found that on 50% of thedesigns, using the following settingsincreased Fmax by more than 25%:

• Add the CORE Generator EDIF files to synthesis

• Apply the -route constraint to: paths or clocks

• Turn resource sharing off

• Turn pipelining/retiming on

• Turn use clock period for unconstrained I/O off.

For additional information about theSynplify Pro synthesis tool, contactSynplicity at (408) 215-6000, or visitwww.synplicity.com.

96 Xcell Journal Summer 2004

Aligning the routing delays almost always creates significantly better results.

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by Paul [email protected]

A new wireless connectivity standard, IEEE802.15.4, defines suitable media accesscontrol (MAC) and PHY layers to enablewireless control and sensing networks forlow-data-rate applications. Opportunitiesinclude networked sensors in industrial,commercial, and health care applications,as well as low-cost toys and games.

The IEEE 802.15.4 standard combineswell with the new ZigBee™ network andapplication support layers. When thesestandards became available in 2003,designers demanded a suitable develop-ment platform almost immediately. Such aplatform had to remain flexible and have arapid design cycle.

CompXs introduced Blencathra, thefirst certified IEEE 802.15.4-compliantdevelopment system, in November 2003(Figure 1). Blencathra leverages the capaci-ty of Xilinx Virtex-II™ FPGAs to provideextensive stack monitoring and debug facil-ities within the FPGA. This helps develop-ment and compliance testing and allowsour customers to observe the operation ofthe stack in real time.

CompXs also offers a MAC/PHY mod-ule built using the low-power, low-costSpartan™-3 family. The module does notinclude the stack monitoring features ofBlencathra, but is ideal for customerswishing to deploy their applications cost-effectively. It also includes an integrated2.4 GHz radio.

Development platforms and modules based on the new ZigBee and IEEE 802.15.4 wireless standards exploit FPGAs.

Virtex-II and Spartan-3Aid Ubiquitous Wireless Control Networking

Virtex-II and Spartan-3Aid Ubiquitous Wireless Control Networking

Summer 2004 Xcell Journal 97

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Wireless Networking for Control ApplicationsZigBee defines network and applicationsupport layers for wireless networks basedon the MAC and PHY layers of IEEE802.15.4. The IEEE standard uses theglobal 2.4 GHz ISM (industrial, scientif-ic, and medical) band, as well as theAmerican 915 MHz and equivalentEuropean 868 MHz unlicensed bands.The maximum data rate in each band is250 Kbps, 40 Kbps, and 20 Kbps, respec-tively. The range is typically 30 metersbut can extend to 100 meters in optimalconditions.

The 802.15.4 physical layer usesdirect sequence spread spectrum tospread the information over a range offrequencies. For devices that transmitinfrequently, this allows for greaterpower conservation than Bluetooth’s™frequency-hopping scheme. At theMAC level, another advantage of802.15.4 is that it has only two powermodes: active or sleep. This greatly sim-plifies power management.

All devices have 64-bit IEEEaddresses, allowing virtually unlimit-ed devices in a network. This allowsfor massive sensor arrays and controlnetworks, but the option also exists toallocate 16-bit addresses to reducepacket size.

IEEE 802.15.4 is well suited for period-ic data (such as sensor outputs generated ata rate defined by the application), intermit-tent data generated externally by a switch,or repetitive low latency data allocated to aspecific time slot (such as mouse data).

The ZigBee Alliance has defined theupper layers of the protocol stack to use theIEEE 802.15.4 MAC and PHY. ZigBeeincludes the parts of the protocol from thenetwork layer to the application layer,including application profiles. The firstprofiles were published in mid-2003.

BlencathraThe Blencathra development platformallows developers to build and analyzeZigBee/802.15.4 designs quickly and at lit-tle design risk. Blencathra implements theentire 802.15.4 MAC and PHY in hardwareusing a Xilinx XC2V1500 Virtex-II FPGA.

Spartan-3 devices support low powerconsumption, low cost, and fast time tomarket – the IEEE standards were pub-lished in October 2003, and by Novemberthe development system and turnkeymodules were fully implemented usingXilinx devices.

An ASIC would likely have providedgreater power savings, but the design cycleis far longer. Choosing the FPGA routeenabled fully developed products to reachthe market very soon after the standardswere first published. Many of the details of

this standard continue to changeand evolve at this early stage.Therefore, the extra flexibility toreconfigure the hardware is valu-able both to customer developersand to CompXs.

Application DevelopmentYou can use the Blencathra devel-opment platform on its own todevelop a pure 802.15.4 wirelesscommunication channel for linksthat require no network process-ing. A wireless keyboard or mouse,for example, requires no addition-al layer to handle network taskssuch as routing. All you need is aradio block (CompXs has a suit-

able radio for development purposes), andyou can set up a representative point-to-point link on the bench. The radio has beendesigned to ease development headaches bydelivering strong performance.

For more complex applications requir-ing network processing capability, theZigBee protocols add a network layer tothe 802.15.4 system. A CompXs daughter-board plugs directly into Blencathra tofacilitate this. The board, namedBannerdale, hosts network layer processingfor a simple ZigBee-compliant network.On board is an eight-bit Flash microcon-troller with EEPROM.

Note that the microcontroller has justone timer and serial peripheral interface(SPI), and only 8K of ROM for the networkcoordinator. This can easily support the net-work layer, demonstrating that you needonly minimal microcontroller resources toimplement ZigBee. The microcontroller

Within the FPGA, CompXs’ IP imple-ments the MAC and PHY state machines,with shared MAC and PHY RAM. Timing,encryption, and modem functional blocksare also implemented in the device.

The 17,280 logic cells of theXC2V1500 FPGA provide vastly morecapacity than needed to implement the802.15.4 MAC and PHY, which aredesigned to have a very small footprint.The remainder of the device, more than75% in fact, is used to implement compli-ance verification logic.

By using the 864 KB of on-chip blockRAM, pipelining the event log to implementa high-speed port on board the FPGA is easy.Through this port, you can inspect activityall the way up and down the 802.15.4 stacksin real time. This is an extremely valuablecapability, because it shows very clearly howchanges at the ZigBee layers affect behaviorthroughout the design.

BowfellCompXs has also created Bowfell, an802.15.4 MAC/PHY module that com-bines easily with ZigBee software andincludes an integrated 2.4 GHz radio. Afterproving the design using the Blencathradevelopment system, you can use thesecost-effective modules to quickly configurenetworks with many ZigBee nodes. Asthere is no need for on-board verificationlogic, the modules are built using the low-power, low-cost Xilinx Spartan-3 FPGA.

98 Xcell Journal Summer 2004

Figure 1 – The Blencathra 802.15.4 developmentplatform with full stack tracing

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may also be able to host the application ifprocessing requirements allow.

Overall, ZigBee typically requiresbetween 4 KB and 30 KB of RAM andROM, depending on the complexity of theapplication. This compares with the 250KB required by Bluetooth, for example. SoZigBee/802.15.4 not only simplifies theprocess of embedding wireless communica-tions into products, but also makes for aconsiderably lower bill of materials in thefinal product.

Note that IEEE 802.15.4 is not dedicat-ed to ZigBee as a network layer. If the net-work processing requirements are verysimple and can be implemented quicklyusing very low memory resources, you candefine your own network layer if you prefer.

Easing the Design ChallengeOff-the-shelf ZigBee software libraries willprovide the fastest and easiest solution asthey become more widely available.Current CompXs libraries include propri-etary network layers as well as ZigBee ver-sion 0.7-compliant network andapplication support layers. These are readyto be integrated with IEEE 802.15.4 onSpartan-3 FPGA-based modules, or as partof a system-on-chip.

The network layer implemented on theBannerdale daughter board for develop-

ment purposes is also available as a link-able library to run on your target proces-sor, or as source code. In fact, CompXsoffers a complete set of development plat-forms, network modules, and tools.Available tools include an 802.15.4 plat-form stack analyzer hat that displays andlogs activity to microsecond accuracy anda passive 802.15.4/ZigBee packet snifferand analyzer (Figure 2).

The Steeple packet sniffer is based onthe IP contained within the FPGA onBlencathra. Steeple will “sniff ” all of thetransmissions on a ZigBee/802.15.4 net-

work and then display those transmis-sions in a convenient form on a PC(Figure 3). It recognizes valid and invalidtransmissions and breaks down the pack-ets of data, displaying them in an easilyunderstood manner.

You can also quickly integrate propri-etary application software with the ZigBeestacks via standard ZigBee APIs.

ConclusionWhen a new networking standard emerges,developers first look for the easiest way toget a standard-compliant network up andrunning. A reconfigurable developmentplatform is important, as well as large num-bers of low-cost modules that can imple-ment the standard-compliant elementswith a good RF stage.

In the case of IEEE 802.15.4 andZigBee, Xilinx FPGAs allowed for easy andrapid designs of suitable developmenttools. These tools will enable many newapplications to benefit from low-cost wire-less networking.

You can find more information on theproducts described here at the CompXs web-site, www.compxs.com. For details about theZigBee organization and the standards itpromotes, visit www.zigbee.org. And to learnhow 802.15.4 and ZigBee can be used inyour products, consider taking a trainingcourse. For information about introductoryand in-depth/hands-on courses, visitwww.zigbeetraining.com.

Figure 2 – The 802.15.4 packet sniffer from CompXs

Figure 3 – A screenshot from Steeple showing a ZigBee network start up

Summer 2004 Xcell Journal 99

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by Abhay MaheshwariDirector, Package EngineeringXilinx, [email protected]

Lead (Pb)-free packaging ispart of a concerted effort in theelectronics industry to elimi-nate Pb in electronic assembly.Only ~0.2% of the Pb world-wide is used for electronicassembly; most of it is used inautomotive applications. Butwhen a hazardous substanceban is implemented, all prod-ucts containing the material areequally affected.

The Pb-free movement inthe electronics industry hasaccelerated since the EuropeanUnion (EU) released a directivecalling for the removal of Pband other hazardous materialsfrom electronics by 2006 aspart of the RoHS (Restrictionof Hazardous Substances).

Maintaining performance and reliability are key challenges as the industry complies with new Pb-free regulations.

Creating Pb-Free Packaging

100 Xcell Journal Summer 2004

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The requirement for Pb-free is indus-try-wide and not exclusive to Xilinx.Although we wish to lead Pb-free imple-mentation efforts to secure advantages inwinning future designs, it is equallyimportant to align with the rest of theindustry in terms of Pb-free technical solu-tions, such as solder ball composition andlead finishes.

Xilinx has made a conscious effort toremain within industry-standard bound-aries for lead finishes and therefore leveragethe infrastructure to satisfy industry needs.However, there are some differences. As aPLD company, Xilinx is in a unique posi-tion because it has the industry’s largest diesizes; the resulting stresses in packages aremuch higher. As a result, the most commonpackage construction materials, such as dieattach and mold compound offered for Pb-free packages, required a significant over-haul to ensure the same levels ofperformance and reliability for Xilinx appli-cations.

Technical ChallengesFigure 1 shows the application of Pb-basedalloys in electronic materials. Pb in tin(Sn)Pb solder is used for electronic assem-bly. The alloy is called eutectic solder,which consists of 63% Sn and 37% Pb.This material has been very well character-ized and understood for the last 40 years,and a drop-in replacement of SnPb for sol-dering applications in electronics has notyet been found.

Typically, when the parts are placed onPCBs and sent through the board assemblyprocess, the SnPb alloy melts to form a sol-der joint. This is what is referred to as thereflow process. The alloy melts at 183°Cand the peak reflow temperature for thisalloy is restricted to 220°C.

But Pb-free replacement alloys in theelectronics industry have higher meltingtemperatures than the current SnPb eutec-tic alloy. As a result, the peak reflow tem-peratures have gone up by 25 to 40°C.This poses a significant restriction on thematerial capability of existing electronicpackages today, as they must be able towithstand temperatures of 245 to 260°C.Figure 2 illustrates this issue.

The initial focus for Pb replacementwas unclear, and mostly viewed as an envi-ronmentally friendly product introductionoffering a marketing advantage. Ourimplementation strategy today is far moreserious than it was two years ago, given theEU directive with its “hard” compliancedate of 2006.

The Xilinx plan is a global strategy ofimplementation and industry standardiza-tion. Xilinx has closely followed the activi-ties of industry consortiums MEPTEC(Microelectronics Packaging and TestEngineering Council) and NEMI(National Electronic ManufacturingInitiatives Inc.) and standards organiza-

Today’s Pb-free packages are capable ofwithstanding higher reflow temperaturesduring assembly. As a result, all packageconstruction material such as die attach,substrate, and mold compound haveimproved significantly so that they too canwithstand higher reflow temperaturerequirements.

Leader of the Pack(age)The Pb-free program at Xilinx was estab-lished in 1999 as a proactive effort toensure future leadership. Xilinx quicklyformed partnerships with customers likeSony™ and Matsushita Electric Industrialfor Pb-free beta-site implementations.

Summer 2004 Xcell Journal 101

Figure 1 – Sources of Pb in the electronics industry

Figure 2 – Pb-free implications on electronic packages

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tions such as IPC and JEDEC (JointElectron Device Engineering Council) toensure that the solutions for Pb-free areaccepted worldwide.

The primary assembly partner of choicewas Amkor™, closely followed bySiliconware Precision Industries. The firstPb-free prototypes were shipped to betacustomers for evaluation in 2001; since2002, Xilinx has shipped Pb-free productsin volume.

The extra letter “G” in current packagedesignations easily identifies Xilinx Pb-freeparts. For example, the Pb-free version of

the VQ100 standard package is VQG100.This unique identification of the productsimplifies inventory and supply chainmanagement.

Backward CompatibilityIn the electronics industry, the ideal con-version to Pb-free is a drop-in replacementof solder finishes and associated materialsin electronic packages that mimic the cur-rent SnPb finishes relative to assembly andreliability. Unfortunately, no such productexists today that allows the industry to

quickly switch over to Pb-free products.There will always be a transition period

for any major change requiring industry-wide implementation. Customers canexpect today’s standard and Pb-free prod-ucts to coexist until the date of transition.From the perspective of component sup-pliers like Xilinx, this calls for carryinginventory of both packages for all productfamilies targeted for the Pb-free market.This is a significant effort in terms of oper-ations, with a supply chain that must bemanaged skillfully until all products arePb-free.

From a user perspective, Xilinx wouldlike to ensure that all system componentsare Pb-free compatible, including all com-ponents, passives, and connectors. Thispresents a significant challenge, however,as all suppliers are clearly not ready all atonce to implement a Pb-free solution.Customers will have different timeframesfor implementation dates using the Pb-freepackage solution, and companies supply-ing parts to the industry will be forced tocarry dual inventories of packages for thesame product.

A creative solution to this problem isbackward compatibility – using Pb-freepackages directly on existing PCBs with nochanges in the assembly process or long-term reliability.

The schematic in Figure 3 illustratesthe requirements and restrictions of back-ward compatibility. Lead frame Pb-freepackages (TQ, PQ, VQ, SO, VO, and soon) are fully backward-compatible withthe proposed Pb-free solutions.

The PBGA (plastic ball grid array)packages are a different story. To date, noobvious backward-compatible solutionexists in the industry. This mandates a dualinventory of Pb-free PBGA parts until theindustry is fully converted to Pb-freeassembly solutions.

Lingering Legacy IssuesThe Pb-free lead frame solution has a matteSn finish on the leads. For the last 30 years,Sn plating has been used on terminal fin-ishes for passive components. There are afew legacy issues relating to a whisker-likestructure formation on Sn-plated leads.

When the electronics industry was in itsinfancy, bright Sn finishes were common.This bright Sn plating was shown to be sus-ceptible to whisker growth (single crystals)in appropriate temperature/time condi-tions. The whiskers would eventually growlarge enough to short out adjacent leads.

The new solution using appropriatematte Sn plating is implemented using anadvanced, well-controlled Sn-plating bathwith special additives resistant to whiskergrowth. Although no standard tests in theindustry exist for whisker growth, Xilinxhas worked very closely with industry con-sortiums and assembly partners to exhaus-tively test for whisker growth in theSn-plating offered for Pb-free lead framepackages. So far, none of the known testshave shown significant whisker growth.

Although most of the industry, includ-ing large suppliers of microprocessors andcontrollers, have made clear commitmentsto move towards this preferred industrysolution, the telecom, networking, storage,and aerospace industries are cautious aboutmatt Sn as a single alternative for Pb-free.As a result, new tests are being proposed

102 Xcell Journal Summer 2004

220 C

Current Tin/Lead System

Pb Free Component

Reflow Profile for Tin/Lead BoardTime (s)

Temp

erat

ure C

245-260 C

Pb Free System

Reflow Profile for Pb Free BoardTime (s)

Temp

erat

ure C

Figure 3 – Pb-free package backward compatibility

This is a significant effort in terms of operations, with a supply chain that must be managed skillfully

until all products are Pb-free.

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with several whisker growth mitigatingsolutions, although as yet no clear agree-ments exist among the industry players.

Pb-Free Flip-ChipsBy definition, flip-chip packages are ballgrid array packages with interconnect solu-tions based on area array solder bumps.The internal interconnection is throughsolder bumps, which are similar in compo-sition to external solder balls.

Xilinx is evaluating its flip-chip pack-ages with large die sizes, and our currentfocus is to introduce Pb-free flip-chippackages in two phases. The primary goalis to be compliant with RoHS.

The first phase for the introduction ofPb-free flip-chip packages will be based oneutectic Sn/Pb solder ball replacement withPb-free solder balls only. The current sched-ule for this implementation is by the end of2004. This will allow packages to be on cus-tomer boards until the 2006 deadline.

The second phase will ensure completecompliance with RoHS mandates by 2006.The primary focus during this stage will becompliance with the RoHS directive forthe solder bumps inside the package at thesilicon-to-substrate interconnect level.Xilinx plans to have a solution establishedat least a year before the 2006 deadline.

Industry ComplianceEuropeThe European Union RoHS legal directivecalls for the restriction of six primarymaterials from electrical and electronicproducts by 2006. These are Pb, mercury,hexavalent chromium, cadmium, and twotypes of flame retardant used in packagesabbreviated as PBB and PDE.

There are some key exemptions inRoHS that have made conversion to Pb-free very complicated from an operationsand business perspective; Figure 4 lists oneexample in which network and storageproducts are exempted. Similar exemp-tions have also been granted to high-Pb

materials and ceramic packages. Most companies in Europe are commit-

ted to implementing Pb-free solutions by theRoHS deadline. Evaluations are ongoingwith samples of Pb-free parts on test boardsto understand the manufacturing issues.

Japan Japan has clearly been the leader for Pb-freeimplementations in most consumer prod-ucts. Many companies such as Sony andNEC™ have issued mandates stating that allconsumer products in 2004 will be Pb-free.

One key challenge has been to developevery component on the board (connectors,passives, boards, and associated materials) asPb-free and capable of higher reflow tem-peratures. This elusive capability has forced

many companies to push their implementa-tion timelines back several times.Nevertheless, it has been clearly establishedthat doing business in Japan requires a Pb-free solution for electronic packages.

North America In North America, laws banning or restrict-ing the use of Pb are already in place formany products, and there is an increasingdemand for a total ban. However, theNorth American electronics industry hasbeen slower than other global regions toadopt the move to Pb-free. This pattern ischanging, however, with RoHS timelinesfor implementation set for July 2006.

Companies are scrambling to under-stand the implications of Pb-free solu-tions and have lobbied to extend thetimelines for implementation to ensurethat the robustness of the solution isproven to their satisfaction. Lobbyinghas yielded significant exemptions in RoHS, as described earlier. Manycompanies are working through industryconsortiums such as NEMI and CALCE(Computer Aided Life CycleEngineering) to understand the robust-ness of industry solutions, proposingnew tests and evaluations to address spe-cific concerns. Until these concerns areaddressed beyond a doubt, Pb-freeimplementation timelines will inevitablybe pushed back.

ConclusionXilinx has successfully introduced Pb-freepackaging solutions for wire-bonded parts,shipping in volume since 2002.

Yet current RoHS exemptions, coupledwith non-backward-compatible PBGAsolutions, pose a significant issue for thesupply chain. These exemptions and restric-tions may result in carrying dual inventoryon specific products for an extended periodof time and hence could have significantcost and logistical implications.

In the long term, it is expected that theindustry will convert to a full Pb-free imple-mentation on PCBs and convert all pack-ages to Pb-free solutions.

Summer 2004 Xcell Journal 103

RoHS Key Exemptions

■ Lead in high melting temperature type solders (i.e. tin-lead solder alloys containing more than 85% lead)

■ Lead in solder for servers, storage, and storage array systems (exemption granted until 2110)

■ Lead in solders for network infrastructure equipment for switching, signaling, transmission as well asnetwork management for telecommunication

■ Lead in electronic ceramic parts (e.g., piezoelectronic devices)

Xilinx has successfully introduced Pb-free packaging solutions forwire-bonded parts, shipping in volume since 2002.

Figure 4 – RoHS key exemptions

Page 104: Xcell Journal Issue 49

by Peter AlfkeDirector, Applications EngineeringXilinx, [email protected]

TechXclusives is an evolving series of tech-nical articles and tutorials written by expertsin Xilinx Applications. TechX articles arepublished on the Xilinx website underwww.xilinx.com/xlnx/xweb/xil_tx_home.jspand are also included in the quarterlyDataSource CD.

These short papers cover a very broadrange of subjects, from the evolution andbest selection of Xilinx FPGAs and certaindesign styles to specific systems and circuitdesign tutorials, as well as advice on subtleissues such as metastability, single-eventupsets, and PC-board signal integrity.

Below is a short description of all arti-cles published before February 2004 organ-ized by four topics: General, Tutorial,Applications, and Electrical.

General Topics

“Choices, Choices, and Opinions”This summary of FPGA and CPLD deviceshelps you select the right technology andFPGA family.

“Evolution and Revolution: RecentProgress in Field-Programmable Logic”FPGAs are now bigger, faster, and cheaper,with better software, faster compile times,

and better technical support. This articleprovides a wide-reaching overview.

“Performance + Time = Memory”You pay for silicon area. In this TechX, KenChapman suggests looking at time-sharingand sequential design as a third dimensionto reduce cost.

Tutorials

“Moving Data Across AsynchronousClock Boundaries”This article explains how to design reliableand predictable asynchronous interfaceswhen multiple unrelated clocks access com-mon data.

“Metastability Delay and Mean TimeBetween Failure in Virtex-II Pro Flip-Flops”This article analyzes the metastable behaviorof Virtex-II Pro™ flip-flops and providesquantitative data for calculating themetastable mean time between failure(MTBF).

“A Thousand Years Between Single-EventUpset (SEU) Failures”SEUs can lead to data loss in configurationlatches or user flip-flops. SEUs are caused byuncontrollable external forces, such as cos-mic rays or neutrons. This article describeshow Xilinx is running large-scale experi-ments that measure and document SEUs ina normal environment.

“IBIS Model Usage”A TechX about I/O buffer informationspecification (IBIS) files, which extractSPICE parameters and present them to users,while protecting proprietary information.

“Magic Numbers”Why do you need a 19.44 MHz clock sig-nal? This article presents the derivations ofthese and other “magic” numbers in tele-com and datacom.

“Digitally Removing a DC Offset (or‘DSP Without Math?’)”This article takes a gentle look at DSP andshows you how to optimize audio telecomfunctions using the SRL16E mode.

“Programmable Development and Test”Learn some simple ways to use the pro-grammable nature of Xilinx devices to helpin product development and even acceler-ate testing on the production line.

“Expanding Virtex-II Multipliers”Find out how to expand the natural bit-width capability of dedicated multipliers ina way that makes best use of Virtex-II™resources.

“Asynchronous FIFO in Virtex-II FPGAs”A FIFO is a popular memory structure tomove data across clock boundaries. Thisarticle provides useful information toimplement FIFOs in your design.

A frequent contributor to this section on www.xilinx.comgives a quick tour through recent articles.A frequent contributor to this section on www.xilinx.comgives a quick tour through recent articles.

TechXclusives: A Valuable Source of InformationTechXclusives: A Valuable Source of Information

104 Xcell Journal Summer 2004

Page 105: Xcell Journal Issue 49

“Does Your Design Have Enough Slack?”This article explores the factors that influ-ence propagation delay, with ways toimprove performance through simulationand better place and route.

“8 x 12 Does Not Equal 12 x 8”How to optimize multipliers implementedin Virtex and Spartan™ CLBs.

“FPGAs Driving Voice-Data Convergence”This article offers an overview of voice dataconvergence technologies, their benefits,and some of the significant challenges fac-ing system designers.

“Color Space Conversion”A discussion of color space con-version, used in broadcast-quality video systems. Itmay appear complicat-ed in theory, but it canbe reduced to a collec-tion of basic functionsthat are well-suited for implementation inXilinx FPGAs (adders,subtracters, multipliers,and delays).

Applications

“Six Easy Pieces (Non-SynchronousCircuit Tricks)”With six proven designs, learn how toimplement certain types of asynchronousfunctions, such as switch debouncer, RC-oscillator, Schmitt trigger, frequency dou-bler, and clock multiplexer.

“Creating Embedded Microcontrollers(Programmable State Machines)”This TechX series describes the design ofvery small processor macros, bringing theadvantages of a processor to a traditionaldesign environment at minimum cost.

“Multiplexer Selection”This article describes several ways to imple-ment multiplexers in Xilinx FPGAs, fromthe straightforward method to alternativetechniques using fewer device resources orachieving higher speed.

“Printed Circuit Board Considerations”A discussion of PC board issues that appliesto all modern systems with fast current andvoltage transitions: VCC and ground planes,VCC decoupling, and transmission linereflections and terminations.

“Printed Circuit Board Modeling Issues”Printed circuit board design has become animportant part of a successful product. Thisarticle describes ways to avoid the pitfalls ofthe “build it and see if it works” method.

“It’s Not Your Father’s PCB Anymore”A discussion of signal integrity design, nowmore necessary than ever if you want tosave time and money and get things towork reliably.

“Those Tiny Little Vias Can Cause BadGround Bounce Problems”This TechX shows how vias between PCboard layers have become an insidious con-tributor to the problems caused by excessiveground bounce from simultaneouslyswitching outputs (SSOs).

“What are Virtex and Spartan-II I/O Pins Doing?”A detailed explanation about how I/O pinsbehave during power up, before and dur-ing configuration, and during normaloperation.

“Jitter”A discussion of the causes, measurement,and management of jitter.

“Power To The People – Not the FPGA!”This article explains how excessive power-on current has finally been designed away,beginning with Virtex-II devices.

“The Old 35 pF Just Disappeared”This TechX reflects on the traditional 35 pFlumped capacitive load, a meaningless andmisleading model of today’s outputs, whichare now so fast that the load acts as a trans-mission line instead of a lumped capacitance.

ConclusionYou can find these and other TechXclusives atwww.xilinx.com/xlnx/xweb/xil_tx_home.jsp.

“Using Leftover Multipliers and BlockRAM in Your Design”How to use free multipliers as shifters andunused block RAMs as state machines,sine-cosine look-up tables, or 20-bitcounters.

“Get Smart About Reset (Think Local,Not Global)”Applying a global reset to your FPGAdesigns is not always a very good idea.This article discusses this highly contro-versial issue.

“Saving Costs with the SRL16E”The SRL16E shift register is available in

every look-up table in every CLB. ThisTechX explains how using this

exciting mode can lead tosignificant cost savings.

“Timing Closure”This article describesa proven methodolo-gy for timing closurein high-speed/high-

density applications tomeet given performance

objectives.

“Relationally Placed Macros”By placing logic blocks relative to eachother, RLOC constraints allow you toincrease speed and use die resources effi-ciently. This article explains the stepsinvolved.

“Reconfiguring Block RAMs”This TechX explores the use of the JTAGport to interrogate and update the contentsof block RAMs and registers while a designis running.

Electrical Issues

“Signal Integrity Tips and Tricks”Controlling crosstalk, ground bounce,ringing, noise margins, impedance match-ing, and decoupling is now critical to a suc-cessful design. This article covers thevarious techniques and design issues toensure that signals are undistorted and donot cause problems.

Summer 2004 Xcell Journal 105

Page 106: Xcell Journal Issue 49
Page 107: Xcell Journal Issue 49
Page 108: Xcell Journal Issue 49

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Page 109: Xcell Journal Issue 49

Xil

inx V

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FPG

As

htt

p:/

/ww

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ilin

x.c

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/de

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Summer 2004 Xcell Journal 109

System Gates (see note 1)

Virtex-II Series EasyPath Solutions (see note 4)

CLB Array (Row x Col)

XC2V

P2*

16 x

22

Number of Slices

1,40

8

Logic Cells (see note 2)

3,16

8

CLB Flip-Flops

2816

Max. Distributed RAM Bits (kbits)

44

# 18 kbits Block RAM

12

Total Block RAM (kbits)

216

# 18x18 Dedicated Multipliers

12

CLB

Reso

urce

sM

emor

y Re

sour

ces

DSP

I/O F

eatu

res

Spee

d

DCM Frequency (min/max)

24/4

20

# DCM Blocks (see note 3)

4

Digitally Controlled Impedance

YES

Maximum Differential I/O Pairs

100

Maximum I/O

204

I/O Standards

LDT-

25, L

VDS-

25, L

VDSE

XT-2

5,

BLVD

S-25

, ULV

DS-2

5, L

VPEC

L-25

, LV

CMO

S25,

LVC

MO

S18,

LV

CMO

S15,

PCI

33, L

VTTL

, LV

CMO

S33,

PCI

-X, P

CI66

, GTL

, G

TL+

, HST

L I (

1.5V

,1.8

V),

HSTL

II (1

.5V,

1.8V

), HS

TL II

I (1.

5V,1

.8V)

, HS

TL IV

(1.5

V,1.

8V),

SSTL

2I,

SSTL

2II,

SSTL

18 I,

SST

L18

II

LDT-

25, L

VPEC

L-33

, LV

DS-3

3, L

VDS-

25,

LVDS

EXT-

33, L

VDSE

XT-2

5,

BLVD

S-25

, ULV

DS-2

5,

LVTT

L, L

VCM

OS3

3,

LVCM

OS2

5, L

VCM

OS1

8,

LVCM

OS1

5, P

CI33

, PCI

66,

PCI-X

, GTL

, GTL

+, H

STL

I, HS

TL II

, HST

L III

, HST

L IV

, SS

TL2I

, SST

L2II,

SST

L3 I,

SS

TL3

II, A

GP,

AGP-

2X

Commercial Speed Grades(slowest to fastest)

-5 -6

-7

Industrial Speed Grades(slowest to fastest)

-5 -6

*XC

2VP4

40

x 2

2 3,

008

6,76

86,

016

9428

504

28

24/4

204

YES

172

348

-5 -6

-7-5

-6

Cloc

k Re

sour

ces

XC2V

P7

*40

x 3

4 4,

928

11,0

889,

856

154

4479

244

24/4

204

YES

196

396

-5 -6

-7-5

-6

XC2V

P20

*56

x 4

69,

280

20,8

8018

,560

290

881,

584

8824

/420

8YE

S27

656

4-5

-6 -7

-5 -6

XC2V

P30

*80

x 4

613

,696

30,8

1627

,392

428

136

2448

136

24/4

208

YES

372

644

-5 -6

-7-5

-6

XC2V

P40

*88

x 5

819

,392

43,6

3238

,784

606

192

3,45

619

224

/420

8YE

S39

680

4-5

-6 -7

-5 -6

XC2V

P50

*88

x 7

023

,616

53,1

3647

,232

738

232

4,17

623

224

/420

8YE

S42

085

2-5

-6 -7

-5 -6

XC2V

P70

*10

4 x

8233

,088

74,4

4866

,176

1,03

432

85,

904

328

24/4

208

YES

492

996

-5 -6

-7-5

-6

XC2V

P100

*12

0 x

9444

,096

99,2

1688

,192

1,37

844

47,

992

444

24/4

2012

YES

572

1,16

4-5

-6 -7

-5 -6

XC2V

P125

*13

6 x

106

55,6

1612

5,13

611

1,23

21,

738

556

10,0

0855

624

/420

12YE

S64

41,

200

-5 -6

-7-5

-6

XC2V

4040

K8

x 8

256

576

512

84

724

24/4

204

YES

4488

-4 -5

-6-4

-5

XC2V

8080

K16

x 8

512

1,15

21,

024

168

144

824

/420

4YE

S60

120

-4 -5

-6-4

-5

XC2V

250

250K

24 x

16

1,53

63,

456

3,07

248

2443

224

24/4

208

YES

100

200

-4 -5

-6-4

-5

XC2V

500

500K

32 x

24

3,07

26,

912

6,14

496

3257

632

24/4

208

YES

132

264

-4 -5

-6-4

-5

XC2V

1000

1M40

x 3

25,

120

11,5

2010

,240

160

4072

040

24/4

208

YES

216

432

-4 -5

-6-4

-5

XC2V

1500

1.5M

48 x

40

7,68

017

,280

15,3

6024

048

864

4824

/420

8YE

S26

452

8-4

-5 -6

-4 -5

XC2V

2000

2M56

x 4

810

,752

24,1

9221

,504

336

561,

008

5624

/420

8YE

S31

262

4-4

-5 -6

-4 -5

XC2V

3000

3M64

x 5

614

,336

32,2

5628

,672

448

961,

728

9624

/420

12YE

S36

072

0-4

-5 -6

-4 -5

XC2V

4000

4M80

x 7

223

,040

51,8

4046

,080

720

120

2,16

012

024

/420

12YE

S45

691

2-4

-5 -6

-4 -5

XC2V

6000

6M96

x 8

833

,792

76,0

3267

,584

1,05

614

42,

592

144

24/4

2012

YES

552

1,10

4-4

-5 -6

-4 -5

XC2V

8000

XCE2

VP30

XCE2

VP40

XCE2

VP50

XCE2

VP70

XCE2

VP10

0

XCE2

VP12

5

XCE2

V300

0

XCE2

V400

0

XCE2

V600

0

XCE2

V800

08M

112

x 10

446

,592

104,

832

93,1

841,

456

168

3,02

416

824

/420

12YE

S55

41,

108

-4 -5

-4 -5

Configuration Memory (Bits)

1.3M

RocketIO™

Transceiver Blocks(3.125 Gbps)

4

RocketIO™

X Transceiver Blocks (10.3125 Gbps)

3.0M

4

4.4M

8

8.2M

8

11.3

M8

15.5

M0

or 1

2

19.0

M0

or 1

6

25.6

M16

or 2

0

33.5

M0

or 2

0

42.7

M0,

20

or 2

4

XC2V

PX20

*56

x 4

69,

792

22,0

3219

,584

306

8815

8488

24/4

208

YES

276

556

Sam

e as

abo

ve

-5 -6

-7TB

D8.

05M

08

0.4M

––

0.6M

––

1.7M

––

2.8M

––

4.1M

––

5.7M

––

7.5M

––

10.5

M–

15.7

M–

21.9

M–

29.1

M–

PowerPC™ Processor Blocks

0 1 1 2 2 2 2 2 2 4 1 – – – – – – – – – – –

EasyPath

– – – – – – – – – – –

Platform FPGAs

* Lo

gic

cell

coun

ts a

re a

mor

e m

eani

ngfu

l mea

sure

men

t of d

ensi

ty fo

r the

Virt

ex-II

Pro

fam

ily s

ince

sys

tem

gat

e co

unt d

oes

not t

ake

into

con

side

ratio

n th

e be

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the

imm

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cks

such

as

Pow

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pro

cess

ors

and

mul

ti-gi

gabi

t tra

nsce

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s. 1.

Sy

stem

Gat

es in

clud

e 20

-30%

of C

LBs

used

as

RAM

2.

Log

ic c

ell =

One

4-In

put L

ook

Up

Tabl

e (L

UT)

+ F

lip F

lop

+ C

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Log

ic.

3.

DCM

= D

igita

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ck M

anag

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a n

o ris

k, n

o ef

fort

cos

t red

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n pa

th fo

r vol

ume

prod

uctio

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:

Virt

ex-II

Pro

Fam

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1.5

Vol

t

Virt

ex-II

Fam

ily –

1.5

Vol

t

Virt

ex-II

Pro

X F

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– 1

.5 V

olt

XC2V

PX70

*10

4 x

8233

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74,4

4866

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308

5544

308

24/4

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YES

492

996

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25.6

0M0

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Impo

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ith

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at

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arti

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data

book

.htm

Page 110: Xcell Journal Issue 49

Xil

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110 Xcell Journal Summer 2004

XC2VP2

204

XC2VP4

348

XC2VP7

396

XC2VP20

564

XC2VP30

692

XC2VP40

804

XC2VP50

852

XC2VP7099

6

XC2VP100

1164

XC2VP125

1200

Virt

ex-II

Pro

(1.5

V)

XC2V40

88

XC2V80

120

XC2V250

200

XC2V500

264

XC2V1000

432

XC2V1500

528

XC2V2000

624

XC2V3000

720

XC2V4000

912

XC2V6000

1104

XC2V8000

1296

Virt

ex-II

(1.5

V)Vi

rtex

-II P

ro X

(1.5

V)

Pins

3A

rea

8892

9214

412

x 1

2 m

m

328

392

408

575

31 x

31

mm

516

728

35 x

35

mm

140

140

8812

017

217

217

225

617

x 1

7 m

m

156

248

248

200

264

324

456

423

x 2

3 m

m

404

416

416

392

456

484

676

427

x 2

7 m

m

204

348

396

672

27 x

27

mm

396

556

556

432

528

624

896

531

x 3

1 m

m

564

564

692

692

720

824

824

824

1152

535

x 3

5 m

m

804

812

1148

635

x 3

5 m

m

852

964

912

1104

1108

1517

40 x

40

mm

996

1040

1040

1704

42.5

x 4

2.5

mm

1164

1200

1696

642

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42.

5 m

m

XC2VPX20

556

556

624

684

684

684

957

Not

es:

1. N

umbe

rs in

tabl

e in

dica

te m

axim

um n

umbe

r of u

ser I

/Os.

2. T

he n

umbe

r of I

/Os

for R

ocke

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GTs

are

not

incl

uded

in th

is ta

ble.

3. W

ithin

the

sam

e fa

mily

, all

devi

ces

in a

par

ticul

ar p

acka

ge a

re p

in-o

ut (f

ootp

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com

patib

le.

4. V

irtex

-II p

acka

ges

FG45

6 an

d FG

676

are

also

foot

prin

t com

patib

le.

5. V

irtex

-II p

acka

ges

FF89

6 an

d FF

1152

are

als

o fo

otpr

int c

ompa

tible

.6.

Roc

ketIO

una

vaila

ble

in th

is p

acka

ge.

40 x

40

mm

XC2VPX70

996

996

Chip

Sca

le P

acka

ges

(CS)

– w

ire-

bond

chi

p-sc

ale

BGA

(0.8

mm

bal

l spa

cing

)

BGA

Pac

kage

s (B

G) –

wir

e-bo

nd s

tand

ard

BGA

(1.2

7 m

m b

all s

paci

ng)

FGA

Pac

kage

s (F

G) –

wir

e-bo

nd fi

ne-p

itch

BG

A (1

.0 m

m b

all s

paci

ng)

FFA

Pac

kage

s (F

F) –

flip

-chi

p fin

e-pi

tch

BGA

(1.0

mm

bal

l spa

cing

)

BFA

Pac

kage

s (B

F) –

flip

-chi

p fin

e-pi

tch

BGA

(1.2

7 m

m b

all s

paci

ng)

Pb-fr

ee s

olut

ions

are

ava

ilabl

e fo

r all

pack

ages

. For

mor

e in

form

atio

n co

ntac

t you

r Xili

nx s

ales

repr

esen

tativ

e or

vis

it w

ww

.xili

nx.c

om/p

bfre

e.

Impo

rtan

t:Ve

rify

all

data

in t

his

docu

men

t w

ith

the

devi

ce d

ata

shee

ts f

ound

at

http

://w

ww

.xili

nx.c

om/p

arti

nfo/

data

book

.htm

XC2VP2

XC2VP4

XC2VP7

XC2VP20

XC2VP30

XC2VP40

XC2VP50

XC2VP70

XC2VP100

XC2VP125

Pack

age

Rock

etIO

(3.1

25G

bps)

Rock

etIO

X

(10G

bps)

Tran

scei

ver

Bloc

ks

4FG

256

4

4FG

456

48

FG67

68

88

4FG

672

48

FF89

68

88

FF11

528

812

16

FF11

486

00

FF15

1716

16

FF17

0420

2024

FF16

966

00

XC2VPX20

8

XC2VPX70

20

XGC1

120

- Ult

ra M

SA

Dev

ice

Rock

etPH

Y Fa

mily

of 1

0Gbp

s Ph

ysic

al L

ayer

Tra

nsce

iver

s

For m

ore

info

rmat

ion

abou

t the

Roc

ketP

HY fa

mily

, vis

it w

ww

.xili

nx.c

om/ro

cket

phy

SONET OC-192SDH STM - 64

G . 709

10G ETHERNET

XGC1

121

- 10G

SO

NET

/SD

H√

XFP

Tran

scei

vers

,SO

NET

/SDH

– b

ased

tr

ansm

issi

on s

yste

ms,

fiber

opt

ic te

st

equi

pmen

t

10G FIBRE CHANNEL

MSA

Mod

ules

XFP

Tran

scei

vers

,SO

NET

/SDH

tr

ansm

issi

on s

yste

ms,

OTN

sys

tem

w/F

EC,

fiber

opt

ic te

st

equi

pmen

t

Applications

XSBI

SFI-4

SFI-4

XGC1

320

- 10G

E/10

GFC

√√

XSBIParallel Interface

FT25

6

FT25

6

FT25

6

Package

XFP

Tran

scei

vers

,da

ta tr

ansm

issi

on

equi

pmen

t, N

ICs,

test

equ

ipm

ent,

edge

rout

ers,

stor

age

area

net

wor

ks

Xil

inx V

irte

x-I

I Seri

es

FPG

As

an

d R

ock

etP

HY

Ph

ysi

cal

Layer

Tran

sceiv

ers

Page 111: Xcell Journal Issue 49

Xil

inx S

part

an

™Seri

es

FPG

As

htt

p:/

/ww

w.x

ilin

x.c

om

/de

vic

es/

Summer 2004 Xcell Journal 111

Pro

du

ct S

ele

ctio

n M

atr

ix

CLB

Reso

urce

sM

emor

y Re

sour

ces

CLK

Reso

urce

sD

SPI/O

Fea

ture

sSp

eed

PRO

M

System Gates (see note 1)

CLB Array (Row x Col)

XC3S

5050

K16

x 1

2

Number of Slices

768

Logic Cells (see note 2 )1,

728

CLB Flip-Flops

1,53

6

Max. Distributed RAM Bits

12K

# Block RAM

4

Block RAM (bits)

72K

Dedicated Multipliers

4

DCM Frequency (min/max)

25/3

26

# DCMs

2

Frequency Synthesis

YES

Phase Shift

YES

Digitally Controlled Impedance

Number of Differential I/O Pairs

Maximum I/O

I/O Standards

Commercial Speed Grades(slowest to fastest)

YES

5612

4Si

ngle

-end

edLV

TTL,

LVC

MO

S3.3

/2.5

/1.8

/1.

5/1.

2, P

CI 3

.3V

– 32

/64-

bit

33M

Hz, S

STL2

Cla

ss I

& II

, SS

TL18

Cla

ss I,

HST

L Cl

ass

I, III

, HST

L1.8

Cla

ss I,

II &

III,

GTL

, GTL

+

Diffe

rent

ial

LVDS

2.5,

Bus

LVD

S2.5

,U

ltra

LVDS

2.5,

LVD

S_ex

t2.5

,RS

DS, L

DT2.

5, L

VPEC

L

-4 -5

Industrial Speed Grades(slowest to fastest)

-4

Configuration Memory (Bits)

.4M

XC3S

200

200K

24

x 2

01,

920

4,32

03,

840

30K

1221

6K12

25/3

264

YES

YES

YES

7617

3-4

-5-4

1.0M

XC3S

400

400K

32

x 2

83,

584

8,06

47,

168

56K

1628

8K16

25/3

264

YES

YES

YES

116

264

-4 -5

-41.

7M

XC3S

1000

10

00K

48 x

40

7,68

017

,280

15,3

6012

0K24

432K

2425

/326

4YE

SYE

SYE

S17

539

1-4

-5-4

3.2M

XC3S

1500

15

00K

64 x

52

13,3

1229

,952

26,6

2420

8K32

576K

3225

/326

4YE

SYE

SYE

S22

148

7-4

-5-4

5.2M

XC3S

2000

20

00K

80 x

64

20,4

8046

,080

40,9

6032

0K40

720K

4025

/326

4YE

SYE

SYE

S27

056

5-4

-5-4

7.7M

XC3S

4000

40

00K

96 x

72

27,6

4862

,208

55,2

9643

2K96

1,72

8K96

25/3

264

YES

YES

YES

312

712

-4 -5

-411

.3M

XC3S

5000

50

00K

104

x 80

33,2

8074

,880

66,5

6052

0K10

41,

872K

104

25/3

264

YES

YES

YES

344

784

-4 -5

-413

.3M

Not

e:

1. S

yste

m G

ates

incl

ude

20-3

0% o

f CLB

s us

ed a

s RA

Ms

2.

For

Spa

rtan

-3, a

Log

ic C

ell i

s de

fined

as

a 4-

inpu

t LU

T +

flip

-flop

3. A

utom

otiv

e Q

-Gra

de S

olut

ions

for S

part

an-3

will

be

avai

labl

e 2H

2004

.

Spar

tan-

3 Fa

mily

– 1

.2 V

olt

(see

not

e 3)

Impo

rtan

t:Ve

rify

all

data

in t

his

docu

men

t w

ith

the

devi

ce d

ata

shee

ts f

ound

at

http

://w

ww

.xili

nx.c

om/p

arti

nfo/

data

book

.htm

Page 112: Xcell Journal Issue 49

Xil

inx S

part

an

™Seri

es

FPG

As

htt

p:/

/ww

w.x

ilin

x.c

om

/de

vic

es/

112 Xcell Journal Summer 2004

CLB

Reso

urce

sM

emor

y Re

sour

ces

CLK

Reso

urce

sI/O

Fea

ture

sSp

eed

System Gates (see note 1)

CLB Array (Row x Col)

XC2S

50E

50K

16 x

24

Number of Slices

768

Logic Cells (see notes 2 and 3)

1,72

8

CLB Flip-Flops

1,53

6

Max. Distributed RAM Bits

24K

# Block RAM

8

Block RAM (bits)

32K

DLL Frequency (min/max)

25/3

20

# DLLs

4

Frequency Synthesis

YES

Phase Shift

YES

Number of Differential I/O Pairs

Maximum I/O

I/O Standards

Commercial Speed Grades(slowest to fastest)

8318

2LV

TTL,

LVCM

OS2

, LV

CMO

S18,

PCI

33, P

CI66

, G

TL, G

TL+

, HST

L I,

HSTL

III,

HSTL

IV, S

STL3

I, S

STL3

II,

SSTL

2 I,

SSTL

2 II,

AG

P-2X

, CT

T, LV

DS, B

LVDS

, LVP

ECL

LVTT

L, L

VCM

OS2

,PC

I33

(3.3

V &

5V)

,PC

I66

(3.3

V), G

TL, G

TL+

,

HS

TL I,

HST

L III

, HST

L IV

,

SS

TL3

I, SS

TL3

II, S

STL2

I,

SSTL

2 II,

AG

P-2X

, CTT

-6 -7

Industrial Speed Grade(slowest to fastest)

-6

Configuration Memory (Bits)

0.6M

XC2S

100E

100K

20 x

30

1,20

02,

700

2,40

037

K10

40K

25/3

204

YES

YES

8620

2-6

-7-6

0.9M

XC2S

150E

150K

24 x

36

1,72

83,

888

3,45

654

K12

48K

25/3

204

YES

YES

114

265

-6 -7

-61.

1M

XC2S

200E

200K

28 x

42

2,35

25,

292

4,70

473

K14

56K

25/3

204

YES

YES

120

289

-6 -7

-61.

4M

XC2S

300E

300K

32 x

48

3,07

26,

912

6,14

496

K16

64K

25/3

204

YES

YES

120

329

-6 -7

-61.

9M

XC2S

400E

400K

40 x

60

4,80

010

,800

9,60

015

0K40

160K

25/3

204

YES

YES

172

410

-6 -7

-62.

7M

XC2S

600E

600K

48 x

72

6,91

215

,552

13,8

2421

6K72

288K

25/3

204

YES

YES

205

514

-6 -7

-64.

0M

XC2S

1515

K8

x 12

192

432

384

6K4

16K

25/2

004

YES

YES

NA

86-5

-6-5

0.2M

XC2S

3030

K12

x 1

843

297

286

413

.5K

624

K25

/200

4YE

SYE

SN

A13

2-5

-6-5

0.4M

XC2S

5050

K16

x 2

476

81,

728

1,53

624

K8

32K

25/2

004

YES

YES

NA

176

-5 -6

-50.

6M

XC2S

100

100K

20 x

30

1,20

02,

700

2,40

037

.5K

1040

K25

/200

4YE

SYE

SN

A19

6-5

-6-5

0.8M

XC2S

150

150K

24 x

36

1,72

83,

888

3,45

654

K12

48K

25/2

004

YES

YES

NA

260

-5 -6

-51.

1M

XC2S

200

200K

28 x

42

2,35

25,

292

4,70

473

.5K

1456

K25

/200

4YE

SYE

SN

A28

4-5

-6-5

1.4M

XCS0

5XL

5K10

x 1

010

023

820

03.

1KN

AN

AN

AN

AN

AN

AN

A77

-4 -5

-40.

05M

XCS1

0XL

10K

14 x

14

196

466

392

6.1K

NA

NA

NA

NA

NA

NA

NA

112

-4 -5

-40.

09M

XCS2

0XL

20K

20 x

20

400

950

800

12.5

KN

AN

AN

AN

AN

AN

AN

A16

0-4

-5-4

0.18

M

XCS3

0XL

30K

24 x

24

576

1,36

81,

152

18.0

KN

AN

AN

AN

AN

AN

AN

A19

2-4

-5-4

0.25

M

XCS4

0XL

40K

28 x

28

784

1,86

21,

568

24.5

KN

AN

AN

AN

AN

AN

AN

A22

4-4

-5-4

Automotive Q-Grade Speed Grade

-6 -6 -6 -6 -6 -6 -6 -5 -5 -5 -5 -5 -5 -4 -4 -4 -4 -40.

33M

Automotive Q-Grade Solutions(see note 4)

✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔

Not

e:

1. S

yste

m G

ates

incl

ude

20-3

0% o

f CLB

s us

ed a

s RA

M

2. L

ogic

cel

l = (1

) 4 In

put (

LUT)

and

a re

gist

er

3. F

or S

part

an-II

E/II/

XL, a

Log

ic C

ell i

s de

fined

as

a 4-

inpu

t LU

T +

a re

gist

er4.

Aut

omot

ive

Q-G

rade

Sol

utio

ns a

re q

ualif

ied

to -4

0ºC

to +

125º

C ju

nctio

n te

mpe

ratu

re fo

r FPG

As. Q

-Gra

de p

rodu

cts

for S

part

an-3

will

be

avai

labl

e 2H

2004

Spar

tan-

II Fa

mily

– 2

.5 V

olt

Spar

tan-

XL F

amily

– 3

.3 V

olt

Spar

tan-

IIE F

amily

– 1

.8 V

olt

Pro

du

ct S

ele

ctio

n

Matr

ix

Impo

rtan

t:Ve

rify

all

data

in t

his

docu

men

t w

ith

the

devi

ce d

ata

shee

ts f

ound

at

http

://w

ww

.xili

nx.c

om/p

arti

nfo/

data

book

.htm

Page 113: Xcell Journal Issue 49

Xil

inx S

part

an

™Seri

es

FPG

As

htt

p:/

/ww

w.x

ilin

x.c

om

/de

vic

es/

Summer 2004 Xcell Journal 113

Not

e 1:

Num

bers

in ta

ble

indi

cate

max

imum

num

ber o

f use

r I/O

sN

ote

2: A

rea

dim

ensi

ons

for l

ead-

fram

e pr

oduc

ts a

re in

clus

ive

of th

e le

ads.

Pb-fr

ee p

acka

ging

ava

ilabl

e fo

r all

devi

ces.

For m

ore

info

rmat

ion

visi

t ww

w.x

ilinx

.com

/pbf

reeAu

tom

otiv

e pr

oduc

ts a

re h

ighl

ight

ed: -

40C

to +

125C

junc

tion

tem

pera

ture

for F

PGAs

.Au

tom

otiv

e Q

-Gra

de p

rodu

cts

will

be

avai

labl

e in

Spa

rtan

-3 fa

mily

2H2

004.

For m

ore

info

rmat

ion

on IQ

Sol

utio

ns p

leas

e vi

sit h

ttp:

//ww

w.x

ilinx

.com

/aut

omot

ive

XC2S50E

XC2S100E

XC2S150E

XC2S200E

XC2S300E

XC2S400E

XC2S600E

I/Os

182

202

265

289

329

410

514

XC2S15

XC2S30

XC2S50

XC2S100

XC2S150

XC2S200

8613

217

619

626

028

4

XCS05XL

XCS10XL

XCS20XL

XCS30XL

XCS40XL

7711

216

019

222

4

6161

192

192

6077

77

112

8692

112

113

192

224

176

202

265

289

196

260

410

514

192

182

146

146

146

146

146

140

140

140

140

160

169

169

6077

77

102

102

8692

9292

113

113

182

182

182

182

182

176

176

176

329

329

329

284

205

Spar

tan-

IIE (1

.8V)

Spar

tan-

II (2

.5V)

Spar

tan-

XL (3

.3V)

XC3S50

XC3S200

XC3S400

XC3S1000

XC3S1500

XC3S2000

XC3S4000

Are

a2

30.2

x 3

0.2

mm

Pins

84

I/Os

124

173

264

391

487

565

712

784

30.6

x 3

0.6

mm

208

34.6

x 3

4.6

mm

240

16.0

x 1

6.0

mm

100

6363

22.0

x 2

2.0

mm

144

97

12 x

12

mm

144

16 x

16

mm

280

17 x

17

mm

256

17 x

17

mm

256

23 x

23

mm

456

264

333

27 x

27

mm

676

391

487

489

27 x

27

mm

256

124

141

141

9797 17

317

317

3

333

XC3S5000

23 x

23

mm

320

221

221

221

PQFP

Pac

kage

s (P

Q) –

wir

e-bo

nd p

last

ic Q

FP (0

.5m

m le

ad s

paci

ng)

PLCC

Pac

kage

s (P

C) –

wir

e-bo

nd p

last

ic c

hip

carr

ier

(1.2

7mm

lead

spa

cing

)

Spar

tan-

3 (1

.2V)

VQFP

Pac

kage

s (V

Q) –

ver

y th

in T

QFP

(0.5

mm

lead

spa

cing

)

TQFP

Pac

kage

s (T

Q) –

thi

n Q

FP (0

.5m

m le

ad s

paci

ng)

Chip

Sca

le P

acka

ges

(CS)

– w

ire-

bond

chi

p-sc

ale

BGA

(0.8

mm

bal

l spa

cing

)

FGA

Pac

kage

s (F

T) –

wir

e-bo

nd fi

ne-p

itch

thi

n BG

A (1

.0 m

m b

all s

paci

ng)

FGA

Pac

kage

s (F

G) –

wir

e-bo

nd fi

ne-p

itch

BG

A (1

.0 m

m b

all s

paci

ng)

BGA

Pac

kage

s (B

G) –

wir

e-bo

nd s

tand

ard

BGA

(1.2

7 m

m b

all s

paci

ng)

31 x

31

mm

900

565

633

633

35 x

35

mm

1156

712

784

132

Pack

ag

e O

pti

on

s an

d U

ser

I/O

1

Impo

rtan

t:Ve

rify

all

data

in t

his

docu

men

t w

ith

the

devi

ce d

ata

shee

ts f

ound

at

http

://w

ww

.xili

nx.c

om/p

arti

nfo/

data

book

.htm

Page 114: Xcell Journal Issue 49

Xil

inx C

PLD

htt

p:/

/ww

w.x

ilin

x.c

om

/de

vic

es

114 Xcell Journal Summer 2004

XCR3

032X

L75

032

XCR3

064X

L15

0064

XCR3

128X

L30

0012

8

XCR3

256X

L60

0025

6

XCR3

384X

L90

0038

4

XCR3

512X

L12

000

512

48 48 48 48 48

365

-5 -7

-10

-7 -1

04

16

686

-6 -7

-10

-7 -1

04

16

108

6-6

-7 -1

0 -7

-10

416

164

7.5

-7 -1

0 -1

2-1

0 -1

24

16

220

7.5

-7 -1

0 -1

2-1

0 -1

24

16

3.3/

5

3.3/

5

3.3/

5

3.3/

5

3.3/

5

3.3/

5

3.3

3.3

3.3

3.3

3.3

3.3

260

7.5

-7 -1

0 -1

2-1

0 -1

24

16

XC2C

3275

032

XC2C

6415

0064

XC2C

128

3000

128

XC2C

256

6000

256

XC2C

384

9000

384

XC2C

512

1200

051

2

40 40 40 40 40 40

System Gates

Macrocells

Product Terms per Macrocell

1.5/

1.8/

2.5/

3.3

Input Voltage Compatible

1.5/

1.8/

2.5/

3.3

33Output Voltage Compatible

Maximum I/O

13

I/O Banking

Min. Pin-to-pin Logic Delay (ns)

-3 -4

-6-6

Commercial Speed Grades(fastest to slowest)

Industrial Speed Grades(fastest to slowest)

3Global Clocks

17

1.5/

1.8/

2.5/

3.3

1.5/

1.8/

2.5/

3.3

641

4-4

-5 -7

-73

17

1.5/

1.8/

2.5/

3.3

1.5/

1.8/

2.5/

3.3

100

24.

5-4

-6 -7

-73

17

1.5/

1.8/

2.5/

3.3

1.5/

1.8/

2.5/

3.3

184

25

-5 -6

-7-7

317

1.5/

1.8/

2.5/

3.3

1.5/

1.8/

2.5/

3.3

240

46

-6 -7

-10

-10

317

1.5/

1.8/

2.5/

3.3

1.5/

1.8/

2.5/

3.3

270

46

-6 -7

-10

-10

317Product Term Clocks per

Function Block

Cool

Runn

er-II

Fam

ily –

1.8

Vol

t

Cool

Runn

er X

PLA

3 Fa

mily

– 3

.3 V

olt

-10

-10

-10

-12

-12

-12-6

IQ Speed Grade

-7 -7 -7 -10

-10

I/OFe

atur

esSp

eed

Cloc

king

48

Pro

du

ct S

ele

ctio

n M

atr

ix –

Co

olR

un

ner™

Seri

es

Pack

ag

e O

pti

on

s an

d U

ser

I/O

* JT

AG p

ins

and

port

ena

ble

are

not p

in c

ompa

tible

in th

is p

acka

ge fo

r thi

s m

embe

r of t

he fa

mily

Not

e 1:

Are

a di

men

sion

s fo

r lea

d-fra

me

prod

ucts

are

incl

usiv

e of

the

lead

s.

Auto

mot

ive

prod

ucts

are

hig

hlig

hted

: -40

C to

+12

5C a

mbi

ent t

empe

ratu

re fo

r CPL

Ds

XC2C512

XCR3032XL

XCR3064XL

XCR3128XL

XCR3256XL

XCR3384XL

3636

XCR3512XL

Are

a1Pi

ns

17.5

x 1

7.5

mm

44

XC2C32

XC2C64

XC2C128

XC2C256

XC2C384

XC2C512

30.6

x 3

0.6

mm

208

12.0

x 1

2.0

mm

44

3333

16.0

x 1

6.0

mm

100

118*

22.0

x 2

2.0

mm

144

486

x 6

mm

5633

45

8 x

8 m

m13

210

010

6

4036

7 x

7 m

m48

108

12 x

12

mm

144

164

16 x

16

mm

280

212

164

212

17 x

17

mm

256

184

212

212

260

220

23 x

23

mm

324

240

270

173

173

173

180

164

172

3333

3636

6884

6480

80

108

120

100

118

118

PQFP

Pac

kage

s (P

Q) –

wir

e-bo

nd p

last

ic Q

FP (0

.5m

m le

ad s

paci

ng)

VQFP

Pac

kage

s (V

Q) –

ver

y th

in T

QFP

(0.5

mm

lead

spa

cing

)

TQFP

Pac

kage

s (T

Q) –

thi

n Q

FP (0

.5m

m le

ad s

paci

ng)

FGA

Pac

kage

s (F

T) –

wir

e-bo

nd fi

ne-p

itch

thi

n BG

A (1

.0 m

m b

all s

paci

ng)

FBG

A P

acka

ges

(FG

) – w

ire-

bond

Fin

e-lin

e BG

A (1

.0 m

m b

all s

paci

ng)

Chip

Sca

le P

acka

ges

(CS)

– w

ire-

bond

chi

p-sc

ale

BGA

(0.8

mm

bal

l spa

cing

)

Chip

Sca

le P

acka

ges

(CP)

– w

ire-

bond

chi

p-sc

ale

BGA

(0.5

mm

bal

l spa

cing

)

Cool

Runn

er X

PLA

3Co

olRu

nner

-II

PLCC

Pac

kage

s (P

C) –

wir

e-bo

nd p

last

ic c

hip

carr

ier

(1.2

7mm

lead

spa

cing

)

Page 115: Xcell Journal Issue 49

Xil

inx C

PLD

htt

p:/

/ww

w.x

ilin

x.c

om

/de

vic

es

Summer 2004 Xcell Journal 115

Pro

du

ct S

ele

ctio

n M

atr

ix –

9500 S

eri

es

Pack

ag

e O

pti

on

s an

d U

ser

I/O

XC9536XV

XC9572XV

XC95144XV

XC95288XV

3434

XC9536XL

XC9572XL

XC95144XL

XC95288XL

3434

3434

8181

117

117

117

117

3836

3836

117

117

192

192

192

192

192

72

34

5236

72

Auto

mot

ive

prod

ucts

are

hig

hlig

hted

: -40

C to

+12

5C a

mbi

ent t

empe

ratu

re fo

r CPL

Ds

Not

e 1:

Are

a di

men

sion

s fo

r lea

d-fra

me

prod

ucts

are

incl

usiv

e of

the

lead

s.

Are

a1Pi

ns

17.5

x 1

7.5

mm

44

23.3

x 1

7.2

mm

100

12.0

x 1

2.0

mm

44

12.0

x 1

2.0

mm

64

16.0

x 1

6.0

mm

100

22.0

x 2

2.0

mm

144

6 x

6 m

m56

8 x

8 m

m13

2

7 x

7 m

m48

12 x

12

mm

144

16 x

16

mm

280

27 x

27

mm

256

17 x

17

mm

256

17 x

17

mm

256

23 x

23

mm

324

XC9536

XC9572

XC95108

XC95144

3434 72

8181

8181

34

XC95216

XC95288

30.2

x 3

0.2

mm

8469

69

31.2

x 3

1.2

mm

160

108

133

133

168

168

168

30.6

x 3

0.6

mm

208

166

168

192

35.0

x 3

5.0

mm

352

166

192

FGA

Pac

kage

s (F

T) –

wir

e-bo

nd fi

ne-p

itch

thi

n BG

A (1

.0 m

m b

all s

paci

ng)

FBG

A P

acka

ges

(FG

) – w

ire-

bond

Fin

e-lin

e BG

A (1

.0 m

m b

all s

paci

ng)

BGA

Pac

kage

s (B

G) –

wir

e-bo

nd s

tand

ard

BGA

(1.2

7 m

m b

all s

paci

ng)

3434XC

9500

XC95

00XL

XC95

00XV

72

TQFP

Pac

kage

s (T

Q) –

thi

n Q

FP (0

.5m

m le

ad s

paci

ng)

VQFP

Pac

kage

s (V

Q) –

ver

y th

in T

QFP

(0.5

mm

lead

spa

cing

)

PQFP

Pac

kage

s (P

Q) –

wir

e-bo

nd p

last

ic Q

FP (0

.5m

m le

ad s

paci

ng)

PLCC

Pac

kage

s (P

C) –

wir

e-bo

nd p

last

ic c

hip

carr

ier

(1.2

7mm

lead

spa

cing

)

Chip

Sca

le P

acka

ges

(CP)

– w

ire-

bond

chi

p-sc

ale

BGA

(0.5

mm

bal

l spa

cing

)

Chip

Sca

le P

acka

ges

(CS)

– w

ire-

bond

chi

p-sc

ale

BGA

(0.8

mm

bal

l spa

cing

)

System Gates

Macrocells

Product Terms per Macrocell

Input Voltage Compatible

Output Voltage Compatible

Maximum I/O

I/O Banking

Min. Pin-to-pin Logic Delay (ns)

Commercial Speed Grades(fastest to slowest)

Industrial Speed Grades(fastest to slowest)

Global Clocks

Product Term Clocks perFunction Block

IQ Speed Grade

I/OFe

atur

esSp

eed

Cloc

king

XC95

3680

036

XC95

7216

0072

XC95

108

2400

108

XC95

144

3200

144

90 90 90 90

3610

-7 -1

0 -1

53

18

7210

-10

-15

318

108

10-7

-10

-15

-20

318

133

10

-5 -6

-10

-15

-7 -1

0 -1

5

-7 -1

0 -1

5 -2

0

-7 -1

0 -1

5-1

0 -1

5

-15

-15

NA

NA

318

5 5 5 5

5 5 5 5

XC95

216

4800

216

9016

610

-10

-15

-20

-10

-15

-20

NA

318

55

XC95

288

6400

Pb-fr

ee s

olut

ions

ava

ilabl

e fo

r all

pack

ages

. For

mor

e in

form

atio

n co

ntac

t you

r Xili

nx s

ales

repr

esen

tativ

e or

vis

it w

ww

.xili

nx.c

om/p

bfre

e.

288

9019

210

-10

-15

-20

-15

-20

NA

318

55

XC95

00 F

amily

– 5

Vol

t

XC95

36XL

800

36

XC95

72XL

1600

72

XC95

144X

L32

0014

4

XC95

288X

L64

0028

8

90 90 90 90

365

-7 -1

03

18

725

-7 -1

03

18

117

5-7

-10

318

192

6

-5 -7

-10

-5 -7

-10

-5 -7

-10

-6 -7

-10

-7 -1

0

-10

-10

NA

NA

318

2.5/

3.3/

5

2.5/

3.3/

5

2.5/

3.3/

5

2.5/

3.3/

5

2.5/

3.3

2.5

/3.3

2.5/

3.3

2.5

/3.3

XC95

00XL

Fam

ily –

3.3

Vol

t

XC95

36XV

800

36

XC95

72XV

1600

72

XC95

144X

V32

0014

4

XC95

288X

V64

0028

8

90 90 90 90

365

-7

318

725

-7

318

117

5-7

3

18

192

6

1 1 2 4

-5 -7

-5 -7

-5 -7

-6 -7

-10

-7 -1

0

NA

NA

NA

NA

318

2.5/

3.3

2.5/

3.3

2.5/

3.3

2.5/

3.3

1.8/

2.5/

3.3

1.8

/2.5

/3.3

1.8/

2.5/

3.3

1.8/

2.5/

3.3

XC95

00XV

Fam

ily –

2.5

Vol

t

Page 116: Xcell Journal Issue 49

Xil

inx D

efe

nse

an

d A

ero

space

htt

p:/

/ww

w.x

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x.c

om

/de

vic

es

116 Xcell Journal Summer 2004

XC30

20*

QPR

ODevice

5962

-899

48

SMD

5Voltage

1500

System Gates

Logic Cells

RAMbus

CFG Bits

MULTs

DLLs

256

–14

779

––

Flip-Flops

256

Max I/Os

64

Packages

PG84

, CB

100

XC30

30*

Non

e 5

2000

360

–22

176

––

360

80PG

84

XC30

42*

5962

-897

13

530

0048

0–

3078

4–

–48

0 96

PG84

, PG

132,

CB1

00

XC30

64*

Non

e 5

4500

68

8 –

4606

4–

–68

8 12

0PG

132

XC30

90*

5962

-898

23

560

00

928

–64

160

––

928

144

PG17

5, C

B164

XC40

05*

5962

-922

52

59K

46

6 62

72

1519

60

––

616

112

PG15

6, C

B164

XC40

10*

5962

-923

05

520

K 95

0 12

800

2834

24

––

1120

16

0PG

191,

CB1

96

XC40

13*

5962

-947

30

530

K 13

68

1843

8 39

3632

–15

36

192

PG22

3, C

B228

XQ40

05E

5962

-975

22

59K

46

6 62

72

9500

8–

–61

6 11

2 PG

156,

CB1

64

XQ40

10E

5962

-975

23

520

K 95

0 12

800

1781

44–

–11

20

160

HQ20

8, P

G19

1, C

B196

XQ40

13E

5962

-975

24

530

K 13

68

1843

8 24

7968

–15

36

192

HQ24

0, P

G22

3, C

B228

XQ40

25E

5962

-975

25

545

K 24

32

3276

8 42

2176

–25

60

256

PG29

9, C

B228

XQ40

28EX

59

62-9

8509

5

18K-

50K

2432

32

768

6681

84

––

2560

25

6 HQ

240,

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352,

PG

299,

CB2

28

XQ40

13XL

59

62-9

8513

3.

3 10

-30K

13

68

18K

3936

32

––

1536

19

2 PQ

240,

BG

256,

PG

223,

CB2

28

XQ40

36XL

59

62-9

8510

3.

3 22

-65K

30

78

42K

8325

28

––

3168

28

8 HQ

240,

BG

352,

PG

411,

CB2

28

XQ40

62XL

59

62-9

8511

3.

3 40

-130

K 54

72

74K

1433

864

––

5376

38

4 HQ

240,

BG

432,

PG

475,

CB2

28

XQ40

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N

one

3.3

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10

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44

8 HQ

240,

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432,

CB2

28

XQV1

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5 10

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27

00

40K

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48

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2400

18

0 PQ

240,

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256,

CB2

28

XQV3

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5962

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72

2.5

3229

70

6912

64

K 17

5184

0 –

461

44

316

PQ24

0, B

G35

2, B

G43

2, C

B228

XQV6

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5962

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73

2.5

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1555

2 96

K 36

0800

0 –

413

824

512

HQ24

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5962

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74

2.5

1124

022

2764

8 12

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6 51

2 BG

560,

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560

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898

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1555

2 28

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3961

632

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4 51

2 BG

432,

CB2

28

XQV1

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1.8

1569

K 27

648

384K

65

8752

0 –

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576

660

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200

640K

10

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48

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3840

0 80

4 BG

560,

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1156

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D 1.

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0 72

0 40

8259

2 40

810

240

432

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6, B

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5

XQ2V

3000

TB

D 1.

530

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3225

6 17

28

1049

4368

96

1228

672

720

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7

XQ2V

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* N

ot fo

r new

des

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TBD

1.5

6000

K 76

032

2592

21

8495

04

144

1267

584

1104

CF

1144

Qua

lifie

d af

ter

QM

LCe

rtifi

cati

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X

Dev

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Nom

encl

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= Q

ualif

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r to

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L Ce

rtifi

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on

QV

R

XQ

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Radi

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lera

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ex-II

Radi

atio

n To

lera

nt

XQR4

013X

L

QPR

O R

adia

tion

Tol

eran

t

Device

3.3 Voltage

10-3

0K System Gates

Logic Cells

RAMbus

CFG Bits

MULTs

DLLs

1368

18

K 39

3632

Flip-Flops

1536

Max I/Os

192

Packages

CB22

8

Total IonizingDose (TID) inKRADs

60

XQR4

036X

L 3.

3 22

-65K

30

78

42K

8325

28

––

3168

28

8 CB

228

60

XQR4

062X

L 3.

3 40

-130

K 54

72

74K

1433

864

––

5376

38

4 CB

228

60

XQVR

300

2.5

3229

70

6912

64

K 17

5184

0 –

461

44

316

CB22

8 10

0

XQVR

600

2.5

6611

11

1555

2 96

K 36

0800

0 –

413

824

512

CB22

8 10

0

XQVR

1000

2.

5 11

2402

2 27

648

128K

61

2777

6 –

424

576

512

CG56

0 10

0

XQR2

V100

0 1.

5 10

00K

1152

0 72

0 40

8259

2 40

810

240

432

BG57

5 20

0

XQR2

V300

0 1.

5 30

00K

3225

6 17

28

1049

4368

96

1228

672

720

CG71

7 20

0

XQR2

V600

0 1.

5 60

00K

7603

2 25

92

2184

9504

14

412

6758

4 11

04

CF11

44

200

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Summer 2004 Xcell Journal 117

Impo

rtan

t:Ve

rify

all

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his

docu

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ith

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devi

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ww

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118 Xcell Journal Summer 2004

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Page 119: Xcell Journal Issue 49

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x.c

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Summer 2004 Xcell Journal 119

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Page 120: Xcell Journal Issue 49

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120 Xcell Journal Summer 2004

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Page 121: Xcell Journal Issue 49

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Summer 2004 Xcell Journal 121

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ws

only

PC (M

S W

indo

ws 2

000/

MS

Win

dow

s XP)

Pl

atfo

rms

PC (M

S W

indo

ws

2000

/MS

Win

dow

s XP

), Li

nux

PC (M

S W

indo

ws

2000

/MS

Win

dow

s XP

), Su

n So

laris

, Lin

uxPC

(MS

Win

dow

s 20

00/M

S W

indo

ws

XP),

Sun

Sola

ris, L

inux

For m

ore

info

rmat

ion

on th

e co

mpl

ete

list o

f Xili

nx IP

pro

duct

s, v

isit

the

Xilin

x IP

Cen

ter a

t htt

p://w

ww

.xili

nx.c

om/ip

cent

er

IP

/CO

RE

*HSP

ICE

Mod

els

avai

labl

e at

the

Xilin

x De

sign

Too

ls C

ente

r at w

ww

.xili

nx.c

om/is

e.**

MXE

II s

uppo

rts

the

sim

ulat

ion

of d

esig

ns u

p to

1 m

illio

n sy

stem

gat

es a

nd is

sol

d as

an

optio

n. Fo

r mor

e in

form

atio

n, v

isit

the

Xilin

x De

sign

Too

ls C

ente

r at w

ww

.xili

nx.c

om/is

e

Page 122: Xcell Journal Issue 49

Xil

inx O

n B

oard

– D

evelo

pm

en

t R

efe

ren

ce B

oard

sh

ttp

://w

ww

.xil

inx

.co

m/b

oa

rd_s

ea

rch

122 Xcell Journal Summer 2004

Boar

d Pa

rt N

umbe

r

ADS-

S3-M

B-EV

L400

Boar

d D

escr

ipti

on

Spar

tan-

3 Ev

alua

tion

Kit w

/Mic

roBl

aze

and

Com

mun

icat

ions

/M

emor

y M

odul

e

Supp

lier

Avne

t Des

ign

Serv

ices

Xilin

x D

evic

e Su

ppor

t

XC3S

400

App

licat

ion

Net

wor

king

, tel

ecom

mun

icat

ion,

dat

a co

mm

unic

atio

n, e

mbe

dded

and

con

sum

er m

arke

ts

Spar

tan-

3

Spar

tan-

IIE

ADS-

XLX-

SP3-

EVL1

500

Spar

tan-

3 Ev

alua

tion

Kit w

ith 3

S150

0 de

vice

Av

net D

esig

n Se

rvic

es

XC3S

1500

-4FG

676

Very

cos

t effe

ctiv

e Sp

arta

n-3

eval

uatio

n pl

atfo

rm; a

llow

s ex

perim

enta

tion

with

the

adva

nced

fe

atur

es o

f the

Spa

rtan

-3 1

500

devi

ce

ADS-

XLX-

SP3-

EVL4

00

Spar

tan-

3 Ev

alua

tion

Kit w

ith 3

S400

dev

ice

Avne

t Des

ign

Serv

ices

XC

3S40

0 Ve

ry c

ost e

ffect

ive

Spar

tan-

3 ev

alua

tion

plat

form

; allo

ws

expe

rimen

tatio

n w

ith th

e ad

vanc

ed

feat

ures

of t

he S

part

an-3

400

dev

ice

DS-K

IT-3

SLC4

00*

Spar

tan-

3 LC

Dev

elop

men

t Kit

Insi

ght (

Mem

ec)

XC3S

400-

4PQ

208

Gen

eral

pur

pose

Spa

rtan

-3 d

evel

opm

ent p

latfo

rm

DS-K

IT-3

SLC4

00-B

AS

Spar

tan-

3 LC

Dev

elop

men

t Kit

w/IS

E Fo

unda

tion

and

JTAG

Cab

le

Insi

ght (

Mem

ec)

XC3S

400-

4PQ

208

Gen

eral

pur

pose

Spa

rtan

-3 d

evel

opm

ent p

latfo

rm

DS-K

IT-3

SLC4

00-P

AK*

Spar

tan-

3 LC

Dev

elop

men

t Kit

w/ W

ebPA

CK C

D an

d JT

AG C

able

In

sigh

t (M

emec

) XC

3S40

0-4P

Q20

8 G

ener

al p

urpo

se S

part

an-3

dev

elop

men

t pla

tform

DS-K

IT-3

SMB1

500*

Sp

arta

n-3

MB

3S15

00 D

evel

opm

ent K

it In

sigh

t (M

emec

) XC

3S15

00-4

FG67

6 G

ener

al p

urpo

se S

part

an-3

dev

elop

men

t pla

tform

DS-K

IT-3

SMB1

500-

ISE

Spar

tan-

3 M

B 3S

1500

Dev

elop

men

t Kit

w/IS

E Fo

unda

tion

and

JTAG

Cab

le

Insi

ght (

Mem

ec)

XC3S

1500

-4FG

676

Gen

eral

pur

pose

Spa

rtan

-3 d

evel

opm

ent p

latfo

rm

DS-K

IT-M

B-3S

LC40

0 Sp

arta

n-3

Mic

roBl

aze

Deve

lopm

ent K

it In

sigh

t (M

emec

) XC

3S40

0-4F

G67

6 Em

bedd

ed m

icro

proc

esso

r

DS-K

IT-M

B-3S

MB1

500

Spar

tan-

3 M

icro

Blaz

e De

velo

pmen

t Kit

Insi

ght (

Mem

ec)

XC3S

1500

-4FG

676

Embe

dded

mic

ropr

oces

sor

HW-A

FX-S

P3-1

500-

DB

NuH

o 3S

1500

Dev

elop

men

t Boa

rd

NuH

oriz

ons

XC3S

1500

Pr

otot

ypin

g, M

icro

Blaz

e So

ft Pr

oces

sor D

evel

opm

ent,

DSP,

Indu

stria

l Sys

tem

s, Da

ta

Com

mun

icat

ions

/ Te

leco

mm

unic

atio

ns

HW-A

FX-S

P3-4

00-D

B

NuH

o 3S

400

Deve

lopm

ent B

oard

N

uHor

izon

s XC

3S40

0-4P

Q20

8C

Prot

otyp

ing,

Mic

roBl

aze

Soft

Proc

esso

r Dev

elop

men

t, DS

P, In

dust

rial S

yste

ms,

Data

Co

mm

unic

atio

ns /

Tele

com

mun

icat

ions

ADS-

S2E-

US2

-SO

L Xi

linx

& C

ypre

ss U

SB 2

.0 to

SCS

I Sys

tem

Sol

utio

n Ki

t Av

net D

esig

n Se

rvic

es

XC2S

300E

-PQ

208

Com

plet

e so

lutio

n fo

r int

erfa

cing

a S

CSI d

rive

to a

hos

t com

pute

r usi

ng U

nive

rsal

Ser

ial B

us

Spec

ifica

tion

Revi

sion

2.0

- pr

ovid

es th

e de

sign

er w

ith a

Win

dow

s re

ady

USB

2.0

to S

CSI

dem

onst

ratio

n de

sign

ADS-

SP2E

-MB-

EVL

Spar

tan-

IIE E

valu

atio

n Ki

t w/M

icro

Blaz

e &

Com

mun

icat

ions

/M

emor

y M

odul

e Av

net D

esig

n Se

rvic

es

XC2S

200E

Pr

otot

ypin

g, D

igita

l Vid

eo, M

ultim

edia

, Tel

ecom

/Dat

acom

ADS-

XLX-

SP2E

-EVL

Sp

arta

n-IIE

Eva

luat

ion

Kit

Avne

t Des

ign

Serv

ices

XC

2S20

0E-6

FT25

6C

Prot

otyp

ing,

Tele

com

/Dat

acom

DS-K

IT-M

B-S2

E3LC

Sp

arta

n-IIE

Mic

roBl

aze

Kit

Insi

ght (

Mem

ec)

Spar

tan-

IIE

Embe

dded

mic

ropr

oces

sor

DS-K

IT-M

B-S2

E6LC

Sp

arta

n-IIE

Mic

roBl

aze

Kit

Insi

ght (

Mem

ec)

Spar

tan-

IIE

Embe

dded

mic

ropr

oces

sor

DS-K

IT-S

2E3L

C*

Spar

tan-

IIE L

C 2S

300E

Dev

elop

men

t Kit

Insi

ght (

Mem

ec)

XC2S

300E

-6FG

456C

G

ener

al p

urpo

se S

part

an-3

dev

elop

men

t pla

tform

DS-K

IT-S

2E3L

C-IS

E-BA

S Sp

arta

n-IIE

LC

Deve

lopm

ent K

it w

/ISE

Base

X In

sigh

t (M

emec

) XC

2S30

0E-6

FG45

6C

DS-K

IT-S

2E6L

C*

Spar

tan-

IIE L

C 2S

600E

Dev

elop

men

t Kit

Insi

ght (

Mem

ec)

XC2S

600E

-6FG

456C

DS-K

IT-S

2E6L

C-IS

E-BA

S Sp

arta

n-IIE

LC

2S60

0E D

evel

opm

ent K

it w

/ISE

Base

X In

sigh

t (M

emec

) XC

2S60

0E-6

FG45

6C

iDEV

2 CA

N, L

IN a

nd T

TCAN

Dev

elop

men

t Pla

tform

and

Sta

rter

Kit

Inte

lliga

Inte

grat

ed D

esig

n, L

td.

XC2S

300E

Au

tom

otiv

e, In

dust

rial

HW-A

FX-D

IGI-2

S200

E

* In

sigh

t Pro

duct

s: A

ppen

d -E

URO

to p

art n

umbe

r for

inte

rnat

iona

l kits

(ex.

DS-

KIT-

2SLC

100-

EURO

); P

ower

Sup

ply

not i

nclu

ded

in -E

URO

kits

Spar

tan-

IIE D

evel

opm

ent B

oard

N

uHor

izon

s XC

2S20

0E

Prot

otyp

ing,

DSP

, Mul

timed

ia, R

econ

figur

able

Com

putin

g

Page 123: Xcell Journal Issue 49

Xil

inx O

n B

oard

– D

evelo

pm

en

t R

efe

ren

ce B

oard

sh

ttp

://w

ww

.xil

inx

.co

m/b

oa

rd_s

ea

rch

Summer 2004 Xcell Journal 123

Boar

d Pa

rt N

umbe

r

ADS-

SP2-

MB-

EVL

Boar

d D

escr

ipti

on

Spar

tan-

II Ev

alua

tion

Kit w

/Mic

roBl

aze

& C

omm

unic

atio

ns/

Mem

ory

Mod

ule

Supp

lier

Avne

t Des

ign

Serv

ices

Xilin

x D

evic

e Su

ppor

t

XC2S

150-

5PQ

208

App

licat

ion

Net

wor

king

, tel

ecom

mun

icat

ion,

dat

a co

mm

unic

atio

n, e

mbe

dded

and

con

sum

er m

arke

ts

Spar

tan-

II

ADS-

XLX-

SP2-

EVL

Spar

tan-

II Ev

alua

tion

Kit

Avne

t Des

ign

Serv

ices

XC

2S15

0-5P

Q20

8 Ve

ry c

ost e

ffect

ive

eval

uatio

n an

d pr

otot

ypin

g pl

atfo

rm to

dev

elop

and

test

des

igns

that

are

ta

rget

ed to

the

Xilin

x Sp

arta

n-II

FPG

A fa

mily

- he

lps

shor

ten

and

sim

plify

the

desi

gn c

ycle

2D F

abric

Boa

rd

2D F

abric

Eva

luat

ion

and

Dem

o Bo

ard

Cros

sbow

Tech

nolo

gies

, Inc

. XC

2S15

0 M

ulti-

proc

essi

ng s

yste

m d

evel

opm

ent;

Net

wor

king

, wire

less

bas

esta

tions

, VoP

gat

eway

s

DS-K

IT-2

S100

* Sp

arta

n-II

100

Deve

lopm

ent K

it In

sigh

t (M

emec

) XC

2S10

0 DS

P, Di

gita

l Vid

eo, I

P-Ba

sed

Syst

ems,

Imag

e Pr

oces

sing

DS-K

IT-2

S200

* Sp

arta

n-II

PCI 2

S200

Dev

elop

men

t Kit

Insi

ght (

Mem

ec)

XC2S

200-

6FG

456C

DS

P, Di

gita

l Vid

eo, I

P-Ba

sed

Syst

ems,

Imag

e Pr

oces

sing

, PCI

, Rec

onfig

urab

le C

ompu

ting

DS-K

IT-2

S200

-ISE-

BAS

Spar

tan-

II PC

I 2S2

00 D

evel

opm

ent K

it w

/ISE

Base

X an

d JT

AG C

able

In

sigh

t (M

emec

) XC

2S20

0-6F

G45

6C

DSP,

Digi

tal V

ideo

, IP-

Base

d Sy

stem

s, Im

age

Proc

essi

ng, P

CI, R

econ

figur

able

Com

putin

g

DS-K

IT-2

S200

-PAK

* Sp

arta

n-II

PCI 2

S200

Dev

elop

men

t Kit

w/W

ebPA

CK C

D an

d JT

AG C

able

In

sigh

t (M

emec

) XC

2S20

0-6F

G45

6C

DSP,

Digi

tal V

ideo

, IP-

Base

d Sy

stem

s, Im

age

Proc

essi

ng, P

CI, R

econ

figur

able

Com

putin

g

DS-K

IT-2

SLC1

00*

Spar

tan-

II LC

2S1

00 D

evel

opm

ent K

it In

sigh

t (M

emec

) XC

2S10

0-5P

Q20

8C

Gen

eral

pur

pose

Spa

rtan

-II d

evel

opm

ent p

latfo

rm

DS-K

IT-2

SLC1

00-IS

E-BA

S Sp

arta

n-II

LC 2

S100

Dev

elop

men

t Kit

w/IS

E Ba

seX

and

JTAG

Cab

le

Insi

ght (

Mem

ec)

XC2S

100-

5PQ

208C

G

ener

al p

urpo

se S

part

an-II

dev

elop

men

t pla

tform

DS-K

IT-2

SLC1

00-P

AK*

Spar

tan-

II LC

2S1

00 D

evel

opm

ent K

it w

/Web

PACK

CD

and

JTAG

Cab

le

Insi

ght (

Mem

ec)

XC2S

100-

5PQ

208C

G

ener

al p

urpo

se S

part

an-II

dev

elop

men

t pla

tform

DS-K

IT-M

BLAZ

E-S2

Sp

arta

n-II

Mic

roBl

aze

Kit

Insi

ght (

Mem

ec)

Spar

tan-

II Em

bedd

ed m

icro

proc

esso

r

DS-K

IT-P

CI32

S-20

0 Sp

arta

n-II

200

PCI D

evel

opm

ent K

it w

/Xili

nx S

ingl

e Pr

ojec

t PC

I325

Lic

ense

In

sigh

t (M

emec

) XC

2S20

0 DS

P, Di

gita

l Vid

eo, I

mag

e Pr

oces

sing

, PCI

, Rec

onfig

urab

le C

ompu

ting

RT-D

AC4/

PCI-D

-OM

NI

Digi

tal O

MN

I Boa

rd

INTE

CO

XC2S

100,

XC2

S150

, XC2

S50

ASIC

Pro

toty

ping

, DSP

, Dat

a St

orag

e, D

ata

Tran

smis

sion

& M

anip

ulat

ion,

Dig

ital V

ideo

, Em

bedd

ed M

icro

proc

esso

r, Em

bedd

ed S

yste

m, I

P-Ba

sed

Syst

ems,

Imag

e Pr

oces

sing

, Lo

w p

ower

des

igns

, Mul

timed

ia, N

avig

atio

n, P

CI, R

econ

figur

able

Com

putin

g, S

eria

l/De

seria

lizat

ion,

Tele

com

/ Da

taco

m, T

elem

atic

s, Vo

IP

RT-D

AC4/

PCI-O

MN

I O

MN

I Boa

rd

INTE

CO

XC2S

100,

XC2

S150

, XC2

S50

ASIC

Pro

toty

ping

, DSP

, Dat

a St

orag

e, D

ata

Tran

smis

sion

& M

anip

ulat

ion,

Dig

ital V

ideo

, Em

bedd

ed M

icro

proc

esso

r, Em

bedd

ed S

yste

m, I

P-Ba

sed

Syst

ems,

Imag

e Pr

oces

sing

, Lo

w p

ower

des

igns

, Mul

timed

ia, N

avig

atio

n, P

CI, R

econ

figur

able

Com

putin

g, S

eria

l/De

seria

lizat

ion,

Tele

com

/ Da

taco

m, T

elem

atic

s, Vo

IP

Mic

roEn

gine

V

CPU

+ F

PGA

(Virt

ex/S

part

an-II

) Mic

roEn

gine

Car

ds

Intr

insy

c, In

c.

Spar

tan-

II Em

bedd

ed S

yste

ms

NPE

565-

M

Spar

tan-

II Po

wer

-PC

Engi

ne

Nor

th P

ole

Engi

neer

ing

XC2S

200

Prot

otyp

ing,

DSP

, Em

bedd

ed S

yste

m, I

ndus

tria

l Aut

omot

ive,

Rec

onfig

urab

le C

ompu

ting

NV-

FPSD

-001

FP

GA

SDRA

M C

ontr

olle

r Eva

luat

ion

Boar

d N

ovte

ch

XC2S

50

Prot

otyp

ing,

DSP

, Dat

a St

orag

e, D

ata

Tran

smis

sion

& M

anip

ulat

ion,

Dig

ital V

ideo

, Em

bedd

ed

Mic

ropr

oces

sor,

Embe

dded

Sys

tem

, IP-

Base

d Sy

stem

s, Im

age

Proc

essi

ng, L

ow p

ower

des

igns

, M

ultim

edia

, Nav

igat

ion,

PCI

, Rec

onfig

urab

le C

ompu

ting,

Ser

ial/D

eser

ializ

atio

n, Te

leco

m /

Data

com

, Tel

emat

ics,

VoIP

SPCM

USB

-EVL

U

SB 2

.0 M

ass

Stor

age

Clas

s Re

fere

nce

Desi

gn

Spec

soft

Cons

ultin

g, In

c.

XC2S

200

Prot

otyp

ing,

Dat

a St

orag

e, E

mbe

dded

Sys

tem

, IP-

Base

d Sy

stem

s

SPCV

USB

-EVL

U

SB 2

.0 V

ideo

Cla

ss R

efer

ence

Des

ign

Spec

soft

Cons

ultin

g, In

c.

XC2S

200

Prot

otyp

ing,

Dat

a Tr

ansm

issi

on &

Man

ipul

atio

n, E

mbe

dded

Sys

tem

, IP-

Base

d Sy

stem

s

* In

sigh

t Pro

duct

s: A

ppen

d -E

URO

to p

art n

umbe

r for

inte

rnat

iona

l kits

(ex.

DS-

KIT-

2SLC

100-

EURO

); P

ower

Sup

ply

not i

nclu

ded

in -E

URO

kits

Page 124: Xcell Journal Issue 49

Xil

inx O

n B

oard

– D

evelo

pm

en

t R

efe

ren

ce B

oard

sh

ttp

://w

ww

.xil

inx

.co

m/b

oa

rd_s

ea

rch

124 Xcell Journal Summer 2004

Boar

d Pa

rt N

umbe

r

ADM

-XPL

Boar

d D

escr

ipti

on

Reco

nfig

urab

le C

ompu

ter B

ased

on

Virt

ex-II

Pro

Supp

lier

Alph

a Da

ta

Xilin

x D

evic

e Su

ppor

t

XC2V

P7, X

C2VP

20

App

licat

ion

DSP,

Reco

nfig

urab

le C

ompu

ting

, Im

age

Proc

essi

ng ,

ASIC

Pro

toty

ping

Virt

ex-II

Pro

PCI P

latfo

rm

Virt

ex-II

Pro

PCI

Pla

tform

FPG

A De

velo

pmen

t Boa

rd

Amiri

x Sy

stem

s, In

c.

XC2V

P7,X

C2VP

20, X

C2VP

30

Net

wor

king

(SAN

, VoI

P, Br

idge

s), C

omm

unic

atio

ns, D

SP, I

mag

e Pr

oces

sing

, Ind

ustr

ial C

ontr

ols,

Inst

rum

enta

tion,

test

and

mea

sure

men

t

ADS-

XLX-

V2PR

O-D

EVP2

0-6

Virt

ex-II

Pro

Dev

elop

men

t Kit

w/X

C2VP

20, -

6 sp

eed

grad

e Av

net D

esig

n Se

rvic

es

XC2V

P20

Prot

otyp

ing,

DSP

, Dat

a St

orag

e, D

ata

Tran

smis

sion

& M

anip

ulat

ion,

Em

bedd

ed M

icro

proc

esso

r, Em

bedd

ed S

yste

m, I

P-Ba

sed

Syst

ems,

Nav

igat

ion,

PCI

, Rec

onfig

urab

le C

ompu

ting,

Ser

ial /

De

seria

lizat

ion

ADS-

XLX-

V2PR

O-D

EVP3

0-6

Virt

ex-II

Pro

Dev

elop

men

t Kit

w/X

C2VP

30, -

6 sp

eed

grad

e Av

net D

esig

n Se

rvic

es

XC2V

P30

Prot

otyp

ing,

DSP

, Dat

a St

orag

e, D

ata

Tran

smis

sion

& M

anip

ulat

ion,

Em

bedd

ed M

icro

proc

esso

r, Em

bedd

ed S

yste

m, I

P-Ba

sed

Syst

ems,

Nav

igat

ion,

PCI

, Rec

onfig

urab

le C

ompu

ting,

Ser

ial /

De

seria

lizat

ion

ADS-

XLX-

V2PR

O-D

EVP7

-5

Virt

ex-II

Pro

Dev

elop

men

t Kit

w/X

C2VP

7, -5

spe

ed g

rade

Av

net D

esig

n Se

rvic

es

XC2V

P7

Prot

otyp

ing,

DSP

, Dat

a St

orag

e, D

ata

Tran

smis

sion

& M

anip

ulat

ion,

Em

bedd

ed M

icro

proc

esso

r, Em

bedd

ed S

yste

m, I

P-Ba

sed

Syst

ems,

Nav

igat

ion,

PCI

, Rec

onfig

urab

le C

ompu

ting,

Ser

ial /

De

seria

lizat

ion

ADS-

XLX-

V2PR

O-D

EVP7

-6

Virt

ex-II

Pro

Dev

elop

men

t Kit

w/X

C2VP

7, -6

spe

ed g

rade

Av

net D

esig

n Se

rvic

es

XC2V

P7

Prot

otyp

ing,

DSP

, Dat

a St

orag

e, D

ata

Tran

smis

sion

& M

anip

ulat

ion,

Em

bedd

ed M

icro

proc

esso

r, Em

bedd

ed S

yste

m, I

P-Ba

sed

Syst

ems,

Nav

igat

ion,

PCI

, Rec

onfig

urab

le C

ompu

ting,

Ser

ial /

De

seria

lizat

ion

ADS-

XLX-

V2PR

O-E

VLP7

-5

Virt

ex-II

Pro

Eva

luat

ion

Kit w

/XC2

VP7,

-5 s

peed

gra

de

Avne

t Des

ign

Serv

ices

XC

2VP7

Ve

ry c

ost e

ffect

ive

eval

uatio

n an

d pr

otot

ypin

g pl

atfo

rm to

dev

elop

and

test

des

igns

targ

eted

to

the

Virt

ex-II

Pro

dev

ice

ADS-

XLX-

V2PR

O-E

VLP7

-6

Virt

ex-II

Pro

Eva

luat

ion

Kit w

/XC2

VP7,

-6 s

peed

gra

de

Avne

t Des

ign

Serv

ices

XC

2VP7

Ve

ry c

ost e

ffect

ive

eval

uatio

n an

d pr

otot

ypin

g pl

atfo

rm to

dev

elop

and

test

des

igns

targ

eted

to

the

Virt

ex-II

Pro

dev

ice

V2PR

O K

it Vi

rtex

-II P

ro™

Dev

elop

men

t Kit

Avne

t Des

ign

Serv

ices

XC

2VP7

, XC2

VP20

, SC2

VP30

Pa

cket

sw

itchi

ng; n

etw

ork

secu

rity;

SAN

, ser

vers

and

sup

er c

ompu

ters

; vid

eo c

ompu

ting/

tran

smis

sion

; Hig

h-sp

eed

seria

l int

erfa

ces

D6PC

Da

nube

6-P

aC

Bitt

War

e, In

c.

XC2V

P20

DSP,

Data

Tran

smis

sion

& M

anip

ulat

ion,

Em

bedd

ed S

yste

m, I

mag

e Pr

oces

sing

, Mul

timed

ia,

Reco

nfig

urab

le C

ompu

ting,

Tele

com

/Dat

acom

DN60

00K1

0S

DN60

00K1

0S A

SIC

Prot

otyp

ing

Engi

ne

DIN

I Gro

up

XC2V

P125

, XC2

VP70

Pr

otot

ypin

g, D

SP, D

ata

Stor

age,

Dat

a Tr

ansm

issi

on &

Man

ipul

atio

n, D

igita

l Vid

eo, E

mbe

dded

M

icro

proc

esso

r, Em

bedd

ed S

yste

m, I

P-Ba

sed

Syst

ems,

Imag

e Pr

oces

sing

, Low

pow

er d

esig

ns,

Mul

timed

ia, N

avig

atio

n, P

CI, R

econ

figur

able

Com

putin

g, S

eria

l/Des

eria

lizat

ion,

Dat

acom

/ Te

leco

m, T

elem

atic

s, Vo

IP

DS-K

IT-2

VP20

FF11

52*

Virt

ex-II

Pro

FF1

152

P20

Deve

lopm

ent K

it In

sigh

t (M

emec

) XC

2VP2

0 in

FF1

152

DS-K

IT-2

VP30

FF11

52*

Virt

ex-II

Pro

FF1

152

P30

Deve

lopm

ent K

it In

sigh

t (M

emec

) XC

2VP3

0 in

FF1

152

DS-K

IT-2

VP4F

F672

* Vi

rtex

-II P

ro F

F672

P4

Deve

lopm

ent K

it In

sigh

t (M

emec

) XC

2VP4

in F

F672

DS-K

IT-2

VP4F

G45

6*

Virt

ex-II

Pro

P4

FG45

6 De

velo

pmen

t Kit

Insi

ght (

Mem

ec)

XC2V

P4 in

FG

456

DSP,

Digi

tal V

ideo

, Em

bedd

ed S

yste

m, I

P-Ba

sed

Syst

ems,

Imag

e Pr

oces

sing

DS-K

IT-2

VP7F

F672

* Vi

rtex

-II P

ro F

F672

P7

Deve

lopm

ent K

it - E

URO

Insi

ght (

Mem

ec)

XC2V

P7 in

FF6

72

DS-K

IT-2

VP7F

G45

6*

Virt

ex-II

Pro

P7

FG45

6 De

velo

pmen

t Kit

Insi

ght (

Mem

ec)

XC2V

P7 in

FG

456

DSP,

Digi

tal V

ideo

, Em

bedd

ed S

yste

m, I

P-Ba

sed

Syst

ems,

Imag

e Pr

oces

sing

BenP

RO-2

VP7-

6 Be

nPRO

N

alla

tech

XC

2VP7

-XC2

VP20

Da

ta N

etw

orks

& D

igita

l Sig

nal p

roce

ssin

g, E

mbe

dded

Sys

tem

, Tel

ecom

SMT3

87

Disk

Sto

rage

Mod

ule

Sund

ance

Mul

tipro

cess

or C

o.

XC2V

P20

DSP,

Data

Sto

rage

, Dat

a Tr

ansm

issi

on &

Man

ipul

atio

n, D

igita

l Vid

eo, E

ncry

ptio

n De

vice

s, Im

age

Proc

essi

ng, R

econ

figur

able

Com

putin

g

TB-V

2P-2

0-M

GT

Virt

ex-II

Pro

Roc

ketIO

Eva

luat

ion

Boar

d To

kyo

Elec

tron

Dev

ice

Lim

ited

XC2V

P20-

6FF8

96

Prot

otyp

ing,

DSP

, Dat

a Tr

ansm

issi

on &

Man

ipul

atio

n, E

mbe

dded

Mic

ropr

oces

sor,

Embe

dded

Sy

stem

, IP-

Base

d Sy

stem

s, Re

conf

igur

able

Com

putin

g, S

eria

l / D

eser

ializ

atio

n

TB-V

2P-3

0-M

GT

Virt

ex-II

Pro

Roc

ketIO

Eva

luat

ion

Boar

d To

kyo

Elec

tron

Dev

ice

Lim

ited

XC2V

P30-

6FF8

96

Prot

otyp

ing,

DSP

, Dat

a Tr

ansm

issi

on &

Man

ipul

atio

n, E

mbe

dded

Mic

ropr

oces

sor,

Embe

dded

Sy

stem

, IP-

Base

d Sy

stem

s, Re

conf

igur

able

Com

putin

g, S

eria

l / D

eser

ializ

atio

n

* In

sigh

t Pro

duct

s: A

ppen

d -E

URO

to p

art n

umbe

r for

inte

rnat

iona

l kits

(ex.

DS-

KIT-

2SLC

100-

EURO

); P

ower

Sup

ply

not i

nclu

ded

in -E

URO

kits

. For

Virt

ex-II

Pro

, 2VP

40 a

nd 2

VP50

boa

rds

are

avai

labl

e up

on c

usto

mer

requ

est.

Page 125: Xcell Journal Issue 49

Xil

inx O

n B

oard

– D

evelo

pm

en

t R

efe

ren

ce B

oard

sh

ttp

://w

ww

.xil

inx

.co

m/b

oa

rd_s

ea

rch

Summer 2004 Xcell Journal 125

Boar

d Pa

rt N

umbe

r

TB-V

2P-7

-MG

T

Boar

d D

escr

ipti

on

Virt

ex-II

Pro

Roc

ketIO

Eva

luat

ion

Boar

d

Supp

lier

Toky

o El

ectr

on D

evic

e Li

mite

d

Xilin

x D

evic

e Su

ppor

t

XC2V

P7-6

FF89

6

App

licat

ion

Prot

otyp

ing,

DSP

, Dat

a Tr

ansm

issi

on &

Man

ipul

atio

n, E

mbe

dded

Mic

ropr

oces

sor,

Embe

dded

Sy

stem

, IP-

Base

d Sy

stem

s, Re

conf

igur

able

Com

putin

g, S

eria

l / D

eser

ializ

atio

n

Virt

ex-II

Pro

XSP-

016

Virt

ex-II

Pro

Pow

erPC

&M

icro

Blaz

e Ev

alua

tion

Boar

d To

kyo

Elec

tron

Dev

ice

Lim

ited

XC2V

P7-5

FG45

6 Pr

otot

ypin

g, D

SP, D

ata

Tran

smis

sion

& M

anip

ulat

ion,

Em

bedd

ed M

icro

proc

esso

r, Em

bedd

ed

Syst

em, I

P-Ba

sed

Syst

ems,

Reco

nfig

urab

le C

ompu

ting

DO-V

2P-M

L300

-EC

Virt

ex-II

Pro

ML3

00 E

valu

atio

n Pl

atfo

rm- E

C ve

rsio

n Xi

linx

Onl

ine

Stor

e XC

2VP7

Pr

otot

ypin

g, D

SP, D

ata

Stor

age,

Dat

a Tr

ansm

issi

on &

Man

ipul

atio

n, D

igita

l Vid

eo, E

mbe

dded

M

icro

proc

esso

r, Em

bedd

ed S

yste

m, I

P-Ba

sed

Syst

ems,

Imag

e Pr

oces

sing

, Mul

timed

ia,

Nav

igat

ion,

PCI

, Rec

onfig

urab

le C

ompu

ting,

Ser

ializ

atio

n / D

eser

ializ

atio

n, Te

leco

m

DO-V

2P-M

L300

-UK

Virt

ex-II

Pro

ML3

00 E

valu

atio

n Pl

atfo

rm- U

K ve

rsio

n Xi

linx

Onl

ine

Stor

e XC

2VP7

Pr

otot

ypin

g, D

SP, D

ata

Stor

age,

Dat

a Tr

ansm

issi

on &

Man

ipul

atio

n, D

igita

l Vid

eo, E

mbe

dded

M

icro

proc

esso

r, Em

bedd

ed S

yste

m, I

P-Ba

sed

Syst

ems,

Imag

e Pr

oces

sing

, Mul

timed

ia,

Nav

igat

ion,

PCI

, Rec

onfig

urab

le C

ompu

ting,

Ser

ializ

atio

n / D

eser

ializ

atio

n, Te

leco

m

DO-V

2P-M

L300

-USA

Vi

rtex

-II P

ro M

L300

Eva

luat

ion

Plat

form

- US

vers

ion

Xilin

x O

nlin

e St

ore

XC2V

P7

Prot

otyp

ing,

DSP

, Dat

a St

orag

e, D

ata

Tran

smis

sion

& M

anip

ulat

ion,

Dig

ital V

ideo

, Em

bedd

ed

Mic

ropr

oces

sor,

Embe

dded

Sys

tem

, IP-

Base

d Sy

stem

s, Im

age

Proc

essi

ng, M

ultim

edia

, N

avig

atio

n, P

CI, R

econ

figur

able

Com

putin

g, S

eria

lizat

ion

/ Des

eria

lizat

ion,

Tele

com

/ Da

taco

m, T

elem

atic

s, Vo

IP

DO-V

2P-M

L300

-WRS

-EC

Virt

ex-II

Pro

ML3

00 E

valu

atio

n Pl

atfo

rm w

ith

Win

dRiv

er to

ols

- EC

vers

ion

Xilin

x O

nlin

e St

ore

XC2V

P7

Prot

otyp

ing,

DSP

, Dat

a St

orag

e, D

ata

Tran

smis

sion

& M

anip

ulat

ion,

Dig

ital V

ideo

, Em

bedd

ed

Mic

ropr

oces

sor,

Embe

dded

Sys

tem

, IP-

Base

d Sy

stem

s, Im

age

Proc

essi

ng, M

ultim

edia

, N

avig

atio

n, P

CI, R

econ

figur

able

Com

putin

g, S

eria

lizat

ion

/ Des

eria

lizat

ion,

Tele

com

DO-V

2P-M

L300

-WRS

-UK

Virt

ex-II

Pro

ML3

00 E

valu

atio

n Pl

atfo

rm w

ith

Win

dRiv

er to

ols

- UK

vers

ion

Xilin

x O

nlin

e St

ore

XC2V

P7

Prot

otyp

ing,

DSP

, Dat

a St

orag

e, D

ata

Tran

smis

sion

& M

anip

ulat

ion,

Dig

ital V

ideo

, Em

bedd

ed

Mic

ropr

oces

sor,

Embe

dded

Sys

tem

, IP-

Base

d Sy

stem

s, Im

age

Proc

essi

ng, M

ultim

edia

, N

avig

atio

n, P

CI, R

econ

figur

able

Com

putin

g, S

eria

lizat

ion

/ Des

eria

lizat

ion,

Tele

com

DO-V

2P-M

L300

-WRS

-USA

Vi

rtex

-II P

ro M

L300

Eva

luat

ion

Plat

form

with

W

indR

iver

tool

s - U

S ve

rsio

n Xi

linx

Onl

ine

Stor

e XC

2VP7

Pr

otot

ypin

g, D

SP, D

ata

Stor

age,

Dat

a Tr

ansm

issi

on &

Man

ipul

atio

n, D

igita

l Vid

eo, E

mbe

dded

M

icro

proc

esso

r, Em

bedd

ed S

yste

m, I

P-Ba

sed

Syst

ems,

Imag

e Pr

oces

sing

, Mul

timed

ia,

Nav

igat

ion,

PCI

, Rec

onfig

urab

le C

ompu

ting,

Ser

ializ

atio

n / D

eser

ializ

atio

n, Te

leco

m /

Data

com

, Tel

emat

ics,

VoIP

HW-A

FX-F

F115

2-30

0 Vi

rtex

-II P

ro P

roto

Boa

rdXi

linx

Onl

ine

Stor

e XC

2VP2

0, X

C2VP

30, X

C2VP

40, X

C2VP

50

Prot

otyp

ing,

DSP

, Dat

a St

orag

e, D

ata

Tran

smis

sion

& M

anip

ulat

ion,

Em

bedd

ed M

icro

proc

esso

r, Em

bedd

ed S

yste

m, I

P-Ba

sed

Syst

ems,

Imag

e Pr

oces

sing

, Nav

igat

ion,

Rec

onfig

urab

le

Com

putin

g, S

eria

l / D

eser

ializ

atio

n, Te

leco

m /

Data

com

, Tel

emat

ics,

VoIP

HW-A

FX-F

F672

-300

Vi

rtex

-II P

ro P

roto

Boa

rd

Xilin

x O

nlin

e St

ore

XC2V

P2, X

C2VP

4, X

C2VP

7 Pr

otot

ypin

g, D

SP, D

ata

Stor

age,

Dat

a Tr

ansm

issi

on &

Man

ipul

atio

n, E

mbe

dded

Mic

ropr

oces

sor,

Embe

dded

Sys

tem

, IP-

Base

d Sy

stem

s, Im

age

Proc

essi

ng, N

avig

atio

n, R

econ

figur

able

Co

mpu

ting,

Ser

ial /

Des

eria

lizat

ion,

Tele

com

/ Da

taco

m, T

elem

atic

s, Vo

IP

HW-A

FX-F

G45

6-30

0 Vi

rtex

-II P

ro P

roto

Boa

rd

Xilin

x O

nlin

e St

ore

XC2V

P2, X

C2VP

4, X

C2VP

7 Pr

otot

ypin

g, D

SP, D

ata

Stor

age,

Dat

a Tr

ansm

issi

on &

Man

ipul

atio

n, E

mbe

dded

Mic

ropr

oces

sor,

Embe

dded

Sys

tem

, IP-

Base

d Sy

stem

s, Im

age

Proc

essi

ng, N

avig

atio

n, R

econ

figur

able

Co

mpu

ting,

Ser

ial /

Des

eria

lizat

ion,

Tele

com

/ Da

taco

m, T

elem

atic

s, Vo

IP

HW-A

FX-S

MA-

HSSD

C2

SMA

To H

SSDC

2 Co

nver

sion

Mod

ule

Xilin

x O

nlin

e St

ore

Supp

orts

boa

rds

with

SM

A co

nnec

tors

HW-A

FX-S

MA-

RJ45

SM

A To

RJ4

5 Co

nver

sion

Mod

ule

Xilin

x O

nlin

e St

ore

Supp

orts

boa

rds

with

SM

A co

nnec

tors

HW-A

FX-S

MA-

SATA

SM

A To

SAT

A Co

nver

sion

Mod

ule

Xilin

x O

nlin

e St

ore

Supp

orts

boa

rds

with

SM

A co

nnec

tors

HW-A

FX-S

MA-

SFP

SM

A To

SFP

Con

vers

ion

Mod

ule

Xilin

x O

nlin

e St

ore

Supp

orts

boa

rds

with

SM

A co

nnec

tors

DO-V

2P-M

L300

-USA

Vi

rtex

-II P

ro M

L300

Eva

luat

ion

Plat

form

- US

vers

ion

Xilin

x Sa

les

Offi

ces

XC2V

P7

Prot

otyp

ing,

DSP

, Dat

a St

orag

e, D

ata

Tran

smis

sion

& M

anip

ulat

ion,

Dig

ital V

ideo

, Em

bedd

ed

Mic

ropr

oces

sor,

Embe

dded

Sys

tem

, IP-

Base

d Sy

stem

s, Im

age

Proc

esin

g, M

ultim

edia

, N

avig

atio

n, P

CI, R

econ

figur

able

Com

putin

g, S

eria

l / D

eser

ializ

atio

n, Te

leco

m /

Data

com

, Te

lem

atic

s, Vo

IP

HW-V

2PRO

-XLV

DS

Virt

ex-II

Pro

XLV

DS

Xilin

x Sa

les

Offi

ces

XC2V

P20

Data

Tran

smis

sion

& M

anip

ulat

ion,

Em

bedd

ed S

yste

m, E

ncry

ptio

n De

vice

s, IP

-Bas

ed S

yste

ms,

Reco

nfig

urab

le C

ompu

ting,

Ser

ial /

Des

eria

lizat

ion,

Tele

com

/ Da

taco

m, T

est E

quip

men

t

* In

sigh

t Pro

duct

s: A

ppen

d -E

URO

to p

art n

umbe

r for

inte

rnat

iona

l kits

(ex.

DS-

KIT-

2SLC

100-

EURO

); P

ower

Sup

ply

not i

nclu

ded

in -E

URO

kits

Page 126: Xcell Journal Issue 49

Xil

inx O

n B

oard

– D

evelo

pm

en

t R

efe

ren

ce B

oard

sh

ttp

://w

ww

.xil

inx

.co

m/b

oa

rd_s

ea

rch

126 Xcell Journal Summer 2004

Boar

d Pa

rt N

umbe

r

ADM

-XPL

/2VP

7-5

Boar

d D

escr

ipti

on

ADM

-XPL

Supp

lier

Alph

a Da

ta

Xilin

x D

evic

e Su

ppor

t

XC2V

1000

, XC2

VP20

, XC2

VP7

App

licat

ion

Prot

otyp

ing,

DSP

, Im

age

Proc

essi

ng, R

econ

figur

able

Com

putin

g

Virt

ex-II

ADM

-XRC

-II

ADM

-XRC

-II

Alph

a Da

ta

XC2V

3000

, XC2

V400

0, X

C2V6

000,

XC2

V800

0 Pr

otot

ypin

g, C

ompr

essi

on, D

SP, E

ncry

ptio

n, R

econ

figur

able

Com

putin

g, S

oftw

are

Radi

o,

Vide

o / I

mag

e Pr

oces

sing

, XM

L pr

oces

sing

ADS-

V2-M

B-DE

V400

0XP

Virt

ex-II

XC2

V400

0XP

Deve

lopm

ent K

it w

ith M

icro

Blaz

e Av

net D

esig

n Se

rvic

es

XC2V

4000

Pr

otot

ypin

g. D

ata

Tran

smis

sion

& M

anip

ulat

ion,

Hig

hend

DSP

, IP-

Base

d Sy

stem

s, PC

I

ADS-

V2-M

B-DE

V600

0XP

Virt

ex-II

XC2

V600

0 De

velo

pmen

t Kit

with

Mic

roBl

aze

Avne

t Des

ign

Serv

ices

XC

2V60

00

Prot

otyp

ing.

Dat

a Tr

ansm

issi

on &

Man

ipul

atio

n, H

ighe

nd D

SP, I

P-Ba

sed

Syst

ems,

PCI

ADS-

XLX-

MB-

DEV1

500

Virt

ex-II

XC2

V150

0 De

velo

pmen

t Kit

with

Mic

roBl

aze

Avne

t Des

ign

Serv

ices

XC

2V15

00

Prot

otyp

ing,

Dat

a Tr

ansm

issi

on &

Man

ipul

atio

n, H

igh

End

DSP,

IP-b

ased

Sys

tem

s, PC

I

ADS-

XLX-

MB-

DEV4

000

Virt

ex-II

XC2

V400

0 De

velo

pmen

t Kit

with

Mic

roBl

aze

Avne

t Des

ign

Serv

ices

XC

2V40

00

Prot

otyp

ing,

Dat

a Tr

ansm

issi

on &

Man

ipul

atio

n, H

igh

End

DSP,

IP-b

ased

Sys

tem

s, PC

I

ADS-

XLX-

PMC-

IRL

PMC

IRL

Refe

renc

e De

sign

Kit

Avne

t Des

ign

Serv

ices

XC

2V10

00-4

FG45

6C/F

F896

C Co

nsum

er, I

ndus

tria

l, IR

L, P

AVE,

Tele

com

/Dat

acom

, Tel

ecom

mun

icat

ions

ADS-

XLX-

V2-D

EV15

00

Virt

ex-II

Dev

elop

men

t Kit

w/X

C2V1

500

devi

ce

Avne

t Des

ign

Serv

ices

XC

2V15

00

Com

plet

e ha

rdw

are

envi

ronm

ent t

o de

velo

p, p

roto

type

, and

test

des

igns

targ

eted

to th

e Vi

rtex

-II F

PGA

fam

ily

ADS-

XLX-

V2-D

EV40

00

Virt

ex-II

XC2

V400

0 De

velo

pmen

t Kit

w/X

C2V4

000

devi

ce

Avne

t Des

ign

Serv

ices

XC

2V40

00

Prot

otyp

ing,

Dat

a Tr

ansm

issi

on &

Man

ipul

atio

n, H

igh

End

DSP,

IP-b

ased

Sys

tem

s, PC

I

ADS-

XLX-

V2-D

EV40

00XP

Vi

rtex

-II X

C2V4

000X

P De

velo

pmen

t Kit

w/h

igh-

curr

ent p

ower

sup

ply

Av

net D

esig

n Se

rvic

es

XC2V

4000

Pr

otot

ypin

g. D

ata

Tran

smis

sion

& M

anip

ulat

ion,

Hig

hend

DSP

, IP-

Base

d Sy

stem

s, PC

I

ADS-

XLX-

V2-D

EV60

00XP

Vi

rtex

-II X

C2V6

000

Deve

lopm

ent K

it w

/hig

h-cu

rren

t pow

er s

uppl

y Av

net D

esig

n Se

rvic

es

XC2V

6000

Pr

otot

ypin

g. D

ata

Tran

smis

sion

& M

anip

ulat

ion,

Hig

hend

DSP

, IP-

Base

d Sy

stem

s, PC

I

ADS-

XLX-

V2-E

VL10

00

Virt

ex-II

XC2

V100

0 Ev

alua

tion

Kit

Avne

t Des

ign

Serv

ices

XC

2V10

00-4

FG25

6 Pr

otot

ypin

g, D

ata

Tran

smis

sion

& M

anip

ulat

ion,

Hig

h En

d DS

P, IP

-bas

ed S

yste

ms

ADS-

XLX-

XV2-

EVL

Virt

ex-II

Hig

h-Sp

eed

Eval

uatio

n Ki

t Av

net D

esig

n Se

rvic

es

XC2V

40

Data

Tran

smis

sion

& M

anip

ulat

ion,

DSP

BCPM

Ba

rrac

uda-

PMC+

Bi

ttW

are,

Inc.

XC

2V10

00

DSP,

Data

Tran

smis

sion

& M

anip

ulat

ion,

Em

bedd

ed S

yste

m, I

mag

e Pr

oces

sing

, Mul

timed

ia,

Reco

nfig

urab

le C

ompu

ting,

Tele

com

/Dat

acom

RFPM

Re

ef-P

MC+

Bi

ttW

are,

Inc.

XC

2V10

00

Prot

otyp

ing,

DSP

, Dat

a St

orag

e, D

ata

Tran

smis

sion

& M

anip

ulat

ion,

Dig

ital V

ideo

, Em

bedd

ed

Mic

ropr

oces

sor,

Embe

dded

Sys

tem

, IP-

Base

d Sy

stem

s, Im

age

Proc

essi

ng, L

ow p

ower

des

igns

, M

ultim

edia

, Nav

igat

ion,

PCI

, Rec

onfig

urab

le C

ompu

ting,

Ser

ial/D

eser

ializ

atio

n, D

atac

om /

Tele

com

, Tel

emat

ics,

VoIP

RMPM

Re

mor

a-PM

C+

Bitt

War

e, In

c.

XC2V

1000

Pr

otot

ypin

g, D

SP, D

ata

Stor

age,

Dat

a Tr

ansm

issi

on &

Man

ipul

atio

n, D

igita

l Vid

eo, E

mbe

dded

M

icro

proc

esso

r, Em

bedd

ed S

yste

m, I

P-Ba

sed

Syst

ems,

Imag

e Pr

oces

sing

, Low

pow

er d

esig

ns,

Mul

timed

ia, N

avig

atio

n, P

CI, R

econ

figur

able

Com

putin

g, S

eria

l/Des

eria

lizat

ion,

Dat

acom

/ Te

leco

m, T

elem

atic

s, Vo

IP

CYL2

T020

1-DV

K M

etro

Link

2T-2

Lin

k La

yer E

valu

atio

n Bo

ard

Cypr

ess

Sem

icon

duct

or C

orpo

ratio

n XC

2V20

00

Data

Tran

smis

sion

& M

anip

ulat

ion,

IP-B

ased

Sys

tem

s, Te

leco

m /

Data

com

PF31

00

PC/1

04-P

lus

Reco

nfig

urab

le M

odul

e Bo

ard

(PF3

100)

De

rivat

ion

Syst

ems,

Inc.

XC

2V10

00, F

G25

6 In

tern

et a

pplia

nce,

indu

stria

l con

trol

DN30

00K1

0 DN

3000

K10

ASIC

Pro

toty

ping

Eng

ine

DIN

I Gro

up

XC2V

4000

, XC2

V600

0, X

C2V8

000

Prot

otyp

ing,

DSP

, Dat

a St

orag

e, D

ata

Tran

smis

sion

& M

anip

ulat

ion,

Dig

ital V

ideo

, Em

bedd

ed

Mic

ropr

oces

sor,

Embe

dded

Sys

tem

, IP-

Base

d Sy

stem

s, Im

age

Proc

essi

ng, L

ow p

ower

des

igns

, M

ultim

edia

, Nav

igat

ion,

PCI

, Rec

onfig

urab

le C

ompu

ting,

Ser

ial/D

eser

ializ

atio

n, Te

leco

m/

Data

com

, Tel

emat

ics,

VoIP

DN30

00K1

0 DN

3000

K10

DIN

I Gro

up

XC2V

4000

, XC2

V600

0, X

C2V8

000

Prot

otyp

ing,

Alg

orith

mic

Acc

eler

atio

n, L

ogic

Em

ulat

ion,

PCI

/ PC

I-X, R

econ

figur

able

Com

putin

g

CHM

2-VM

E-60

4-SZ

Ch

amel

eon

II VM

E Re

conf

igur

able

Com

putin

g Bo

ard

DRS

Tact

ical

Sys

tem

s Wes

t, In

c.

XC2V

6000

Pr

otot

ypin

g, D

SP, I

P-Ba

sed

Syst

ems,

Imag

e Pr

oces

sing

, Rec

onfig

urab

le C

ompu

ting,

Tele

com

/ Da

taco

m, T

elem

atic

s

APB-

2V10

00

Virt

ex-II

Pro

toty

ping

Boa

rd fo

r 2V1

000

ErSt

Ele

ctro

nics

XC

2V10

00

Prot

otyp

ing,

Dat

a Tr

ansm

issi

on &

Man

ipul

atio

n, E

mbe

dded

Mic

ropr

oces

sor,

Embe

dded

Sys

tem

, IP

-Bas

ed S

yste

ms,

Imag

e Pr

oces

sing

, Mul

timed

ia, R

econ

figur

able

Com

putin

g, S

eria

l /

Dese

rializ

atio

n, Te

leco

m /

Data

com

, VoI

P

* In

sigh

t Pro

duct

s: A

ppen

d -E

URO

to p

art n

umbe

r for

inte

rnat

iona

l kits

(ex.

DS-

KIT-

2SLC

100-

EURO

); P

ower

Sup

ply

not i

nclu

ded

in -E

URO

kits

Page 127: Xcell Journal Issue 49

Xil

inx O

n B

oard

– D

evelo

pm

en

t R

efe

ren

ce B

oard

sh

ttp

://w

ww

.xil

inx

.co

m/b

oa

rd_s

ea

rch

Summer 2004 Xcell Journal 127

Boar

d Pa

rt N

umbe

r

APB-

2V15

00

Boar

d D

escr

ipti

on

Virt

ex-II

Pro

toty

ping

Boa

rd fo

r 2V1

500

Supp

lier

ErSt

Ele

ctro

nics

Xilin

x D

evic

e Su

ppor

t

XC2V

1500

App

licat

ion

Prot

otyp

ing,

Dat

a Tr

ansm

issi

on &

Man

ipul

atio

n, E

mbe

dded

Mic

ropr

oces

sor,

Embe

dded

Sys

tem

, IP

-Bas

ed S

yste

ms,

Imag

e Pr

oces

sing

, Mul

timed

ia, R

econ

figur

able

Com

putin

g, S

eria

l /

Dese

rializ

atio

n, Te

leco

m /

Data

com

, VoI

P

Virt

ex-II

APB-

2V20

00

Virt

ex-II

Pro

toty

ping

Boa

rd fo

r 2V2

000

ErSt

Ele

ctro

nics

XC

2V20

00

Prot

otyp

ing,

Dat

a Tr

ansm

issi

on &

Man

ipul

atio

n, E

mbe

dded

Mic

ropr

oces

sor,

Embe

dded

Sys

tem

, IP

-Bas

ed S

yste

ms,

Imag

e Pr

oces

sing

, Mul

timed

ia, R

econ

figur

able

Com

putin

g, S

eria

l /

Dese

rializ

atio

n, Te

leco

m /

Data

com

, VoI

P

APB-

2V30

00

Virt

ex-II

Pro

toty

ping

Boa

rd fo

r 2V3

000

ErSt

Ele

ctro

nics

XC

2V30

00

Prot

otyp

ing,

Dat

a Tr

ansm

issi

on &

Man

ipul

atio

n, E

mbe

dded

Mic

ropr

oces

sor,

Embe

dded

Sys

tem

, IP

-Bas

ed S

yste

ms,

Imag

e Pr

oces

sing

, Mul

timed

ia, R

econ

figur

able

Com

putin

g, S

eria

l /

Dese

rializ

atio

n, Te

leco

m /

Data

com

, VoI

P

APB-

2V40

00

Virt

ex-II

Pro

toty

ping

Boa

rd fo

r 2V4

000

ErSt

Ele

ctro

nics

XC

2V40

00

Prot

otyp

ing,

Dat

a Tr

ansm

issi

on &

Man

ipul

atio

n, E

mbe

dded

Mic

ropr

oces

sor,

Embe

dded

Sys

tem

, IP

-Bas

ed S

yste

ms,

Imag

e Pr

oces

sing

, Mul

timed

ia, R

econ

figur

able

Com

putin

g, S

eria

l /

Dese

rializ

atio

n, Te

leco

m /

Data

com

, VoI

P

APB-

2V60

00

Virt

ex-II

Pro

toty

ping

Boa

rd fo

r 2V6

000

ErSt

Ele

ctro

nics

XC

2V60

00

Prot

otyp

ing,

Dat

a Tr

ansm

issi

on &

Man

ipul

atio

n, E

mbe

dded

Mic

ropr

oces

sor,

Embe

dded

Sys

tem

, IP

-Bas

ed S

yste

ms,

Imag

e Pr

oces

sing

, Mul

timed

ia, R

econ

figur

able

Com

putin

g, S

eria

l /

Dese

rializ

atio

n, Te

leco

m /

Data

com

, VoI

P

APB-

2V80

00

Virt

ex-II

Pro

toty

ping

Boa

rd fo

r 2V8

000

ErSt

Ele

ctro

nics

XC

2V80

00

Prot

otyp

ing,

Dat

a Tr

ansm

issi

on &

Man

ipul

atio

n, E

mbe

dded

Mic

ropr

oces

sor,

Embe

dded

Sys

tem

, IP

-Bas

ed S

yste

ms,

Imag

e Pr

oces

sing

, Mul

timed

ia, R

econ

figur

able

Com

putin

g, S

eria

l /

Dese

rializ

atio

n, Te

leco

m /

Data

com

, VoI

P

GVA

-300

DS

P Ha

rdw

are

Acce

lera

tor,

Virt

ex-II

(GVA

-300

) G

V &

Ass

ocia

tes,

Inc.

XC

2V15

00-4

, 200

0-4

or 3

000-

4 DS

P

GVA

-325

DS

P Ha

rdw

are

Acce

lera

tor,

Virt

ex-II

(GVA

-325

) G

V &

Ass

ocia

tes,

Inc.

XC

2V15

00-4

, 200

0-4

or 3

000-

4 DS

P

GVA

-350

DS

P Ha

rdw

are

Acce

lera

tor,

Virt

ex-II

(GVA

-350

) G

V &

Ass

ocia

tes,

Inc.

XC

2V40

00-4

, 600

0-4

or 8

000-

4 DS

P

DS-K

IT-M

BLAZ

E-V2

Vi

rtex

-II M

icro

Blaz

e Ki

t In

sigh

t (M

emec

) Vi

rtex

-II

Embe

dded

mic

ropr

oces

sor

DS-K

IT-V

2LC1

000*

Vi

rtex

-II L

C100

0 In

sigh

t (M

emec

) XC

2V10

00

Digi

tal V

ideo

, Im

age

Proc

essi

ng, T

elec

om /

Data

com

DS-K

IT-V

2LC1

000-

ISE

Virt

ex-II

LC1

000

w/IS

E Fo

unda

tion

and

JTAG

Cab

le

Insi

ght (

Mem

ec)

XC2V

1000

Di

gita

l Vid

eo, I

mag

e Pr

oces

sing

, Tel

ecom

/ Da

taco

m

DS-K

IT-V

2MB1

000*

Vi

rtex

-II M

B 2V

1000

Dev

elop

men

t Kit

Insi

ght (

Mem

ec)

XC2V

1000

-4FG

456C

DS

P, Di

gita

l Vid

eo, E

mbe

dded

Sys

tem

, Im

age

Proc

essi

ng, R

econ

figur

able

Com

putin

g,

Tele

com

/ Da

taco

m,

DS-K

IT-V

2MB1

000-

ISE

Virt

ex-II

MB

2V10

00 D

evel

opm

ent K

it w

/ISE

Foun

datio

n an

d JT

AG C

able

Insi

ght (

Mem

ec)

XC2V

1000

-4FG

456C

DS

P, Di

gita

l Vid

eo, E

mbe

dded

Sys

tem

, Im

age

Proc

essi

ng, R

econ

figur

able

Com

putin

g,

Tele

com

/ Da

taco

m,

Mic

roEn

gine

V-II

CP

U +

FPG

A (V

irtex

-II) M

icro

Engi

ne C

ards

In

trin

syc,

Inc.

Vi

rtex

-II

Embe

dded

Sys

tem

s

ASPE

-100

0 Ad

vanc

ed S

igna

l Pro

cess

ing

Engi

ne (A

SPE)

M

ultip

le A

cces

s Co

mm

unic

atio

ns

XC2V

1000

DS

P, Re

conf

igur

able

Com

putin

g, Te

leco

m /

Data

com

BenA

DDA-

2V25

0-4-

xx

BenA

DDA

Nal

late

ch

XC2V

250

- XC2

V600

0 In

frare

d Pr

oces

sing

, Mob

ile C

omm

unic

atio

ns S

yste

ms,

Mul

ti-ch

anne

l, M

ulti-

mod

e re

ceiv

ers,

Wid

eban

d Ca

ble

Syst

ems

BenB

LUE-

II-2V

4000

-4-0

1 Be

nBLU

E-II

Nal

late

ch

XC2V

4000

- XC

2V80

00

ASIC

Pro

toty

ping

, Im

age

Proc

essi

ng, R

econ

figur

able

Com

putin

g, S

oftw

are

Defin

ed R

adio

Da

ta P

roce

ssin

g

BenD

ATA-

DD-2

V300

0 Be

nDAT

A-DD

N

alla

tech

XC

2V30

00-X

C2V8

000

Data

Tran

smis

sion

& M

anip

ulat

ion,

Imag

e Pr

oces

sing

BenD

ATA-

WS-

2V40

00-4

-01

BenD

ATA-

WS

Nal

late

ch

XC2V

4000

- XC

2V80

00

Imag

e Pr

oces

sing

42-0

55-0

1 SO

NET

/ SD

H A

TM-P

OS

Boar

d N

etQ

uest

Cor

pora

tion

XC2V

4000

Da

ta Tr

ansm

issi

on &

Man

ipul

atio

n, E

mbe

dded

Sys

tem

, IP-

Base

d Sy

stem

s, M

ultim

edia

, Te

leco

m /

Data

com

* In

sigh

t Pro

duct

s: A

ppen

d -E

URO

to p

art n

umbe

r for

inte

rnat

iona

l kits

(ex.

DS-

KIT-

2SLC

100-

EURO

); P

ower

Sup

ply

not i

nclu

ded

in -E

URO

kits

Page 128: Xcell Journal Issue 49

Xil

inx O

n B

oard

– D

evelo

pm

en

t R

efe

ren

ce B

oard

sh

ttp

://w

ww

.xil

inx

.co

m/b

oa

rd_s

ea

rch

128 Xcell Journal Summer 2004

Boar

d Pa

rt N

umbe

r

42-0

59-0

1

Boar

d D

escr

ipti

on

Gig

abit

IP C

onte

nt P

roce

ssor

Boa

rd

Supp

lier

Net

Que

st C

orpo

ratio

n

Xilin

x D

evic

e Su

ppor

t

XC2V

4000

App

licat

ion

Data

Tran

smis

sion

& M

anip

ulat

ion,

Em

bedd

ed S

yste

m, I

P-Ba

sed

Syst

ems,

Mul

timed

ia,

Tele

com

/ Da

taco

m

Virt

ex-II

42-0

60-0

1 SO

NET

/ SD

H / P

DH G

room

er B

oard

N

etQ

uest

Cor

pora

tion

XC2V

3000

Da

ta Tr

ansm

issi

on &

Man

ipul

atio

n, E

mbe

dded

Sys

tem

, IP-

Base

d Sy

stem

s, M

ultim

edia

, Te

leco

m /

Data

com

XL90

00

XL 9

000

Mul

ti-Po

rt C

amer

a Li

nk P

CI F

ram

e G

rabb

er

Nov

tech

XC

2V20

00 (c

an b

e su

bstit

uted

by

XC2V

2000

-XC2

V800

0)

Data

Sto

rage

, Dat

a Tr

ansm

issi

on &

Man

ipul

atio

n, D

igita

l Vid

eo, I

mag

e Pr

oces

sing

GR-

PCI-X

C2V

LEO

N P

CI V

irtex

-II D

evel

opm

ent B

oard

Pe

nder

Ele

ctro

nic

Desi

gn

XC2V

3000

Pr

otot

ypin

g, D

SP, D

ata

Stor

age,

Dat

a Tr

ansm

issi

on &

Man

ipul

atio

n, D

igita

l Vid

eo, E

mbe

dded

M

icro

proc

esso

r, Em

bedd

ed S

yste

m, I

P-Ba

sed

Syst

ems,

Imag

e Pr

oces

sing

, Low

pow

er d

esig

ns,

Mul

timed

ia, N

avig

atio

n, P

CI, R

econ

figur

able

Com

putin

g, S

eria

l/Des

eria

lizat

ion,

Tele

com

/ Da

taco

m, T

elem

atic

s, Vo

IP

Jock

oBoa

rd

Jock

oBoa

rd S

OC

Virt

ex-II

Pro

toty

ping

Pla

tform

Re

alFa

st O

pera

ting

Syst

ems A

B XC

2V10

00

Embe

dded

Sys

tem

s

600-

0042

2 PR

O-3

100

Virt

ex-II

FPG

A Pr

oces

sing

Eng

ine

Spec

trum

Sig

nal P

roce

ssin

g XC

2V30

00, X

C2V6

000

DSP,

Data

Tran

smis

sion

& M

anip

ulat

ion,

Rec

onfig

urab

le C

ompu

ting

650-

0007

5 eP

MC-

8120

Sp

ectr

um S

igna

l Pro

cess

ing

XC2V

6000

DS

P, Da

ta tr

ansm

issi

on &

Man

ipul

atio

n, R

econ

figur

able

Com

putin

g

SMT3

51-G

Mem

ory

Mod

ule

351-

GSu

ndan

ce M

ultip

roce

ssor

Co.

XC

2V10

00

Base

Ban

d Ra

dar S

ampl

ing,

Cel

lula

r / P

CS B

ase

Stat

ions

, Com

mun

icat

ions

, Dig

ital R

adio

Re

ceiv

ers,

Gen

eral

Dat

a Lo

ggin

g, IF

Rad

ar S

ampl

ing,

Mul

ti-Ch

anne

l Rec

eive

rs,

Spec

trum

Ana

lyse

rs

SMT3

51-M

M

emor

y M

odul

e 35

1-M

Su

ndan

ce M

ultip

roce

ssor

Co.

XC

2V10

00

Base

Ban

d Ra

dar S

ampl

ing,

Cel

lula

r / P

CS B

ase

Stat

ions

, Com

mun

icat

ions

, Dig

ital R

adio

Re

ceiv

ers,

Gen

eral

Dat

a Lo

ggin

g, IF

Rad

ar S

ampl

ing,

Mul

ti-Ch

anne

l Rec

eive

rs,

Spec

trum

Ana

lyse

rs

SMT3

65E

DSP

Mod

ule

Sund

ance

Mul

tipro

cess

or C

o.

XC2V

6000

Im

age

Proc

essi

ng, I

ndus

tria

l, M

edic

al, T

elec

omun

icat

ions

SMT3

98-1

000-

4-Z1

FP

GA

Mod

ule

1000

-4-Z

1 Su

ndan

ce M

ultip

roce

ssor

Co.

XC

2V10

00

Base

Ban

d Ra

dar S

ampl

ing,

Cel

lula

r / P

CS B

ase

Stat

ions

, Com

mun

icat

ions

, Dig

ital R

adio

Re

ceiv

ers,

Gen

eral

Dat

a Lo

ggin

g, IF

Rad

ar S

ampl

ing,

Imag

ing,

Mul

ti-Ch

anne

l Rec

eive

rs,

Spec

trum

Ana

lyse

rs

SMT3

98-2

000-

4-Z1

FP

GA

Mod

ule

2000

-4-Z

1 Su

ndan

ce M

ultip

roce

ssor

Co.

XC

2V20

00

Base

Ban

d Ra

dar S

ampl

ing,

Cel

lula

r / P

CS B

ase

Stat

ions

, Com

mun

icat

ions

, Dig

ital R

adio

Re

ceiv

ers,

Gen

eral

Dat

a Lo

ggin

g, IF

Rad

ar S

ampl

ing,

Imag

ing,

Mul

ti-Ch

anne

l Rec

eive

rs,

Spec

trum

Ana

lyse

rs

SMT3

98-3

000-

4-Z4

-Q2

FPG

A M

odul

e 30

00-4

-Z4-

Q2

Sund

ance

Mul

tipro

cess

or C

o.

XC2V

3000

Ba

se B

and

Rada

r Sam

plin

g, C

ellu

lar /

PCS

Bas

e St

atio

ns, C

omm

unic

atio

ns, D

igita

l Rad

io

Rece

iver

s, G

ener

al D

ata

Logg

ing,

IF R

adar

Sam

plin

g, Im

agin

g, M

ulti-

Chan

nel R

ecei

vers

, Sp

ectr

um A

naly

sers

SMT3

98-8

000-

4-Z4

-Q2

FPG

A M

odul

e 80

00-4

-Z4-

Q2

Sund

ance

Mul

tipro

cess

or C

o.

XC2V

8000

Ba

se B

and

Rada

r Sam

plin

g, C

ellu

lar /

PCS

Bas

e St

atio

ns, C

omm

unic

atio

ns, D

igita

l Rad

io

Rece

iver

s, G

ener

al D

ata

Logg

ing,

IF R

adar

Sam

plin

g, Im

agin

g, M

ulti-

Chan

nel R

ecei

vers

, Sp

ectr

um A

naly

sers

SMT3

70

Dual

Cha

nnel

A/D

and

D/A

Mod

ule

Sund

ance

Mul

tipro

cess

or Te

chno

logy

Ltd

. XC

2V10

00

Base

Ban

d Ra

dar S

ampl

ing,

Cel

lula

r / P

CS B

ase

Stat

ions

, Dig

ital R

adio

Rec

eive

rs, G

ener

al D

ata

Logg

ing

and

I/O C

ontr

ol, I

F Ra

dar S

ampl

ing,

Inst

rum

enta

tion,

Mul

ti-Ch

anne

l Rec

eive

rs, S

onar

, Sp

ectr

um A

naly

sers

XT20

00-X

XT

ENSA

Mic

ropr

oces

sor E

mul

atio

n Ki

t (XT

2000

-X)

Tens

ilica

, Inc

. XC

2V60

00-4

Pr

otot

ypin

g, E

mbe

dded

Sys

tem

s

DO-V

2000

-MLT

A Vi

rtex

-II M

ultim

edia

Boa

rd

Xilin

x O

nlin

e St

ore

XC2V

2000

Pr

otot

ypin

g, D

SP, D

ata

Stor

age,

Dat

a Tr

ansm

issi

on &

Man

ipul

atio

n, D

igita

l Vid

eo, E

mbe

dded

M

icro

proc

esso

r, Em

bedd

ed S

yste

m, I

P-Ba

sed

Syst

ems,

Imag

e Pr

oces

sing

, Mul

timed

ia,

Reco

nfig

urab

le C

ompu

ting,

Tele

com

/ Da

taco

m, V

oIP

* In

sigh

t Pro

duct

s: A

ppen

d -E

URO

to p

art n

umbe

r for

inte

rnat

iona

l kits

(ex.

DS-

KIT-

2SLC

100-

EURO

); P

ower

Sup

ply

not i

nclu

ded

in -E

URO

kits

Page 129: Xcell Journal Issue 49

Xil

inx O

n B

oard

– D

evelo

pm

en

t R

efe

ren

ce B

oard

sh

ttp

://w

ww

.xil

inx

.co

m/b

oa

rd_s

ea

rch

Summer 2004 Xcell Journal 129

Boar

d Pa

rt N

umbe

r

HW-A

FX-F

F115

2-20

0

Boar

d D

escr

ipti

on

FF11

52-2

00 P

roto

Boa

rd

Supp

lier

Xilin

x O

nlin

e St

ore

Xilin

x D

evic

e Su

ppor

t

XC2V

3000

, XC2

V400

0, X

C2V6

000,

XC2

V800

0

App

licat

ion

Prot

otyp

ing,

DSP

, Dat

a St

orag

e, D

ata

Tran

smis

sion

& M

anip

ulat

ion,

Em

bedd

ed S

yste

m,

Mul

timed

ia, P

CI, R

econ

figur

able

Com

putin

g, Te

leco

m /

Data

com

, Tel

emat

ics,

VoIP

Virt

ex-II

Virt

ex a

nd V

irte

x-E

HW-A

FX-F

G25

6-20

0 FG

256-

200

Prot

o Bo

ard

Xilin

x O

nlin

e St

ore

XC2V

1000

, XC2

V250

, XC2

V40,

XC2

V500

, XC

2V80

Pr

otot

ypin

g, D

SP, D

ata

Stor

age,

Dat

a Tr

ansm

issi

on &

Man

ipul

atio

n, E

mbe

dded

Sys

tem

, M

ultim

edia

, PCI

, Rec

onfig

urab

le C

ompu

ting,

Tele

com

/ Da

taco

m, T

elem

atic

s, Vo

IP

HW-A

FX-F

G45

6-20

0 FG

456

Virt

ex-II

Pro

to B

oard

Xi

linx

Onl

ine

Stor

e XC

2V10

00, X

C2V2

50, X

C2V5

00

Prot

otyp

ing,

DSP

, Dat

a St

orag

e, D

ata

Tran

smis

sion

& M

anip

ulat

ion,

Em

bedd

ed S

yste

m,

IP-B

ased

Sys

tem

s, M

ultim

edia

, PCI

, Rec

onfig

urab

le C

ompu

ting,

Tele

com

/ Da

taco

m,

Tele

mat

ics,

VoIP

HW-A

FX-F

G67

6-20

0 FG

676

Virt

ex-II

Pro

to B

oard

Xi

linx

Onl

ine

Stor

e XC

2V15

00, X

C2V2

000,

XC2

V300

0 Pr

otot

ypin

g, D

SP, D

ata

Stor

age,

Dat

a Tr

ansm

issi

on &

Man

ipul

atio

n, E

mbe

dded

Sys

tem

, IP

-Bas

ed S

yste

ms,

Mul

timed

ia, P

CI, R

econ

figur

able

Com

putin

g, Te

leco

m /

Data

com

, Te

lem

atic

s, Vo

IP

ADS-

VE-M

B-DE

V Vi

rtex

-E D

evel

opm

ent K

it w

/Mic

roBl

aze

Avne

t Des

ign

Serv

ices

XC

V100

0E

Net

wor

king

, tel

ecom

mun

icat

ion,

dat

a co

mm

unic

atio

n, e

mbe

dded

and

con

sum

er m

arke

ts

ADS-

VE-M

B-EV

L Vi

rtex

-E E

valu

atio

n Ki

t w/M

icro

Blaz

e Av

net D

esig

n Se

rvic

es

XCV1

00E

Net

wor

king

, tel

ecom

mun

icat

ion,

dat

a co

mm

unic

atio

n, e

mbe

dded

and

con

sum

er m

arke

ts

ADS-

XLX-

VE-D

EV

Virt

ex-E

Dev

elop

men

t Kit

Avne

t Des

ign

Serv

ices

XC

V100

0E

Com

mun

icat

ions

, Em

bedd

ed C

ontr

ol, L

AN R

oute

rs, L

AN S

witc

h, N

etw

orki

ng, W

AN A

cces

s, xD

SL E

quip

men

t

ADS-

XLX-

VE-E

VL

Virt

ex-E

Eva

luat

ion

Kit

Avne

t Des

ign

Serv

ices

XC

V100

E

Very

cos

t effe

ctiv

e ev

alua

tion

and

prot

otyp

ing

plat

form

to d

evel

op a

nd te

st d

esig

ns ta

rget

ed

to th

e Vi

rtex

-E d

evic

e

DN20

00K1

0 DN

2000

K10

DIN

I Gro

up

XCV1

000,

XCV

1000

E, X

CV16

00E,

XCV

2000

E Pr

otot

ypin

g, A

lgor

ithm

ic A

ccel

erat

ion,

Log

ic E

mul

atio

n, P

CI /

PCI-X

GVA

-290

DS

P Ha

rdw

are

Acce

lera

tor,

Virt

ex-E

(GVA

-290

) G

V &

Ass

ocia

tes,

Inc.

2-

XCV1

000E

, 160

0E o

r 200

0Es

DSP

BenA

DIC-

2000

E Be

nADI

C N

alla

tech

XC

V200

0E, X

CV60

0E

Mul

ticha

nnel

Dat

a Ac

quis

ition

& S

oftw

are

Radi

o, P

hase

d Ar

ray

Rada

r, Sm

art A

nten

na A

rray

s

BenE

RA-1

000E

-6-A

Be

nERA

N

alla

tech

XC

V100

0E-X

CV20

00E

Com

mun

icat

ions

& R

eal-T

ime

syst

ems,

DSP,

Imag

e Pr

oces

sing

, Rec

onfig

urab

le C

ompu

ting

BenF

AD-2

000E

Be

nFAD

N

alla

tech

XC

V200

0E

Broa

dban

d w

irele

ss/s

atel

lite

com

mun

icat

ions

, Dat

a Ac

quis

ition

/sig

nal a

naly

sis

syst

ems

42-0

47-0

1 SO

NET

/ SD

H P

OS

PCI N

IC C

ard

Net

Que

st C

orpo

ratio

n XC

V600

Da

ta Tr

ansm

issi

on &

Man

ipul

atio

n, IP

-Bas

ed S

yste

ms,

Mul

timed

ia, T

elec

om /

Data

com

42-0

53-0

1 SO

NET

/ SD

H A

TM P

CI N

IC C

ard

Net

Que

st C

orpo

ratio

n XC

V600

Da

ta Tr

ansm

issi

on &

Man

ipul

atio

n, IP

-Bas

ed S

yste

ms,

Mul

timed

ia, T

elec

om /

Data

com

DO-D

I-DSP

-DK2

Xt

rem

eDSP

Dev

elop

men

t Kit

Xilin

x O

nlin

e St

ore

2V30

00

High

Per

form

ance

DSP

DO-D

I-DSP

-DK2

-SG

Xt

rem

eDSP

Dev

elop

men

t Kit

+ S

yste

m G

ener

ator

for D

SP

Xilin

x O

nlin

e St

ore

2V30

00

Hard

war

e in

the

loop

from

Sim

ulin

k us

ing

Syst

em G

ener

ator

sof

twar

e an

d hi

gh p

erfo

rman

ce

DSP

boar

d

HW-A

FX-B

G35

2-10

0 BG

352-

100

Prot

o Bo

ard

Xilin

x O

nlin

e St

ore

XCV1

50, X

CV20

0, X

CV30

0

Prot

otyp

ing,

DSP

, Dat

a St

orag

e, D

ata

Tran

smis

sion

& M

anip

ulat

ion,

Dig

ital V

ideo

, Em

bedd

ed

Syst

em, I

P-Ba

sed

Syst

ems,

Imag

e Pr

oces

sing

, Mul

timed

ia, N

avig

atio

n, P

CI, R

econ

figur

able

Co

mpu

ting,

Tele

com

/ Da

taco

m, T

elem

atic

s, Vo

IP

HW-A

FX-B

G43

2-10

0 BG

432-

100

Prot

o Bo

ard

Xilin

x O

nlin

e St

ore

XCV3

00/E

, XCV

400/

E, X

CV60

0/E,

XCV

800

Prot

otyp

ing,

DSP

, Dat

a St

orag

e, D

ata

Tran

smis

sion

& M

anip

ulat

ion,

Dig

ital V

ideo

, Em

bedd

ed

Syst

em, I

P-Ba

sed

Syst

ems,

Imag

e Pr

oces

sing

, Mul

timed

ia, N

avig

atio

n, P

CI, R

econ

figur

able

Co

mpu

ting,

Tele

com

/ Da

taco

m, T

elem

atic

s, Vo

IP

* In

sigh

t Pro

duct

s: A

ppen

d -E

URO

to p

art n

umbe

r for

inte

rnat

iona

l kits

(ex.

DS-

KIT-

2SLC

100-

EURO

); P

ower

Sup

ply

not i

nclu

ded

in -E

URO

kits

Page 130: Xcell Journal Issue 49

Xil

inx O

n B

oard

– D

evelo

pm

en

t R

efe

ren

ce B

oard

sh

ttp

://w

ww

.xil

inx

.co

m/b

oa

rd_s

ea

rch

130 Xcell Journal Summer 2004

Boar

d Pa

rt N

umbe

r

HW-A

FX-B

G56

0-10

0

Boar

d D

escr

ipti

on

BG56

0-10

0 Pr

oto

Boar

d

Supp

lier

Xilin

x O

nlin

e St

ore

Xilin

x D

evic

e Su

ppor

t

XCV1

000/

E, X

CV16

00E,

XCV

2000

E, X

CV40

0/E,

XC

405E

, XCV

600/

E, X

CV80

0, X

CV81

2E

App

licat

ion

Prot

otyp

ing,

DSP

, Dat

a St

orag

e, D

ata

Tran

smis

sion

& M

anip

ulat

ion,

Dig

ital V

ideo

, Em

bedd

ed

Syst

em, I

P-Ba

sed

Syst

ems,

Imag

e Pr

oces

sing

, Mul

timed

ia, N

avig

atio

n, P

CI, R

econ

figur

able

Co

mpu

ting,

Tele

com

/ Da

taco

m, T

elem

atic

s, Vo

IP

Virt

ex-II

Rock

etPH

Y

Cool

Runn

er-II

HW-A

FX-P

Q24

0-10

0 PQ

240-

100

Prot

o Bo

ard

Xilin

x O

nlin

e St

ore

XCV1

00, X

CV15

0, X

CV20

0, X

CV30

0, X

CV50

Pr

otot

ypin

g, D

SP, D

ata

Stor

age,

Dat

a Tr

ansm

issi

on &

Man

ipul

atio

n, D

igita

l Vid

eo, E

mbe

dded

Sy

stem

, IP-

Base

d Sy

stem

s, Im

age

Proc

essi

ng, M

ultim

edia

, Nav

igat

ion,

PCI

, Rec

onfig

urab

le

Com

putin

g, Te

leco

m /

Data

com

, Tel

emat

ics,

VoIP

HW-A

FX-P

Q24

0-11

0 PQ

240-

110

Prot

o Bo

ard

Xilin

x O

nlin

e St

ore

XCV1

00, X

CV15

0, X

CV20

0, X

CV30

0, X

CV50

Pr

otot

ypin

g, D

SP, D

ata

Stor

age,

Dat

a Tr

ansm

issi

on &

Man

ipul

atio

n, D

igita

l Vid

eo, E

mbe

dded

Sy

stem

, IP-

Base

d Sy

stem

s, Im

age

Proc

essi

ng, M

ultim

edia

, Nav

igat

ion,

PCI

, Rec

onfig

urab

le

Com

putin

g, Te

leco

m /

Data

com

, Tel

emat

ics,

VoIP

HWK-

RPHY

2XFP

-1

Rock

etPH

Y XF

P Ki

t Xi

linx

Sale

s O

ffice

s XG

C112

0 10

G U

ltra

MSA

Da

ta S

tora

ge, D

ata

Stor

age

(10

Gig

abit

Fibr

e Ch

anne

l), D

ata

Tran

smis

sion

& M

anip

ulat

ion,

Da

taco

m (1

0 G

igab

it Et

hern

et),

Seria

l / D

eser

ializ

atio

n, Te

leco

m (S

onet

OC-

192

/ FEC

), Te

leco

m /

Data

com

HWK-

RPHY

2XFP

-M

Rock

etPH

Y XF

P Ki

t with

XFP

Mod

ule

Xilin

x Sa

les

Offi

ces

XGC1

120

10G

Ultr

a M

SA

Data

Sto

rage

, Dat

a St

orag

e (1

0 G

igab

it Fi

bre

Chan

nel),

Dat

a Tr

ansm

issi

on &

Man

ipul

atio

n,

Data

com

(10

Gig

abit

Ethe

rnet

), Se

rial /

Des

eria

lizat

ion,

Tele

com

(Son

et O

C-19

2 / F

EC),

Tele

com

/ Da

taco

m

HWK-

RPHY

-DVL

P Ro

cket

PHY

Deve

lopm

ent K

it Xi

linx

Sale

s O

ffice

s XC

2VP2

0, X

GC1

120

10G

Ultr

a M

SA

Data

Sto

rage

, Dat

a St

orag

e (1

0 G

igab

it Fi

bre

Chan

nel),

Dat

a Tr

ansm

issi

on &

Man

ipul

atio

n,

Data

com

(10

Gig

abit

Ethe

rnet

), En

cryp

tion

Devi

ces,

Rout

ers,

Seria

l / D

eser

ializ

atio

n, Te

leco

m

(Son

et O

C-19

2 / F

EC),

Tele

com

/ Da

taco

m, T

est E

quip

men

t

HW-A

FX-C

OO

L2-2

56M

C Co

olRu

nner

-II E

valu

atio

n Bo

ard

NuH

oriz

ons

XC2C

256

Low

pow

er d

esig

ns

* In

sigh

t Pro

duct

s: A

ppen

d -E

URO

to p

art n

umbe

r for

inte

rnat

iona

l kits

(ex.

DS-

KIT-

2SLC

100-

EURO

); P

ower

Sup

ply

not i

nclu

ded

in -E

URO

kits

ADS-

XLX-

CR2-

EVL

Cool

Runn

er-II

Eva

luat

ion

Kit

Avne

t Des

ign

Serv

ices

XC

2C25

6-VQ

100

Low

pow

er d

esig

ns

Digi

lab-

XC2

Digi

lent

Coo

lRun

ner-I

I Dev

elop

men

t Boa

rd

Digi

lent

XC

2C25

6 Lo

w p

ower

des

igns

, Tel

ecom

/ Da

taco

m

DS-K

IT-2

C256

* Co

olRu

nner

-II D

evel

opm

ent K

it In

sigh

t (M

emec

) XC

2C25

6 Lo

w p

ower

des

igns

DS-K

IT-2

C256

-PAK

* Co

olRu

nner

-II D

evel

opm

ent K

it w

/Web

PACK

CD

and

JTAG

Cab

le

Insi

ght (

Mem

ec)

XC2C

256

Low

pow

er d

esig

ns

MXC

K-10

0-00

3 M

echa

tron

ics

Cool

Runn

er-II

Pro

toty

ping

Boa

rd

Mec

hatr

onic

s Tes

t Equ

ipm

ent

XC2C

64

Embe

dded

Sys

tem

, Low

pow

er d

esig

ns

Page 131: Xcell Journal Issue 49

Xil

inx O

n B

oard

– D

evelo

pm

en

t R

efe

ren

ce B

oard

sh

ttp

://w

ww

.xil

inx

.co

m/b

oa

rd_s

ea

rch

Summer 2004 Xcell Journal 131

Boar

d Pa

rt N

umbe

rBo

ard

Des

crip

tion

Supp

lier

Xilin

x D

evic

e Su

ppor

tA

pplic

atio

n

Cool

Runn

er X

PLA

3

* In

sigh

t Pro

duct

s: A

ppen

d -E

URO

to p

art n

umbe

r for

inte

rnat

iona

l kits

(ex.

DS-

KIT-

2SLC

100-

EURO

); P

ower

Sup

ply

not i

nclu

ded

in -E

URO

kits

ADS-

XLX-

X3-E

VL

XPLA

3 Ev

alua

tion

Kit

Avne

t Des

ign

Serv

ices

XC

R325

6XL

Low

pow

er d

esig

ns

XCR

Digi

lab

Cool

Runn

er D

evel

opm

ent B

oard

Di

gile

nt

XCR3

064X

L Lo

w p

ower

des

igns

ET-X

CR

Emul

atio

n Te

chno

logy

XCR

Dev

elop

men

t Boa

rd

Emul

atio

n Te

chno

logy

, Inc

. XC

R306

4XL

Low

pow

er d

esig

ns

DS-K

IT-X

PLA3

Co

olRu

nner

XPL

A3 D

evel

opm

ent K

it In

sigh

t (M

emec

) XC

R325

6XL

Low

pow

er d

esig

ns

DS-K

IT-X

PLA3

-PAK

Co

olRu

nner

XPL

A3 D

evel

opm

ent K

it w

/Web

PACK

CD

and

JTAG

Cab

le

Insi

ght (

Mem

ec)

XCR3

256X

L Lo

w p

ower

des

igns

MXC

K-10

0-00

2 M

echa

tron

ics

Cool

Runn

er D

evel

opm

ent B

oard

M

echa

tron

ics T

est E

quip

men

t XC

R306

4XL,

XCR

3128

XL

Low

pow

er d

esig

ns

HW-A

FX-D

IGI-X

CR30

64XL

Di

gila

b XC

R bo

ard

NuH

oriz

ons

XCR3

064X

L Lo

w p

ower

des

igns

XC95

00 S

erie

s

PBX-

84

PBX8

4 Xi

linx

Prot

otyp

ing

Boar

d AL

Will

iam

s XC

9510

8, X

C957

2 Em

bedd

ed S

yste

m

DB-C

PLD-

PQ

ASIC

entr

um X

C950

0 De

velo

pmen

t Kit

ASIC

entr

um

XC95

72

Embe

dded

Sys

tem

XC95

Di

gila

b XC

9500

Dev

elop

men

t Boa

rd

Digi

lent

XC

9510

8 Em

bedd

ed S

yste

m

XCR-

DEV-

BRD

XCR

Deve

lopm

ent B

oard

Di

gile

nt

XC95

108,

XCR

3064

XL

Auto

mot

ive,

Nav

igat

ion,

Tele

mat

ics

DS-K

IT-9

5XL*

XC

9572

XL D

evel

opm

ent K

it In

sigh

t (M

emec

) XC

9572

XL-1

0VQ

64

Low

pow

er d

esig

ns

DS-K

IT-9

5XL-

PAK*

XC

9572

XL D

evel

opm

ent K

it w

/Web

PACK

CD

and

JTAG

Cab

le

Insi

ght (

Mem

ec)

XC95

72XL

-10V

Q64

G

ener

al p

urpo

se S

part

an-II

dev

elop

men

t pla

tform

DS-K

IT-9

5XL-

PAK*

XC

9514

4XV

Deve

lopm

ent K

it w

/Web

PACK

CD

and

JTAG

Cab

le

Insi

ght (

Mem

ec)

XC95

144X

V-10

TQ14

4C

Low

pow

er d

esig

ns

DS-K

IT-9

5XV*

XC

9514

4XV

Deve

lopm

ent K

it In

sigh

t (M

emec

) XC

9514

4XV-

10TQ

144C

Lo

w p

ower

des

igns

84-0

050

Logi

cFle

x JK

Mic

rosy

stem

s, In

c XC

9572

XL

DSP,

Data

Sto

rage

, Dat

a Tr

ansm

issi

on &

Man

ipul

atio

n, E

mbe

dded

Mic

ropr

oces

sor,

Embe

dded

Sy

stem

, IP-

Base

d Sy

stem

s, Lo

w p

ower

des

igns

, Ser

ial /

Des

eria

lizat

ion,

Tele

com

/ Da

taco

m

MXC

K-04

4-00

1 CP

LD Ju

nior

Boa

rd

Mec

hatr

onic

s XC

9536

, XC9

572

Ever

ythi

ng, D

atac

om

MXC

K-08

4-00

4 CP

LD P

roto

typi

ng B

oard

M

echa

tron

ics

XC95

72, X

C951

44

Tele

com

, ind

ustr

ial c

ontr

ols,

inst

rum

enta

tions

, etc

.

MP1

000T

X G

igab

it Et

hern

et P

hy P

roto

typi

ng B

oard

M

etan

etw

orks

XC

9514

4XL

Data

Tran

smis

sion

& M

anip

ulat

ion,

Tele

com

/ Da

taco

m

SBX2

SB

X2 S

ystr

onix

Sy

stro

nix

XC95

72

Embe

dded

Sys

tem

Logi

CRAF

T Lo

giCR

AFT

Eval

uatio

n Sy

stem

Xy

lon

d.o.

o.

XCV9

5144

-VQ

100,

XC9

572-

VQ64

; XC

2S15

0-BG

256

on IC

U d

augh

terc

ard

Auto

mot

ive,

Indu

stria

l, Hu

man

-Mac

hine

Inte

rface

s

Page 132: Xcell Journal Issue 49

Xil

inx I

P R

efe

ren

ce G

uid

eh

ttp

://w

ww

.xil

inx

.co

m/i

pce

nte

r

132 Xcell Journal Summer 2004

Function

Virt

ex-II

Pro

Virt

ex-II

Virt

ex-E

Spar

tan-

3

Spar

tan-

IIE

Spar

tan-

II

Vendor Name

Audio, Video & Image Processing

Burst Locked PLL (BURST_PLL) Pinpoint Solutions, Inc. V-II V-E S3 S-IIE

Color Space Converter, RGB2YCrCb (CSC) CAST, Inc. V-II V-E S-IIE S-II

Huffman Decoder (HUFFD) CAST, Inc. V-II V-E S-IIE S-II

JPEG Fast Codec (JPEG_FAST_C) CAST, Inc. V-IIP V-II V-E S3

JPEG, 2000 Encoder (JPEG2K_E) CAST, Inc. V-IIP V-II V-E

JPEG, Fast color image decoder (FASTJPEG_C DECODER) Barco-Silex V-II V-E

JPEG, Fast Decoder (JPEG_FAST_D) CAST, Inc. V-IIP V-II V-E S-IIE

JPEG, Fast Encoder (JPEG_FAST_E) CAST, Inc. V-IIP V-II V-E

JPEG, Fast gray scale image decoder (FASTJPEG_BW DECODER) Barco-Silex V-II V-E

JPEG, Motion Codec V1.0 (CS6190) Amphion Semiconductor, Ltd. V-II V-E

JPEG, Motion Decoder (CS6150) Amphion Semiconductor, Ltd. V-II V-E

JPEG, Motion Encoder (CS6100) Amphion Semiconductor, Ltd. V-II V-E

Motion JPEG Decoder (JPEG Decoder) 4i2i Communications Ltd. V-IIP V-II V-E S3 S-IIE

Motion JPEG Encoder (JPEG Encoder) 4i2i Communications Ltd. V-IIP V-II V-E S3 S-IIE

MPEG-2 HDTV I & P Encoder (DV1 HDTV) Duma Video, Inc. V-II

MPEG-2 SDTV I & P Encoder (DV1 SDTV) Duma Video, Inc. V-II

NTSC Color Separator (NTSC-COSEP) Pinpoint Solutions, Inc. V-II V-E S3 S-IIE

Communication & Networking

ADPCM, 1024 Channel Simplex (CS4190) Amphion Semiconductor, Ltd. V-II

ADPCM, 256 Channel Simplex (CS4130) Amphion Semiconductor, Ltd. V-II V-E

ADPCM, 512 Channel Duplex (CS4180) Amphion Semiconductor, Ltd. V-II

ADPCM, 768 Channel Amphion Semiconductor, Ltd. V-II

AES Decryption Family (CS5200) Amphion Semiconductor, Ltd. V-II V-E S-II

AES Encryption CAST, Inc. V-IIP V-II V-E S3 S-IIE

AES Encryption Family (CS5200) Amphion Semiconductor, Ltd. V-II V-E S-II

AES Standard Encryptor/Decryptor Helion Technology Limited V-IIP V-II V-E S3 S-IIE

AES Tiny Encryptor/Decryptor Helion Technology Limited V-IIP V-II V-E S3 S-IIE

ATM Adaption Layer 1 (AAL1) ModelWare, Inc. V-II V-E

ATM Cell Processor (CC200) Paxonet Communications, Inc. V-IIP V-II

Bit Stream Analyzer and Data Extractor (Parser) Telecom Italia Lab S.p.A. V-IIP V-II S-IIE

Bluetooth Baseband Processor (BOOST Lite) NewLogic GmbH V-II

CAM for Internet Protocol (IPlogiCAM) Telecom Italia Lab S.p.A. V-IIP V-II S-IIE

Convolutional Encoder (CONV_ENC) Telecom Italia Lab S.p.A. V-IIP V-II S-IIE

CRC-32 for 10 Gbps OC192 systems (CORE-CRC-128) Calyptech Design Services S3

CRC-32 for 40 Gbps OC-768 systems (CORE-CRC-256) Calyptech Design Services V-IIP V-II

DES and DES3 Encryption Engine (MC-XIL-DES) Memec Design V-II V-E S-IIE S-II

DES Encryption CAST, Inc. V-II V-E S-II

DES3 Encryption CAST, Inc. V-IIP V-II V-E S3 S-IIE

Distributed Sample Descrambler (DSD) Telecom Italia Lab S.p.A. S-II

Distributed Sample Scrambler (DSS) Telecom Italia Lab S.p.A. S-II

DVB Satellite Modulator (MC-XIL-DVBMOD) Memec Design V-II V-E S-II

Email Trigger Amirix Systems, Inc. V-IIP

Ethernet MAC, 1 Gigabit Full Duplex (PE-GMAC0) Mentor Graphics Corporation V-II

Ethernet MAC, 10/100 Zuken, Inc. V-II V-E

Ethernet MAC, 10/100 (MAC) CAST, Inc. V-IIP V-II S3 S-IIE

Ethernet MAC, 10/100 (PE-MACMII) Mentor Graphics Corporation V-II S-II

Ethernet MAC, 10G (CC410) Paxonet Communications, Inc. V-II

Ethernet PCS, 10G (CC411) Paxonet Communications, Inc. V-IIP V-II

Ethernet PCS, 10G (MC-XIL-10GEPCS) Memec Design V-II

Framer, 1.25 Gb/s GFP (CC224) Paxonet Communications, Inc. V-IIP V-II S3 S-IIE

Framer, 2.5 Gb/s GFP (CC226) Paxonet Communications, Inc. V-IIP V-II

Framer, 8-Bit Multichannel GFP (CC225) Paxonet Communications, Inc. V-IIP V-II

Framer, 8-Bit Transparent GFP (CC124) Paxonet Communications, Inc. V-IIP V-II

Framer, E1 (CC303) Paxonet Communications, Inc. V-IIP V-II S-IIE

Framer, OC12 (CC351) Paxonet Communications, Inc. V-IIP V-II

Framer, OC192/10 GB/s GFP (CC327) Paxonet Communications, Inc. V-IIP V-II

Framer, OTU2 (CC481) Paxonet Communications, Inc. V-IIP V-II

Visit the Xilinx IP Center for more details at www.xilinx.com/ipcenter

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Summer 2004 Xcell Journal 133

Framer, STS192/STM64 (CC314) Paxonet Communications, Inc. V-IIP V-II

Framer, T1 (CC302) Paxonet Communications, Inc. V-IIP V-II S-IIE

Framer/Digital Wrapper, STS48 OTN (CC381) Paxonet Communications, Inc. V-IIP V-II

G.709 Compliant FEC Core (CC345) Paxonet Communications, Inc. V-IIP V-II

HDLC, Single-Channel (MC-XIL-HDLC) Memec Design V-IIP V-II S3

HyperTransport Cave 16-Bit GDA Technologies, Inc. V-IIP V-II

Interleaver Deinterleaver (INT_DEINT) Telecom Italia Lab S.p.A. V-IIP V-II S-IIE

Inverse Multiplexer for ATM (IMA) ModelWare, Inc. V-II V-E

Mapper, E1 (CC333) Paxonet Communications, Inc. V-IIP V-II S-IIE

MD5 Message Digest Algorithm CAST, Inc. V-IIP V-II S3 S-IIE

Noisy Transmission Channel Model (CHANNEL) Telecom Italia Lab S.p.A. V-IIP V-II S-IIE

Path Processor, OC12c (CC321) Paxonet Communications, Inc. V-IIP V-II

Path Processor, STS192/STM64 (CC324) Paxonet Communications, Inc. V-IIP V-II

Reed Solomon Decoder (MC-XIL-RSDEC) Memec Design V-II S-IIE S-II

Reed Solomon Encoder (MC-XIL-RSENC) Memec Design V-II S-IIE S-II

Reed-Solomon Decoder (RS_DEC) Telecom Italia Lab S.p.A. V-IIP V-II S-IIE

SDLC Controller (SDLC) CAST, Inc. V-IIP V-II V-E S3 S-IIE

SHA-1 Encryption Processor CAST, Inc. V-II V-E S-IIE S-II

SPI 4.2 Interface (CC401) Paxonet Communications, Inc. V-IIP V-II

Turbo Decoder (TURBO_DEC) Telecom Italia Lab S.p.A. V-II

Turbo Decoder, 3GPP SysOnChip, Inc. V-II V-E

Turbo Decoder, 3GPP (S3000) iCoding Technology, Inc. V-II V-E S-IIE

Turbo Decoder, DVB-RCS (S2000) iCoding Technology, Inc. V-II V-E

Turbo Decoder, DVB-RCS (TC1000) TurboConcept V-II V-E

Turbo Decoder, UMTS Hardwired Interleaver Telecom Italia Lab S.p.A. V-IIP V-II V-E

Turbo Decoder, UMTS Mother Interleaver (UMTS_ADDRESS_GEN) Telecom Italia Lab S.p.A. V-IIP V-II V-E S-IIE

Turbo Encoder (TURBO_ENC) Telecom Italia Lab S.p.A. V-IIP V-II S-IIE

Turbo Encoder, DVB-RCS (S2001) iCoding Technology, Inc. V-II V-E

Turbo Product Code Decoder, 160 Mbps (TC3404) TurboConcept V-II V-E

Turbo Product Code Decoder, 25 Mbps (TC3000) TurboConcept V-II V-E

Turbo Product Code Decoder, 30 Mbps (TC3401) TurboConcept V-E S-IIE

ATM Utopia Level 2 Master and Slave w/OPB Interface Xilinx V-IIP V-II V-E S-IIE S-II

UTOPIA Level-2 PHY Side RX Interface (UTOPIA L2 PHY Rx) Telecom Italia Lab S.p.A. V-IIP V-II S-IIE

UTOPIA Level-2 PHY Side TX Interface (UTOPIA L2 PHY Tx) Telecom Italia Lab S.p.A. V-IIP V-II S-IIE

UTOPIA RX Level 2 Master Interface (UTOPIA2M_RX) Telecom Italia Lab S.p.A. V-IIP V-II S-IIE

UTOPIA TX Level 2 Master Interface (UTOPIA2M_TX) Telecom Italia Lab S.p.A. V-IIP V-II S-IIE

Viterbi Decoder (VITERBI_DEC) Telecom Italia Lab S.p.A. V-IIP V-II S-IIE

3G FEC Package Xilinx V-II V-E

8b/10b Decoder Xilinx V-IIP V-II V-E S-3 S-IIE S-II

8b/10b Encoder Xilinx V-IIP V-II V-E S-3 S-IIE S-II

AWGN - Additive White Gaussian Noise Xilinx V-IIP V-II

Convolutional Encoder Xilinx V-IIP V-II V-E S-3 S-IIE S-II

Ethernet 1000BASE-X PCS/PMA Xilinx V-IIP

Ethernet MAC, 1 Gigabit Half/Full duplex with GMII or 1000BASE-X PCS/PMA Xilinx V-IIP V-II V-E S-IIE

Ethernet MAC, 10 Gigabit Full Duplex with XGMII or XAUI Xilinx V-IIP V-II

Interleaver/De-interleaver Xilinx V-IIP V-II V-E S-3 S-IIE S-II

Reed Solomon Decoder Xilinx V-IIP V-II V-E S-3 S-IIE S-II

Reed Solomon Encoder Xilinx V-IIP V-II V-E S-3 S-IIE S-II

SPI-3 (POS-PHY L3) Link Layer Interface, 1-Ch Xilinx V-IIP V-II V-E S-IIE S-II

SPI-3 (POS-PHY L3) Link Layer Interface, 2-Ch Xilinx V-IIP V-II V-E S-IIE S-II

SPI-3 (POS-PHY L3) Link Layer Interface, 4-Ch Xilinx V-IIP V-II V-E S-IIE S-II

SPI-3 (POS-PHY L3) Link Layer Interface, Multi-Channel Xilinx V-IIP V-II V-E S-3 S-IIE S-II

SPI-3 (POS-PHY L3) Physical Layer Interface Xilinx V-E

SPI-4.1 (Flexbus 4) Interface Core, 1-Channel Xilinx V-II

SPI-4.1 (Flexbus 4) Interface Core, 4-Channel Xilinx V-II

SPI-4.2 (POS-PHY L4) Multi-Channel Interface Xilinx V-IIP V-II

SPI-4.2 (POS-PHY L4) to SPI-4.1 (Flexbus 4) Bridge Xilinx V-II

SPI-4.2 (POS-PHY L4) to XGMII (10GE MAC) Bridge Xilinx V-II

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134 Xcell Journal Summer 2004

SPI-4.2 Lite (POS_PHY L4) Xilinx V-II S-3

Turbo Decoder, Convolutional, 3GPP Compliant Xilinx V-II V-E

Turbo Decoder, Convolutional, 3GPP2/CDMA2000 Xilinx V-IIP V-II S-3

Turbo Decoder, Product Code Xilinx V-IIP V-II S-3

Turbo Encoder, Convolutional, 3GPP Compliant Xilinx V-II V-E

Turbo Encoder, Convolutional, 3GPP2/CDMA2000 Xilinx V-IIP V-II S-3

Turbo Encoder, Product Code Xilinx V-IIP V-II S-3

Viterbi Decoder, General Purpose Xilinx V-IIP V-II V-E S-3 S-IIE S-II

Viterbi Decoder, IEEE 802-compatible Xilinx V-IIP V-II V-E S-3 S-IIE S-II

XAPP 289: Common Switch Interface CSIX-L1

Reference Design Xilinx V-IIP V-II

XAUI Xilinx V-IIP

Digital Signal Processing

Discrete Cosine Transform (eDCT) eInfochips Pvt. Ltd. V-II V-E S-IIE S-II

Discrete Cosine Transform, 2D Inverse (IDCT) CAST, Inc. V-II V-E S-II

Discrete Cosine Transform, Combined 2D Forward/Inverse (DCT_FI) CAST, Inc. V-II V-E S-II

Discrete Cosine Transform, Forward 2D (DCT) CAST, Inc. V-II V-E S-II

Discrete Cosine Transform, Forward/Inverse (FIDCT) Telecom Italia Lab S.p.A. V-IIP V-II S-IIE

Discrete Cosine Transform, forward/inverse 2D (DCT/IDCT 2D) Barco-Silex V-II V-E S-II

Discrete Wavelet Transform, Combined 2D Forward/Inverse (RC_2DDWT) CAST, Inc. V-II V-E S-II

Discrete Wavelet Transform, Line-based programmable forward (LB_2DFDWT) CAST, Inc. V-II V-E S-II

FIR Filter using DPRAM eInfochips Pvt. Ltd. V-II V-E S-IIE S-II

FIR Filter, Parallel Distributed Arithmetic eInfochips Pvt. Ltd. V-II V-E S-IIE S-II

TMS32025 DSP Processor (C32025) CAST, Inc. V-II V-E S-II

Bit Correlator Xilinx V-IIP V-II V-E S-IIE S-II

Cascaded Integrator Comb (CIC) Filter Xilinx V-IIP V-II V-E S-IIE S-II

CORDIC Xilinx V-IIP V-II V-E S-3 S-IIE S-II

Digital Down Converter (DDC) Xilinx V-IIP V-II V-E S-IIE S-II

Digital Up Converter (DUC) Xilinx V-IIP V-II S-3

Direct Digital Synthesizer (DDS) Xilinx V-IIP V-II V-E S-3 S-IIE S-II

DOCSIS ITU-T J.83 Modulator Xilinx V-IIP V-II S-3

Fast Fourier Transform Xilinx V-IIP V-II S-3

FFT/IFFT for Virtex-II, 1024-Point Complex Xilinx V-II

FFT/IFFT for Virtex-II, 16-Point Complex Xilinx V-II

FFT/IFFT for Virtex-II, 256-Point Complex Xilinx V-II

FFT/IFFT for Virtex-II, 64-Point Complex Xilinx V-II

FFT/IFFT, 1024-Point Complex Xilinx V-E

FFT/IFFT, 16-Point Complex Xilinx V-II V-E

FFT/IFFT, 256-Point Complex Xilinx V-II V-E

FFT/IFFT, 32-Point Complex Xilinx V-IIP V-II V-E S-IIE S-II

FFT/IFFT, 64-, 256-, 1024-Point Complex Xilinx V-IIP V-II S-3

FFT/IFFT, 64-Point Complex Xilinx V-E

FIR Filter, Distributed Arithmetic (DA) Xilinx V-IIP V-II V-E S-3 S-IIE S-II

FIR Filter, MAC Xilinx V-IIP V-II V-E S-3 S-IIE S-II

LFSR, Linear Feedback Shift Register Xilinx V-IIP V-II V-E S-3 S-IIE S-II

Math Function

Floating Point Adder (DFPADD) Digital Core Design V-II S-II

Floating Point Comparator (DFPCOMP) Digital Core Design V-II S-II

Floating Point Divider (DFPDIV) Digital Core Design V-II S-II

Floating Point Multiplier (DFPMUL) Digital Core Design V-II V-E S-II

Floating Point Square Root Operator (DFPSQRT) Digital Core Design V-II V-E S-II

Floating Point to Integer Converter (DFP2INT) Digital Core Design V-II S-II

Integer to Floating Point Converter (DINT2FP) Digital Core Design V-II S-II

Accumulator Xilinx V-IIP V-II V-E S-3 S-IIE S-II

Adder Subtracter Xilinx V-IIP V-II V-E S-3 S-IIE S-II

Divider, Pipelined Xilinx V-II V-E S-IIE S-II

Multiply Accumulator (MAC) Xilinx V-IIP V-II S-3 S-IIE S-II

Multiply Generator Xilinx V-IIP V-II V-E S-3 S-IIE S-II

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Summer 2004 Xcell Journal 135

Sine Cosine Look Up Table Xilinx V-IIP V-II V-E S-3 S-IIE S-II

Twos Complementer Xilinx V-IIP V-II V-E S-3 S-IIE S-II

Memories & Storage Element

RLDRAM Memory Controller Avnet Design Services V-II

SDRAM Controller, DDR (EP525) Eureka Technology V-IIP V-II S3 S-IIE

SDRAM Controller, DDR (MC-XIL-SDRAMDDR) Memec Design V-II V-E S-II

Block Memory, Dual-Port Xilinx V-IIP V-II V-E S-3 S-IIE S-II

Block Memory, Single-Port Xilinx V-IIP V-II V-E S-3 S-IIE S-II

Content Addressable Memory (CAM) Xilinx V-IIP V-II V-E S-3 S-IIE S-II

Distributed Memory Xilinx V-IIP V-II V-E S-3 S-IIE S-II

FIFO, Asynchronous Xilinx V-IIP V-II V-E S-3 S-IIE S-II

FIFO, Synchronous Xilinx V-IIP V-II V-E S-3 S-IIE S-II

Microprocessor, Controller & Peripheral

16450 UART (H16450) CAST, Inc. V-II V-E S-IIE S-II

16450 UART w/Synchronous Interface (H16450S) CAST, Inc. V-II V-E S-IIE S-II

16550 UART w/FIFOs & synch interface (H16550S) CAST, Inc. V-II V-E S-IIE S-II

16550 UART w/FIFOs (H16550) CAST, Inc. V-II V-E S-IIE S-II

2910A Microprogram Controller (C2910A) CAST, Inc. S-II

2D Multiprocessing Interface Fabric (2D-fabric402C) Crossbow Technologies, Inc. V-IIP V-II S-IIE S-II

68000 Compatible Microprocessor (C68000) CAST, Inc. V-IIP V-II V-E S3 S-IIE

80186 Compatible Microprocessor (e80186) eInfochips Pvt. Ltd. V-II

8051 Base Compatible Microcontroller (DR8051BASE) Digital Core Design V-II S-II

8051 Compatible Microcontroller (C8051) CAST, Inc. V-IIP V-II V-E S3 S-IIE S-II

8051 Compatible Microcontroller (FLIP8051 Thunder) Dolphin Integration V-IIP V-II S-IIE

8051 Microcontroller, PicoBlaze Emulated (PB8051-MX/TF) Roman-Jones, Inc. V-IIP V-II S3 S-IIE

8051 RISC Microcontroller (DR8051) Digital Core Design V-II S-II

80515 High-speed 8-bit RISC Microcontroller (R80515) CAST, Inc.

8052 Compatible Microcontroller (DR8052EX) Digital Core Design V-II S-II

80C51 Compatible RISC Microcontroller (R8051) CAST, Inc. V-E S-II

8237 Programmable DMA Controller (C8237) CAST, Inc. V-II V-E S-II

8250 UART (H8250) CAST, Inc. V-II V-E S-IIE S-II

8254 Programmable Interval Timer/Counter (C8254) CAST, Inc. V-II V-E S-II

8254 Programmable Interval Timer/Counter (e8254) eInfochips Pvt. Ltd. V-II S-II

8255 Programmable I/O Controller (e8255) eInfochips Pvt. Ltd. V-II S-II

8259A Programmable Interrupt Controller (C8259A) CAST, Inc. V-II V-E S-II

Compact Video Controller (logiCVC) Xylon d.o.o. V-II S-II

CRT Controller (C6845) CAST, Inc. V-II V-E S-IIE S-II

FPU for Microblaze (Quixilica) QinetiQ Limited V-IIP V-II

Internet Appliance (socPiP-1A_Platform) SoC Solutions, LLC V-II V-E

Java Processor, 32-bit (Lightfoot) Digital Communications Technologies, Ltd. V-II S-II

Java Processor, Configurable (LavaCORE) Derivation Systems, Inc. V-II

MIPS system controller (ES500) Eureka Technology V-II V-E

Motor Controller - 3 phase (MLCA_4) MEET Ltd. S-IIE S-II

Operating System Accelerator (Sierra S16) RealFast Operating Systems AB V-II S-IIE S-II

PIC125x Fast RISC Microcontroller (DFPIC125X) Digital Core Design V-II S-II

PIC1655x Fast RISC Microcontroller (DFPIC1655X) Digital Core Design V-II S-II

PIC165X Compatible Microcontroller (C165X) CAST, Inc. V-IIP V-II V-E S3 S-IIE

PIC165x Fast RISC Microcontroller (DFPIC165X) Digital Core Design V-II V-E S-II

PIC16C55X Compatible RISC Microcontroller (C1655x) CAST, Inc. V-II V-E S-IIE S-II

PowerPC Bus Master (EP201) Eureka Technology V-IIP V-II S3 S-IIE

PowerPC Bus Slave (EP100) Eureka Technology V-IIP V-II S3 S-IIE

RISC Processor, 16-bit Proprietary (AX1610) Loarant Corporation V-IIP V-II S3 S-IIE

UART, Generic Compact (MC-XIL-UART) Memec Design V-IIP V-II S3

XTENSA-V Configurable 32-bit Microprocessor Tensilica, Inc. V-II

Z80 Compatible Microprocessor (CZ80CPU) CAST, Inc. V-II V-E S3 S-II

Z80 Compatible Programmable Counter/Timer (CZ80CTC) CAST, Inc. V-IIP V-II V-E S3 S-IIE

Z80 Peripheral I/O Controller (CZ80PIO) CAST, Inc. V-II V-E S-IIE S-II

1 Gigabit Ethernet MAC w/PLB interface Xilinx V-IIP

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136 Xcell Journal Summer 2004

10/100 Ethernet MAC Lite w/OPB interface Xilinx V-IIP V-II V-E S-IIE S-II

10/100 Ethernet MAC w/OPB interface Xilinx V-IIP V-II V-E S-IIE S-II

16450 UART w/OPB interface Xilinx V-IIP V-II V-E S-3 S-IIE S-II

16550 UART w/OPB interface Xilinx V-IIP V-II V-E S-3 S-IIE S-II

Arbiter and Bus Structure w/OPB interface Xilinx V-IIP V-II V-E S-3 S-IIE S-II

Arbiter and Bus Structure w/PLB interface Xilinx V-IIP

ATM Utopia Level 2 Master and Slave w/OPB Interface Xilinx V-IIP V-II V-E S-IIE S-II

ATM Utopia Level 2 Master and Slave w/PLB Interface Xilinx V-IIP

BRAM Controller w/LMB interface Xilinx V-IIP V-II V-E S-IIE S-II

BRAM Controller w/OPB interface Xilinx V-IIP V-II V-E S-3 S-IIE S-II

BRAM Controller w/PLB interface Xilinx V-IIP

BSP Generator (SW only) Xilinx V-IIP

DCR Bus Structure Xilinx V-IIP

External Memory Controller (EMC) w/OPB interface (Includes support for Flash, SRAM, ZBT, System ACE) Xilinx V-IIP V-II V-E S-3 S-IIE S-II

External Memory Controller (EMC) w/PLB interface (Includes support for Flash, SRAM, ZBT, System ACE) Xilinx V-IIP

GPIO w/OPB interface Xilinx V-IIP V-II V-E S-3 S-IIE S-II

HDLC Controller (Single Channel) w/OPB interface Xilinx V-IIP V-II V-E S-3 S-IIE S-II

HDLC Controller (Multi (256) Channel) w/OPB interface Xilinx V-IIP V-II V-E S-3 S-IIE S-II

IIC w/OPB interface Xilinx V-IIP V-II V-E S-3 S-IIE S-II

Interrupt Controller (IntC) w/DCR interface Xilinx V-IIP V-II V-E S-IIE S-II

Interrupt Controller (IntC) w/OPB interface Xilinx V-IIP V-II V-E S-3 S-IIE S-II

IPIF Address Decode w/OPB interface Xilinx V-IIP V-II V-E S-IIE S-II

IPIF DMA w/OPB interface Xilinx V-IIP V-II V-E S-IIE S-II

IPIF Interrupt Controller w/OPB interface Xilinx V-IIP V-II V-E S-IIE S-II

IPIF Master/Slave Attachment w/OPB interface Xilinx V-IIP V-II V-E S-IIE S-II

IPIF Read/Write Packet FIFO w/OPB interface Xilinx V-IIP V-II V-E S-IIE S-II

IPIF Scatter/Gather w/OPB interface Xilinx V-IIP V-II V-E S-IIE S-II

IPIF Slave Attachment w/PLB interface Xilinx V-IIP

JTAG UART w/OPB interface Xilinx V-IIP V-II V-E S-3 S-IIE S-II

Memory Test Utility (SW only) Xilinx V-IIP

MicroBlaze Soft RISC Processor Xilinx V-IIP V-II V-E S-3 S-IIE S-II

MicroBlaze Source Code Xilinx V-IIP V-II V-E S-3 S-IIE S-II

ML300 VxWorks BSP (SW only) Xilinx V-IIP

OPB2DCR Bridge Xilinx V-IIP

OPB2OPB Bridge (Lite) Xilinx V-IIP V-II V-E S-3 S-IIE S-II

OPB2PCI Full Bridge (32/33) Xilinx V-IIP V-II V-E S-3 S-IIE S-II

OPB2PLB Bridge Xilinx V-IIP

PicoBlaze (XAPP 213: PicoBlaze 8-bit Microcontroller for Virtex-E and Spartan-II/E Devices) - REFERENCE DESIGN Xilinx V-E S-IIE S-II

PicoBlaze (XAPP 627: PicoBlaze 8-bit Microcontroller for Virtex-II and Virtex-II Pro Devices) - REFERENCE DESIGN Xilinx V-IIP V-II

PLB2OPB Bridge Xilinx V-IIP

SDRAM Controller w/OPB interface Xilinx V-IIP V-II V-E S-3 S-IIE S-II

SDRAM Controller w/PLB interface Xilinx V-IIP

SPI Master and Slave w/OPB interface Xilinx V-IIP V-II V-E S-3 S-IIE S-II

Systems Reset Module Xilinx V-IIP

Timebase/Watch Dog Timer (WDT) w/OPB interface Xilinx V-IIP V-II V-E S-3 S-IIE S-II

Timer/Counter w/OPB interface Xilinx V-IIP V-II V-E S-3 S-IIE S-II

UART Lite w/OPB interface Xilinx V-IIP V-II V-E S-3 S-IIE S-II

UltraContoller Solution: A lightweight PowerPC Microcontroller (XAPP672) - REFERENCE DESIGN Xilinx V-IIP

VxWorks Board Support Package (BSP) Xilinx V-IIP

Standard Bus Interface

LIN - Local Interconnect Network Bus Controller (iLIN) Intelliga Integrated Design, Ltd. V-IIP V-II V-E S-3 S-IIE

PCI 64-bit/66-MHz master/target interface (EC240) Eureka Technology V-II V-E

PCI Host Bridge (EP430) Eureka Technology V-II V-E

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Summer 2004 Xcell Journal 137

PCI, 64-bit Target Interface (PCI-T64) CAST, Inc. V-IIP V-II S-IIE

PCI-PCI Bridge (EP440) Eureka Technology V-IIP V-II S-3 S-IIE

Serial Protocol Interface Slave (SPI Slave) CAST, Inc. V-II V-E S-IIE

Two-Wire Serial Interface - I2C (MC-XIL-TWSI) Memec Design V-IIP V-II V-E S-3 S-IIE S-II

USB 1.1 Function Controller (CUSB) CAST, Inc. V-IIP V-II S-3 S-IIE

USB 2.0 Function Controller (CUSB2) CAST, Inc. V-IIP V-II V-E S-3 S-IIE

Arbiter Telecom Italia Lab S.p.A. V-IIP V-II S-IIE

CAN 2.0 B Compatible Network Controller (LogiCAN) Xylon d.o.o. V-IIP V-II S-3 S-IIE

CAN Bus Controller (MC-XIL-OPB-XCAN) Memec Design V-IIP V-II V-E S-3 S-IIE S-II

CAN Bus Controller 2.0B CAST, Inc. V-IIP V-II S-3 S-IIE

CAN Bus Controller with 32 Mail Boxes Robert Bosch GmbH V-IIP V-II S-3 S-IIE

HyperTransport Cave, 8-bit GDA Technologies, Inc. V-IIP V-II

I2C Bus Controller (I2C) CAST, Inc. V-II V-E S-3 S-II

I2C Bus Controller Master (DI2CM) Digital Core Design V-II V-E S-II

I2C Bus Controller Slave (DI2CS) Digital Core Design V-II V-E S-II

I2C Bus Controller Slave Base (DI2CSB) Digital Core Design V-II V-E S-II

I2C Two-Wire Serial Interface Master-Only (MC-XIL-TWSIMO) Memec Design V-II V-E S-IIE S-II

I2C Two-Wire Serial Interface Master-Slave (MC-XIL-TWSIMS) Memec Design V-II V-E S-IIE S-II

HyperTransport Single-Ended Slave Core Xilinx V-IIP V-II

Advanced Switching Endpoint Core Xilinx V-IIP

PCI Express Endpoint Core Xilinx V-IIP

PCI32 Interface Design Kit (DO-DI-PCI32-DKT) Xilinx V-IIP V-II V-E S-IIE S-II

PCI32 Interface, IP Only (DO-DI-PCI32-IP) Xilinx V-IIP V-II V-E S-3 S-IIE S-II

PCI32 Single-Use License for Spartan (DO-DI-PCI32-SP) Xilinx S-3 S-IIE S-II

PCI64 & PCI32, IP Only (DO-DI-PCI-AL) Xilinx V-IIP V-II V-E S-3 S-IIE S-II

PCI64 Interface Design Kit (DO-DI-PCI64-DKT) Xilinx V-IIP V-II V-E S-IIE S-II

PCI64 Interface, IP Only (DO-DI-PCI64-IP) Xilinx V-IIP V-II V-E S-IIE S-II

PCI-X 64/133 Interface for Virtex-II (DO-DI-PCIX64-VE).Includes PCI 64 bit interface at 33 MHz Xilinx V-IIP V-II

PCI-X 64/66 Interface for Virtex-E (DO-DI-PCIX64-VE).Includes PCI 64 bit interface at 33 MHz Xilinx VE

RapidIO 8-bit port LP-LVDS Phy Layer (DO-DI-RIO8-PHY) Xilinx V-IIP V-II

RapidIO Logical (I/O) and Transport Layer (DO-DI-RIO8-LOG) Xilinx V-IIP V-II

RapidIO Phy Layer to PLB Bridge reference design - REFERENCE DESIGN Xilinx V-IIP

XAPP653: Virtex-II Pro/Spartan-3 3.3V PCI Reference Design - REFERENCE DESIGN Xilinx V-IIP S-3

Backplanes and Gigabit Serial I/O

Aurora 201, 401and 804 Designs - REFERENCE DESIGN Xilinx V-IIP

WP160: Emulating External SERDES Devices with Embedded RocketIO Transceivers - WHITE PAPER Xilinx V-IIP

XAPP 649: SONET Rate Conversion in Virtex-II Pro Devices - REFERENCE DESIGN Xilinx V-IIP

XAPP 651: SONET and OTN Scramblers/Descramblers - REFERENCE DESIGN Xilinx V-IIP

XAPP 652: Word Alignment and SONET/SDH Framing - REFERENCE DESIGN Xilinx V-IIP

XAPP660: Partial Reconfiguration of RocketIO Attributes using PPC405 core (DCR Bus) - REFERENCE DESIGN Xilinx V-IIP

XAPP661: RocketIO Transceiver Bit-Error Rate Tester (BERT) - REFERENCE DESIGN Xilinx V-IIP

XAPP662: Partial Reconfig. of RocketIO Attributes using PPC405 core (PLB or OPB bus) + RocketIO Transceiver Bit-Error Rate Tester (BERT) - REFERENCE DESIGN Xilinx V-IIP

Page 138: Xcell Journal Issue 49

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171

Page 139: Xcell Journal Issue 49

FPGA

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