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THE AUTHORITATIVE JOURNAL FOR PROGRAMMABLE LOGIC USERS Issue 49 Summer 2004 R Xcell journal Xcell journal THE AUTHORITATIVE JOURNAL FOR PROGRAMMABLE LOGIC USERS ISSUE 49, SUMMER 2004 XCELL JOURNAL XILINX, INC. COVER STORY Celebrating 20 Years of Leadership COVER STORY Celebrating 20 Years of Leadership Designing High-Speed Serial Links Designing High-Speed Serial Links SIGNAL INTEGRITY Issues, Tools, and Methodologies High-Speed Interconnect Debugging MGT Designs Power Distribution Networks BACKPLANES Next-Generation Serial Backplanes Create ATCA-Compliant Designs Mesh Fabric Switching DSP XtremeDSP Kit-II Increase Image Processing System Performance Low-Cost Co-Processing SIGNAL INTEGRITY Issues, Tools, and Methodologies High-Speed Interconnect Debugging MGT Designs Power Distribution Networks BACKPLANES Next-Generation Serial Backplanes Create ATCA-Compliant Designs Mesh Fabric Switching DSP XtremeDSP Kit-II Increase Image Processing System Performance Low-Cost Co-Processing

Xcell Journal Issue 49

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  • T H E A U T H O R I T A T I V E J O U R N A L F O R P R O G R A M M A B L E L O G I C U S E R S

    Issue 49Summer 2004

    R

    Xcell journalXcell journalT H E A U T H O R I T A T I V E J O U R N A L F O R P R O G R A M M A B L E L O G I C U S E R S

    ISSUE 49, SUMM

    ER 2004XCELL JOURNAL

    XILINX, INC.

    COVER STORYCelebrating 20 Years of Leadership

    COVER STORYCelebrating 20 Years of Leadership

    Designing High-SpeedSerial Links

    Designing High-SpeedSerial Links

    SIGNAL INTEGRITY

    Issues, Tools, andMethodologies

    High-Speed Interconnect

    Debugging MGT Designs

    Power DistributionNetworks

    BACKPLANES

    Next-Generation SerialBackplanes

    Create ATCA-CompliantDesigns

    Mesh Fabric Switching

    DSP

    XtremeDSP Kit-II

    Increase Image ProcessingSystem Performance

    Low-Cost Co-Processing

    SIGNAL INTEGRITY

    Issues, Tools, andMethodologies

    High-Speed Interconnect

    Debugging MGT Designs

    Power DistributionNetworks

    BACKPLANES

    Next-Generation SerialBackplanes

    Create ATCA-CompliantDesigns

    Mesh Fabric Switching

    DSP

    XtremeDSP Kit-II

    Increase Image ProcessingSystem Performance

    Low-Cost Co-Processing

  • Your AASSIICC

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    FPGA. Our unique staggered pad technology delivers a ton of I/Os for total connectivity

    solutions. Plus our XCITE technology improves signal integrity, while eliminating hundreds

    of resistors to simplify board layout and reduce your bill of materials.

    With the lowest cost per I/O and lowest cost per logic cell, Spartan-3 Platform

    FPGAs are the perfect fit for any design and any budget.

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    2004 Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124. Europe +44-870-7350-600; Japan +81-3-5321-7711; Asia Pacific +852-2-424-5200; Xilinx is a registered trademark, Spartan and XtremeDSP are trademarks, and The Programmable Logic Company is a service mark of Xilinx, Inc.

  • AAs I was preparing to write this editorial, I asked myself: What did I do in the past that was relativelysimple then, but has gotten vastly more complicated now? The answer was tuning up a cars engine.Ive always liked cars. As a teenager, I would get together with my buddies on weekends to extractthe finest performance from our machines. We lived for the automotive trinity: high speed, loudsounds, and great looks.I remember replacing the spark plugs, which were factory-set to a gap clearance specific to my carsengine. However, this factory setting was rarely correct. If the gap was too wide, I tapped the end ofthe spark plug on the garage floor and remeasured. If it was too tight, I used a screwdriver to spreadopen the electrode, widening the gap.

    Tuning up a cars engine used to be quite easy. I wasnt concerned with tight tolerances close wasgood enough. But advances in automotive technology have made it virtually impossible for me towork on my car anymore.

    Similarly, advances in PCB technologies pose far more difficult engineering challenges today thanthey did just a short time ago. Feature size reduction, market demands, and the need for reducedpower consumption have driven core voltages down and operating frequencies up. These changes insignal voltage and frequency require new design practices that take into account electrical effects thatcould previously be ignored.

    This issue features a section on signal integrity issues, tools, and methodologies pertaining to high-speed PCB design. We also have a section on end-to-end programmable solutions for line cards andhigh-speed serial backplanes. Together with many of our partners, Xilinx is addressing these issues tohelp you resolve the technical difficulties that affect performance, system development, and productintroduction schedules.

    As the new Managing Editor for Xcell, Id like your feedback on the signal integrity series in thisissue, as I endeavor to continually improve the magazine. Please visit our website atwww.xilinx.com/si_xcell.htm, where you will find a short survey form.

    L E T T E R F R O M T H E E D I T O R

    Xilinx, Inc.2100 Logic DriveSan Jose, CA 95124-3400Phone: 408-559-7778FAX: 408-879-47802004 Xilinx, Inc.All rights reserved.

    Xcell is published quarterly. XILINX, the Xilinx logo,CoolRunner, RocketChips, Rocket IP, Spartan, StateBENCH,StateCAD, Virtex, Virtex-II, and XACT are registered trade-marks of Xilinx, Inc. ACE Controller, ACE Flash, AllianceSeries, AllianceCORE, Bencher, ChipScope, ConfigurationLogic Cell, CORE Generator, CoreLINX, Dual Block, EZTag,Fast CLK, Fast CONNECT, Foundation, Gigabit SpeedsandBeyond!, HardWire, HDL Bencher, IRL, J Drive, Jbits, LCA,LogiBLOX, Logic Cell, Logic Professor, MicroBlaze, MicroVia,MultiLINX, NanoBlaze, PicoBlaze, PLUSASM, PowerGuide,PowerMaze, QPro, Real-PCI, RocketIO, RocketPHY, SelectIO,SelectRAM, SelectRAM+, Silicon Xpresso, Smartguide,Smart-IP, SmartSearch, SMARTswitch, System ACE, TestbenchIn A Minute, TrueMap, UIM, VectorMaze, VersaBlock,VersaRing, Virtex-4, Virtex-II Pro, Virtex-II Pro X, Virtex-IIEasyPath, Wave Table, WebFITTER, WebPACK,WebPOWERED, XABLE, XAPP, X-BLOX+, XC designated prod-ucts, XChecker, XDM, XEPLD, Xilinx Foundation Series, XilinxXDTV, Xinfo, XtremeDSP, and ZERO+ are trademarks, andThe Programmable Logic Company is a service mark ofXilinx, Inc. Other brand or product names are registeredtrademarks or trademarks of their respective owners.

    The articles, information, and other materials included inthis issue are provided solely for the convenience of ourreaders. Xilinx makes no warranties, express, implied,statutory, or otherwise, and accepts no liability with respectto any such articles, information, or other materials ortheir use, and any use thereof is solely at the risk of theuser. Any person or entity using such information in anyway releases and waives any claim it might have againstXilinx for any loss, damage, or expense caused thereby.

    Close Isnt Good Enough Anymore

    Xcell journalXcell journal

    Forrest CouchManaging Editor

    EDITOR IN CHIEF Carlis [email protected]

    MANAGING EDITOR Forrest [email protected]

    ASSISTANT MANAGING EDITOR Charmaine Cooper Hussain

    XCELL ONLINE EDITOR Tom [email protected]

    ADVERTISING SALES Dan Teie1-800-493-5551

    ART DIRECTOR Scott Blair

  • For Synchronous Signals, Timing Is EverythingMentor Graphics highlights a proven methodology forimplementing pre-layout Tco correction and flight timesimulation with Virtex-II and Virtex-II Pro FPGAs.

    T A B L E O F C O N T E N T S

    High-Speed PCB Design: Issues, Tools, and MethodologiesIn this series on signal integrity, Xcell explores tools andmethods you can use to combat signal and power integritydistortions throughout product development.

    Celebrating 20 Years of LeadershipCelebrating 20 Years of Leadership

    When the Xilinx founders created their first business plan in 1984, they agreed on a lofty goal: To be the leading company designing, manufacturing, marketing, and supporting user-configurable logic arrays for the application-specific market.

    58C O V E R S T O R Y

    9

    58

    The Next Gold StandardThe Advanced Telecom Compute Architecture standardhas great potential for widespread adoption in next-generation infrastructure applications.

    66

    16

  • Secure Your ConsumerDesign with CoolRunner-II CPLDsCoolRunner-II CPLDs offer unique features to ensure a more secure design and reduce the risk of reverse engineering. 92

    Create ATCA-CompliantDesigns Xilinx and Avnet have released a new design kit that reduces time to market for a wide range of serial backplane applications.

    65

    S U M M E R 2 0 0 4, I S S U E 4 9 Xcell journalXcell journalBackplane CharacterizationTechniquesHigh-bandwidth measurements of backplane differential channels are critically important for all high-speed serial links.

    31

    Better... Stronger...FasterVirtex-II Pro FPGAs offer marked performance advantages over a competing device.

    53

    Celebrating 20 Years of Leadership . . . . . . . . . . . . . . . . . . . .6

    High-Speed PCB Design: Issues, Tools, and Methodologies . . . . .9

    Interfacing SMA Connectors to Virtex-II Pro MGTs . . . . . . . . . .12

    For Synchronous Signals, Timing Is Everything . . . . . . . . . . . .16

    Designing High-Speed Interconnects for FPGAs . . . . . . . . . . . .20

    Accurate Multi-Gigabit Link Simulation with HSPICE . . . . . . . .24

    Eyes Wide Open . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

    Backplane Characterization Techniques . . . . . . . . . . . . . . . . .31

    A Low-Cost Solution for Debugging MGT Designs . . . . . . . . . .36

    Tolerance Calculations in Power Distribution Networks . . . . . . .40

    High-Speed PCB Design Resources . . . . . . . . . . . . . . . . . . . .44

    The FPGA Dynamic Probe . . . . . . . . . . . . . . . . . . . . . . . . . .47

    Xilinx 6.2i Design Tools . . . . . . . . . . . . . . . . . . . . . . . . . . .50

    Better ... Stronger ... Faster . . . . . . . . . . . . . . . . . . . . . . . .53

    The Next Gold Standard . . . . . . . . . . . . . . . . . . . . . . . . . . .58

    Next-Generation Serial Backplanes . . . . . . . . . . . . . . . . . . . .62

    Create ATCA-Compliant Designs . . . . . . . . . . . . . . . . . . . . . .65

    Ethernet Aggregation with GFP Framing in Virtex-II Pro . . . . . .68

    Mesh Fabric Switching with Virtex-II Pro FPGAs . . . . . . . . . . .71

    Programming Flash Memory Using the JTAG Port . . . . . . . . . .77

    Developing the New Platform Flash PROM . . . . . . . . . . . . . .80

    Accelerate and Verify Algorithms with XtremeDSP Kit-II . . . . . .82

    Increase Image Processing System Performance with FPGAs . .85

    Enabling Low-Cost DSP Co-Processing with Spartan-3 FPGAs . .88

    Secure Your Consumer Design with CoolRunner-II CPLDs . . . . .92

    Improving Synplify Pro Performance for FPGA Designs . . . . . .94

    Virtex-II and Spartan-3 Aid Wireless Control Networking . . . . .97

    Creating Pb-Free Packaging . . . . . . . . . . . . . . . . . . . . . . . .100

    TechXclusives: A Valuable Source of Information . . . . . . . . . .104

    Reference Pages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109

    To subscribe to the Xcell Journal or to view the web-based Xcell Online Journal, visit www.xilinx.com/publications/xcellonline/.

  • By Xilinx Staff

    In 1984 when Xilinx was founded, config-urable logic arrays were viewed as exoticcuriosities, the semiconductor industry wasmired in a slump, and the personal computer destined to become the driving force in sili-con consumption had just been introducedto skeptical reviews. Thats why many peoplethought that Xilinx founders Ross Freeman,Bernie Vonderschmitt, and Jim Barnett wereoverly ambitious with their written missive.But the driving force in their plans was thegoal of leadership that sometimes vague,often elusive goal that all high technologycompanies seek but few ever attain.

    Today, everyone in the industry knowsthat the Xilinx founders made good on theirpromise. As we enter our third decade as thepreeminent supplier of programmable logicdevices (owning more than 50 percent of themarket), we increasingly find that our tech-nology is the preferred choice for most digitallogic designs. By almost any definition, Xilinxis setting a new standard for success.

    Indeed, todays stated vision makes ourfounding fathers objective seem comparativelytame. As Xilinx celebrates its 20th year inbusiness, our market leadership is unques-tioned and our current goal stretches far intouncharted territory: To put a programmabledevice in every piece of electronic equipmentwithin the next 10 years. This guiding prin-ciple is etched into the mind of every Xilinx

    Celebrating 20 Years of Leadership

    Xilinx CEO Wim Roelandts in the Xilinx Hall of Patents.

    6 Xcell Journal Summer 2004

    When the Xilinx founders created their first business plan in 1984,they agreed on a lofty goal: To be the leading company designing,manufacturing, marketing, and supporting user-configurable logicarrays for the application-specific market.

  • employee around the world, and is theemotional force behind the steady streamof innovation and operational excellencefor which Xilinx is known.

    Leadership Starts from WithinTalk to our CEO Wim Roelandts aboutleadership, and you wont hear a lot aboutmarket share dominance, a litany of indus-try firsts, or impressive statistics that typifymost companies definitions of what itmeans to be a leader. Instead, Wim speakspassionately about core values, manage-ment philosophy, corporate culture, andbuilding a legacy. Thats why the secondXilinx company goal is: To build a compa-ny that sets a new standard for managinghigh-tech companies. Xilinx was namedThe Best Managed SemiconductorCompany by Forbes magazine in 2004, justone indicator that this goal is now a reality.

    Wims own style draws upon his years ofexperience at Hewlett-Packard, somethingof a high-tech pioneer itself in terms of cor-porate culture with its legendary HP Way.But he makes it clear that his teams goal forXilinx is a new, unique style of management:one that combines the best of traditionalhard-driving, top-down, win-at-all-costsapproaches with softer, consensus-orient-ed, people-centric models. And he insistsyou can have the best of both worlds. Wehave a culture where people are treated withrespect, where there is consensus manage-ment, and still we are a leader. How do wedo it? Through innovation! We have aprocess that fosters innovation, and withinnovation comes leadership.

    VP of Human Resources Peg Wynndescribes the competitive attitude at Xilinxlike this: Were fierce competitors withhearts of gold. That competitive attitudehas led to no shortage of innovation andindustry firsts at Xilinx during its first 20years, as more than 900 patents attest. Sucha record of achievement is the result of awell-thought-out process to inspireemployees to greatness, with a business

    well as earn us a top-10 rating in Fortunemagazines Best Places To Work for thelast four years.

    Innovation and LeadershipXilinx has put the structure in place tomake all employees and partners success-ful. It begins with focus. From our incep-tion in 1984, Xilinx strategy has relied ona partnership model through which wedevelop mutually beneficial relationshipswith experts in manufacturing, sales, andother activities that are impractical for usto do ourselves. For example, companyfounder Bernie Vonderschmitt essentiallyinvented the fabless semiconductor modelon a handshake agreement with Seiko in1984. That agreement saw the first Xilinx-designed chips roll off the manufacturinglines at Seikos plants. Today, Xilinx relies and in fact, drives forward our manu-facturing partners as we reach new mile-stones together.

    Since 1984, Xilinx has developed anextensive and growing ecosystem of part-nerships for a wide variety of needs. Wepartner with experts in sales, design tools,intellectual property cores, and chip designservices a strategy that has allowed anunwavering focus on our own areas of corecompetence: designing, marketing, andsupporting our programmable chips. Youcan only be a leader in a few areas so youhave to define where you want to be aleader and use partners to complementwhat you do, says Wim. We want to bea leader in technology and in innovation.To do that, we need partners and therealways has to be something in it for thepartner it has to make them better. Ourphilosophy on partnerships is that itshould minimally be a ratio of 51 to 49, infavor of our partner.

    The Xilinx track record of innovation isimpressive. Since inventing the FPGA in1984, Xilinx has progressively achievednew technological milestones ahead of itscompetition, and set new standards for

    model that allows the company to focus onwhat it does best.

    A Holistic Management PhilosophyXilinx leadership is based on its ability tocontinuously innovate. Therefore, its man-agement philosophy is based on simpletenets:

    People want to do a good job and theycome to Xilinx to do their best work

    Work has to have meaning and value

    The company must provide a sense of community

    There must be an opportunity for personal growth

    Everyone should be an owner.

    Because of this, a rare team attitudeexists at Xilinx that is not often found inthe hallways and meeting rooms of otherhigh-technology companies. It mesheswith a sense of quiet confidence that per-vades the company. In fact, about theonly leadership statistic that Wim likesto spend any time discussing is anemployee retention percentage that is theenvy of the industry. We have set thestandard for employee turnover in ourindustry. Its something like five or sixpercent, compared to an average in themid 20s in our business.

    Wim talks a lot about the importance ofwalking the talk, or as he puts it, main-taining consistency and credibility withthe employee base as well as with the com-panys other stakeholders: partners, cus-tomers, and shareholders. Its one reasonwhy he is fanatical about returning e-mailsfrom employees, and moves his office everyyear to a new location to get a differentperspective on the company. Such an atti-tude underpins a sense of values andintegrity that has led Xilinx to be voted theMost Respected Public Company by itspeers in the Fabless SemiconductorOrganization (FSA) two years in a row, as

    Summer 2004 Xcell Journal 7

    Since inventing the FPGA in 1984, Xilinx has progressively achieved new technological milestones ahead of its competition.

  • semiconductor design. Most recently, wewere the first to produce productiondevices in 90 nm process geometries. Alongwith Intel, we are also producing themost chips on state-of-the-art 300 mmwafers both testaments to the designprowess of our engineering teams. Notcontent to rest on our laurels or followtrends, Xilinx management proudly pointsto the ratio of employees working on futurebusiness activities: about three-quarters ofthe company.

    Being a leader means taking risks, saysVP of Marketing Sandeep Vij. And theculture here at Xilinx rewards risk-taking.The whole concept behind our technology programmability was based on a giant

    risk by the founders. Thats what inspiresinnovation. Because of the way we are setup, every employee feels like an owner,people feel like they are part of a team;theyre part of something beyond an indi-vidual contribution. And with innovationcomes leadership, although its not alwaysan overnight effect.

    In fact, Sandeep looks at the first 20years of Xilinx in two distinct phases.First was the decade that saw the first fewgenerations of products take shape; mar-ket adoption of programmable technolo-gy happened on a gradual basis. Nextcame the decade when Xilinx productsbecame more mainstream; new mile-stones were reached including one mil-lion devices shipped, one billiontransistors on a chip, and $1 billion inrevenue. Leadership is different thanbeing a winner, Sandeep notes. In ourview of the world, there can be more thanone winner in fact, thats required

    because we want our partners to win too.There are a lot of intangibles in being aleader. A leader evokes respect. A leaderinspires people to follow. A leader has tolook at whats happening today and see itsimpact on the future. Thats what thefounders of Xilinx did 20 years ago, andthats what we must continuously do now.

    Leading the Way to the FutureWim likes to call Xilinx a reconfigurablecompany, a tribute not just to the innovativetechnology the company delivers to a widerange of electronics companies, but also tothe flexible management style that he sees asessential to survival in high technology. Thechallenge is in keeping Xilinx nimble andresponsive. Every day we change. Whetherits the technology, a business process, or ourgeographical focus, we have to be comfort-able with change. And we have to continueto re-innovate from within. What elsewould you expect from the company thatinvented programmable chips?

    Original Xilinx MissionStatement 1984

    To be the leading company designing, manufacturing, marketing, and supporting

    user-configurable logic arrays for the application-

    specific market.

    Xilinxs strategies to be the leading company are:

    1. Maximize our strengths in product architecture and design

    2. Complement our strengths witha long-term fab partner who hashigh quality, high volume, com-petitive cost capability, and state-of-the-art process technology

    3. Provide a logic solution that is easier to design-in and morecost-effective than SSI/MSI, PALS,and gate arrays with densities of4,000 to 5,000 unit cells

    4. Provide support for all user volumes with both softwired and hardwired products

    5. Develop and support design tools to minimize the customersdesign efforts

    8 Xcell Journal Summer 2004

  • by Suresh Sivasubramaniam Senior Design EngineerXilinx, [email protected]

    Philippe GarraultTechnical Marketing EngineerXilinx, [email protected]

    RocketIO transceivers are a standard fea-ture on the most advanced Xilinx FPGAs.Our first-generation transceivers operate inthe 1-3.125 Gbps bandwidth, while the lat-est generation transceivers have an operat-ing bandwidth of up to 10 Gbps.

    These data rates mean that bit periodand signal rise and fall times are extremelysmall. Designing physical links/channelson a PCB for these high-speed deviceswith small amplitude and timing budgetsnecessitates a careful analysis of the possiblesignal integrity (SI) and power integrity(PI) distortions.

    SI/PI issues and reduced amplitude andtiming budgets are not limited to just high-speed serial links. In recent years, theamount of logic cells inside Xilinx deviceshas grown tremendously. Additionally, thepin count on device packages has gone froma few to more than a thousand. IncreasedI/O performance, in conjunction with thelarge number of I/Os available, means thatfor each of your new designs, a lot moretransistors are switching more often.

    High-Speed PCB Design:Issues, Tools, and Methodologies

    High-Speed PCB Design:Issues, Tools, and Methodologies

    Summer 2004 Xcell Journal 9

    In this series on signal integrity, Xcell explores tools and methods you can use to combat signal and power integrity distortions throughout product development.

    In this series on signal integrity, Xcell explores tools and methods you can use to combat signal and power integrity distortions throughout product development.

    Table of Contents:

    Ten Reasons Why Performing SI Simulations is a Good Idea . . . . . . . 11

    Interfacing SMA Connectors to Virtex-II Pro MGTs . . . . . . . . . . . . . . . 12

    For Synchronous Signals, Timing Is Everything . . . . . . . . . . . . . . . . . 16

    Designing High-Speed Interconnects for High-Bandwidth FPGAs. . . . . . 20

    Accurate Multi-Gigabit Link Simulation with HSPICE. . . . . . . . . . . . . . 24

    Eyes Wide Open . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

    Backplane Characterization Techniques . . . . . . . . . . . . . . . . . . . . . . 31

    A Low-Cost Solution for Debugging MGT Designs . . . . . . . . . . . . . . . 36

    Tolerance Calculations in Power Distribution Networks . . . . . . . . . . . . 40

    High-Speed PCB Design Resources . . . . . . . . . . . . . . . . . . . . . . . . . 44

    Table of Contents:

    Ten Reasons Why Performing SI Simulations is a Good Idea . . . . . . . 11

    Interfacing SMA Connectors to Virtex-II Pro MGTs . . . . . . . . . . . . . . . 12

    For Synchronous Signals, Timing Is Everything . . . . . . . . . . . . . . . . . 16

    Designing High-Speed Interconnects for High-Bandwidth FPGAs. . . . . . 20

    Accurate Multi-Gigabit Link Simulation with HSPICE. . . . . . . . . . . . . . 24

    Eyes Wide Open . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

    Backplane Characterization Techniques . . . . . . . . . . . . . . . . . . . . . . 31

    A Low-Cost Solution for Debugging MGT Designs . . . . . . . . . . . . . . . 36

    Tolerance Calculations in Power Distribution Networks . . . . . . . . . . . . 40

    High-Speed PCB Design Resources . . . . . . . . . . . . . . . . . . . . . . . . . 44

    www.xilinx.com/si_xcell.htm S I G N A L I N T E G R I T Y

  • Additional requirements for the effi-cient design of high-speed buses may bedictated by the needs of a specific applica-tion. For example, a 266 MHz, 64-bitDDR RAM interface will be sensitive toskew between the different byte lanes.Large parallel buses also have the potentialto generate simultaneous switching output(SSO) noise and voltage droop. All of thesefactors translate into the need to manage thetransient current demands of a particularapplication through proper design of thepower distribution system (PDS).

    Resistance, Inductance, and Capacitance Pull the StringsIn general, SI and PI issues arise whendesigners pay inadequate attention to thesebroad categories:

    Termination schemes

    Skin effect (frequency-dependentattenuation)

    Dielectric losses

    Impedance discontinuities/reflections

    Data coding (DC balanced codes, runlength, channel memory)

    Equalization/pre-emphasis

    Inter-symbol interference

    Crosstalk

    Decoupling/bypassing in power distribution

    Board stack-up

    Signal edge rates.

    The common denominator in theseproblems is poor management of the threebad boys of electric circuits: resistance,inductance, and capacitance (Figure 1). Inaddition, you must understand andemploy the right measurement tech-niques in the lab to accurately measureand validate designs against simulationsor design specifications.

    Bill Hargin believes that ForSynchronous Signals, Timing IsEverything. His article outlines a methodfor extracting correction values that can beapplied to the clock-to-out and flight timenumbers. The resulting timing values inthe datasheet are representative of the actu-al load and topology of your design. Thistechnique specifically applies to source-synchronous links.

    Predicting the interconnect perform-ance of high-speed links made of complexvia, connector, and trace structures is noeasy task. However, as Ansofts LawrenceWilliams explains in Designing High-Speed Interconnects for High-BandwidthFPGAs, combining electromagnetic, cir-cuit, and system simulations greatly helpsin the design of reliable and fast data trans-mission channels.

    When designing multi-gigabit asynchro-nous channels, you must carefully analyzethe links physical and electrical properties.In his article, Accurate Multi-Gigabit LinkSimulation with HSPICE, Dr. ScottWedge explains how the combination of anEM solver, coupled transmission lines, S-parameter support, and SPICE and IBISmodeling to the HSPICE circuit simula-tor helps accurately account for high-speedsignal distortions.

    With Eyes Wide Open, Steve Bakershows you how to use the RocketIO DesignKit for ICX to evaluate pre-layoutoptions (such as placement, connectors, orstackup) as well as post-layout options (suchas detailed routing structures) to achievehigh-speed serial link performance.

    As much as Xilinx recommends SI simu-lation and analysis before manufacturing aPCB, there are two very valuable lab instru-ments that you can use on prototype/explo-ration boards. With these instruments, youcan characterize interconnect properties andhigh-speed signal behavior, explore differenttopology performances, or extract simula-tion models. In his article, Backplane

    The objective is to build systems rightthe first time.

    Minimize SI/PI EffectsIn this special series on signal integrity, wehave assembled articles that will provide youwith practical and technical resourcestowards achieving that goal. From character-ization and model extraction techniques inthe lab to methods for simulating signaldegradations of synchronous parallel/asyn-chronous serial systems to case studies, thisseries covers many aspects of SI.

    In a sidebar to this article, XilinxPrincipal Engineer Austin Lesea lists TenReasons Why Performing SI Simulations isa Good Idea. Although this may soundvery familiar to some of you, understand-ing the benefits of performing SI analysisthroughout the design cycle can help youachieve your performance, reliability, andtime-to-market goals.

    Interfacing SMA Connectors toVirtex-II Pro MGTs details Warren Millerand Vince Gavagans experience designingthe interface between Virtex-II Promulti-gigabit transceivers (MGTs) and SubMiniature version A (SMA) connectors forthe Virtex-II Pro Aurora Design Kit.Through prototyping and time domainreflectometry (TDR) measurements, theyillustrate how SMA connector choice influ-ences signal quality.

    Figure 1 The three bad boys of electric cir-cuits (Courtesy of Educators Corner/AgilentTechnologies)

    The common denominator in these problems is poor management of the threebad boys of electric circuits: resistance, inductance, and capacitance.

    10 Xcell Journal Summer 2004

    www.xilinx.com/si_xcell.htmS I G N A L I N T E G R I T Y

  • Summer 2004 Xcell Journal 11

    www.xilinx.com/si_xcell.htm S I G N A L I N T E G R I T Y

    Characterization Techniques, Eric Bogatinexplains the need for making measurements,illustrating the concept of measurement andmodel bandwidth. He also discusses SMAlaunches, information contained in TDRtraces, and differential S-parameters.

    In A Low-Cost Solution for DebuggingMGT Designs, Joel Tan presents a solu-tion comprising a bit-error rate testingmodule connected to a flexible on-chiplogic analyzer core, both implemented inFPGA fabric. Together with theChipScope Pro software suite, these two

    components allow you to perform diagnos-tic testing, debugging, and development ofan MGT system without the use of expen-sive lab equipment such as logic analyzersand BERT testers.

    And in Tolerance Calculations in PowerDistribution Networks, Sun MicrosystemsIstvan Novak walks you through differentscenarios of bypass capacitor configurationsto demonstrate the importance and influ-ence of the capacitors technology, value, andnumber in designing a decoupling/powerdistribution network.

    ConclusionWe hope you will find in this seriesinstructive material on the sources ofSI/PI effects, along with practical infor-mation about the resources and toolsavailable to you. Our experience tells usthat careful simulations, analysis, andmeasurements of PI and SI effects early inthe design process guarantees first-timesuccess more often than not.

    If youd like to send us feedback aboutthe topics discussed, please e-mail us at [email protected]

    by Austin LeseaPrincipal Engineer, Advanced Products GroupXilinx, Inc.

    Not so long ago, the rise and fall times ofsignals, the coupling from one trace toanother, and the de-coupling of powerdistribution on a PCB were tasks thatwere routinely handled by a few simplerules. Occasionally, you might use theback of an envelope, scribbling down afew equations to make sure that thedesign would work.

    Those days are gone forever. Sub-nanosecond, single-ended I/O rise andfall times, 3 to 10 Gb transceivers, andtens of ampere power needs at around 1Vhave all led to increased engineeringrequirements.

    Your choice is simple: simulate nowand have a working result on the firstPCB, or simulate later after a series offailed boards. The cost of signal integritytools more than outweighs the cost ofmaking the board over and over with suc-cessive failures.

    In keeping with the theme of this spe-cial issue, here are my 10 best reasons whysignal integrity engineering is a good idea:

    1. Youre tired of making PCBs over and over and still not having them work.

    Seriously, without simulating all signals, aswell as power and ground, you risk makinga PCB that will just not work. IR (voltage)drop, inadequate bypassing or de-coupling,crosstalk, and ground bounce are just a fewof the possible problems.

    2. Youre tired of being late to market andwatching your competition succeed.

    Every time you have to fix a problem witha PCB, it necessitates a new or changed lay-out, a new fabrication, and another assemblycycle. It also requires the re-verification of allparameters. Taking the time to do thesethings right has both monetary and competi-tive advantages.

    3. Youre tired of spending all this money, only to scrap the first three versions of PCBs and all of the components that went with them.

    See reason number two.

    4. Your eye pattern is winking at you.

    If the eye pattern of a high-speed serial linkis closing, or closed, its likely that the linkhas a serious problem and will have dribblingerrors or worse, will be unable to synchro-nize at all. You must simulate every elementof the design to assure an error-free channel.

    5. All 1s or all 0s suddenly breaks the system.

    Unfortunately, many systems do not have achoice of what data may be processed. Oftenthe data pattern will create conditions that, ifnot simulated a priori, will cause errors inthe system.

    6. Hot and cold, fast and slow, and high and low voltages cause failures.

    Without simulating the corners of the sil-icon used as well as the environmental fac-tors, youre playing Russian Roulette withfive of the six chambers loaded.

    Ten Reasons Why Performing SI Simulations is a Good Idea7. You cannot meet timing, and you

    are unable to find out why.

    Poor signal integrity is the primary causeof adding jitter to all signals in a design.Ground bounce, crosstalk, and reflectionsall conspire to add jitter. And once added,jitter is virtually impossible to remove.

    8. The FCC Part 15 or VDE EMI/RFItest fails every time you test a board.

    Radiated and conducted radio frequencyemissions, as well as susceptibility to radiofrequency sources, is a sign of poor SIpractices. Fixing the problem by shieldingincreases the system cost substantially, andmay not even be possible in extreme cases.

    9. Customers complain, but when youget the boards back, you dont findany problems.

    One of the biggest problems with SI isthat the errors and failures observed are dif-ficult to correlate and sometimes impossi-ble to find. Was it a problem with voltage,temperature, or with the data pattern itself?It might have been someone turning lightson and off (ground disturbance). Dont riska return that cannot be fixed.

    And last, but certainly not the least:

    10. Your manager has suggested thatyou look for other employment.

    Do not let this happen to you. Stay cur-rent, educated, and productive. Get theright tools to do the job. Realize that signalintegrity engineering is a valuable and irre-placeable skill in great demand in todaysdesign environments.

  • by Warren MillerVP of Marketing [email protected]

    Vince GavaganDesign [email protected]

    While designing the Avnet Design ServicesVirtex-II Pro 3.125 Gbps Aurora DesignKit, we found that there were a variety ofoptions for the interface between theVirtex-II Pro multi-gigabit transceivers(MGTs) and the SubMiniature version A(SMA) connectors on the board. After try-ing a few of these options and measuringthe results on the prototype board, we dis-covered that the signal integrity perform-ance of the interface varied widelydepending on the type of SMA connectorused, the location, and characteristics of theboard traces.

    In this article, well review several specif-ic design options and their impact on signalintegrity. Our test results will show why thefinal optimal design was selected. Wellalso provide detailed measurements on thesignal integrity of the final design.

    Interfacing SMA Connectorsto Virtex-II Pro MGTsInterfacing SMA Connectorsto Virtex-II Pro MGTs

    12 Xcell Journal Summer 2004

    SMA connector choice has a surprising effect on signal integrity.SMA connector choice has a surprising effect on signal integrity.

    www.xilinx.com/si_xcell.htmS I G N A L I N T E G R I T Y

  • Avnet Virtex-II Pro Aurora Design KitThe Aurora Design Kit includes the AvnetDesign Services Virtex-II Pro evaluationboard and its associated documentation,board support package, applications code,and example designs. The Aurora referencedesign has been ported to the board; anexample design communicating betweenserial ports at 3.125 Gbps demonstrates thefeatures and capabilities of the design kit.The circuit board used in the design kit isshown in Figure 1.

    The hardware features of the evaluationboard include the user FPGA, on-boardmemory, on-board communications,expansion, and configuration. A completeblock diagram of the boards hardwarecomponents is shown in Figure 2.

    The user FPGA is a Virtex-II ProXC2VP7-FF896 device that includes anembedded PowerPC processor, eighthigh-speed serial I/O channels, andRocketIO MGTs.

    The high-speed communications func-tions of the board include eight SMA con-nectors (TX/RX pairs for two RocketIOports) with board-configurable loop-backfor two RocketIO transceivers and pads forfour additional RocketIO ports.

    The connectors featured on boardinclude two 140-pin general-purpose I/Oexpansion connectors (AvBus), up to 30LVDS pairs, and a standard 50-pin 0.1-inch header for custom expansion.

    You can configure the FPGA via twoXilinx XC18V04-VQ44 PROMs, aParallel IV cable for JTAG, and fly-wiresupport for Parallel-III and Multilinxconfiguration cables.

    Mictor connectors are available toaccess the remaining high-speed I/O sig-nals (MGTs) on the device for test or char-acterization.

    Prototype DesignWhen we first received the prototypedesign from the manufacturing house, wetested the MGT-to-SMA connections. Inpreliminary testing, we used a loop-backconnection over an SMA cable from oneMGT to another. No FR4 of significantlength was inserted.

    Test packets were simple 00 to FF datawords (256 bytes) with idle sequences(k28.5, d21.4, d21.5, d21.5) betweenpackets. We captured eye diagrams usingthe repeating idle sequence (Figure 3).Although the eye opening is fairly clean,the pattern is a repeating idle sequence andthus doesnt provide a very extensive test.

    During our initial prototype testing, wesent several thousand packets successfully.However, testing additional boards

    Memory includes Micron DDRSDRAM (64 MB) for use as code storagespace for the PowerPC and packet storagefor serial I/O ports. Communication canalso occur over a standard RS-232 serialport for simple monitor or debug functions.

    An included 5.0V AC/DC power supplyprovides up to 22.5W for the on-board TexasInstruments 3.3V 6A module andNational Semiconductor linear regulators.

    Summer 2004 Xcell Journal 13

    Clocks(4)

    AVBus

    Power SupplyTexas Instruments

    PT5401ANational Semiconductor

    LP3961ELP3966ELP2995M

    SMA(4)

    SMA(4)

    PPC Debug

    P4 JTAG

    Config/JTAG

    Proms18V04(2)

    MicronDDR SDRAM

    (64 MB)MT46V16M16 (2)

    Console

    50-pin Header

    LED 7 Seg

    Mictor Pads

    LEDs(8)

    Switches(8)

    ConfigurableLoop-back

    Rocket IO

    Rocket IO

    181 I/O68 I/O

    4 I/O

    47 I/O

    32

    Virtex-II ProXC2VP7-FF896

    Figure 1 The Avnet Virtex-II Pro evaluation board. The eight SMA connectors are located in the upper middle of the board, very close to the FPGA.

    Figure 2 Block diagram of the Aurora Design Kit circuit board

    www.xilinx.com/si_xcell.htm S I G N A L I N T E G R I T Y

  • revealed that performance was not repeat-able, and in fact was much worse for themajority of boards. Because these initialboards used -5 speed grade parts, we sur-mised that the errors could be attributed tothe 2.0 Gbps limitation of the -5 speedgrade devices.

    Yet procurement of -6 speed grade partsrevealed that this was not the case; a sub-stantial number of errors continued tooccur. Because the design includes twoRocketIOs that are looped back via FR4 onthe board in addition to the SMA break-out, we repeated the test using the non-SMA loop-back. These tests yieldedsubstantially better results. In fact, the non-SMA loop-back was capable of 3.125 Gbpswith identical payload and zero errors.

    During these tests, we performed TimeDomain Reflectometry (TDR) on theboard as well, with results shown in

    Figure 4. After reviewing these results, weconcluded that although the boardimpedance was matched very well, asevere impedance mismatch existed at theSMA connectors.

    This information suggested we shouldlook more closely at the layout, and we

    determined that during thedesign phase, a stub was over-looked. As the FPGA and SMAsboth reside on the top (compo-nent) side of the PCB, and thetraces are also on layer one (a 100Ohm differential impedancemicro-strip), a stub is created atthe through-hole SMA.

    Prior to a board spin, twoboards were used to test the theory.Testing unmodified boards with15 inches of FR4 (using an FR4characterization board) yielded thefollowing results:

    We modified the poorer performingboard by cutting the through-hole stubprotruding from the backside of the boardand grinding the stub flush with the back-side of the board.

    With stubs cut, we observed the follow-ing results:

    With stubs filed flush, we obtained thefollowing results:

    This seemed to be a promisingapproach, so we decided to try anotheroption to eliminate the stub before doing are-layout of the board. The SMAs wereremoved from board #2 and placed on thebackside of the board. This effectivelyremoved the stub, since the via and centerSMA conductor became part of the intend-ed transmission line.

    Testing this modified board yielded zeroerrors. This confirmed our finding that the

    14 Xcell Journal Summer 2004

    Board #1:

    # of packets # byte errors

    Test 1 0x10000 (65,536) 136

    Test 2 0x10000 (65,536) 306

    Board #2:

    # of packets # byte errors

    Test 1 0x10000 (65,536) 5527

    Test 2 0x10000 (65,536) 8270

    Board #2:

    # of packets # byte errors

    Test 1 0x10000 (65,536) 168

    Test 2 0x10000 (65,536) 273

    Board #2:

    # of packets # byte errors

    Test 1 0x10000 (65,536) 115

    Test 2 0x10000 (65,536) 134

    Figure 3 Eye diagrams of 2.5 Gbps (left)and 3.125 Gbps(right)

    Figure 4 Initial TDR results

    www.xilinx.com/si_xcell.htmS I G N A L I N T E G R I T Y

  • stub was the cause of the unacceptableerror rate and that a layout change wasrequired to remove the stub.

    Because we wanted to keep the SMAson the top side and minimize modifica-tion to the existing microstrip, a boardspin was required. Noting the perform-ance of surface-mount SMAs in simula-tion, we decided to proceed with a similarSMA configuration for the board spin.

    Revision of the Prototype DesignThe prototype board was redesigned toeliminate the stub by using a surface-mountSMA connector. More extensive testingwould also be necessary to further verify theoperation of the new board design.

    In addition to FR4 characterization,we chose to use a more exhaustive test pat-tern to validate the performance of thenew board. Furthermore, partial reconfig-uration would allow on-the-fly adjust-ments to MGT parameters such aspre-emphasis and differential swing. Theresults are shown in Figure 5.

    The test setup parameters were:

    MGT 4 connected through a 12-inchRG 316 cable (Johnson 415-0029-012)to a 20-inch FR4 trace on the XilinxMGT characterization board (Xilinx)

    Pre-emphasis at 25% (setting 2 of 0-3)and differential swing of 600 mV (setting 2 of 0-4)

    Test pattern is PRBS32 (using the XilinxBERT design)

    MGT 6 connected through 24-inchRG316 (manufacturer unknown) to 15-inch FR4 characterization board (Xilinx)

    Pre-emphasis at 25% (setting 2 of 0-3)and differential swing of 600 mV (setting 2 of 0-4).

    Test pattern is PRBS32.

    We ran the test until the 16550 UARTtimed out (an evaluation-licensed core); thetotal frames are shown in Figure 6. Note thatthere are no errors; hence the bit error rate iszero. Also, the error factor is defined on pagenine and table 2 in Xilinx Application NoteXAPP661 as the shortest gap between errors,expressed in frames. Becausethere are no errors, it makessense that this would be infinite.

    The final TDR test resultsare shown in Figure 7. A carefulreading of the results shows a50% improvement over the pre-vious reading and confirms theimprovement of the new design.

    ConclusionDuring the design phase, you must be verycareful to identify all sources of trace andstub length. In particular, watch for a mis-match between your choice for through-hole or surface-mount SMA devices andthe layout of your traces between the SMAconnector and the Virtex-II Pro FPGA. Wefound it was easy to control the length andimpedance of the traces, but we overlookedthe impact SMA connector choice had onthe signal integrity.

    Detailed design files and test measure-ments are available with the purchase of anAvnet Design Services Virtex-II Pro 3.125Gbps Aurora Design Kit. You can order thekit, part number ADS-XLX-V2PRO-EVLP7-6, for $599.

    This design kit is just one of many avail-able to speed the development cycle forcomplex processor, communications,FPGA, DSP, and networking applications.All of our design kits are modular and canaccept matching add-on modules, applica-tions software, design and debug tools, andcompatible IP cores. For more informa-tion, visit www.avnetavenue.com.

    Summer 2004 Xcell Journal 15

    Figure 7 TDR measurement results of the revised design show a 50% improvement, supporting the bit error rate test results.

    We found it was easy to control the length and impedance of the traces, but we

    overlooked the impact SMA connector choice had on the signal integrity.

    Figure 5 MGT settings

    Figure 6 Test results

    www.xilinx.com/si_xcell.htm S I G N A L I N T E G R I T Y

  • For Synchronous Signals, Timing Is Everything For Synchronous Signals, Timing Is Everything

    16 Xcell Journal Summer 2004

    Mentor Graphics highlights a proven methodology for implementing pre-layout Tco correction and flight time simulation with Virtex-II and Virtex-II Pro FPGAs.

    Mentor Graphics highlights a proven methodology for implementing pre-layout Tco correction and flight time simulation with Virtex-II and Virtex-II Pro FPGAs.

    by Bill HarginProduct Manager, HyperLynxMentor Graphics [email protected]

    Weve all heard the phrase timing iseverything, and this is certainly the casefor the majority of digital outputs onmodern FPGAs. Timing-calculationerrors of 10 or 20 percent were fine at 20MHz, but at 200 MHz and above, theyreabsolutely unacceptable.

    As Xilinx Senior Field ApplicationsEngineer Jerry Chuang points out, Thetoughest case usually is a memory orprocessor bus interface. Most designersknow that they have to account for Tco(clock-to-output) as it relates to flighttime, but dont really know how.

    Another signal integrity engineeringmanager who preferred to remain anony-mous explains, Weve got lots of thingsthat hang on the hairy edge of working.Thats one of the reasons why they giveyou so many knobs to turn on newermemory interfaces.

    To complicate matters, manufacturerdatasheets and application notes usemultiple, often-conflicting definitions ofmany of the variables and proceduresinvolved, requiring you to investigate theconventions used by manufacturer A ver-sus manufacturer B. Most of the recentlypublished signal integrity books eithergloss over the subject or avoid it alto-gether. We hope that this article willserve to blow away some of the fog andreinforce some standard definitions.

    www.xilinx.com/si_xcell.htmS I G N A L I N T E G R I T Y

  • System Timing for Synchronous SignalsAn FPGA team will typically place androute an FPGA according to their specifictiming requirements, leaving system-leveltiming issues to be negotiated later with thesystem-design team. With the sub-nanosec-ond timing margins associated with manysignals, its common for the system side tobe faced with PCB floor-planning changes,part rotation, and sometimes the need tonegotiate pin swaps with the FPGA team toaccommodate timing goals. Proactive, pre-layout timing analysis and some carefulaccounting can keep both the FPGA andsystem teams from spending a month ormore chasing timing problems.

    Two classes of signals pose problems forFPGA designers and their downstream coun-terparts at the system level: timing-sensitivesynchronous signals and asynchronous,multi-gigabit serial I/Os. Well concentrate onparallel, synchronous designs in this article.

    MarginsThe system-timing spreadsheet for syn-chronous designs is based on two classictiming equations:

    Tco_test(Max) + Jitter + TFlight(Max) + TSetup < TCycle

    Tco_test(Min) + TFlight(Min) > THold

    Or, once Tco_test is corrected, becomingTco_sys, as outlined in this article:

    Tco_sys(Max) + Jitter + Tpcb_delay(Max) + TSetup < TCycle

    Tco_sys(Min) + Tpcb_delay(Min) > THold

    Each nets timing is initially set up witha small, positive timing margin. This mar-gin is allocated to the TFlight(Max) andTFlight(Min) values (or Tpcb_delay[Max]and Tpcb_delay[Min], respectively) in thepreceding equations; these are timing con-tributions of the PCB interconnect betweeneach nets driver and receivers.

    If there is insufficient margin left todesign the interconnects, either the siliconnumbers need to be retargeted andredesigned, or the system speed must beslowed. Figure 1 shows how timing marginsshrink relative to frequency.

    There are two ways to come up with theinterconnect values for the timing spread-

    what that will be. Knowing what loading thevendor assumed when publishing Tco is crit-ical so that you can adjust for the differencebetween that load and your real one.

    The Recipe for a ProblemAs shown in Figure 2, if the reference load issignificantly different from the actual loadthat the output buffer will see in yourdesign, the sum of the datasheet and PCB-interconnect timing values will not repre-sent actual system timing. Actual or totaldelay may be represented as:

    Total Delay = Tco_sys + Tpcb_delay

    Tco_test + Tpcb_delay

    where Tpcb_delay is the extra intercon-nect delay between the time at which thedriver switches high or low until a givenreceiver switches.

    Note that this PCB delay is not justthe time it takes for a signal to travel alongthe trace (sometimes called copper delay

    sheet. Some signalintegrity tools auto-matically make calcu-lations that produce asingle flight-timevalue. However, espe-cially for designers justlearning about thetiming challenges ofhigh-speed systems, atwo-step approach ismore instructive. First,you learn how to cor-rect a datasheets driverTco value to match the behavior in your realsystem; second, you add the additional delaybetween the driver and each of its receivers.

    Data Book ValuesInitially, timing spreadsheets are populatedwith values from the silicon vendors databook. Youll need first-order estimates fromsilicon designers on the values of Tco andsetup and hold times for each system com-ponent. You can usually obtain this datafrom the component datasheet.

    Test and Simulation Reference LoadsTo arrive at the datasheet value for yourdrivers Tco, standard simulation test loads(or reference loads) provide an artificialinterface between the silicon designer andthe system designer.

    Youd prefer, of course, to have Tco spec-ified into the actual transmission-lineimpedance youre driving on your PCB, butthe silicon provider has no way of knowing

    Summer 2004 Xcell Journal 17

    0 20 40 60 80 100

    300 MHz

    100 MHz

    30 MHz

    10 MHz

    < 1 ns

    4 ns

    14 ns

    70 ns

    Clk to QSetup/HoldTrace DelayMargin

    +-

    +-

    Tco into a non-standard test load

    Tco into actual interconnect load

    Driver

    Driver Receiver

    Transmission Line

    Test Load

    ReferenceWaveform

    ActualWaveforms

    Tco_test

    Tpcb_delay

    Vih

    Vm

    Vm

    Tco_sys

    Figure 1 Drastically narrowed system-timing margins, as clock frequency moves from 10 to 300 MHz, are shown in red.

    Figure 2 If the reference load and the actual load in your design differ, youve got to make an adjustment in your system timing spreadsheet to compensate.The red driver waveforms illustrate the difference, and the impact, on Tco.

    www.xilinx.com/si_xcell.htm S I G N A L I N T E G R I T Y

  • or propagation delay). Here, Tpcb_delayaccounts for effects such as ringing at thereceiver, as shown in Figure 3. Its value could(on a poorly terminated net) easily be longerthan the simple copper delay.

    Calculating accurate timing involvesmore than finding Tpcb_delay. If the dif-ference between Tco_sys and Tco_test issignificant even in the neighborhood of100 ps your board may not functionproperly if you dont account for the differ-ence. But because Tco_test is a value creat-ed with an assumed test load, it almostnever matches Tco_sys, the clock-to-out-put delay youll see in your actual system.

    For example, Lee Ritchey, author of Getit Right the First Time and founder of theconsulting firm Speeding Edge, was hired toresolve a timing problem on a 200 MHzmemory system. After digging into thedesign, he found that unadjusted datasheet

    values were used, based on Tco values thatwere measured on a 50 pF load rather thansomething resembling the designs 50 Ohmtransmission-line load. As a result, thisimproper accounting threw timing off byjust over one nanosecond, he says. Thats20 percent of the total timing budget, amajor error.

    In the following sections, well see howyou can correct Tco_test to become Tco_sys,avoiding this type of error altogether.

    The ProcessMeasuring Tco_testTo measure Tco_test, you need to set up asimulation with just the driver model andthe datasheet test load. Though theyre anoptional sub-parameter in the IBIS specifica-tion, most IBIS models (including XilinxIBIS models) contain a record of the testload (Cref, Rref, Vref ) and the measurementvoltage (Vmeas) to use with these values.Figure 4 shows these values for theLVTTL8F buffer in the Virtex-II Pro IBISmodel, as well as a generic reference load dia-gram taken from the IBIS specification.

    Once youve gathered these load valuesfrom the IBIS model, you simulate risingand falling edges, and for each, measurethe time from the beginning of switchinguntil the driver pin crosses the Vmeasthreshold. These are the Tco_test values.

    Obtaining Tcomp, the Timing-Correction ValueNow you need to calculate a compensationvalue, Tcomp, that will convert the datasheetTco value into the actual Tco youll see inyour system. Tcomp is the delay between thetime the driving signal, probed at the output,crosses Vmeas into the silicon manufacturersstandard reference load, and the time itcrosses Vmeas for your actual system load.Tcomp is then used as a modification to theTco value from the vendor datasheet, asshown in Figure 5.

    The revised computation of actual delayfrom the previous equation is then:

    Total Delay = Tco_sys + Tpcb_delay= (Tco_test + Tcomp) + Tpcb_delay

    Note that Tcomp may be negative or pos-itive, depending on whether the actual load

    in your system is smaller or larger than thestandard test load. Traditionally, silicon ven-dors used capacitive test loads (like 35 pF) tomeasure Tco; almost all real PCB transmis-sion lines do not present as heavy a load, soTcomp is usually negative in this situation.

    Xilinx, for its current generation ofFPGAs, uses a 0 pF test load for outputdriver wave shape accuracy. Real transmis-sion lines will represent a different load some mixture of inductance, capacitance,and resistance. Because the transmission-line load is heavier than a 0 pF open load,Tcomp will be positive. Simulation is theonly way to accurately predict the exactvalue of Tcomp.

    Simulating Tpcb_delayAt this point in the process, youve complet-ed the first step in finding accurate delays foryour timing spreadsheet, and youve compen-sated the datasheet Tco to match your realsystem load. Next, you need to determineTpcb_delay, the additional delay caused bythe interconnect from driver to receiver.

    A signal integrity simulator is the onlyway to accurately do this, because only asimulator can account for subtle effects likereflections, receiver input capacitance, lineloss, and so forth.

    From here, well explore some detailedexamples based on Xilinx-provided IBISmodels the process of calculating Tcompand then using the HyperLynx simulatorto determine an interconnects Tpcb_delaythrough pre-layout topology analysis. Youcould enter the values that we come up withdirectly into your system-timing spreadsheet.

    The process using Mentor GraphicsHyperLynx product is straightforward. Youlook up the manufacturers test load in theIBIS model (see Figure 4), enter it in theLineSim schematic, set up your actual inter-connect topology just below the referenceload, and begin a simulation, probing atboth drivers so that you can measure Tcompand Tpcb_delay, as shown in Figure 6.

    Running the Numbers on a Real ProblemAn important design for an electronic equip-ment manufacturer had a Xilinx FPGA talk-ing to a bank of SRAMs at 125 MHz,meaning the cycle time (Tcycle) was 8 ns.

    18 Xcell Journal Summer 2004

    Figure 3 PCB delay refers to the differencebetween the driver waveform switching throughVmeas and the waveform at the receiver as itswitches through Vih (rising) or Vil (falling).Finding this value requires simulation, not just asimple copper-delay calculation.

    Figure 4 Mentor Graphics HyperLynx VisualIBIS Editor, a free tool for navigating the 50,000-plus lines of Xilinx Virtex-II Pro, Virtex-II, andSpartan IBIS models, shows reference load infor-mation for an LVTTL8F buffer as well as theassumed connections from the IBIS specification for Cref, Rref, and Vref in the insert.

    www.xilinx.com/si_xcell.htmS I G N A L I N T E G R I T Y

  • The Xilinx datasheet specified Tco as 4 ns (i.e.,Tco_test). The SRAMs setup time was 2 ns.

    Some of the traces connecting the FPGAto an SRAM were six inches long; a signalintegrity simulation showed a worst-casemaximum PCB delay (to the receivers farthreshold) of 2.5 ns. This yielded in thedesigns timing spreadsheet a total time of 4 + 2.5 + 2 = 8.5 ns (Tco_test + Tpcb_delay+ Tsetup), violating the 8 ns cycle time.

    However, the Tco value, when correctedfor the actual design load, was 4-1.2 = 2.8 ns(Tco_sys = Tco_test + Tcomp), meaningthat the actual total delay value was 2.8 + 2.5 + 2 = 7.3 ns (Tco_sys + Tpcb_delay+ Tsetup), leaving an acceptable timing margin of 700 ps.

    Note that in this calculation, we meas-ured to the time at which the receiver signalcrossed the farthest-away threshold to getthe worst-case, longest possible Tpcb_delay.For a rising edge, we measured to the lastcrossing of Vih; for a falling edge, to the lastcrossing of Vil.

    ConclusionFor seamless interaction between the FPGAdesigner and the system designer, its prudentto do as much pre-layout, what-if analysisas possible. And, though not covered explicit-ly in this article, you can also verify that yourlaid-out printed circuit boards meet yourtiming requirements using a post-layout sim-ulator with batch analysis capabilities.

    Some Mentor products that perform thistype of analysis are HyperLynx, ICX, andXTK. Running these simulations, youre revis-ing simulated representations of interconnectcircuits in minutes as compared to the weeksrequired to spin actual PCB prototypes.

    The new HyperLynx Tco simulator isavailable on Mentor Graphics website,www.mentor.com/hyperlynx/tco/. Included withthe Tco simulator are the Virtex-II Pro,Virtex-II, and Spartan IBIS models;boilerplate schematics that will help you makeadjustments to data book Tco values; and adetailed tutorial on Tco and flight-time cor-rection that parallels this article.

    Summer 2004 Xcell Journal 19

    +-

    +-

    Tco into a non-standard test load

    Tco into actual interconnect load

    Driver

    Driver Receiver

    Transmission Line

    Test Load

    ReferenceWaveform

    ActualWaveforms

    Tco_test

    Tpcb_delay

    Total Delay

    Vih

    Vm

    Vm

    Tco_sys

    TcompFlight Time

    What is Flight Time?

    In this article, weve shown conceptu-ally how Tco values specified into asilicon vendors test load can be cor-rected on a per-net basis to give theactual clock-to-output (Tco) timingyoull see on your PCB, and thenadded to the additional trace delaysbetween drivers and receivers to giveaccurate timing values. However, sig-nal integrity (SI) tools actually dealwith corrected timing values in a dif-ferent (but equal) way.

    The most convenient outputfrom an SI tool is a single number called flight time shown inFigure 5 as (Total Delay - Tco_test)or (Tpcb_delay - Tcomp). You canadd this value to the standard databook Tco values in your timing spread-sheet to give the same effect as the two-step process described in this article.

    When an SI tool calculates timingvalues, it 1) simulates each driver modelinto the vendors test load, measures thetime for the output to cross the Vmeasthreshold, and stores the value(Tco_test); 2) simulates the actual netsin the design and measures the time atwhich each receiver switches (TotalDelay); and 3) for each receiver, sub-tracts the driver-switching-into-test-loadtime from the receiver time (Total Delay Tco_test). The resulting flight time isa single number that can be added toeach nets row in a timing spreadsheet,and that both compensates Tco_test foractual system loading and accounts forthe interconnect delay between driverand receiver.

    The term flight time is some-what unfortunate, although itsbecome the industry standard. Thename suggests the total propagationdelay between driver and receiver, butthe value calculated is actually thedelay derated to compensate for thereference load. For old-style capaci-tive reference loads (e.g., 50 pF),flight time can even be negative.

    Figure 5 Tcomp, highlighted here, can be used to compensate for data book Tco values in system timing calculations. Tcomp is positive when the actual load exceeds the reference load, and negative when thereference load is larger. Signal integrity tools actually use a one-step process that combines the effect ofTcomp and Tpcb_delay into a single value called flight time (see sidebar, What is Flight Time?).

    Figure 6 Total Delay, Tco_test, Tcomp, Tco_sys,and Tpcb_delay, as well as flight time, are allmeasurable for this falling-edge waveform usingMentor Graphics' HyperLynx software.

    www.xilinx.com/si_xcell.htm S I G N A L I N T E G R I T Y

  • by Lawrence Williams, Ph.D.Director of Business DevelopmentAnsoft [email protected]

    The push toward FPGA platform solutionswith high-bandwidth DSP and gigahertz-speed I/O functionality has led to devicesthat place greater demands on PCB design.The high serial data rates of Xilinx Virtex-II Pro FPGAs (3.125 Gbps) and Virtex-II Pro X FPGAs (10 Gbps) requirecareful signal integrity design for propersystem operation.

    In this article, well explain how to com-bine commercial electromagnetic (EM)software with circuit and system simulationto characterize transmission lines, vias, andconnectors for systems that incorporatehigh-bandwidth FPGAs [1]. We used two-dimensional EM simulation to extract qua-sistatic circuit models for the PCBtransmission lines and three-dimensionalEM simulation to extract models for viasand connectors. For end-to-end simula-tions, we applied a convolution simulator.Thus, its possible to achieve reliable datatransmission with proper use of moderndesign tools.

    High-Performance PCB DesignPCB designers aim to create interconnectsthat reliably transmit high-speed serial sig-nals. Transmission lines, via structures, andconnectors are the building blocks of thedesign and all have their particular chal-lenges. These structures are designed indi-vidually to meet particular metrics and arethen assembled into a system-level intercon-nect to evaluate end-to-end performance.

    The most common PCB transmissionstructures are the microstrip and striplinetransmission line; they are easy to con-struct, and you can use both for signalingat gigabit speeds. Designers have also usedsingle-ended lines successfully for lowerspeed designs; modern gigabit designs usedifferential signaling because of the advan-tages of noise immunity and reliable cur-rent return paths. The key parametersassociated with PCB transmission lines arethe characteristic impedance, delay, inser-tion loss, and crosstalk.

    Designing High-Speed Interconnects for High-Bandwidth FPGAs

    20 Xcell Journal Summer 2004

    Commercial EM software combines with circuit and system simulation to achieve reliable data transmission.

    www.xilinx.com/si_xcell.htmS I G N A L I N T E G R I T Y

  • Via structures allow you to route circuittraces between layers of a multilayer board.Vias are particularly useful for transitioningfrom the pins of a ball grid array or connec-tor down to stripline traces within theboard. The most common and inexpensivevia structure is the through-hole via.

    Alternatives to the through-hole via arethe blind via and the back-drilled via.Although these alternatives generally pro-vide higher performance, most high-vol-ume designs continue to use the lower costthrough-hole via. Key issues in the designof through-hole via structures are untermi-nated via stubs and antipad radii.

    Connectors provide an electrical andmechanical interface between circuitboards, or between boards and cabling.Connector performance is highly depend-ent on the escape-routing PCB interface.Designs can succeed or fail depending onthe choice of route layer and resultant viastub length, antipad dimensions, boardmaterials, and escape-routing layout.Additionally, transmission bends withinconnectors skew the transmission path andcan lead to mode conversion.

    Electromagnetic Model ExtractionThe most common printed circuit boardmaterial is FR4. Although inexpensive forcircuit fabrication, FR4 suffers significantdielectric losses at high frequencies. Typicalmaterial properties for FR4 are r = 4.2and loss tangent tand = 0.022.

    An alternative to FR4 is to use a lowerloss Getek material. Getek IIs materialproperties are r = 3.4 and loss tangenttand = 0.006. Figure 1 depicts a layer with-in a typical backplane board. The layerheight is 0.272 mm (10.7 mils); trace widthis 0.125 mm; trace separation is 0.250 mm.Half-ounce copper plating for the tracesprovides a trace thickness of 0.7 mils.

    We performed simulations using thetwo-dimensional, quasistatic finite elementsimulator within the Ansoft Q3D softwaresuite. The stripline geometries weredesigned to provide nominally 100 Ohmsof differential impedance, and simulationsconfirmed that the impedance was within4% of the nominal value.

    Figure 2 depicts three methods by

    Although accurate, MoM simulationsare also the most computationally expen-sive. A compromise that offers the accuracyof planar EM simulations and some of thespeed of circuit simulation is to use a com-bination of the two (Figure 2B). AnsoftDesigner allows you to subdivide intercon-nects into a model with circuit elementsand EM elements. Circuit elements areused for long, uniform sections of the cou-pled transmission line. EM simulation isused for all coupled line bends, as shown inFigure 2. This solver on demandapproach automatically calls the planar EMsolver whenever a bend is encountered.

    Figure 3 plots the results of the three sim-ulation methods outlined in Figure 2. Allmethods accurately predict the insertion loss.The circuit model cannot provide meaning-

    which you can model the PCB intercon-nects. The simplest is to use a coupled-linecircuit model (Figure 2A), found in popu-lar high-frequency circuit simulators likeAnsoft Designer. In this instance, theinterconnect is modeled with a uniformdifferential coupled transmission line with-out any discontinuities.

    On the other end of the modeling spec-trum is a full-wave planar EM field simulatorbased on the method of moments (MoM)(Figure 2C). The Ansoft Designer PlanarEM simulator separates the traces into thou-sands of triangular elements. Numerical sim-ulations compute the current flow on alltriangles based on the EM coupling betweenthem. As such, these computations com-pletely characterize signal transmission andreflection on the interconnect.

    Summer 2004 Xcell Journal 21

    BS W

    r = 3.4, tan = 0.006

    Layer B W S Zse Zd Zcom

    S10 0.272 0.125 0.250 49.15 96.05 25.13All dimensions are in millimeters

    Figure 1 Two-dimensional quasistatic simulations performed on stripline transmission structures using Ansoft Q3D. The table lists single-ended, differential, and common impedances.

    Figure 2 You can model PCB interconnects using various methods. Circuit models (A) are the simplest and least expensive computationally; planar EM (MoM) simulations (C)

    are most expensive computationally but also the most accurate; a combined circuit + planar EM (B) provides accurate results with relatively low computational effort.

    www.xilinx.com/si_xcell.htm S I G N A L I N T E G R I T Y

  • ful return loss, as it does not contain any ofthe coupled line bends. The circuit plus pla-nar EM method (solver on demand) pro-vides return loss results that are in closeagreement with the planar EM results. Thismethod provides accurate results with agreatly reduced computational expense.

    ViasA common signal integrity design practiceis to place high-speed route layers on oppo-site sides of the board in order to avoidopen-circuit via stubs [2]. Figure 4 depictstwo via structures: a best case and worstcase. The best case occurs when routingfrom the top layer to layer S10, as this

    results in a very short (10.75mil) via stub. The worst caseoccurs when routing to layerS1, leaving a very long (123.95mil) via stub.

    Figure 5 plots the inser-tion and return loss of an iso-lated differential viacomputed using the three-dimensional full-wave fieldsolver Ansoft HFSS. Thesolid blue curve representsthe via that transitions to

    layer S1. This is considered the worst case,as it has a very significant open-circuitedvia stub and an associated resonance in theinsertion loss near 6.5 GHz. The dashedred curve represents the via that transi-tions to layer S10. This is considered thebest case, as it provides a very flat inser-tion loss response to 10 GHz, and returnloss is good to roughly 4.5 GHz.

    Another consideration when designingvias are the antipads that exist on all powerand ground layers. Figure 6 depicts two dif-ferential via structures with antipad radii of0.5 mm and 0.7 mm. You can improve per-formance by using the larger antipad radius

    [2]. We performed simulations using AnsoftHFSS to predict the performance of each.

    Figure 7 shows the swept frequencyresults for both via antipad radii for differ-ential vias routing to layer S1 (worst case).As you can see in the plot, a significantincrease in bandwidth is possible with thissimple modification. The resonance in the

    22 Xcell Journal Summer 2004

    VHDM Connector

    Best

    Cas

    e

    Route Layer: s10(Via Stub: 10.75 mil)

    VHDM Connector

    Wor

    st C

    ase

    Route Layer: s1(Via Stub: 123.95 mil)

    Antipad Radius: 0.5 mm(From Layout)

    Antipad Radius: 0.7 mm(Test Case)

    Figure 3 PCB interconnect simulationresults show that allmethods outlined inFigure 2 accurately predict insertion loss.Return loss cannot bepredicted with the circuit model alone.

    Figure 4 Vias that transitionfrom the top to thebottom of a boardprovide minimalopen-circuited viastubs and best-caseperformance.

    Figure 5 Through-hole via performance assimulated usingAnsoft HFSS. Note the sharp resonance in theinsertion loss for the worst-case viarouted to layer S1.

    Figure 6 Antipad radiishould be suffi-ciently large toavoid capacitivecoupling to powerand ground.

    Figure 8 MolexVHDM-HSD connector as modeled in Ansoft HFSS

    Figure 7 Differential via performance for layer S1 (worst-case) routing for two antipad radii

    www.xilinx.com/si_xcell.htmS I G N A L I N T E G R I T Y

  • insertion loss has been pushed up from6.5 GHz to roughly 7.75 GHz. This isone of the simplest modifications thatcan be made to a PCB board file andshould be considered for all high-per-formance designs.

    ConnectorsA common connector used to transitionbetween boards and differential coaxialcables is the Molex very high densitymetric-high-speed differential (VHDM-HSD). Ansoft HFSS performed simula-tions of such a connector (Figure 8). Onone side of the connector are three twin-ax cables; on the other side is a backplaneboard with its associated escape routing.

    Figure 9 plots the insertion andreturn loss versus frequency for theVHDM connector without the escaperouting. This connector provides a veryflat insertion loss across the band. Returnloss is below 10 dB up to 3 GHz.

    Results for the connector (includingall escape routing) are computed by cas-cading S-parameters from the individualHFSS models for the connector and thebackplane escape routing. Including thebackplane board, escape routing to themodel has a significant effect.

    Figure 10 plots the differential S-parameters for a channel containing aworst case via transition that leaves a longunterminated via stub. The performanceof the VHDM connector is dominatedby the sharp resonance of the via stubthat manifests itself at 6.5 GHz.

    System SimulationIt is possible to cascade results generatedfrom EM and circuit simulations to get afull system simulation. Figure 11 plotscircuit simulation results displaying theinsertion and return loss up to 10 GHz.As expected, the channel has a responsesimilar to a low pass filter.

    We performed time domain simula-tion using the system simulator inAnsoft Designer. This simulator uses aconvolution algorithm to process thefrequency domain channel data withuser-defined input bitstreams.Insertion and return loss are included

    in the simulation. A 3.2 Gbps pseu-do-random bit source with a 1Vpeak-to-peak amplitude and 125 psrisetime was applied to the channel.The channel was terminated in sin-gle-ended 50 Ohm resistors.

    Figure 12 shows the resulting eyediagram as very clear and open,despite the significant channelimpairments in the frequency domainresults. We did not apply any pre-emphasis in the simulation. You

    should anticipate thatsome pre-emphasis wouldsharpen the time-domainresponse.

    ConclusionModern platform FPGAdevices provide widebandwidth processing andhigh-speed I/O. Serial I/Owith speeds in the gigabit

    realm creates new challenges for PCBdesigners.

    You can solve the high-speed I/Ochallenges posed by modern platformFPGA devices using EM, circuit andsystem simulators. Although wefocused our attention on the passiveinterconnect in this article, it is possi-ble to include nonlinear I/O driversand receivers in the simulation toobtain additional insight to systemperformance. Indeed, you can use anew tool from Ansoft calledNexxim to simulate all circuitbehavior for systems including EM-based models, linear, and nonlinearcircuits. Visit www.ansoft.com formore information about AnsoftDesigner and Nexxim.

    References[1] Williams, L., S. Rousselle, and B. Boots,Cray Supercomputer 3.2 Gb/s SerialInterconnect Simulation Using Full-waveElectromagnetics, in DesignCon 2004Conference Proceedings, Santa Clara,CA, Feb. 2-5, 2004.

    [2] Williams, L., S. Rousselle, and B. Boots, Circuit board design for 10Gbit XFP optical modules. EDN, May 29, 2002, pp. 63-70.

    Summer 2004 Xcell Journal 23

    Figure 9 Differential S-parameters for the Molex VHDM-HSD connector in isolation

    Figure 10 Differential S-parameters for the Molex VHDM-HSD connector with backplane escape routing. This worst-case channel with large via stub

    shows signature resonance at 6.5 GHz.

    Figure 11 Full-channel cascaded performance using themodels developed from EM simulations up to 10 GHz

    Figure 12 Full-channel eye diagram using convolutionsystem simulator in Ansoft Designer for the cascaded

    model with a 125 ps risetime

    VHDM Connector

    Wor

    st C

    ase

    Route Layer: s1(Via Stub: 123.95 mil)

    www.xilinx.com/si_xcell.htm S I G N A L I N T E G R I T Y

  • With a built-in EM solver, coupled transmission lines,S-parameter support, and IBIS I/O buffer models,HSPICE provides a comprehensive multi-gigabit signal integrity simulation solution.

    With a built-in EM solver, coupled transmission lines,S-parameter support, and IBIS I/O buffer models,HSPICE provides a comprehensive multi-gigabit signal integrity simulation solution.

    Accurate Multi-Gigabit Link Simulation with HSPICEAccurate Multi-Gigabit Link Simulation with HSPICE

    24 Xcell Journal Summer 2004

    www.xilinx.com/si_xcell.htmS I G N A L I N T E G R I T Y

  • by Scott Wedge, Ph.D.Sr. Staff EngineerSynopsys, [email protected]

    The Xilinx Serial Tsunami Initiative hasresulted in a host of multi-gigabit serial I/Osolutions that offer reduced costs, simplersystem designs, and scalability to meet newbandwidth requirements. Serial solutionsare now deployed in a variety of electronicproducts across a range of industries.Reduced pin count, reduced connector andpackage costs, and higher speeds havemotivated the trend towards serialization oftraditionally parallel interfaces.

    RocketIO multi-gigabit transceivers(MGTs), for example, offer tremendousperformance and functionality for connect-ing chips, boards, and backplanes at gigabitspeeds. Whether your application isInfiniBand, PCI Express, or 10Gigabit Application Unit Interface(XAUI), RocketIO MGTs offer ideal inter-face solutions.

    However, the transition from slow, widesynchronous parallel buses to multi-lane,multi-gigabit asynchronous serial channelsintroduces new physical and electricaldesign challenges that traditionally fallmore into the realm of radio frequency(RF) design than digital I/O design. Thephysical characteristics of the signal chan-nel must be known and carefully controlledto ensure proper performance. At suchhigh data rates, you must take into accounta long list of analog, RF, and electromag-netic effects to guarantee a working design.

    Life in the Fast LaneReliable operation of multiple transmit andreceive lanes running up to 3.125 Gbpsrequires special attention to power condi-tioning, reference clock design, and to thedesign of the lanes themselves. You mustmatch the differential signal trace lengthsto tight tolerances. A length mismatch of1.4 mm will produce a timing skew ofroughly 10 ps, which is appreciable at thesedata rates. You must carefully control traceimpedances and keep reference planesintact to avoid mismatches and signalreflections. Spacing between lanes must be

    Lossy, coupled transmission line mod-eling with the W-element

    Single-ended and mixed-mode S-parameter modeling with the S-element

    I/O buffer modeling with I/O BufferInformation Specification (IBIS) models and encrypted netlists.

    Getting from Maxwell to ModelsAccording to electromagnetic theory, at highfrequencies every millimeter of metal willinfluence electrical behavior. As depicted inFigure 1, one challenge in multi-gigabit SI isto reduce the significant aspects of EM the-ory into something useful for circuit-levelsimulation. Maxwells equations must bereduced to something manageable; youmust analyze the electromagnetic character-istics of the interconnect system to build anappropriate model for circuit simulation.

    HSPICE includes a built-in electromag-netic field solver for computing the electri-cal characteristics of coupled transmissionline systems. The solver is ideal for multi-lane, multi-gigabit applications. It uses aGreens function boundary element and fil-ament method that yields very accurateresistance, inductance, conductance, and

    adequate to avoid crosstalk, but remainspace-efficient.

    Meeting these challenges requires usingsignal integrity (SI) simulations to uncoverand help solve potential problems beforefabrication. This is nothing new, but thetrick is to now take into account severalpreviously ignored factors that are detri-mental to gigabit link design.

    Consider the traces. Perhaps by nowyouve grown accustomed to using trans-mission lines in signal integrity simula-tions. But simple lossless, uncoupledtransmission line models are just not goodenough for MGT links. Frequency-dependent conductor and dielectric losses especially in FR4 are substantial andmandate a more sophisticated approach.Your basic gigabit trace is a differential cou-pled transmission line with considerableloss and must be treated as such to findoptimal driver pre-emphasis settings.

    To address these and other problems,HSPICE provides a comprehensive set ofSI simulation and modeling capabilities tohelp you achieve the necessary accuracy formulti-gigabit SI simulations. HSPICEincludes:

    Built-in electromagnetic (EM) solvertechnology for trace geometries

    Summer 2004 Xcell Journal 25

    S-element Single-Ended ScatteringParameters

    S-element Mixed-Mode Scattering Parameters

    W-element LossyCoupled TransmissionLine RLGC Models

    Figure 1 Achieving accurate gigabit signaling channel simulations mandates the use of models that can take into account key electromagnetic effects.

    www.xilinx.com/si_xcell.htm S I G N A L I N T E G R I T Y

  • capacitance (RLGC) matrices for the typesof differential traces youll need for gigabitdesign. You need only perform a fieldsolver analysis for each unique cross-sec-tional geometry.

    HSPICE field solver analysis will pro-duce a characterization of the interconnectsystem in terms of distributed RLGCmatrices. Frequency-dependent loss effectsare included in the Rs and Gd matrix ele-ments. Be sure to enable these field solveroptions; at gigabit data rates these lossescan be substantial.

    The conductor losses ( ) and dielec-tric losses ( ) are both significant at3.125 Gbps, and must be well modeled todetermine your pre-emphasis needs forlong lane lengths. Dont guess when speci-fying your material properties. The relativedielectric constant (4.2-4.7 for FR4) willinfluence line impedance (C matrix) values; electrical conductivity (5.8e7 forcopper) will show up as skin effect (Rmatrix) losses; and dielectric loss tangentvalues (typically 0.015-0.03 for FR4) willshow up as substrate (G matrix) losses.

    Fortunately, board manufacturers aregetting better at measuring and sharingsuch information. Many accurate W-ele-ment RLGC matrix models are availabledirectly from vendors. Be sure to verify thatfrequency-dependent Rs and Gd values areincluded to ensure that loss modeling wastaken into account. HSPICEs built-in EMsolver is also well suited for copper cablegeometries in cases where manufacturersdo not have W-element models available.

    Mixed-Mode Scattering ParametersAs shown in Figure 2, accurate SI simula-tion of multi-gigabit links involves a varietyof models. For certain package, trace, con-nector, backplane, and cable sections,measured data or very accurate three-dimensional EM solver data is often avail-able in the form of scattering parameters(Figure 3).

    S-parameters represent complex ratiosof forward and reflected voltage waves.Used as an alternative to other frequencydomain representations (such as Y- or Z-parameters), S-parameters lack the dramaticmagnitude variations that other representa-

    26 Xcell Journal Summer 2004

    Figure 2 Simulations for MGT chip-to-chip, backplane, and copper cable applications combine a diverse set of models for accurate signal integrity predictions.

    Figure 3 Typical scattering parameters for an interconnect system showing the transmission coefficient(S21) for one interconnect (violet), the reflection coefficient (S11) for the same interconnect (green), and thecoupling coefficient (S31) between adjacent interconnects (light blue) over a frequency sweep of 0-10 GHz.

    www.xilinx.com/si_xcell.htmS I G N A L I N T E G R I T Y

  • tions have associated with high-frequencyresonance. In addition, they can be meas-ured directly with vector network analyz-ers. With differential traces the norm forXAUI and other links, mixed-mode S-parameters are particularly useful. Theyprovide a means to characterize a differen-tial trace in terms of its differential, com-mon-mode, and cross-coupled behavior.

    HSPICE provides single-ended andmixed-mode S-parameter modeling capa-bility through the S-element. You can inputS-parameter data in Touchstone file,CITI file, or table formats. Make sure yourS-parameter data covers as broad a frequen-cy range as possible with good sampling.

    HSPICE will apply convolution calcu-lations that need high-frequency values forcrisp simulations of waveform rises andfalls. If you have data up to 20 or 40 GHz,use it. A frequency range nine times yourdata rate (28 GHz for 3.125 Gbps) is con-sidered optimal, although often hard tocome by. Good low-frequency data(including DC) is also important fordirect-coupled applications.

    Beware of measurement noise with S-parameters. A poor network analyzer cali-bration can result in S-parameter data thatwill make your passive traces appear tohave gain. HSPICE also supports S-param-eter modeling for active devices, as is com-mon with some RF/microwave designs.HSPICE uses a convolution algorithm forS-parameter modeling that is not limited topassive devices, avoiding the creation ofintermediate, reduced-order modelsrequired by other time-domain simulationapproaches. HSPICE uses the S-parameterresponse directly for maximum accuracy.

    I/O Buffer Modeling Ideally, you can perform SI simulationsusing transistor-level models and netlistsfor the input/output buffers. This level ofdetail may be unwieldy, but is sometimesnecessary. The IBIS standard provides ameans of encapsulating the key electricalcharacteristics of I/O buffers into accuratebehavioral models. These models includedata tables for buffer drive and switchingability, and package parasitic information.These models may or may not be appro-

    priate for high-speed applications,depending on their intended use. Be sureto check the notes in the header of yourIBIS model files so that youre not push-ing the model outside its range of validity.There is also a new IBIS InterconnectModeling Specification (ICM) forexchanging S-parameter and RLGCmatrix data for connectors, cables, pack-ages, and other types of interconnects.

    Another advantage of IBIS is that itallows vendors to deliver good buffer mod-els to their customers without disclosingproprietary design information. This is alsoaccomplished with encrypted HSPICEnetlists. Multi-gigabit transceiver modelingis particularly difficult, so be prepared tosee several buffer modeling approaches.

    In the case of RocketIO transceivers,Xilinx provides special MGT models verifiedwith HSPICE; visit the Xilinx SupportSPICE Suite at www.xilinx.com/support/software/spice/spice-request.htm for moreinformation. Whether youre using IBIS,SPICE netlist, or encrypted buffer models,HSPICE provides the most comprehe