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Xcell Journal Issue 50 - Xilinx...THE AUTHORITATIVE JOURNAL FOR PROGRAMMABLE LOGIC USERS R ISSUE 50, FALL 2004 XCELL JOURNAL XILINX, INC. Xcell journal COVER STORY COVER STORY FPGAs

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  • T H E A U T H O R I T A T I V E J O U R N A L F O R P R O G R A M M A B L E L O G I C U S E R S

    R

    Xcell journalXcell journalT H E A U T H O R I T A T I V E J O U R N A L F O R P R O G R A M M A B L E L O G I C U S E R S

    ISSUE 50, FALL 2004XCELL JOURNAL

    XILINX, INC.

    COVER STORY FPGAs on MarsCOVER STORY FPGAs on Mars

    MEMORY DESIGN

    Streaming Data at 10 Gbps

    Control Your QDR Designs

    PARTNERSHIP

    20 Years of Partnership

    Author! Author!

    Programmable World 2004

    SOFTWARE

    Algorithmic C Synthesis

    The Need for Speed

    MANUFACTURING

    Lower PCB Mfg. Costs

    Optimize PCB Routability

    MEMORY DESIGN

    Streaming Data at 10 Gbps

    Control Your QDR Designs

    PARTNERSHIP

    20 Years of Partnership

    Author! Author!

    Programmable World 2004

    SOFTWARE

    Algorithmic C Synthesis

    The Need for Speed

    MANUFACTURING

    Lower PCB Mfg. Costs

    Optimize PCB Routability

    Issue 50Fall 2004

  • Your ASIC

    The world’s lowest-cost FPGAs

    Spartan-3 Platform FPGAs deliver everything you need at the price you want. Leading the way in 90nm

    process technology, the new Spartan-3 devices are driving down costs in a huge range of high-capability,

    cost-sensitive applications. With the industry’s widest density range in its class — 50K to 5 Million

    gates — the Spartan-3 family gives you unbeatable value and flexibility.

    Lots of features … without compromising on price

    Check it out. You get 18x18 embedded multipliers for XtremeDSP™ processing in a low-cost

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    solutions. Plus our XCITE technology improves signal integrity, while eliminating hundreds

    of resistors to simplify board layout and reduce your bill of materials.

    With the lowest cost per I/O and lowest cost per logic cell, Spartan-3 Platform

    FPGAs are the perfect fit for any design … and any budget.

    MAKE IT YOUR ASIC

    The Programmable Logic CompanySM

    For more information visitwww.xilinx.com/spartan3

    Make ItThe New SPARTAN™-3

    Pb-free devicesavailable now

    ©2004 Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124. Europe +44-870-7350-600; Japan +81-3-5321-7711; Asia Pacific +852-2-424-5200; Xilinx is a registered trademark, Spartan and XtremeDSP are trademarks, and The Programmable Logic Company is a service mark of Xilinx, Inc.

  • EEver have one of those days where you’re working hard, nose to the grindstone, striving to make sureyour latest project is on time and on target; and then suddenly out of nowhere, you overhear some-one complimenting your efforts? It’s not a comment that you solicited, but independently you findout that all of your hard work is recognized as the best among your peers and you’re headed in theright direction.CMP Media LLC, the parent company of EETimes, just dropped quite a few kudos on the Xilinxdoorstep. Most of you know that every year CMP conducts a PCB and IC electronic design toolindustry survey to sample the engineering community’s view on design tool providers. This year, at the2004 Design Automation Conference, CMP announced the results of their first FPGA vendor survey.

    The ratings are striking. In 21 out of 22 categories measuring everything from best pre-sales supportto brand and tool awareness, from most ethical company to customer loyalty, FPGA designers choseXilinx as the top FPGA vendor. We received the highest rankings in best after-sales support, bestdocumentation, current technology leader, technology leader in three years, clear vision of thefuture, best integration with other vendors’ tools, well-managed company, and more.

    We were also able to hear the industry concerns. Respondents cited the accuracy and integrity of FPGAtools as their biggest design issue, followed closely by functional verification, timing closure, and theability of those tools to easily handle complex designs. They also said that the majority of their designtime was spent in place and route, synthesis, and HDL simulation, followed by timing analysis andfloorplanning. One-third of the respondents also use formal verification, while almost half regularlyuse signal integrity and C language system-level tools.

    On behalf of all of the employees at Xilinx, thank you. We hear you loud and clear. Our primary goalis to put a programmable device in every piece of electronic equipment over the next 10 years. It’s niceto hear that we’re on the right path to get there.

    L E T T E R F R O M T H E E D I T O R

    Xilinx, Inc.2100 Logic DriveSan Jose, CA 95124-3400Phone: 408-559-7778FAX: 408-879-4780©2004 Xilinx, Inc.All rights reserved.

    The Xcell Journal is published quarterly. XILINX, the Xilinxlogo, CoolRunner, RocketChips, Rocket IP, Spartan,StateBENCH, StateCAD, Virtex, Virtex-II, and XACT are regis-tered trademarks of Xilinx, Inc. ACE Controller, ACE Flash,Alliance Series, AllianceCORE, Bencher, ChipScope,Configuration Logic Cell, CORE Generator, CoreLINX, DualBlock, EZTag, Fast CLK, Fast CONNECT, Foundation, GigabitSpeeds…and Beyond!, HardWire, HDL Bencher, IRL, JDrive, Jbits, LCA, LogiBLOX, Logic Cell, Logic Professor,MicroBlaze, MicroVia, MultiLINX, NanoBlaze, PicoBlaze,PLUSASM, PowerGuide, PowerMaze, QPro, Real-PCI,RocketIO, RocketPHY, SelectIO, SelectRAM, SelectRAM+,Silicon Xpresso, Smartguide, Smart-IP, SmartSearch,SMARTswitch, System ACE, Testbench In A Minute, TrueMap,UIM, VectorMaze, VersaBlock, VersaRing, Virtex-4, Virtex-IIPro, Virtex-II Pro X, Virtex-II EasyPath, Wave Table,WebFITTER, WebPACK, WebPOWERED, XABLE, XAPP, X-BLOX+, XC designated products, XChecker, XDM, XEPLD,Xilinx Foundation Series, Xilinx XDTV, Xinfo, XtremeDSP,and ZERO+ are trademarks, and The Programmable LogicCompany is a service mark of Xilinx, Inc. Other brand orproduct names are registered trademarks or trademarks oftheir respective owners.

    The articles, information, and other materials included inthis issue are provided solely for the convenience of ourreaders. Xilinx makes no warranties, express, implied,statutory, or otherwise, and accepts no liability with respectto any such articles, information, or other materials ortheir use, and any use thereof is solely at the risk of theuser. Any person or entity using such information in anyway releases and waives any claim it might have againstXilinx for any loss, damage, or expense caused thereby.

    Thank You for MakingXilinx Number One

    Xcell journalXcell journal

    Forrest CouchManaging Editor

    EDITOR IN CHIEF Carlis [email protected]

    MANAGING EDITOR Forrest [email protected]

    ASSISTANT MANAGING EDITOR Charmaine Cooper Hussain

    XCELL ONLINE EDITOR Tom [email protected]

    ADVERTISING SALES Dan Teie1-800-493-5551

    ART DIRECTOR Scott Blair

  • Next-Generation DataTransport over Metro Area NetworksThe Xilinx GFP core enables efficient

    transport of LAN/SAN over

    SONET-based networks. 64

    Celebrating 20 Years of PartnershipTurning an industry cliché into

    a successful business model.

    21

    F A L L 2 0 0 4, I S S U E 5 0 Xcell journalXcell journalC O V E R S T O R Y

    FPGAs on MarsXilinx FPGAs have transitioned from

    a flight ASIC prototyping platform

    to playing integral roles in the

    Mars Exploration Rover Mission.

    8

    Streaming Data at 10 GbpsUsing a Virtex-II FPGA to stream data from DDR-SDRAM to OC-192 serializers.

    13

    View from the Top ................................................................5

    FPGAs on Mars.....................................................................8

    Streaming Data at 10 Gbps .................................................13

    Control Your QDR Designs ....................................................16

    Celebrating 20 Years of Partnership.......................................21

    Author! Author! .................................................................25

    Experience Programmable World 2004..................................30

    Managing Partial Dynamic Reconfiguration .............................32

    Nucleus RTOS for Xilinx FPGAs..............................................38

    Implement an Embedded System with FPGAs .........................43

    Algorithmic C Synthesis .......................................................46

    Design Tool Performance Lowers Costs...................................52

    The Need for Speed ............................................................54

    Lower Your PCB Manufacturing Costs.....................................57

    Plan FPGA Signal Assignments..............................................60

    Next-Generation Data Transport.............................................64

    Designing Next-Generation Wireless Systems ..........................68

    Meeting Interoperability Standards ........................................70

    Xilinx Partner Yellow Pages ..................................................74

    Reference Pages .................................................................82

    To receive a free subscription to the printed Xcell Journal,

    or to view the Web-based Xcell Online, visit www.xilinx.com/xcell/.

    http://www.xilinx.com/xcell/

  • We recently emergedfrom a three-yearrecession that was oneof the longest anddeepest in our history,yet things are gettingbetter. The semicon-ductor industry typi-cally moves in atwo-year cycle, unlessit is influenced by

    events such as the 9/11 tragedy. Therefore, aftertwo years of growth, an overbuilding of capacitywill likely occur, with another market correctionin 2006. This is a normal and predictable cycle;it’s the way our industry usually works.

    These capacity-driven recessions tend to beshallow and short – the last one was in 1996and lasted about 18 months. For Xilinx® dur-ing that period, we had a few negative growthquarters, with an overall 1% growth.

    The market recovery is still fragile, drivenprimarily by the U.S. and China. And not all ofthe industries that we deal with are yet in recov-ery, which I think is good because it helps usmaintain a steady growth pattern as they beginto improve later in the year.

    Overall, Xilinx is in an extremely good posi-tion – our business processes, our manufactur-ing technology, our circuit innovation, and oursoftware are poised to take full advantage of thecurrent market conditions.

    The economy is improving and most analysts predict that the semiconductor industry will grow for the next two years.Here’s what I see ahead for Xilinx.

    Preparing for a Bright FuturePreparing for a Bright Future

    Fall 2004 Xcell Journal 5

    Viewfrom the top

    by Wim RoelandtsCEO, Xilinx, Inc.

  • The Growing Asian MarketsA significant and quickly growing segmentof our business comes from the Japaneseand Asia-Pacific markets – our businessthere is now more than three times higherthan it was just four years ago. This comesboth from systems that are designed andmanufactured there as well as from manu-facturing outsourced from other countries.Plus, Japanese business is starting toexpand and is beginning to help drive theworld economy forward.

    I believe our business in Asia will con-tinue to grow over the years to come. Wesee a big shift taking place, driven primarilyby the next big trend in our industry – dig-ital consumer electronics. The core of thisbusiness will be in Asia, and we are puttinga lot of our resources there to help meet thedemand. We recently began staffing a facil-ity in Singapore that will eventually housemore than 200 employees.

    Going MainstreamEight years ago, when I joined Xilinx, I saidthat we will put a programmable chip inevery system, and it’s now becoming a reali-ty. Our ability to shrink our products intosmaller and smaller geometries at lowercosts, coupled with the recession (whichmeans that many of our customers can nolonger afford the high costs of designing andbuilding ASICs) is moving more and moreof our customers to take full advantage ofthe many benefits of programmable logic.

    Market forces, combined with our low-cost technology advances, are driving pro-grammable logic into the mainstream – ourdevices are now used in all types of prod-ucts and the trend continues to grow. Overthe next two or three years, when these newdesigns go into production, our businesswill expand significantly. Programmablelogic is indeed taking over; it is becomingmainstream and finding new marketswhere it’s never been used before.

    Because cores allow us to provide a morecomplete solution, our customers have todo less work to produce more and betterdesigns. And they want to buy cores fromXilinx because they want to have the assur-ance of ongoing long-term support. We arein fact increasing our investments in IP andcores to meet the increasing demand. Wealready have many more cores than ourcompetitors, and thus we are very wellpositioned to take advantage of thesetrends.

    Xilinx Strategy for the FutureHere are some of the long-term objectivesthat define our strategy for the next five to10 years.

    Setting the StandardWe will continue to set the standard forhow to manage a high-tech company. Ithink we have already done a phenomenal

    job – we’re admired as a company thatmanages its people well, treats its peoplewell, and at the same time is innovative andwins in the market. And of course, the coreof our culture is innovation. We want tocontinue to bring new technologies, newcircuitries, new innovative marketing pro-grams, and new channels of distribution.This will continue to be the core of ourstrategy because it’s what makes Xilinxexcel in everything we do.

    Leading Manufacturing TechnologyWe will continue to reduce our manufac-turing costs. We made a lot of progress inthe last year and now we need to move onto the next step. My intention is to makesure that all of our organizations arefocused on low-cost, high-volume capabili-ties. The consumer electronics and auto-motive industries require us to reduce costsand ramp production faster than everbefore. We will continue to innovate with-

    Beating Moore’s LawSemiconductor technology typically fol-lows Moore’s Law, which states that everytwo years the number of transistors thatcan be fabricated on a chip will double –this law has held true for many years. As weapproach finer and finer process geome-tries, moving from 130 nm to 90 nm anddown to 65 nm, it becomes increasinglydifficult to manufacture devices. Xilinx isleading the industry in the developmentand use of these advanced technologies,which means that we are often the first tosolve difficult process problems – that’sboth the good and the bad news. We usu-ally get to market first with the mostadvanced manufacturing processes, but wealso put a lot of effort into getting it right.

    We also have a strategy for significantlyimproving performance through innova-tive architectural designs – the best exam-ple is our new Virtex-4™ family. In fact,

    most of our performance improvements inthe Virtex-4 family come from circuitenhancements. The Virtex-4 ASMBLarchitecture allows us to create devices thatare optimized for specific applications, pro-viding just the features and performancethat are needed at the lowest possible cost.As you can see, our innovation is not just inCMOS technology – we are way ahead ofour competition in both device manufac-turing technology and architecture.

    Reducing Design Costs with IPOur marketplace is changing rapidly, andour customers must operate differentlytoday than they did four years ago. Theirown customers are much more cost-con-scious, and thus they are much more wor-ried about return on investments. Ourcustomers have fewer engineers because ofthe recession, so they demand more fromus – it’s one of the reasons why we areincreasing our investments in IP and cores.

    6 Xcell Journal Fall 2004

    V I E W F R O M T H E T O P

    Programmable logic is indeed taking over; it is becoming mainstream and finding new markets where it’s never been used before.

  • in all of our organizations to achieve thisongoing objective. For programmable logicto achieve its full potential in mainstreamelectronics, we must become even moreefficient and productive – and we will.

    Yet, while we continue to develop morehigh-volume strategies and products, wewill continue to lead the high-end, high-performance market that has traditionallybeen the core of our business. We are doinga phenomenal job with our Virtex productline, with 70% to 80% market share, andthat will continue as well.

    Creating PartnershipsPartnerships are a key strategy that allowus to focus on what we do best whileallowing other companies to provide theproducts and services they do best – wecall it our Partner Ecosystem. We willcontinue to build strong partnerships notonly with our suppliers but with our cus-tomers as well.

    We want to engage our customers earlyin their design process so that we can pro-vide the best possible service and supportthroughout their entire design and manu-facturing cycle. This requires a broad rangeof services from a number of ecosystempartners, and that requires a well coordi-nated and comprehensive approach. Wehave been successful with our partnershipprogram in the past and we intend tostrengthen it by making it easier for ourcustomer partners – and our technologypartners – to work more closely togetherfor the benefit of all.

    Expanding Our MarketsWe are already the leader in programma-ble logic technology, and now it’s time forus to become a leader in all programma-ble technology, including DSP andembedded processing. Our technologyalready provides significant advantages inthese areas, and it’s time for us to capital-ize on these strengths. We want to be thechampion of programmability because we

    are the only company that can providethe advantages of programmable logic,high-performance DSP, and embeddedprocessing all on one device.

    We are the largest company in program-

    mable logic, with 50% market segmentshare. However, the embedded processormarket and the DSP markets also offer sig-nificant market opportunity.

    Brand RecognitionXilinx is already well respected and recog-nized in our marketplace, and we willcontinue to build our brand worldwide.Our success in the first 10 years was basedon two innovations: FPGAs and fablessmanufacturing. When we started in1985, neither of these ideas was credible.Only the Xilinx founders believed they

    would work. Yet we made them possibleand we made them credible.

    Our second 10 years were based on twothings: becoming the technology leader inour industry and establishing a unique

    business culture that fostersinnovation. In that we havealso been very successful.

    For the next 10 years, wewant to extend our brand andestablish Xilinx as a globalleader, recognized not only bythe engineering community butalso by the financial communi-ty. We want to be recognizednot only for our innovative cul-ture but also for our financialstability, management depth,the global reach and diversity ofour products, and by the brandname we create.

    Going GlobalWe will continue to expandglobally and place ourresources close to the marketsthey serve. If 20% of our busi-ness is in Asia, we will strive toplace 20% of our resourcesthere because we want to beclose to our customers andunderstand their needs. That’swhy we opened up a new fac-tory headquarters in Singapore

    and a new design center in India. We wantto have a presence in Asia just like we havein Europe and the United States.

    ConclusionInnovation remains the core of Xilinx. I

    believe innovation is the only thing thatmatters because if you innovate, there is nocompetition. That’s the reason why wehave gained market share every single yearin the last six years.

    As you can see I’m very excited aboutour current situation, and I’m even moreexcited about our future.

    V I E W F R O M T H E T O P

    Fall 2004 Xcell Journal 7

    For the next 10 years, we want to extend our brand and establish Xilinx as a global leader,recognized not only by the engineering community but also by the financial community.

  • by David RatterField Applications EngineerNu Horizons [email protected]

    Selecting the correct components for any engi-neering project can be a critical and difficultchoice. This is clearly true for engineers at the JetPropulsion Laboratory (JPL) when they mustselect components used on high-stakes flight proj-ects, and especially important on high-profile mis-sions like the Mars Exploration Rover Mission.

    On Mars there are no tow trucks or auto clubsto call if something stops working. So how didXilinx FPGAs go from performing a predomi-nantly flight ASIC prototyping role to beingdesigned into and flown in projects like the Marslander and rovers? And what does the future holdfor Xilinx and JPL space missions?

    Xilinx FPGAs have transitioned from a flight ASIC prototyping platform to playing integral roles in the Mars Exploration Rover Mission.

    Xilinx FPGAs have transitioned from a flight ASIC prototyping platform to playing integral roles in the Mars Exploration Rover Mission.

    FPGAs on MarsFPGAs on Mars

    8 Xcell Journal Fall 2004

  • The needs of JPL’s design engineers werethe main driving force behind the paradigmshift from ASIC prototype to flight-quali-fied part, as were the Xilinx testing, pro-cessing, and manufacturing flows for itsradiation-tolerant FPGAs. Engineeringneeds demand meeting mission require-ments, both from a functional/performanceviewpoint and a time-to-working-productviewpoint. Xilinx FPGAs provide inherentdesign advantages to meet those needs: highgate densities, rich on-board architecturalfeatures, large I/O counts with multiple I/Ostandards, and the ability to be repro-grammed at any time.

    The second reason for the transitionwas JPL’s qualification of Xilinx radiation-tolerant FPGAs into more and more flightsituations.

    The net results of these efforts can easi-ly be seen on the Mars Exploration Rovers.Inside of each rover (named Discovery andSpirit), two Virtex ™ XQVR1000s servedas the main brains that controlled themotors. Four Xilinx XQR4062XL devicesin the 4000XL family controlled the Marslander pyrotechnics, crucial to the success-ful multi-phase descent and landing proce-dure. Also evident, although not as visible,are the increasing number of future flightmissions that JPL engineers are designingwith Xilinx radiation-tolerant FPGAs.

    In this article, we’ll briefly documentthe parts qualification and design steps,along with the past, present, and future ofFPGA-based flight opportunities at JPL.

    Flight ConsiderationsThere are three steps that must be accom-plished before any part can be used in aflight application for JPL. The first is ageneral flight approval for a part. The sec-ond can be referred to as mission-specificapproval. The third is additional designrequirements for flight-based semicon-ductors.

    General Flight ApprovalsJPL must give general flight approvalbefore any part can be used for a flightapplication. This process requires that themanufacturer perform numerous addition-al processing, testing, and quality steps

    parameters might include the number oftemperature cycles, total ionizing dose, andpredicted rate of radiation exposure. It ispossible that parts with general flightapproval will not get mission-specific flightapproval.

    Specific Flight Design ConsiderationsOnly after a part has met the above two cri-teria can it be used in a flight mission. Thedesign process entails incorporating space-specific flight design requirements thatinclude, but are not limited to, the follow-ing single-event phenomena:

    • Single-event latch-up (SEL)

    • Single-event upsets (SEU)

    • Single-event transients (SET)

    • Single-event functional interrupts(SEFIs)

    In the case of Xilinx radiation-tolerantFPGAs, all single-event phenomena aretaken into account either through the radi-ation-tolerant manufacturing and process-ing steps or through well-documenteddesign practices:

    • The epitaxial layer of Xilinx radiation-tolerant FPGAs eliminates SELs.

    • Triple-mode redundancy (commonlyreferred to as TMR) mitigates SEUsand SETs.

    • “Scrubbing,” or reprogramming theFGPA, takes care of SEFIs and theaccumulation of SEUs.

    Let’s discuss the latter two design fea-tures in more detail.

    In simple terms, a design with TMRrequires three sets of key logic elements, witha voting structure that allows only the major-ity decision to propagate through the circuit.The theory is that statistically you are goingto get an SEU over some time period. Whenthis upset occurs, it will disrupt a single ele-ment (net, route, or bit). When this happensand the element it disrupts is being used, theother two “correct” elements will have thecorrect value; thus, the correct value will bepassed out of the circuit. This is especiallyimportant in circuits that use feedback, suchas counters and state machines.

    over and above the normal commercialprocessing steps.

    JPL also meticulously examines devicestatistical and quality data that is constantlyupdated by the semiconductor manufactur-ers. They also examine additional parame-ters in this phase, including temperatureconsiderations and packaging materials aswell as semiconductor characteristics (forexample, are there voids or contaminantsthat in zero gravity could migrate and causefailures?). Only after JPL engineers haveconducted exhaustive research and analysisdo they approve parts for flight use.

    JPL Radiation Effects Group scientistswork directly with Xilinx to unify andcontinually improve the testing, process-ing, and manufacturing steps used forXilinx radiation-tolerant parts. This closecustomer/manufacturer relationship hasresulted in a much superior radiation-tol-erant product from Xilinx, and for JPL, ahigh-reliability manufacturing processgives them the utmost confidence.

    Specific Flight ApprovalsEven after a part or parts has general flightapproval, it still must receive mission-specific flight approval. Mission-specificapproval is exactly what the term implies:JPL scientists and engineers review themission-specific environments that theparts will encounter. This includes adetailed risk assessment.

    JPL takes into account all aspects of theflight to predict what the part(s) will faceduring the mission’s lifetime. Some of these

    Fall 2004 Xcell Journal 9

  • Numerous approaches can be takenwith respect to scrubbing, from simplyreprogramming the FPGA to partial recon-figuration. The simplest method of scrub-bing is to completely reprogram the FPGAat some periodic rate (typically 1/10 thecalculated upset rate).

    For example, if an SEU will occur onceevery 10 days, then you would reprogramthe FPGA every day. However, when youreprogram the FPGA it is not operationalduring that reprogram time (on the orderof micro to milliseconds). For situationsthat cannot tolerate that type of interrup-tion, partial reconfiguration is available.This technique allows the FPGA to bereprogrammed while still operational.

    The PastAlthough the both the Discovery and Spiritrovers are still on the surface of Mars andactive, they were launched in June and July2003 and landed on Mars in January 2004.This means, obviously, that the engineeringwas completed in the past.

    As stated earlier, the Mars ExplorationRovers used XQVR1000 devices and thelander used XQR4062XLs. TheXQR4062XLs were used during thedescent and landing of the rovers on thesurface of Mars, while the XQVR1000swere used to control all of the brushed DCand stepper motors for the wheels, steering,antennas, camera, and other instrumentson the rovers themselves.

    Both the XQR4062XL and XQVR1000designs used TMR for SEU and SET miti-gation as well as scrubbing. JPL engineersachieved TMR in their designs by analyz-ing the design for feedback nets and otherlow-level design details (as detailed inXilinx application note XAPP197), andthen inserted or replaced logic with TMRlibrary elements. After the designs werefunctionally implemented, the engineerswent back through the design and insertedthe TMR logic where necessary and madeother space-specific design changes.

    Due to the critical nature of theXQR4062XL’s role, FPGA redundancy wasutilized to mitigate all single-event phe-nomena. The scrubbing techniqueemployed was a complete reconfiguration.

    When an upset condition was detected, theFPGA in question was completely repro-grammed, while the redundant FPGAsremained functional. On the other hand,because of its non-time critical nature, whena fault condition was detected on one of theXQVR1000s, the rover was temporarilyhalted, the FPGA was reprogrammed, andthe rover went back on its merry way.

    All of the mitigation techniques on theMars Exploration Rovers worked exactlyas designed by JPL engineers. During theseven-month voyage from Earth to Mars,the Xilinx radiation-tolerant FPGAs onthe lander were “left on.” During thattime JPL collected data of interest,including the upset rate. The upset ratespredicted for the FPGAs by JPL matchedalmost exactly the actual upset ratesobserved. Also, the upset detection andmitigation techniques implemented onthe FPGAs performed their functionsflawlessly and allowed for robust and reli-able operation.

    The PresentJPL is currently working on flight designswith both Virtex-II™, the latest Xilinxradiation-tolerant family, as well as Virtexradiation-tolerant FPGAs. These new mis-sions will fly in the next two to five yearsand are becoming more and more sophisti-cated in both mission electronic require-ments and design implementation. Thesecurrent projects more fully utilize theFPGA’s inherent benefits.

    JPL is particularly interested in the abil-ity to update or revise designs while thespacecraft is either in flight to its final des-tination or already there. This will allowengineers to implement algorithmenhancements after the spacecraft has leftEarth, enabling them to constantlyimprove design performance during a longmission timeline. This, coupled with par-tial reconfiguration, will allow an FPGA-based design to have one portion of itsdesign upgraded while the rest of thedesign remains completely operational.

    There have been some breakthroughs inthe area of single event mitigation and cor-rection. Xilinx, in partnership with SandiaLabs, recently produced a TMR tool that

    10 Xcell Journal Fall 2004

    Animation by Dan Maas, Maas Digital LLC(c) 2002 Cornell University. All rights reserved.This work was performed for the Jet PropulsionLaboratory, California Institute of Technology,sponsored by the United States Government underPrime Contract # NAS7-1407 between theCalifornia Institute of Technology and NASA.Copyright and other rights in the design drawingsof the Mars Exploration Rover are held by theCalifornia Institute of Technology (Caltech)/ JetPropulsion Laboratory (JPL). Use of the MERdesign has been provided to Cornell courtesy ofNASA, JPL, and Caltech.

  • will XTMR a design. The XTMR tooltakes in a synthesized netlist, analyzes it,and applies the appropriate TMR measuresand space-specific design modifications toproduce a final XTMR netlist. Not onlydoes this guarantee a much more robustTMR design, it also takes what used to takean engineer days or weeks to perform andreduces the process to a matter of minutes.

    The FutureWho knows that the future has in store?The new missions have more demandingrequirements: more speed and more inte-gration, with an ongoing goal of less spaceand less weight. On the Xilinx front, eachsubsequent family of radiation-tolerantFPGAs (like Virtex-II Pro™ devices) willprovide more integration, more architec-tural features, and more capabilities.

    The need for more integration, speed,and reduced space and weight goes hand inhand with continually improving radia-tion-tolerant FPGAs. Xilinx advances inFPGA technology and the improvementsin radiation testing and processing madepossible by their relationship with JPLcome together to spell success.

    ConclusionThe collaborative efforts between JPL, theXilinx aerospace and defense team, andlocal support (provided by the manufactur-er’s representative, Norcomp SC, and NuHorizons Electronics Distribution) helpedpave the way for Xilinx to go from a pre-dominantly ASIC prototyping role tobecome key components in the successfuldesign and implementation of the MarsExploration Rovers.

    Current JPL flight projects that willlaunch in the years to come are alreadybeing designed using the latest Virtex andVirtex-II Xilinx high-reliability FPGAs.And the continual release of bigger, faster,and better Xilinx radiation-tolerant fami-lies means that with Xilinx and JPL, noteven the sky is the limit.

    For more information, please visithttp: / /marsrovers . jpl .nasa.gov/home/ , w w w . x i l i n x . c o m / e s p / m i l _ a e r o /index.htm, www.norcompsc.com, andwww.nuhorizons.com.

    Fall 2004 Xcell Journal 11

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    We recently launched the Xcell Publishing Alliance to help you publish your technical ideas. We can help you –

    from concept research and development, through planning and implementation, all the way to publication and marketing.

    Submit articles for our Web-based Xcell Online or our printed Xcell Journal and we will assign an editor and a graphics artist to work

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  • by David BanasPresidentTao of Digital, Inc. [email protected]

    You’d like to use DDR-SDRAM as the stor-age medium for OC-192 test pattern gener-ation to dramatically increase the length ofpatterns available to you. However, whenyou take the standard approach to archi-tecting this interface and attempt imple-mentation in a FPGA, you find that theFIFO read clock enable signals don’t meetthe timing requirements. Your projectbudget can’t afford an ASIC. How can youget around this issue and make the FPGAwork as the needed interface?

    Fortunately, the Xilinx® digital clockmanager (DCM) provides the answer. Aslong as you’ve got sufficient global clockresources available, you can use theDCM’s quadrature-phase outputs to clockthe outputs of the four FIFO groupsdirectly. This eliminates the need for clock

    enable signals in the 320 MHz clockdomain and yields a design that willachieve timing closure at that speed.

    Standard ArchitectureFigure 1 shows the standard architectureused to design a streaming data interfacebetween DDR-SDRAM and OC-192 seri-alizers. All of the design blocks shown inthis figure, with the exception of theFIFO/MUX controller, are available asdirectly instantiated elements (the DDRflip-flop), Xilinx CORE Generator™modules (MUX x and FIFO n), or Xilinx-provided reference designs (DDR-SDRAM controller).

    DDR-SDRAM ControllerThe DDR-SDRAM controller is a modifiedXilinx-provided reference design. I modifiedit to provide a continuously streaming modeof operation. The controller provides thenecessary address and control signals fordriving a standard PC-1600/2100 DDR-

    SDRAM module and also converts the databus from a 64-bit DDR mode to a 128-bitSDR mode to facilitate a simpler clockingscheme inside the FPGA.

    The controller stops fetching data frommemory and disables the write enable sig-nal to the FIFOs when it detects thatFIFO_0’s high watermark signal has goneactive (not shown in Figure 1).

    The frequency of clock 1 is 100 MHz,yielding a burst data rate of 12.8 Gbps.This data rate is 28% higher than thatrequired by the serializer, leaving room foroverhead tasks such as DRAM refresh.

    FIFOsThe eight FIFO blocks represent standard,asynchronous FIFO elements generatedusing the CORE Generator tool. TheFIFOs serve a dual purpose. First, they pro-vide elastic buffering between two asyn-chronous clock domains. Second, theywork in conjunction with the MUX x andFIFO/MUX controller blocks to provide

    Using a Virtex-II/Pro FPGA to stream data from DDR-SDRAM to OC-192 serializers.

    Streaming Data at 10 Gbps

    Fall 2004 Xcell Journal 13

  • the data bus width reduction. This is nec-essary to convert from the 128-bit data buspresented by the DDR-SDRAM controllerto the 16-bit data bus required by typicalOC-192 serializers. I will explain this func-tionality in more detail.

    MUXsThe two multiplexer blocks represent stan-dard 4-to-1 synchronous 16-bit bus multi-plexers also generated using the COREGenerator tool.

    DDR Flip-flopThe DDR flip-flop is a directly instantiat-ed element of the Virtex-II™/Pro™ archi-tecture. Its two inputs are multiplexed ontoits single output through successive clock-ing at both clock edges. In this way, thedata A input is clocked through to data outat the rising edge of the clock, while data Bis clocked through at the falling edge.

    FIFO/MUX ControllerThe FIFO/MUX controller is the onlyfully custom element in the architecture

    (1/[320 MHz]). The numbers identifyingthe various data intervals correspond to theindex of a particular 16-bit word in asequence of data, which is at least 24 16-bitwords in length. The FIFO outputs areupdated once every four clock cycles inquadrature succession, as shown in the tim-ing diagram.

    The two multiplexers select from amongthe four FIFO groups in the same succes-sion. However, a delay is imposed on themultiplexer selection sequence such that the

    FIFO outputs are allowedthree clock cycles to prop-agate to the multiplexerinputs before being select-ed, as shown.

    By designing this way,I can apply a multi-cycledelay constraint to theFIFO outputs and thusease the task of the placeand route engine. This isvery helpful when design-ing in a 320 MHz clockdomain. The DDR flip-flop selects from amongits two inputs in standardfashion, as shown. Theresult is a 640 Mword/sdata stream at the output,yielding a data rate to theserializer of 10.24 Gbps.

    Implementation ResultsUp to this point, the pro-posed architecture appearsto satisfy the designrequirements. However,when I tried to implement

    this approach in a XC2V1000-6BG575part, I couldn’t get the propagation delays ofthe FIFO read clock enable signals underthe 3.125 ns period constraint imposed bythe 320 MHz clock. Therefore, I came upwith the following modification to the basicarchitecture (Figure 3), which resulted insuccessful timing closure.

    Modification DescriptionIn the modified architecture shown inFigure 3, I eliminated the clock 1 domainsection of the design, as it is irrelevant to

    (also shown in Figure 1). Its operation isstraightforward and you can easily under-stand it by looking at the timing diagramof Figure 2.

    Note that while the signals generated bythe FIFO/MUX controller are not explicit-ly shown in the timing diagram, theirbehavior is implicitly depicted there. Forinstance, the outputs of FIFOs 0 and 1only change when the enable A signal fromthe FIFO/MUX controller is active.

    Likewise, whenever a multiplexer out-

    put changes, it is the respective select X sig-nal from the FIFO/MUX controller thatdictates which of the multiplexer’s fourinputs gets clocked through to its output.

    Timing DiscussionAs mentioned previously, Figure 2 depicts atiming diagram that describes the dynamicbehavior of the architecture shown inFigure 1. The clock signal shown is clock 2from Figure 1. (The clock 1 domain doesnot contain any novel design features.)

    The clock period “T” is 3.125 ns

    14 Xcell Journal Fall 2004

    CLK_1

    ADDR/CNTRL

    64 Bits

    16 Bits 16 Bits 16 Bits

    16 Bits

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    Enable A

    Data A

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    ClkA

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    To DDR-SRAMModule

    DDR-SRAMCONTROLLER

    CLK_1_DOMAIN CLK_2_DOMAIN

    FIFO_0Write ClkWrite En

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    FIFO_1

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    Data In Data Out

    Read ClkRead En

    From DDR-SRAMModule

    Figure 1 – Standard architecture

  • the discussion. The only design block thatchanged in the modified architecture is theFIFO/MUX controller; all other designblocks remain unchanged.

    Instead of generating clock-enable sig-

    nals, the controller block generates four 80MHz clocks in a quadrature phase arrange-ment. This is very easy to accomplish whendesigning for the Xilinx Virtex-II/Pro archi-tecture, as the DCMs in that architecture

    have quadrature phase outputs. All I had todo was divide down the 320 MHz clock by afactor of four, using an additional DCM, togenerate the original 80 MHz clock signal.

    When I apply these quadrature-phased80 MHz clocks directly to the four FIFOgroups, respectively – without using anyclock enable signals – the data at all FIFOoutputs is exactly as required by the originalarchitecture. You can see this fairly easily byenvisioning these four clocks overlaid atopthe four FIFO n/n signals in the timing dia-gram of Figure 2.

    Notice that the rising edges of the fourclocks line up perfectly with the changesin the outputs of the four FIFO groups.You no longer need to use clock enables togovern the FIFO read clocking and have,therefore, eliminated the one group of sig-nals that failed to achieve timing closure.Of course, you must have two additionalDCMs and five additional global clockbuffers available to make use of thisapproach.

    ConclusionBy taking advantage of the designtechnique presented here, OC-192test pattern generation hardwaredesigners can avail themselves ofthe low cost and large capacity ofstandard DDR-SDRAM modules,thereby making possible the use ofextremely long test patterns orautomated testing with manyshorter patterns, all without incur-ring the cost of ASIC design andproduction.

    The technique presented herewill also find applicability in thearea of direct digital synthesis(DDS) of arbitrary waveforms,where a high-speed digital wave-form is used, in conjunction withPWM or Sigma/Delta modula-tion and subsequent low-pass fil-tering, to produce arbitrarywaveforms with great precisionand repeatability.

    If you have any questions or sug-gestions, please contact me, DavidBanas, at (415) 846-5837, or e-mailat [email protected]

    Fall 2004 Xcell Journal 15

    CLK

    T

    FIFO 0/1 0/1 8/9 16/17X

    FIFO 2/3 2/3 10/11 18/19X

    FIFO 4/5 4/5 12/13 20/21X

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    3T

    T

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    MUX_B X

    DATA OUT X

    CLK_2_DOMAIN

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    FIFO/MUXCONTROLLER

    MU

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    FIFO_1

    FIFO_2

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    FIFO_6

    FIFO_6

    FIFO_7

    Figure 2 – Output data timing

    Figure 3 – Modified architecture

  • by Jerry A. LongTechnical Marketing Manager, Chronology Division Forte Design [email protected]

    As design requirements push memoryinterfaces to operate at 200 MHz andbeyond, a new set of timing challengesenters the design arena. Timing analysisplays an increasingly prominent role inthe identification and resolution of systemoperation issues.

    It’s likely that you will use doubledata rate (DDR) or Quad Data Rate(QDR™) memory devices in your nexthigh-speed design, which brings theadded need to design signal skew intothe memory controller to ensure properclock/data relationships.

    Xilinx® has simplified the use of thesedevices by providing high-performanceexternal memory interfaces directly fromtheir Virtex-II™ FPGAs. And to clearlyunderstand interface timing and potentialissues, Chronology has added features toits TimingDesigner® tool to streamlinethe exchange of critical timing data withthe Xilinx ISE software suite.

    A step-by-step guide to solving QDR memory data capture challenges with Virtex-II FPGAs.A step-by-step guide to solving QDR memory data capture challenges with Virtex-II FPGAs.

    Control Your QDR DesignsControl Your QDR Designs

    16 Xcell Journal Fall 2004

  • TimingDesigner generates place androute constraints, allowing direct use ofpost-place-and-route timing informationto verify desired FPGA interface operation.You can accurately determine the properclock/data relationship for yourDDR/QDR memory interface design,export the information as constraint datainto ISE, and automatically get visual veri-fication of design success.

    For the purposes of this design guide,we’ll use a QDR SRAM device to illustrate asource-synchronous interface design.Stepping through the design flow, we imple-mented a QDR memory controller in aXilinx X2V50 Virtex-II Pro™ FPGA with afocus on the interface signals required for aread operation, utilizing a 133 MHz masterclock. The memory device is a Micron™ 18Mb QDR II four-word burst SRAM(MT54W1MH18J).

    The features and principles outlined hereare not necessarily unique to high-speedmemory design. TimingDesigner’s robusttiming diagram-based analysis features, cou-pled with its Xilinx-specific import/exportcapabilities, allow a level of integration thatcan be applied to any timing-critical designinterface for Xilinx FPGAs.

    QDR Interface Timing RequirementsQDR SRAM devices have unique timingrequirements for successful read operations.In order to guarantee accurate data capture,QDR devices require the capture clock to becenter-aligned within the valid data window.For source-synchronous designs, this meansshifting the optional-use echo data clocksupplied by the QDR device.

    Center Alignment of Capture Clock EdgesProper timing for read operations of QDRSRAM interface designs requires you tocenter-align the edges of the capture clockwithin the valid window of the data bus foraccurate data capture, as shown in Figure 1.This is because most SRAM devices typi-cally have a positive setup and a positivehold requirement, and both are roughly thesame value. So it makes sense to center theclock edge within the data valid window tomaximize the safety margin for latchingdata. To accomplish this, the memory con-

    clock/data relationship to ensure that vari-ous temperature effects the design mayencounter (or other unforeseen influences)won’t cause an excessive amount of drift insignal position during the read operationand result in a violation of the setup orhold time requirement of the receiving reg-ister. In theory, a center-aligned clock edgewill maximize the setup and hold times formost devices, allowing sufficient safetymargins for signal drift.

    However, some devices, like the VirtexII-Pro device, have a negative hold timerequirement, which simply means that datacan transition to the next value before theclock edge that latches it. In effect, thischaracteristic places the clock edge to theright (delayed) of the data transition. So forthese devices, if you center-align the cap-ture clock within the actual data valid win-dow, you may be satisfying the setup/holdrequirements of the device, but the safetymargin achieved will be greater for the holdrequirement than for setup.

    The ideal solution is to provide a maxi-mum safety margin for both the setup andhold requirements of a device, which trans-lates to “balancing” these margins. Thisprovides equal amounts of safety for both,as illustrated in Figure 2.

    troller must skew the capture clock.For source-synchronous capture of read

    data from a QDR device, you must use theoptional echo clock signals (typically CQand CQ#) provided from the QDR device.With the Virtex-II Pro family of FPGAs,skewing this clock is easily accomplishedusing one of the digital clock managers(DCM). However, the amount of phase shiftnecessary to achieve a safe margin is anunknown, given the external PCB skew

    effects on both the incoming data and itsassociated clock, as well as the associatedrouting delays encountered within the FPGAfabric. TimingDesigner will help us to accu-rately determine this phase shift value.

    Capturing Read Data in Virtex-II Pro DevicesYou can skew (or delay) the clock signal byusing PCB trace delay techniques, or bydesigning clock delay into the memory con-troller design. Because PCB trace delay tech-niques aren’t very flexible, it makes moresense to use the incidental PCB trace delaycoupled with internal FPGA routing delayand use the Virtex-II Pro DCM element asthe “adjustable” component for phase shiftwithin the FPGA memory controller design.

    Typically, memory manufacturers rec-ommend center alignment of the

    Fall 2004 Xcell Journal 17

    Figure 1 – Illustration of center-aligned clock/data relationship

    Figure 2 – Center alignment of device minimum data valid window

  • To accomplish this balance, you mustdetermine the minimum data valid windowfor the receiving device, and center that win-dow within the actual data valid windowprovided from the memory device, givenyour design parameters. Using the minimumsetup and hold characteristics of the receiv-ing device, determine a minimum “safe” datavalid window with the following formula:

    Min Data Valid Window = Min Setup + Min Hold

    Because the placement of the resultingminimum data valid window is tied to theplacement of the clock signal, skewing theclock will effectively skew the minimumdata valid window. As indicated in Figure

    2, as long as the data bus transitions out-side of the receiver’s minimum data validwindow, safe data capture is ensured.

    Determining the Clock/Data RelationshipTo determine the required clock skew,

    you create a timing diagram illustrating theclock/data relationship of a read operationfor the QDR device based on the actualread timing diagrams acquired directlyfrom the memory device’s data sheet. To bemore descriptive of the signal relationshipsin the diagram, name the read data clocksignal C_Mem and the data bus signalQ_Mem to reflect the signals as they appearat the pins of the memory device.

    To model those same signals as theyappear at the pins of the FPGA, after theiraccumulated flight path delay from theQDR device, create the signals C_FPGAand Q_FPGA. Figure 3 is a block diagramillustrating the signal path relationshipsjust described.

    The resulting QDR memory read dia-gram is displayed in Figure 4. The data busrepresents the transition period necessaryfor all elements of the data bus betweenvalid data words. The PCB trace delayaccumulated by both data and clock is rep-resented with separate variables: tPCBdatafor the delay associated with the data sig-nal and tPCBclock for the delay associatedwith the clock. This allows you to easilyvary the values and see the effect on thedesign results.

    Creating Constraints with TimingDesignerKnowing the timing relationship of anexternal clock and its associated data as itarrives at the pins of the FPGA provides aunique advantage for accurate data captureand design success. The Xilinx timing con-straint OFFSET is used along with its asso-ciated keywords to provide initial timinginformation to ISE, so that proper place-ment of data capture elements and theirassociated routing delays will be adequatefor the design. As illustrated in Figure 5,TimingDesigner provides direct dynamicaccess to any measurement within a timingdiagram for generation of a place and routeconstraint file (UCF).

    For this design example, you need tomeasure the offset for the data (Q_FPGA)and clock (C_FPGA) signals, and the dura-tion of the valid data window at the pins ofthe FPGA controller. This can be donedirectly from the timing diagram usingTimingDesigner measurements, as indicat-ed in Figure 4. You’ll also need the readdata clock period measurement.

    Generating Constraint InformationTimingDesigner’s Dynamic Text dialogbox offers a way to reference timing dia-gram measurements from within a vendor’sspecific timing constraint syntax. UsingISE’s OFFSET timing constraint syntax,you reference the measured offset values in

    18 Xcell Journal Fall 2004

    MasterClock

    Qin_Data

    Cin_Clock

    Q_FPGA

    C_FPGA

    DCM Phase Skew (tSK)

    Routing Delay (tRt)

    Q_Mem

    C_MemK, K#

    R#

    W#

    Addr

    D

    CQ, CQ#Q

    Internal Logic Element

    DCM

    QDRController

    FPGA/ASIC

    QDR

    SRAM

    Data Flight Time (tPCBdata)

    Clock Flight Time (tPCBclock)

    Figure 3 – Illustration of signal delay paths for QDR read operation

    Figure 4 – Clock/data timing diagram of QDR read operation

  • the Dynamic Text dialog box to assembleconstraints for transfer into the ISE con-straints file. The syntax for this designexample is illustrated below:

    OFFSET = IN %mOFFSET_IN.min VALID%mDVW.min ns BEFORE “rd_clk” TIMEGRPRdClkRisingFFs;OFFSET = IN %mOFFSET_IN_F.min VALID%mDVW.min ns BEFORE “rd_clk” TIMEGRPRdClkFallingFFs;

    The VALID keyword is for specifyingthe duration of the incoming data validwindow, and is used for hold time calcula-tions in ISE. The signal rd_clk is the pinname in the design code associated withthe C_FPGA clock signal in the timing dia-gram. Notice that two offset specificationsmust be declared – one for the rising clockedge and one for the falling clock edge –because this is a dual-data rate read opera-tion. Also notice the “%” syntax that indi-cates dynamic text access of measuredvalues in the timing diagram.

    The Dynamic Text dialog box willresolve the dynamically referenced meas-urements and allow direct transfer of theinformation into the UCF constraintsfile. Once the UCF file has been assem-bled, execute a place and route in the ISEtool set.

    Take Control of Your DesignAfter initial place and routeis complete, you can gener-ate a timing report usingthe TRACE timing analysistool within ISE, andimport that into the timingdiagram. This will allowyou to determine the actualrouting delays so that youcan specify the necessaryphase shift for the readclock. You then enter thephase shift attribute intoISE, execute a final placeand route, and generate atiming report. When com-plete, you then re-importthe timing report to gaugehow well the constraintswere met.

    Determining Routing DelaysFor this design example, ISE placed theread data capture registers into the I/Oblocks of the Virtex-II Pro devices,because they capture data from the inputpads and have a common clock and resetsignal. This is a default setting for ISE’smapping process and is appropriate forthis design example.

    As the I/O blocks have only one routingpath for input data signals, the TRACEreport includes this data path delay in thesetup and hold requirements of the I/Oblock registers. However, the clock signalhas several possible paths from the inputpad to the capture register, and this designexample uses a path through the DCM ele-ment for phase shift control. So you mustdetermine the routing and element delaysfor the clock path to achieve proper phaseshifting of the clock.

    A TRACE analysis report is generated inverbose mode to get the needed timinginformation. This report is limited to 16paths per constraint (the data bus is 16bits). Briefly look at the report and makenote of the worst-case setup path for thedata bus in preparation for import into thetiming diagram.

    To import the desired TRACE analysisreport information (saved as a TWX file)

    into TimingDesigner, map the worst-casesetup path identified earlier to the associ-ated waveform in the diagram(Q_FPGA), and then import the infor-mation to create variables for the routingand element delays. Mapping the FPGAports guides TimingDesigner to thedesired signal information, and allows forautomatic updates of existing variables ifsuccessive place and route executions arenecessary.

    Visualization at the Capture RegisterAfter importing the timing results, createanother clock signal (Cin_FPGA) to rep-resent the clock characteristics at the datacapture register. You then add the setupand hold requirements obtained in theTRACE report import as TimingDesignerconstraints on the data signal relative tothe register clock, as shown in Figure 6.

    Notice that the indicated setup andhold margin results from the diagrammatch the slack values from the initialTRACE timing report, and indicate thatthe setup paths are failing by about 2 ns,but the hold time paths have more thanenough margin. You need to shift theclock so that both the setup and hold timemeasurements are met with roughly thesame margin.

    Fall 2004 Xcell Journal 19

    PCBDesign Flow

    TimingDesignerConcept

    BlockDiagram

    Verification

    HDL and/orDesign Entry

    PhysicalDesign

    Production

    Design InterfaceModeling

    DesignCreation

    Design InterfaceAnalysis

    Design InterfaceDocumentation

    UCF

    *.txt

    Synthesis

    Map

    Place and Route

    BitGen

    SpeedPrint

    TRACE

    TWXBIT

    ISE

    Timing BudgetsPartitioning Timing

    Constraints

    What-if AnalysisOptimization Static Timing

    Analysis

    End-User DocTiming Data Archival

    Figure 5 – TimingDesigner offers an intuitive interface to ISE’s design flow.

  • Making AdjustmentsUsing the imported information obtainedfrom the TRACE timing analysis reportand the measured values from our timingdiagram, you can obtain the attribute valuefor the necessary DCM phase shift (seesidebar, “Balancing the Data ValidWindow”). For this example, the attributevalue was determined to be 108, for a shiftof 3.165 ns. You then enter this value intothe ISE tool flow, and execute a secondplace and route to shift the clock and prop-erly balance the setup/hold margins.

    Verifying the ResultsRe-importing the new post-place-and-routetiming report using the previous import set-tings will automatically update all of thenecessary values, and correctly re-positionthe register clock signal (Cin_FPGA). This isillustrated in Figure 7. Examination of thesetiming results shows that the setup and hold

    requirements for a read data capture in thedesign are now balanced with respect tomargin (slack), giving the safest possibleresult for any unforeseen signal drift.

    ConclusionUsing TimingDesigner together withXilinx Virtex-II Pro devices allows opti-mal safety margins for setup and holdrequirements, which are necessary foraccurate data exchange with a QDRSRAM memory controller.

    By following a design process that com-bines the use of TimingDesigner timingdiagrams and ISE’s post-place-and-routetiming reports, you can create an accurateanalysis of your design’s critical timingrelationships. Using timing diagrams, youcan account for PCB trace delays andother external factors that will affect thesignal relationship at the pins of yourFPGA device.

    ISE’s TRACE timing analyzer providestiming reports that give you details on theroute delays and constraint requirements ofyour FGPA device. Together, these toolsallow you to accurately capture andexchange critical interface timing informa-tion, and allow visual verification that yourdesign will perform as desired.

    To learn more about TimingDesignerand the Chronology Division of Forte Design Systems, please visitwww.timingdesigner.com.

    Balancing the Data Valid Window

    You can determine the amount ofDCM-generated phase shift neededfor the clock signal to balance the datawindow using the following procedure:

    1. Subtract the minimum data valid window for the Virtex-II Pro devicefrom the design’s actual data validwindow, and divide that result by two.This accounts for the differencebetween the two valid data windows(DlyDVW).

    DlyDVW = (DVWactual – DVW_VIImin) / 2

    2. Subtract the offset measurement madeat the pins of the FPGA device fromthe required setup time for the captureregisters, to account for device setuprequirements (DlyRelSU).

    DlyRelSU = IOBsu – OFFSET

    3. Determine total clock path delay fromthe TRACE timing report (Xtcd).

    Xtcd =

    4. Add up the necessary delays (valuesobtained in 1 and 2 above), and sub-tract the total clock path delay (valuefrom 3 above).

    Clk_offset = (DlyDVW + DlyRelSU) – Xtcd

    5. Finally, determine the correct ISEattribute value to control DCM phaseshift with the formula:

    phase shift attribute = (Clk_offset/Clk_period)*256

    Figure 7 – Balanced setup and hold of data capture register

    Figure 6 – Setup and hold of data capture register after initial placement

    20 Xcell Journal Fall 2004

  • by Xilinx Staff

    “Partnership” might possibly be the mostoverused word in the high-technologyindustry. But at Xilinx®, it transcendscliché as a foundation principle behind thecompany’s highly successful business modelsince its inception.

    Today, the Xilinx way of thinkingreflects a rare mindset about the value of aninterconnected ecosystem of like-mindedcompanies and the benefits such anapproach can bring to Xilinx, its customers,and to the partners themselves.

    To say that Xilinx was founded on theSpirit of Partnership is no overstatement.In the original 1984 business plan, the sec-ond bullet under the “strategy” section(after the primary strategy point of “maxi-mizing our strength in product architectureand design”) articulated the idea to partnerwith complementary suppliers. The Xilinxfounders thought that through an extremefocus on a few core competencies, Xilinxcould deliver highly differentiated productsand drive technology innovation forward.

    Most notably at the outset was the needfor a manufacturing partner. The foundersfundamentally believed that there was noneed to fund such a capability in-house – aradical concept in the era of “real men ownfabs.” (The average price tag for a fab at thetime was $300 million, about one-tenth oftoday’s going rate, but still a hefty invest-ment for a startup company in 1984.)

    Turning an industry cliché into a successful business model.

    Celebrating 20 Years of Partnership

    Fall 2004 Xcell Journal 21

    VP of Worldwide Marketing Sandeep Vij in the Xilinx Hall of Patents

  • Company founder Bernie Vonderschmittleveraged past relationships and his solid rep-utation for fair play to negotiate a manufac-turing deal with Japanese giant Seiko, whichagreed to allow Xilinx-designed chips to beproduced in its fabs. Sealed with only ahandshake, Xilinx had its first partner andthe industry had a new model – the fablesssemiconductor company.

    In short order Xilinx signed up anothercritical partner as its first distributor,because the founders viewed the salesprocess as they did manufacturing: essen-tial, yes, but not necessarily something thecompany needed to “own.” As with Seiko,the distribution agreement was built onmutual trust and a benefit to both sides – abenefit that could be measured beyond justdollars and cents.

    Since then, Xilinx has formed partner-ships with a wide range of other suppliersin the semiconductor supply chain, allguided by a consistent principle.

    “When we look at forming a partner-ship, the first question we ask is ‘what’s init for you?’” Xilinx CEO Wim Roelandtssays, explaining a philosophy that mayseem counterintuitive to the traditionalapproach. “It really should be weighted51-49 in the partner’s favor. They need toget something out of it, as much – if notmore – than we do.”

    Such an approach has helped Xilinxassemble critical components to fill the“solution gap” in its offerings, allowing it tofocus on developing the core technologyfor which it has gained the deserved repu-tation of a world-class innovator. It has alsomade Xilinx one of the most respectedcompanies in all of high technology and afavorite among complementary suppliersboth large and small.

    “For us, a partnership is more than afinancial transaction or relationship. It real-ly is about shared goals and ways of think-ing,” says Sandeep Vij, vice president ofworldwide marketing at Xilinx. “Yes, we

    “Programmable technology requires thesmallest geometries and advanced processes –and we must be a leader in those areas. Weare willing to invest to be able to achieve suchthings as producing the world’s largest dies,to be first to 90 nm. And our partners mustbe, too.”

    Ooi also points out that because Xilinx isa mission-critical supplier to its customers,its partners must share that sense of urgencyand flexibility. “They have to be able to scalewith us,” he says of an increasingly valuableasset in the cyclical semiconductor industry.

    Vincent Tong, vice president of prod-uct technology, agrees, adding that thenumber-one criterion for a Xilinx partneris to be a “technology leader.

    “We can’t afford to partner with compa-nies that aren’t leaders in what they aredoing. Three or four years ago, when itcame to manufacturing, you could kind ofthrow a design over the wall. Today weneed to be engaged tightly with our part-ners to drive technology forward. We havemore than 80 process engineers and wedon’t even own a fab,” he says, underscor-ing the commitment level of Xilinx even inareas in which it chooses to partner.

    Through its partnership strategy inmanufacturing, Xilinx is already pushinginto areas beyond the current state-of-the-art, including joint development work in75 and 65 nm process geometries.

    The Link to the CustomerAs with manufacturing, Xilinx made thedecision early on that it would work withpartners to sell and distribute its products(notably, field support of those products wasalways viewed as a critical internal function).

    “It was a decision borne out of necessityand practicality,” explains Vice President ofSales Steve Haynes, who’s been with thecompany for nearly 20 years. “We knewthat as a company we needed to focus onwhat we do best – design, technology, inno-vation. We needed a ready-made channel to

    use partnerships to maintain our own focusand we know it doesn’t make sense econom-ically for us to invest in all areas. But itcomes down to results – our partnerships areaimed at making breakthroughs that allowour customers to scale new heights.”

    Manufacturing PartnershipsManufacturing still represents the most sub-stantial of the Xilinx partnering strategies, ifonly because of the cost of today’s modern fab-rication facility. Xilinx has emerged as one ofonly a small handful of semiconductor com-panies that truly “pushes the envelope” whenit comes to implementing new technologyprocesses. Recently, it became the first compa-ny to ship a production device based on 90nm process geometries, considered the leadingedge of expertise. It also is among the leadersin the use of 300 mm wafers to produce itschips. Both manufacturing achievementsallow Xilinx to reach new price/performancemilestones with its products and further dis-tance itself from its competitors.

    Although such advances are enabled bychoosing the right type of company to part-ner with (for manufacturing, Xilinx partnerswith UMC™ and IBM™), Xilinx itself is akey contributor to driving manufacturingadvancements. The company has more than100 engineers on-site at UMC, for example,working in tandem with their R&D teams.And because of the “regular” nature of itsstructure, programmable logic technology isan excellent means for manufacturers tocharacterize new processes, as UMC hasdone with its last several generations of newprocess nodes. But perhaps the secret ingre-dient is mindset.

    “Our partners must share our view on risk-taking. They must be willing to engage injoint risk-taking and be willing to try newthings. It is the only way to stay on top of lead-ing-edge technology, to truly innovate,” saysB.C. Ooi, Xilinx vice president of operationsand the man responsible for seeing that Xilinxproducts stay on the leading edge.

    22 Xcell Journal Fall 2004

    ...Programmable logic technology is an excellent means for manufacturers to characterize new processes...

  • get our technology in the hands of the cus-tomers. There were, and still are, firms thatbring an expertise and reach that we couldn’tor didn’t want to develop ourselves.”

    Today Xilinx uses a network of close to30 partners to deliver its products to cus-tomers around the world. Some are broad-line distributors who sell complementarytechnology to round out the use of program-mable logic. Others are regional or verticalmarket specialists. In most cases, Xilinx is themost significant product line they represent,and in all cases the relationship is based onmutual trust and shared values.

    “When a customer looks at a rep [resen-tative], they are looking at Xilinx. We haveto be on the same page in all facets of therelationship. We have to know them as wellas we know ourselves,” says Haynes.

    Haynes and his team meet regularly withsales partners to align their goals and strate-gies, and make sure the company’s productsare being represented consistently with the“Xilinx Way.”

    The formula is surely working, as Xilinxsales and customer satisfaction metricsshow. But it’s a constantly evolving process,as Haynes well knows. “Good partnershipsevolve. Our channel looks a lot differentthan it did 20 years ago. It’s like being in amarriage – you have to work at it.”

    Comprehensive SolutionsThe design and use of programmable logichas become an increasingly complex process.In the early days of Xilinx, third-party designtools were just coming to market as the EDAindustry took shape, and commercial IP coreswere almost non-existent. Today, they, alongwith a set of other capabilities, are essential todeveloping multi-million gate, multi-func-tion systems on chip (SoCs). Thus, the Xilinxpartnership model has expanded significantlyto include technology partners who canround out the core offering.

    “Today’s markets call for a completesolution, which includes the FPGA and afull set of components and tools,” saysSenior Manager of StrategicRelationships Jasbinder Bhoot, whooversees all of the partnership programsat Xilinx. “Xilinx has been successfullydelivering for years the best FPGA prod-ucts in the industry. Now, together withour partners, we have a focused emphasison providing comprehensive solutions toour customers. We seek out and collabo-rate with best-in-class companies tocomplement our product offerings withEDA tools, IP, design services, referencedesigns and manufacturing kits.”

    Xilinx partners must share our senseof business integrity and win-win philos-ophy. “We are fairly selective inwho we work with. Yes,they must bring a best-of-breed offering,and yes, it mustmake econom-ic sense for

    both sides. But these are the companieswith whom we will be on the front lineswith our customers, so we have to be insynch on many different levels,” explainsBhoot.

    Bhoot and his team use well-definedmetrics to gauge how effective each andevery partnership is for Xilinx and itscustomers. And they are constantly onthe lookout for new areas to developpartnerships and make Xilinx technolo-gy more accessible and complete.

    Today, Xilinx counts some 250 com-plementary technology and serviceproviders in its “ecosystem” of companiesthat help it deliver the most robust solu-tions in the industry. From industry lead-ers such as IBM™, Cadence™, MentorGraphics®, Synopsys™, Synplicity™

    and Wind River™ to specializedexperts in key areas, Xilinx

    partnerships provide maxi-mum breadth and

    depth of technologyofferings.

    Today, Xilinx counts some 250 complementary technology and service providers in its “ecosystem” of companies that

    help it deliver the most robust solutions in the industry.

    Fall 2004 Xcell Journal 23

    Jasbinder Bhoot, Senior Manager of Strategic Relationships

  • 24 Xcell Journal Fall 2004

    Among the areas in which Xilinx partners are:

    • Intellectual property cores. Xilinxworks closely with independent third-party core developers to produce abroad selection of industry-standardsolutions, deemed AllianceCORE™,dedicated for use in and optimizedfor Xilinx programmable logic.

    • Design tools. Xilinx’s AllianceEDApartners are among the tool leadersfor each step in the design process,including such critical areas as high-level design, synthesis, logic verifica-tion, and complete PCB design.Xilinx and its partners develop themethodologies and tool flows thathelp make programmable logic usersproductive and well positioned totake full advantage of Xilinx devices.

    • Design services. Xperts are a globalnetwork of certified design expertstrained to take full advantage of thefeatures present in the Xilinx PlatformFPGAs, software, and IP cores. Whencustomers need design expertise, theycan access a sophisticated resourcedatabase and quickly identify designconsultants in their own regions.

    • Embedded development tools.Xilinx AllianceEmbedded partners are experts in the field of embeddedsystems – inclusive of compiler,debugger, IDE, and trace/visibility

    tools – as well as RTOS require-ments. They support the Xilinx commitment to deliver high-per-formance, cost-effective embedded processor-based solutions.

    • Reference designs. Xilinx teams upwith industry-leading semiconduc-tor vendors to develop referencedesigns for accelerating its cus-tomers’ product and system time to market.

    The Spirit of PartnershipXilinx has developed a successfulformula for delivering a steadystream of innovation and technol-ogy firsts to the market in its first20 years. Its partnership approachis an essential element of that for-mula, and although no oneintends to alter the basic strategy,the technology industry mandatesthat change is a constant.

    “Xilinx is in a much differ-ent position as a company nowthan when we first started 20years ago,” Roelandts says.“Resource-wise we could con-sider doing more things our-selves. But we know that thekey to our success has been ourfocus. That has enabled ourinnovation, which is why we area leader. In that respect, part-

    nerships make even more sense, especiallyas the world gets more complicated. Ourchallenge is to continue to develop theright set of relationships with companiesthat share our vision and make sure we all

    derive a benefit. We will not waver on thebasic principles that guide our partner-ship strategy, but we will keep the processdynamic to address new market needsand conditions.”

    So don’t expect to see Xilinx buildingits own fab in the next 20 years. Butthanks to is unique Spirit of Partnership,it’s a safe bet that Xilinx and its partnerswill continue to set the standard for inno-vation and best business practices in thesemiconductor industry.

    Xilinx has developed a successful formula for delivering a steady stream of innovation and technology firsts to

    the market in its first 20 years.

  • by Clive “Max” MaxfieldPresidentTechBites [email protected]

    When reading a technical book, you maysometimes find yourself muttering, “Ha!The author is a complete and utter idiot! I could have done a better job than that!”

    Or you may be working on an interest-ing project – or have just developed a novelsolution to some problem – when you sud-denly think, “I could write a really coolbook about this!”

    That initial flush of enthusiasm sooncools, however, when you start to mull overthings in a little more detail, realizing thatyou don’t actually have a clue where tostart. Is there a market for such a book?What should it cover? Who will create thegraphics? How will you find a publisher foryour masterpiece?

    Given these imponderables, it usuallydoesn’t take long before you’ve talked your-self out of becoming an author. This isunfortunate, because there may be a lot ofpotential readers out there who could real-ly benefit from your expertise. And ofcourse, being known as an author can onlyenhance your career prospects and makeyour family and friends very proud.

    Turn your terrific idea into a technical tome through the Xcell Publishing Alliance.

    Author! Author!

    Fall 2004 Xcell Journal 25

  • To assist authors-to-be (like yourself?),Xilinx® has created an innovative new pro-gram called the Xcell Publishing Alliance.The program is designed to help you takeyour magnum opus from initial concept,through planning and implementation, allthe way to publication, fame, and glory.

    In fact, as I pen these words, I’m bask-ing in the glow of having just received theauthor copies of my latest book, “TheDesign Warrior’s Guide to FPGAs:Devices, Tools, and Flows.” This book wasmade possible in large part by Xilinx andMentor Graphics®, both of whom provid-ed me with access to a wide variety ofexperts and information sources. Thus, inthis article I thought I’d walk you throughthe process of creating a book – using “TheDesign Warrior’s Guide” as an example –and then discuss what Xilinx can do to helpyou create your very own tour de force.

    Topical QuestionsThe very first thing you have to decide onis a topic. What exactly would you like towrite about? There’s little point in spendingvast amounts of precious time and effortcreating a book that no one actually wantsto read.

    I’ve been fortunate in this regard,because I’ve tended to write books on top-ics that interest me and that I would liketo read myself. Happily, the folks whoread my books seem to enjoy them also.For example, my very first effort – “Bebopto the Boolean Boogie: AnUnconventional Guide to Electronics” –was recently re-released in its second edi-tion due to popular demand.

    Looking back, I realized that most ofmy tomes were introductory in nature, sothe time seemed right to focus on a partic-ular topic in more depth. FPGAs havebecome phenomenally powerful andsophisticated in recent years. Today’s

    I felt that this background informationwould be useful to less-technical readers,while techno-weenies could leap directlyinto the more challenging middle sectionof the book. Among many other topics,this section takes an in-depth look at:

    • FPGA versus ASIC design styles

    • Schematic-based design flows (yes, theyare still used to support legacy designs)

    • HDL-based design flows

    • Silicon virtual prototyping for FPGAs

    • C/C++-based design flows

    • DSP-based design flows

    • Embedded processor-based design flows

    • Modular and incremental design

    • High-speed design

    • Migrating ASIC designs to FPGAs,and vice versa

    One thing I recall from my collegedays is that despite having scores of text-books, I was unable to find the fact I waslooking for in any of them. For this rea-son, “The Design Warrior’s Guide”includes a third section boasting a host ofperipheral topics, including:

    • Choosing the right device

    • Gigabit serial interfaces

    • Reconfigurable computing

    • Field programmable node arrays(FPNAs)

    • Independent design tools

    • Creating a design flow based on open-source tools

    Just looking at the above lists makes myeyes water, because I well remember theresearch and effort that went into fleshing

    FPGA devices can be used to implementextremely large and complex functionsthat previously could be realized onlyusing ASICs, and thus an increasing num-ber of design engineers are starting to usethe little rascals. When I began to lookaround, however, there seemed to be adearth of useful material in this arena.

    Readership to ShoreOnce you’ve decided on your topic, youwill have to flesh it out into an outline, andeventually grow it into a full-blown pro-posed contents list. An integral part of thisprocess is to decide who your audience is,because the type of information you willcover will typically vary depending onwhether you are talking to engineeringgurus or novices.

    I personally dislike reading books thattalk down to me as though I am the villageidiot. But equally, I’m less than enamoredby books that try to impress me with theauthor’s brilliance, or those that require meto return to college just to wend my wearyway through the first chapter.

    In the case of “The Design Warrior’sGuide to FPGAs,” I wanted to address theneeds of an unusually wide audience,including students, sales and marketingprofessionals in the EDA arena, and full-blown engineers. For this reason, I devotedthe first section of the book to fundamen-tal concepts such as:

    • What are FPGAs and why are they ofinterest?

    • Underlying technologies, such as anti-fuses, flash memory, and SRAM cells

    • Alternative architectures and concepts

    • Different programming techniques

    • Who are the various players in the FPGA space?

    26 Xcell Journal Fall 2004

    The Xcell Publishing Alliance is designed to help you take your magnum opus from initial concept, through planning and

    implementation, all the way to publication, fame, and glory.

  • out these topics when I finally got aroundto writing the book.

    In StyleYet another point to ponder before you leapinto the fray is the style you intend to use.To a large extent this will be determined byyour target audience, but it will also bestrongly influenced by your personality.

    I soon become disgruntled when read-ing boring books. Unfortunately, thisseems to cover the vast majority of techni-cal books out there (although there are afew notable exceptions). It’s almost asthough someone sent out a memo saying,“Whatever you do, don’t make engineeringbooks interesting – otherwise all sorts offolks might decide to read them.”

    Fortunately, I didn’t receive this memo,so I don’t feel bound to follow it. As a sim-ple rule of thumb, I tend to write the sortof book that I personally would like toread. Thus, I use a somewhat informal,chatty style – much like this article – and Ialso like to include nuggets of trivia andtidbits of information, such as “Where didthis come from?” or “Why do we do thingsthis way rather than that?”

    Furthermore, in my later books I’vestarted to include little pronunciationnotes as sidebar items for technicalacronyms and terms. I do this because ifyou mispronounce a word when talking tosomeone in the industry, you immediatelybrand yourself as an outsider. Some engi-neers have been known to scoff at me forthis, but I’ve received many e-mails fromless-technical readers that say, “Only theother day you saved me from a potentiallyembarrassing situation.”

    Yes, There’s MoreAt some stage, of course, you are going tohave to actually put pen to paper (or fingersto keyboard). Writing a book-length proj-ect isn’t easy. You may start off full of vimand enthusiasm, but as you approach themiddle of the project things seem to slowdown and become increasingly difficult –much like wading through molasses. Andthen, suddenly, you’ll find that you’ve crest-ed the brow of the hill and are racing downthe other side towards the finish line.

    Another consideration is creatinggraphics. I personally go by the adage that“a picture is worth a thousand words,” so

    I festoon my writings with graphics wherev-er I can. For technical books and whitepapers, I tend to use line art created inMicrosoft™ Visio™, an incredibly usefuland easy-to-use tool. As an example, consid-er a sample illustration from “The DesignWarrior’s Guide” (Figure 1), which reflects asimple multiplexer-based FPGA architec-ture. Logic gates are not usually shown withgray fills and shadows, but I think it looksmore interesting – and it’s my book.

    Another consideration is finding some-one to help you proofread and copyedityour work and to offer suggestions as topresentation and style. Although many edi-tors can discourse for hours on the manyand varied uses of the apostrophe, theloathsome split infinitive, and parallel sen-tence structure, actually finding one whohas a clue what you are talking about tech-nology-wise can be somewhat taxing.

    And last, but certainly not least, onceyou’ve finally finished, you will need tofind a publisher who can take your master-piece, lay it out, print it, distribute it, andpromote it far and wide.

    The Xcell Publishing AllianceAll of the above may seem a little over-whelming at first, but things aren’t asdaunting as they appear. The idea