Xcell Journal Issue 50 - Xilinx...THE AUTHORITATIVE JOURNAL FOR PROGRAMMABLE LOGIC USERS R ISSUE 50, FALL 2004 XCELL JOURNAL XILINX, INC. Xcell journal COVER STORY COVER STORY FPGAs

T H E A U T H O R I T A T I V E J O U R N A L F O R P R O G R A M M A B L E L O G I C U S E R S

R

Xcell journalXcell journalT H E A U T H O R I T A T I V E J O U R N A L F O R P R O G R A M M A B L E L O G I C U S E R S

ISSUE 50, FALL 2004XCELL JOURNAL

XILINX, INC.

COVER STORY FPGAs on MarsCOVER STORY FPGAs on Mars

MEMORY DESIGN

Streaming Data at 10 Gbps

Control Your QDR Designs

PARTNERSHIP

20 Years of Partnership

Author! Author!

Programmable World 2004

SOFTWARE

Algorithmic C Synthesis

The Need for Speed

MANUFACTURING

Lower PCB Mfg. Costs

Optimize PCB Routability

MEMORY DESIGN


Control Your QDR Designs

PARTNERSHIP

20 Years of Partnership

Author! Author!

Programmable World 2004

SOFTWARE

Algorithmic C Synthesis

The Need for Speed

MANUFACTURING

Lower PCB Mfg. Costs

Optimize PCB Routability

Issue 50Fall 2004

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©2004 Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124. Europe +44-870-7350-600; Japan +81-3-5321-7711; Asia Pacific +852-2-424-5200; Xilinx is a registered trademark, Spartan and XtremeDSP are trademarks, and The Programmable Logic Company is a service mark of Xilinx, Inc.

EEver have one of those days where you’re working hard, nose to the grindstone, striving to make sureyour latest project is on time and on target; and then suddenly out of nowhere, you overhear some-one complimenting your efforts? It’s not a comment that you solicited, but independently you findout that all of your hard work is recognized as the best among your peers and you’re headed in theright direction.

CMP Media LLC, the parent company of EETimes, just dropped quite a few kudos on the Xilinxdoorstep. Most of you know that every year CMP conducts a PCB and IC electronic design toolindustry survey to sample the engineering community’s view on design tool providers. This year, at the2004 Design Automation Conference, CMP announced the results of their first FPGA vendor survey.

The ratings are striking. In 21 out of 22 categories measuring everything from best pre-sales supportto brand and tool awareness, from most ethical company to customer loyalty, FPGA designers choseXilinx as the top FPGA vendor. We received the highest rankings in best after-sales support, bestdocumentation, current technology leader, technology leader in three years, clear vision of thefuture, best integration with other vendors’ tools, well-managed company, and more.

We were also able to hear the industry concerns. Respondents cited the accuracy and integrity of FPGAtools as their biggest design issue, followed closely by functional verification, timing closure, and theability of those tools to easily handle complex designs. They also said that the majority of their designtime was spent in place and route, synthesis, and HDL simulation, followed by timing analysis andfloorplanning. One-third of the respondents also use formal verification, while almost half regularlyuse signal integrity and C language system-level tools.

On behalf of all of the employees at Xilinx, thank you. We hear you loud and clear. Our primary goalis to put a programmable device in every piece of electronic equipment over the next 10 years. It’s niceto hear that we’re on the right path to get there.

L E T T E R F R O M T H E E D I T O R

Xilinx, Inc.2100 Logic DriveSan Jose, CA 95124-3400Phone: 408-559-7778FAX: 408-879-4780©2004 Xilinx, Inc.All rights reserved.

The Xcell Journal is published quarterly. XILINX, the Xilinxlogo, CoolRunner, RocketChips, Rocket IP, Spartan,StateBENCH, StateCAD, Virtex, Virtex-II, and XACT are regis-tered trademarks of Xilinx, Inc. ACE Controller, ACE Flash,Alliance Series, AllianceCORE, Bencher, ChipScope,Configuration Logic Cell, CORE Generator, CoreLINX, DualBlock, EZTag, Fast CLK, Fast CONNECT, Foundation, GigabitSpeeds…and Beyond!, HardWire, HDL Bencher, IRL, JDrive, Jbits, LCA, LogiBLOX, Logic Cell, Logic Professor,MicroBlaze, MicroVia, MultiLINX, NanoBlaze, PicoBlaze,PLUSASM, PowerGuide, PowerMaze, QPro, Real-PCI,RocketIO, RocketPHY, SelectIO, SelectRAM, SelectRAM+,Silicon Xpresso, Smartguide, Smart-IP, SmartSearch,SMARTswitch, System ACE, Testbench In A Minute, TrueMap,UIM, VectorMaze, VersaBlock, VersaRing, Virtex-4, Virtex-IIPro, Virtex-II Pro X, Virtex-II EasyPath, Wave Table,WebFITTER, WebPACK, WebPOWERED, XABLE, XAPP, X-BLOX+, XC designated products, XChecker, XDM, XEPLD,Xilinx Foundation Series, Xilinx XDTV, Xinfo, XtremeDSP,and ZERO+ are trademarks, and The Programmable LogicCompany is a service mark of Xilinx, Inc. Other brand orproduct names are registered trademarks or trademarks oftheir respective owners.

The articles, information, and other materials included inthis issue are provided solely for the convenience of ourreaders. Xilinx makes no warranties, express, implied,statutory, or otherwise, and accepts no liability with respectto any such articles, information, or other materials ortheir use, and any use thereof is solely at the risk of theuser. Any person or entity using such information in anyway releases and waives any claim it might have againstXilinx for any loss, damage, or expense caused thereby.

Thank You for MakingXilinx Number One

Xcell journalXcell journal

Forrest CouchManaging Editor

EDITOR IN CHIEF Carlis [email protected]

MANAGING EDITOR Forrest [email protected]

ASSISTANT MANAGING EDITOR Charmaine Cooper Hussain

XCELL ONLINE EDITOR Tom [email protected]

ADVERTISING SALES Dan Teie1-800-493-5551

ART DIRECTOR Scott Blair

Next-Generation DataTransport over Metro Area NetworksThe Xilinx GFP core enables efficient

transport of LAN/SAN over

SONET-based networks. 64

Celebrating 20 Years of PartnershipTurning an industry cliché into

a successful business model.

21

F A L L 2 0 0 4, I S S U E 5 0 Xcell journalXcell journalC O V E R S T O R Y

FPGAs on MarsXilinx FPGAs have transitioned from

a flight ASIC prototyping platform

to playing integral roles in the

Mars Exploration Rover Mission.

8

Streaming Data at 10 GbpsUsing a Virtex-II FPGA to stream data from DDR-SDRAM to OC-192 serializers.

13

View from the Top ................................................................5

FPGAs on Mars.....................................................................8

Streaming Data at 10 Gbps .................................................13

Control Your QDR Designs ....................................................16

Celebrating 20 Years of Partnership.......................................21

Author! Author! .................................................................25

Experience Programmable World 2004..................................30

Managing Partial Dynamic Reconfiguration .............................32

Nucleus RTOS for Xilinx FPGAs..............................................38

Implement an Embedded System with FPGAs .........................43

Algorithmic C Synthesis .......................................................46

Design Tool Performance Lowers Costs...................................52

The Need for Speed ............................................................54

Lower Your PCB Manufacturing Costs.....................................57

Plan FPGA Signal Assignments..............................................60

Next-Generation Data Transport.............................................64

Designing Next-Generation Wireless Systems ..........................68

Meeting Interoperability Standards ........................................70

Xilinx Partner Yellow Pages ..................................................74

Reference Pages .................................................................82

To receive a free subscription to the printed Xcell Journal,

or to view the Web-based Xcell Online, visit www.xilinx.com/xcell/.

http://www.xilinx.com/xcell/

We recently emergedfrom a three-yearrecession that was oneof the longest anddeepest in our history,yet things are gettingbetter. The semicon-ductor industry typi-cally moves in atwo-year cycle, unlessit is influenced by

events such as the 9/11 tragedy. Therefore, aftertwo years of growth, an overbuilding of capacitywill likely occur, with another market correctionin 2006. This is a normal and predictable cycle;it’s the way our industry usually works.

These capacity-driven recessions tend to beshallow and short – the last one was in 1996and lasted about 18 months. For Xilinx® dur-ing that period, we had a few negative growthquarters, with an overall 1% growth.

The market recovery is still fragile, drivenprimarily by the U.S. and China. And not all ofthe industries that we deal with are yet in recov-ery, which I think is good because it helps usmaintain a steady growth pattern as they beginto improve later in the year.

Overall, Xilinx is in an extremely good posi-tion – our business processes, our manufactur-ing technology, our circuit innovation, and oursoftware are poised to take full advantage of thecurrent market conditions.

The economy is improving and most analysts predict that the semiconductor industry will grow for the next two years.Here’s what I see ahead for Xilinx.

Preparing for a Bright FuturePreparing for a Bright Future

Fall 2004 Xcell Journal 5

Viewfrom the top

by Wim RoelandtsCEO, Xilinx, Inc.

The Growing Asian MarketsA significant and quickly growing segmentof our business comes from the Japaneseand Asia-Pacific markets – our businessthere is now more than three times higherthan it was just four years ago. This comesboth from systems that are designed andmanufactured there as well as from manu-facturing outsourced from other countries.Plus, Japanese business is starting toexpand and is beginning to help drive theworld economy forward.

I believe our business in Asia will con-tinue to grow over the years to come. Wesee a big shift taking place, driven primarilyby the next big trend in our industry – dig-ital consumer electronics. The core of thisbusiness will be in Asia, and we are puttinga lot of our resources there to help meet thedemand. We recently began staffing a facil-ity in Singapore that will eventually housemore than 200 employees.

Going MainstreamEight years ago, when I joined Xilinx, I saidthat we will put a programmable chip inevery system, and it’s now becoming a reali-ty. Our ability to shrink our products intosmaller and smaller geometries at lowercosts, coupled with the recession (whichmeans that many of our customers can nolonger afford the high costs of designing andbuilding ASICs) is moving more and moreof our customers to take full advantage ofthe many benefits of programmable logic.

Market forces, combined with our low-cost technology advances, are driving pro-grammable logic into the mainstream – ourdevices are now used in all types of prod-ucts and the trend continues to grow. Overthe next two or three years, when these newdesigns go into production, our businesswill expand significantly. Programmablelogic is indeed taking over; it is becomingmainstream and finding new marketswhere it’s never been used before.

Because cores allow us to provide a morecomplete solution, our customers have todo less work to produce more and betterdesigns. And they want to buy cores fromXilinx because they want to have the assur-ance of ongoing long-term support. We arein fact increasing our investments in IP andcores to meet the increasing demand. Wealready have many more cores than ourcompetitors, and thus we are very wellpositioned to take advantage of thesetrends.

Xilinx Strategy for the FutureHere are some of the long-term objectivesthat define our strategy for the next five to10 years.

Setting the StandardWe will continue to set the standard forhow to manage a high-tech company. Ithink we have already done a phenomenal

job – we’re admired as a company thatmanages its people well, treats its peoplewell, and at the same time is innovative andwins in the market. And of course, the coreof our culture is innovation. We want tocontinue to bring new technologies, newcircuitries, new innovative marketing pro-grams, and new channels of distribution.This will continue to be the core of ourstrategy because it’s what makes Xilinxexcel in everything we do.

Leading Manufacturing TechnologyWe will continue to reduce our manufac-turing costs. We made a lot of progress inthe last year and now we need to move onto the next step. My intention is to makesure that all of our organizations arefocused on low-cost, high-volume capabili-ties. The consumer electronics and auto-motive industries require us to reduce costsand ramp production faster than everbefore. We will continue to innovate with-

Beating Moore’s LawSemiconductor technology typically fol-lows Moore’s Law, which states that everytwo years the number of transistors thatcan be fabricated on a chip will double –this law has held true for many years. As weapproach finer and finer process geome-tries, moving from 130 nm to 90 nm anddown to 65 nm, it becomes increasinglydifficult to manufacture devices. Xilinx isleading the industry in the developmentand use of these advanced technologies,which means that we are often the first tosolve difficult process problems – that’sboth the good and the bad news. We usu-ally get to market first with the mostadvanced manufacturing processes, but wealso put a lot of effort into getting it right.

We also have a strategy for significantlyimproving performance through innova-tive architectural designs – the best exam-ple is our new Virtex-4™ family. In fact,

most of our performance improvements inthe Virtex-4 family come from circuitenhancements. The Virtex-4 ASMBLarchitecture allows us to create devices thatare optimized for specific applications, pro-viding just the features and performancethat are needed at the lowest possible cost.As you can see, our innovation is not just inCMOS technology – we are way ahead ofour competition in both device manufac-turing technology and architecture.

Reducing Design Costs with IPOur marketplace is changing rapidly, andour customers must operate differentlytoday than they did four years ago. Theirown customers are much more cost-con-scious, and thus they are much more wor-ried about return on investments. Ourcustomers have fewer engineers because ofthe recession, so they demand more fromus – it’s one of the reasons why we areincreasing our investments in IP and cores.

6 Xcell Journal Fall 2004

V I E W F R O M T H E T O P

Programmable logic is indeed taking over; it is becoming mainstream and finding new markets where it’s never been used before.

in all of our organizations to achieve thisongoing objective. For programmable logicto achieve its full potential in mainstreamelectronics, we must become even moreefficient and productive – and we will.

Yet, while we continue to develop morehigh-volume strategies and products, wewill continue to lead the high-end, high-performance market that has traditionallybeen the core of our business. We are doinga phenomenal job with our Virtex productline, with 70% to 80% market share, andthat will continue as well.

Creating PartnershipsPartnerships are a key strategy that allowus to focus on what we do best whileallowing other companies to provide theproducts and services they do best – wecall it our Partner Ecosystem. We willcontinue to build strong partnerships notonly with our suppliers but with our cus-tomers as well.

We want to engage our customers earlyin their design process so that we can pro-vide the best possible service and supportthroughout their entire design and manu-facturing cycle. This requires a broad rangeof services from a number of ecosystempartners, and that requires a well coordi-nated and comprehensive approach. Wehave been successful with our partnershipprogram in the past and we intend tostrengthen it by making it easier for ourcustomer partners – and our technologypartners – to work more closely togetherfor the benefit of all.

Expanding Our MarketsWe are already the leader in programma-ble logic technology, and now it’s time forus to become a leader in all programma-ble technology, including DSP andembedded processing. Our technologyalready provides significant advantages inthese areas, and it’s time for us to capital-ize on these strengths. We want to be thechampion of programmability because we

are the only company that can providethe advantages of programmable logic,high-performance DSP, and embeddedprocessing all on one device.

We are the largest company in program-

mable logic, with 50% market segmentshare. However, the embedded processormarket and the DSP markets also offer sig-nificant market opportunity.

Brand RecognitionXilinx is already well respected and recog-nized in our marketplace, and we willcontinue to build our brand worldwide.Our success in the first 10 years was basedon two innovations: FPGAs and fablessmanufacturing. When we started in1985, neither of these ideas was credible.Only the Xilinx founders believed they

would work. Yet we made them possibleand we made them credible.

Our second 10 years were based on twothings: becoming the technology leader inour industry and establishing a unique

business culture that fostersinnovation. In that we havealso been very successful.

For the next 10 years, wewant to extend our brand andestablish Xilinx as a globalleader, recognized not only bythe engineering community butalso by the financial communi-ty. We want to be recognizednot only for our innovative cul-ture but also for our financialstability, management depth,the global reach and diversity ofour products, and by the brandname we create.

Going GlobalWe will continue to expandglobally and place ourresources close to the marketsthey serve. If 20% of our busi-ness is in Asia, we will strive toplace 20% of our resourcesthere because we want to beclose to our customers andunderstand their needs. That’swhy we opened up a new fac-tory headquarters in Singapore

and a new design center in India. We wantto have a presence in Asia just like we havein Europe and the United States.

ConclusionInnovation remains the core of Xilinx. I

believe innovation is the only thing thatmatters because if you innovate, there is nocompetition. That’s the reason why wehave gained market share every single yearin the last six years.

As you can see I’m very excited aboutour current situation, and I’m even moreexcited about our future.

V I E W F R O M T H E T O P


For the next 10 years, we want to extend our brand and establish Xilinx as a global leader,recognized not only by the engineering community but also by the financial community.

by David RatterField Applications EngineerNu Horizons [email protected]

Selecting the correct components for any engi-neering project can be a critical and difficultchoice. This is clearly true for engineers at the JetPropulsion Laboratory (JPL) when they mustselect components used on high-stakes flight proj-ects, and especially important on high-profile mis-sions like the Mars Exploration Rover Mission.

On Mars there are no tow trucks or auto clubsto call if something stops working. So how didXilinx FPGAs go from performing a predomi-nantly flight ASIC prototyping role to beingdesigned into and flown in projects like the Marslander and rovers? And what does the future holdfor Xilinx and JPL space missions?

Xilinx FPGAs have transitioned from a flight ASIC prototyping platform to playing integral roles in the Mars Exploration Rover Mission.

Xilinx FPGAs have transitioned from a flight ASIC prototyping platform to playing integral roles in the Mars Exploration Rover Mission.

FPGAs on MarsFPGAs on Mars


The needs of JPL’s design engineers werethe main driving force behind the paradigmshift from ASIC prototype to flight-quali-fied part, as were the Xilinx testing, pro-cessing, and manufacturing flows for itsradiation-tolerant FPGAs. Engineeringneeds demand meeting mission require-ments, both from a functional/performanceviewpoint and a time-to-working-productviewpoint. Xilinx FPGAs provide inherentdesign advantages to meet those needs: highgate densities, rich on-board architecturalfeatures, large I/O counts with multiple I/Ostandards, and the ability to be repro-grammed at any time.

The second reason for the transitionwas JPL’s qualification of Xilinx radiation-tolerant FPGAs into more and more flightsituations.

The net results of these efforts can easi-ly be seen on the Mars Exploration Rovers.Inside of each rover (named Discovery andSpirit), two Virtex ™ XQVR1000s servedas the main brains that controlled themotors. Four Xilinx XQR4062XL devicesin the 4000XL family controlled the Marslander pyrotechnics, crucial to the success-ful multi-phase descent and landing proce-dure. Also evident, although not as visible,are the increasing number of future flightmissions that JPL engineers are designingwith Xilinx radiation-tolerant FPGAs.

In this article, we’ll briefly documentthe parts qualification and design steps,along with the past, present, and future ofFPGA-based flight opportunities at JPL.

Flight ConsiderationsThere are three steps that must be accom-plished before any part can be used in aflight application for JPL. The first is ageneral flight approval for a part. The sec-ond can be referred to as mission-specificapproval. The third is additional designrequirements for flight-based semicon-ductors.

General Flight ApprovalsJPL must give general flight approvalbefore any part can be used for a flightapplication. This process requires that themanufacturer perform numerous addition-al processing, testing, and quality steps

parameters might include the number oftemperature cycles, total ionizing dose, andpredicted rate of radiation exposure. It ispossible that parts with general flightapproval will not get mission-specific flightapproval.

Specific Flight Design ConsiderationsOnly after a part has met the above two cri-teria can it be used in a flight mission. Thedesign process entails incorporating space-specific flight design requirements thatinclude, but are not limited to, the follow-ing single-event phenomena:

• Single-event latch-up (SEL)

• Single-event upsets (SEU)

• Single-event transients (SET)

• Single-event functional interrupts(SEFIs)

In the case of Xilinx radiation-tolerantFPGAs, all single-event phenomena aretaken into account either through the radi-ation-tolerant manufacturing and process-ing steps or through well-documenteddesign practices:

• The epitaxial layer of Xilinx radiation-tolerant FPGAs eliminates SELs.

• Triple-mode redundancy (commonlyreferred to as TMR) mitigates SEUsand SETs.

• “Scrubbing,” or reprogramming theFGPA, takes care of SEFIs and theaccumulation of SEUs.

Let’s discuss the latter two design fea-tures in more detail.

In simple terms, a design with TMRrequires three sets of key logic elements, witha voting structure that allows only the major-ity decision to propagate through the circuit.The theory is that statistically you are goingto get an SEU over some time period. Whenthis upset occurs, it will disrupt a single ele-ment (net, route, or bit). When this happensand the element it disrupts is being used, theother two “correct” elements will have thecorrect value; thus, the correct value will bepassed out of the circuit. This is especiallyimportant in circuits that use feedback, suchas counters and state machines.

over and above the normal commercialprocessing steps.

JPL also meticulously examines devicestatistical and quality data that is constantlyupdated by the semiconductor manufactur-ers. They also examine additional parame-ters in this phase, including temperatureconsiderations and packaging materials aswell as semiconductor characteristics (forexample, are there voids or contaminantsthat in zero gravity could migrate and causefailures?). Only after JPL engineers haveconducted exhaustive research and analysisdo they approve parts for flight use.

JPL Radiation Effects Group scientistswork directly with Xilinx to unify andcontinually improve the testing, process-ing, and manufacturing steps used forXilinx radiation-tolerant parts. This closecustomer/manufacturer relationship hasresulted in a much superior radiation-tol-erant product from Xilinx, and for JPL, ahigh-reliability manufacturing processgives them the utmost confidence.

Specific Flight ApprovalsEven after a part or parts has general flightapproval, it still must receive mission-specific flight approval. Mission-specificapproval is exactly what the term implies:JPL scientists and engineers review themission-specific environments that theparts will encounter. This includes adetailed risk assessment.

JPL takes into account all aspects of theflight to predict what the part(s) will faceduring the mission’s lifetime. Some of these


Numerous approaches can be takenwith respect to scrubbing, from simplyreprogramming the FPGA to partial recon-figuration. The simplest method of scrub-bing is to completely reprogram the FPGAat some periodic rate (typically 1/10 thecalculated upset rate).

For example, if an SEU will occur onceevery 10 days, then you would reprogramthe FPGA every day. However, when youreprogram the FPGA it is not operationalduring that reprogram time (on the orderof micro to milliseconds). For situationsthat cannot tolerate that type of interrup-tion, partial reconfiguration is available.This technique allows the FPGA to bereprogrammed while still operational.

The PastAlthough the both the Discovery and Spiritrovers are still on the surface of Mars andactive, they were launched in June and July2003 and landed on Mars in January 2004.This means, obviously, that the engineeringwas completed in the past.

As stated earlier, the Mars ExplorationRovers used XQVR1000 devices and thelander used XQR4062XLs. TheXQR4062XLs were used during thedescent and landing of the rovers on thesurface of Mars, while the XQVR1000swere used to control all of the brushed DCand stepper motors for the wheels, steering,antennas, camera, and other instrumentson the rovers themselves.

Both the XQR4062XL and XQVR1000designs used TMR for SEU and SET miti-gation as well as scrubbing. JPL engineersachieved TMR in their designs by analyz-ing the design for feedback nets and otherlow-level design details (as detailed inXilinx application note XAPP197), andthen inserted or replaced logic with TMRlibrary elements. After the designs werefunctionally implemented, the engineerswent back through the design and insertedthe TMR logic where necessary and madeother space-specific design changes.

Due to the critical nature of theXQR4062XL’s role, FPGA redundancy wasutilized to mitigate all single-event phe-nomena. The scrubbing techniqueemployed was a complete reconfiguration.

When an upset condition was detected, theFPGA in question was completely repro-grammed, while the redundant FPGAsremained functional. On the other hand,because of its non-time critical nature, whena fault condition was detected on one of theXQVR1000s, the rover was temporarilyhalted, the FPGA was reprogrammed, andthe rover went back on its merry way.

All of the mitigation techniques on theMars Exploration Rovers worked exactlyas designed by JPL engineers. During theseven-month voyage from Earth to Mars,the Xilinx radiation-tolerant FPGAs onthe lander were “left on.” During thattime JPL collected data of interest,including the upset rate. The upset ratespredicted for the FPGAs by JPL matchedalmost exactly the actual upset ratesobserved. Also, the upset detection andmitigation techniques implemented onthe FPGAs performed their functionsflawlessly and allowed for robust and reli-able operation.

The PresentJPL is currently working on flight designswith both Virtex-II™, the latest Xilinxradiation-tolerant family, as well as Virtexradiation-tolerant FPGAs. These new mis-sions will fly in the next two to five yearsand are becoming more and more sophisti-cated in both mission electronic require-ments and design implementation. Thesecurrent projects more fully utilize theFPGA’s inherent benefits.

JPL is particularly interested in the abil-ity to update or revise designs while thespacecraft is either in flight to its final des-tination or already there. This will allowengineers to implement algorithmenhancements after the spacecraft has leftEarth, enabling them to constantlyimprove design performance during a longmission timeline. This, coupled with par-tial reconfiguration, will allow an FPGA-based design to have one portion of itsdesign upgraded while the rest of thedesign remains completely operational.

There have been some breakthroughs inthe area of single event mitigation and cor-rection. Xilinx, in partnership with SandiaLabs, recently produced a TMR tool that


Animation by Dan Maas, Maas Digital LLC(c) 2002 Cornell University. All rights reserved.This work was performed for the Jet PropulsionLaboratory, California Institute of Technology,sponsored by the United States Government underPrime Contract # NAS7-1407 between theCalifornia Institute of Technology and NASA.Copyright and other rights in the design drawingsof the Mars Exploration Rover are held by theCalifornia Institute of Technology (Caltech)/ JetPropulsion Laboratory (JPL). Use of the MERdesign has been provided to Cornell courtesy ofNASA, JPL, and Caltech.

will XTMR a design. The XTMR tooltakes in a synthesized netlist, analyzes it,and applies the appropriate TMR measuresand space-specific design modifications toproduce a final XTMR netlist. Not onlydoes this guarantee a much more robustTMR design, it also takes what used to takean engineer days or weeks to perform andreduces the process to a matter of minutes.

The FutureWho knows that the future has in store?The new missions have more demandingrequirements: more speed and more inte-gration, with an ongoing goal of less spaceand less weight. On the Xilinx front, eachsubsequent family of radiation-tolerantFPGAs (like Virtex-II Pro™ devices) willprovide more integration, more architec-tural features, and more capabilities.

The need for more integration, speed,and reduced space and weight goes hand inhand with continually improving radia-tion-tolerant FPGAs. Xilinx advances inFPGA technology and the improvementsin radiation testing and processing madepossible by their relationship with JPLcome together to spell success.

ConclusionThe collaborative efforts between JPL, theXilinx aerospace and defense team, andlocal support (provided by the manufactur-er’s representative, Norcomp SC, and NuHorizons Electronics Distribution) helpedpave the way for Xilinx to go from a pre-dominantly ASIC prototyping role tobecome key components in the successfuldesign and implementation of the MarsExploration Rovers.

Current JPL flight projects that willlaunch in the years to come are alreadybeing designed using the latest Virtex andVirtex-II Xilinx high-reliability FPGAs.And the continual release of bigger, faster,and better Xilinx radiation-tolerant fami-lies means that with Xilinx and JPL, noteven the sky is the limit.

For more information, please visithttp: / /marsrovers . jpl .nasa.gov/home/ , w w w . x i l i n x . c o m / e s p / m i l _ a e r o /index.htm, www.norcompsc.com, andwww.nuhorizons.com.


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writing, editing, and marketing.

We recently launched the Xcell Publishing Alliance to help you publish your technical ideas. We can help you –

from concept research and development, through planning and implementation, all the way to publication and marketing.

Submit articles for our Web-based Xcell Online or our printed Xcell Journal and we will assign an editor and a graphics artist to work

with you to make your work look as good as possible. Submit yourbook concepts and we will bring our partnership with Elsevier,

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For more information on this exciting and highly rewarding program, please contact:

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[email protected]

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© 2004 Xilinx, Inc. 2100 Logic Drive, San Jose, CA 95124. Europe +44-870-7350-7722; Japan +81-3-5321-7711; Asia Pacific +852-2-424-5200;Xilinx is a registered trademark and The Programmable Logic Company is a service mark of Xilinx, Inc.

by David BanasPresidentTao of Digital, Inc. [email protected]

You’d like to use DDR-SDRAM as the stor-age medium for OC-192 test pattern gener-ation to dramatically increase the length ofpatterns available to you. However, whenyou take the standard approach to archi-tecting this interface and attempt imple-mentation in a FPGA, you find that theFIFO read clock enable signals don’t meetthe timing requirements. Your projectbudget can’t afford an ASIC. How can youget around this issue and make the FPGAwork as the needed interface?

Fortunately, the Xilinx® digital clockmanager (DCM) provides the answer. Aslong as you’ve got sufficient global clockresources available, you can use theDCM’s quadrature-phase outputs to clockthe outputs of the four FIFO groupsdirectly. This eliminates the need for clock

enable signals in the 320 MHz clockdomain and yields a design that willachieve timing closure at that speed.

Standard ArchitectureFigure 1 shows the standard architectureused to design a streaming data interfacebetween DDR-SDRAM and OC-192 seri-alizers. All of the design blocks shown inthis figure, with the exception of theFIFO/MUX controller, are available asdirectly instantiated elements (the DDRflip-flop), Xilinx CORE Generator™modules (MUX x and FIFO n), or Xilinx-provided reference designs (DDR-SDRAM controller).

DDR-SDRAM ControllerThe DDR-SDRAM controller is a modifiedXilinx-provided reference design. I modifiedit to provide a continuously streaming modeof operation. The controller provides thenecessary address and control signals fordriving a standard PC-1600/2100 DDR-

SDRAM module and also converts the databus from a 64-bit DDR mode to a 128-bitSDR mode to facilitate a simpler clockingscheme inside the FPGA.

The controller stops fetching data frommemory and disables the write enable sig-nal to the FIFOs when it detects thatFIFO_0’s high watermark signal has goneactive (not shown in Figure 1).

The frequency of clock 1 is 100 MHz,yielding a burst data rate of 12.8 Gbps.This data rate is 28% higher than thatrequired by the serializer, leaving room foroverhead tasks such as DRAM refresh.

FIFOsThe eight FIFO blocks represent standard,asynchronous FIFO elements generatedusing the CORE Generator tool. TheFIFOs serve a dual purpose. First, they pro-vide elastic buffering between two asyn-chronous clock domains. Second, theywork in conjunction with the MUX x andFIFO/MUX controller blocks to provide

Using a Virtex-II/Pro FPGA to stream data from DDR-SDRAM to OC-192 serializers.



the data bus width reduction. This is nec-essary to convert from the 128-bit data buspresented by the DDR-SDRAM controllerto the 16-bit data bus required by typicalOC-192 serializers. I will explain this func-tionality in more detail.

MUXsThe two multiplexer blocks represent stan-dard 4-to-1 synchronous 16-bit bus multi-plexers also generated using the COREGenerator tool.

DDR Flip-flopThe DDR flip-flop is a directly instantiat-ed element of the Virtex-II™/Pro™ archi-tecture. Its two inputs are multiplexed ontoits single output through successive clock-ing at both clock edges. In this way, thedata A input is clocked through to data outat the rising edge of the clock, while data Bis clocked through at the falling edge.

FIFO/MUX ControllerThe FIFO/MUX controller is the onlyfully custom element in the architecture

(1/[320 MHz]). The numbers identifyingthe various data intervals correspond to theindex of a particular 16-bit word in asequence of data, which is at least 24 16-bitwords in length. The FIFO outputs areupdated once every four clock cycles inquadrature succession, as shown in the tim-ing diagram.

The two multiplexers select from amongthe four FIFO groups in the same succes-sion. However, a delay is imposed on themultiplexer selection sequence such that the

FIFO outputs are allowedthree clock cycles to prop-agate to the multiplexerinputs before being select-ed, as shown.

By designing this way,I can apply a multi-cycledelay constraint to theFIFO outputs and thusease the task of the placeand route engine. This isvery helpful when design-ing in a 320 MHz clockdomain. The DDR flip-flop selects from amongits two inputs in standardfashion, as shown. Theresult is a 640 Mword/sdata stream at the output,yielding a data rate to theserializer of 10.24 Gbps.

Implementation ResultsUp to this point, the pro-posed architecture appearsto satisfy the designrequirements. However,when I tried to implement

this approach in a XC2V1000-6BG575part, I couldn’t get the propagation delays ofthe FIFO read clock enable signals underthe 3.125 ns period constraint imposed bythe 320 MHz clock. Therefore, I came upwith the following modification to the basicarchitecture (Figure 3), which resulted insuccessful timing closure.

Modification DescriptionIn the modified architecture shown inFigure 3, I eliminated the clock 1 domainsection of the design, as it is irrelevant to

(also shown in Figure 1). Its operation isstraightforward and you can easily under-stand it by looking at the timing diagramof Figure 2.

Note that while the signals generated bythe FIFO/MUX controller are not explicit-ly shown in the timing diagram, theirbehavior is implicitly depicted there. Forinstance, the outputs of FIFOs 0 and 1only change when the enable A signal fromthe FIFO/MUX controller is active.

Likewise, whenever a multiplexer out-

put changes, it is the respective select X sig-nal from the FIFO/MUX controller thatdictates which of the multiplexer’s fourinputs gets clocked through to its output.

Timing DiscussionAs mentioned previously, Figure 2 depicts atiming diagram that describes the dynamicbehavior of the architecture shown inFigure 1. The clock signal shown is clock 2from Figure 1. (The clock 1 domain doesnot contain any novel design features.)

The clock period “T” is 3.125 ns


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Figure 1 – Standard architecture

the discussion. The only design block thatchanged in the modified architecture is theFIFO/MUX controller; all other designblocks remain unchanged.

Instead of generating clock-enable sig-

nals, the controller block generates four 80MHz clocks in a quadrature phase arrange-ment. This is very easy to accomplish whendesigning for the Xilinx Virtex-II/Pro archi-tecture, as the DCMs in that architecture

have quadrature phase outputs. All I had todo was divide down the 320 MHz clock by afactor of four, using an additional DCM, togenerate the original 80 MHz clock signal.

When I apply these quadrature-phased80 MHz clocks directly to the four FIFOgroups, respectively – without using anyclock enable signals – the data at all FIFOoutputs is exactly as required by the originalarchitecture. You can see this fairly easily byenvisioning these four clocks overlaid atopthe four FIFO n/n signals in the timing dia-gram of Figure 2.

Notice that the rising edges of the fourclocks line up perfectly with the changesin the outputs of the four FIFO groups.You no longer need to use clock enables togovern the FIFO read clocking and have,therefore, eliminated the one group of sig-nals that failed to achieve timing closure.Of course, you must have two additionalDCMs and five additional global clockbuffers available to make use of thisapproach.

ConclusionBy taking advantage of the designtechnique presented here, OC-192test pattern generation hardwaredesigners can avail themselves ofthe low cost and large capacity ofstandard DDR-SDRAM modules,thereby making possible the use ofextremely long test patterns orautomated testing with manyshorter patterns, all without incur-ring the cost of ASIC design andproduction.

The technique presented herewill also find applicability in thearea of direct digital synthesis(DDS) of arbitrary waveforms,where a high-speed digital wave-form is used, in conjunction withPWM or Sigma/Delta modula-tion and subsequent low-pass fil-tering, to produce arbitrarywaveforms with great precisionand repeatability.

If you have any questions or sug-gestions, please contact me, DavidBanas, at (415) 846-5837, or e-mailat [email protected].


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Figure 3 – Modified architecture

by Jerry A. LongTechnical Marketing Manager, Chronology Division Forte Design [email protected]

As design requirements push memoryinterfaces to operate at 200 MHz andbeyond, a new set of timing challengesenters the design arena. Timing analysisplays an increasingly prominent role inthe identification and resolution of systemoperation issues.

It’s likely that you will use doubledata rate (DDR) or Quad Data Rate(QDR™) memory devices in your nexthigh-speed design, which brings theadded need to design signal skew intothe memory controller to ensure properclock/data relationships.

Xilinx® has simplified the use of thesedevices by providing high-performanceexternal memory interfaces directly fromtheir Virtex-II™ FPGAs. And to clearlyunderstand interface timing and potentialissues, Chronology has added features toits TimingDesigner® tool to streamlinethe exchange of critical timing data withthe Xilinx ISE software suite.

A step-by-step guide to solving QDR memory data capture challenges with Virtex-II FPGAs.A step-by-step guide to solving QDR memory data capture challenges with Virtex-II FPGAs.

Control Your QDR DesignsControl Your QDR Designs


TimingDesigner generates place androute constraints, allowing direct use ofpost-place-and-route timing informationto verify desired FPGA interface operation.You can accurately determine the properclock/data relationship for yourDDR/QDR memory interface design,export the information as constraint datainto ISE, and automatically get visual veri-fication of design success.

For the purposes of this design guide,we’ll use a QDR SRAM device to illustrate asource-synchronous interface design.Stepping through the design flow, we imple-mented a QDR memory controller in aXilinx X2V50 Virtex-II Pro™ FPGA with afocus on the interface signals required for aread operation, utilizing a 133 MHz masterclock. The memory device is a Micron™ 18Mb QDR II four-word burst SRAM(MT54W1MH18J).

The features and principles outlined hereare not necessarily unique to high-speedmemory design. TimingDesigner’s robusttiming diagram-based analysis features, cou-pled with its Xilinx-specific import/exportcapabilities, allow a level of integration thatcan be applied to any timing-critical designinterface for Xilinx FPGAs.

QDR Interface Timing RequirementsQDR SRAM devices have unique timingrequirements for successful read operations.In order to guarantee accurate data capture,QDR devices require the capture clock to becenter-aligned within the valid data window.For source-synchronous designs, this meansshifting the optional-use echo data clocksupplied by the QDR device.

Center Alignment of Capture Clock EdgesProper timing for read operations of QDRSRAM interface designs requires you tocenter-align the edges of the capture clockwithin the valid window of the data bus foraccurate data capture, as shown in Figure 1.This is because most SRAM devices typi-cally have a positive setup and a positivehold requirement, and both are roughly thesame value. So it makes sense to center theclock edge within the data valid window tomaximize the safety margin for latchingdata. To accomplish this, the memory con-

clock/data relationship to ensure that vari-ous temperature effects the design mayencounter (or other unforeseen influences)won’t cause an excessive amount of drift insignal position during the read operationand result in a violation of the setup orhold time requirement of the receiving reg-ister. In theory, a center-aligned clock edgewill maximize the setup and hold times formost devices, allowing sufficient safetymargins for signal drift.

However, some devices, like the VirtexII-Pro device, have a negative hold timerequirement, which simply means that datacan transition to the next value before theclock edge that latches it. In effect, thischaracteristic places the clock edge to theright (delayed) of the data transition. So forthese devices, if you center-align the cap-ture clock within the actual data valid win-dow, you may be satisfying the setup/holdrequirements of the device, but the safetymargin achieved will be greater for the holdrequirement than for setup.

The ideal solution is to provide a maxi-mum safety margin for both the setup andhold requirements of a device, which trans-lates to “balancing” these margins. Thisprovides equal amounts of safety for both,as illustrated in Figure 2.

troller must skew the capture clock.For source-synchronous capture of read

data from a QDR device, you must use theoptional echo clock signals (typically CQand CQ#) provided from the QDR device.With the Virtex-II Pro family of FPGAs,skewing this clock is easily accomplishedusing one of the digital clock managers(DCM). However, the amount of phase shiftnecessary to achieve a safe margin is anunknown, given the external PCB skew

effects on both the incoming data and itsassociated clock, as well as the associatedrouting delays encountered within the FPGAfabric. TimingDesigner will help us to accu-rately determine this phase shift value.

Capturing Read Data in Virtex-II Pro DevicesYou can skew (or delay) the clock signal byusing PCB trace delay techniques, or bydesigning clock delay into the memory con-troller design. Because PCB trace delay tech-niques aren’t very flexible, it makes moresense to use the incidental PCB trace delaycoupled with internal FPGA routing delayand use the Virtex-II Pro DCM element asthe “adjustable” component for phase shiftwithin the FPGA memory controller design.

Typically, memory manufacturers rec-ommend center alignment of the


Figure 1 – Illustration of center-aligned clock/data relationship

Figure 2 – Center alignment of device minimum data valid window

To accomplish this balance, you mustdetermine the minimum data valid windowfor the receiving device, and center that win-dow within the actual data valid windowprovided from the memory device, givenyour design parameters. Using the minimumsetup and hold characteristics of the receiv-ing device, determine a minimum “safe” datavalid window with the following formula:

Min Data Valid Window = Min Setup + Min Hold

Because the placement of the resultingminimum data valid window is tied to theplacement of the clock signal, skewing theclock will effectively skew the minimumdata valid window. As indicated in Figure

2, as long as the data bus transitions out-side of the receiver’s minimum data validwindow, safe data capture is ensured.

Determining the Clock/Data RelationshipTo determine the required clock skew,

you create a timing diagram illustrating theclock/data relationship of a read operationfor the QDR device based on the actualread timing diagrams acquired directlyfrom the memory device’s data sheet. To bemore descriptive of the signal relationshipsin the diagram, name the read data clocksignal C_Mem and the data bus signalQ_Mem to reflect the signals as they appearat the pins of the memory device.

To model those same signals as theyappear at the pins of the FPGA, after theiraccumulated flight path delay from theQDR device, create the signals C_FPGAand Q_FPGA. Figure 3 is a block diagramillustrating the signal path relationshipsjust described.

The resulting QDR memory read dia-gram is displayed in Figure 4. The data busrepresents the transition period necessaryfor all elements of the data bus betweenvalid data words. The PCB trace delayaccumulated by both data and clock is rep-resented with separate variables: tPCBdatafor the delay associated with the data sig-nal and tPCBclock for the delay associatedwith the clock. This allows you to easilyvary the values and see the effect on thedesign results.

Creating Constraints with TimingDesignerKnowing the timing relationship of anexternal clock and its associated data as itarrives at the pins of the FPGA provides aunique advantage for accurate data captureand design success. The Xilinx timing con-straint OFFSET is used along with its asso-ciated keywords to provide initial timinginformation to ISE, so that proper place-ment of data capture elements and theirassociated routing delays will be adequatefor the design. As illustrated in Figure 5,TimingDesigner provides direct dynamicaccess to any measurement within a timingdiagram for generation of a place and routeconstraint file (UCF).

For this design example, you need tomeasure the offset for the data (Q_FPGA)and clock (C_FPGA) signals, and the dura-tion of the valid data window at the pins ofthe FPGA controller. This can be donedirectly from the timing diagram usingTimingDesigner measurements, as indicat-ed in Figure 4. You’ll also need the readdata clock period measurement.

Generating Constraint InformationTimingDesigner’s Dynamic Text dialogbox offers a way to reference timing dia-gram measurements from within a vendor’sspecific timing constraint syntax. UsingISE’s OFFSET timing constraint syntax,you reference the measured offset values in


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Figure 4 – Clock/data timing diagram of QDR read operation

the Dynamic Text dialog box to assembleconstraints for transfer into the ISE con-straints file. The syntax for this designexample is illustrated below:

OFFSET = IN %mOFFSET_IN.min VALID%mDVW.min ns BEFORE “rd_clk” TIMEGRPRdClkRisingFFs;OFFSET = IN %mOFFSET_IN_F.min VALID%mDVW.min ns BEFORE “rd_clk” TIMEGRPRdClkFallingFFs;

The VALID keyword is for specifyingthe duration of the incoming data validwindow, and is used for hold time calcula-tions in ISE. The signal rd_clk is the pinname in the design code associated withthe C_FPGA clock signal in the timing dia-gram. Notice that two offset specificationsmust be declared – one for the rising clockedge and one for the falling clock edge –because this is a dual-data rate read opera-tion. Also notice the “%” syntax that indi-cates dynamic text access of measuredvalues in the timing diagram.

The Dynamic Text dialog box willresolve the dynamically referenced meas-urements and allow direct transfer of theinformation into the UCF constraintsfile. Once the UCF file has been assem-bled, execute a place and route in the ISEtool set.

Take Control of Your DesignAfter initial place and routeis complete, you can gener-ate a timing report usingthe TRACE timing analysistool within ISE, andimport that into the timingdiagram. This will allowyou to determine the actualrouting delays so that youcan specify the necessaryphase shift for the readclock. You then enter thephase shift attribute intoISE, execute a final placeand route, and generate atiming report. When com-plete, you then re-importthe timing report to gaugehow well the constraintswere met.

Determining Routing DelaysFor this design example, ISE placed theread data capture registers into the I/Oblocks of the Virtex-II Pro devices,because they capture data from the inputpads and have a common clock and resetsignal. This is a default setting for ISE’smapping process and is appropriate forthis design example.

As the I/O blocks have only one routingpath for input data signals, the TRACEreport includes this data path delay in thesetup and hold requirements of the I/Oblock registers. However, the clock signalhas several possible paths from the inputpad to the capture register, and this designexample uses a path through the DCM ele-ment for phase shift control. So you mustdetermine the routing and element delaysfor the clock path to achieve proper phaseshifting of the clock.

A TRACE analysis report is generated inverbose mode to get the needed timinginformation. This report is limited to 16paths per constraint (the data bus is 16bits). Briefly look at the report and makenote of the worst-case setup path for thedata bus in preparation for import into thetiming diagram.

To import the desired TRACE analysisreport information (saved as a TWX file)

into TimingDesigner, map the worst-casesetup path identified earlier to the associ-ated waveform in the diagram(Q_FPGA), and then import the infor-mation to create variables for the routingand element delays. Mapping the FPGAports guides TimingDesigner to thedesired signal information, and allows forautomatic updates of existing variables ifsuccessive place and route executions arenecessary.

Visualization at the Capture RegisterAfter importing the timing results, createanother clock signal (Cin_FPGA) to rep-resent the clock characteristics at the datacapture register. You then add the setupand hold requirements obtained in theTRACE report import as TimingDesignerconstraints on the data signal relative tothe register clock, as shown in Figure 6.

Notice that the indicated setup andhold margin results from the diagrammatch the slack values from the initialTRACE timing report, and indicate thatthe setup paths are failing by about 2 ns,but the hold time paths have more thanenough margin. You need to shift theclock so that both the setup and hold timemeasurements are met with roughly thesame margin.


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Figure 5 – TimingDesigner offers an intuitive interface to ISE’s design flow.

Making AdjustmentsUsing the imported information obtainedfrom the TRACE timing analysis reportand the measured values from our timingdiagram, you can obtain the attribute valuefor the necessary DCM phase shift (seesidebar, “Balancing the Data ValidWindow”). For this example, the attributevalue was determined to be 108, for a shiftof 3.165 ns. You then enter this value intothe ISE tool flow, and execute a secondplace and route to shift the clock and prop-erly balance the setup/hold margins.

Verifying the ResultsRe-importing the new post-place-and-routetiming report using the previous import set-tings will automatically update all of thenecessary values, and correctly re-positionthe register clock signal (Cin_FPGA). This isillustrated in Figure 7. Examination of thesetiming results shows that the setup and hold

requirements for a read data capture in thedesign are now balanced with respect tomargin (slack), giving the safest possibleresult for any unforeseen signal drift.

ConclusionUsing TimingDesigner together withXilinx Virtex-II Pro devices allows opti-mal safety margins for setup and holdrequirements, which are necessary foraccurate data exchange with a QDRSRAM memory controller.

By following a design process that com-bines the use of TimingDesigner timingdiagrams and ISE’s post-place-and-routetiming reports, you can create an accurateanalysis of your design’s critical timingrelationships. Using timing diagrams, youcan account for PCB trace delays andother external factors that will affect thesignal relationship at the pins of yourFPGA device.

ISE’s TRACE timing analyzer providestiming reports that give you details on theroute delays and constraint requirements ofyour FGPA device. Together, these toolsallow you to accurately capture andexchange critical interface timing informa-tion, and allow visual verification that yourdesign will perform as desired.

To learn more about TimingDesignerand the Chronology Division of Forte Design Systems, please visitwww.timingdesigner.com.

Balancing the Data Valid Window

You can determine the amount ofDCM-generated phase shift neededfor the clock signal to balance the datawindow using the following procedure:

1. Subtract the minimum data valid window for the Virtex-II Pro devicefrom the design’s actual data validwindow, and divide that result by two.This accounts for the differencebetween the two valid data windows(DlyDVW).

DlyDVW = (DVWactual – DVW_VIImin) / 2

2. Subtract the offset measurement madeat the pins of the FPGA device fromthe required setup time for the captureregisters, to account for device setuprequirements (DlyRelSU).

DlyRelSU = IOBsu – OFFSET

3. Determine total clock path delay fromthe TRACE timing report (Xtcd).

Xtcd = <from TRACE report>

4. Add up the necessary delays (valuesobtained in 1 and 2 above), and sub-tract the total clock path delay (valuefrom 3 above).

Clk_offset = (DlyDVW + DlyRelSU) – Xtcd

5. Finally, determine the correct ISEattribute value to control DCM phaseshift with the formula:

phase shift attribute = (Clk_offset/Clk_period)*256

Figure 7 – Balanced setup and hold of data capture register

Figure 6 – Setup and hold of data capture register after initial placement


by Xilinx Staff

“Partnership” might possibly be the mostoverused word in the high-technologyindustry. But at Xilinx®, it transcendscliché as a foundation principle behind thecompany’s highly successful business modelsince its inception.

Today, the Xilinx way of thinkingreflects a rare mindset about the value of aninterconnected ecosystem of like-mindedcompanies and the benefits such anapproach can bring to Xilinx, its customers,and to the partners themselves.

To say that Xilinx was founded on theSpirit of Partnership is no overstatement.In the original 1984 business plan, the sec-ond bullet under the “strategy” section(after the primary strategy point of “maxi-mizing our strength in product architectureand design”) articulated the idea to partnerwith complementary suppliers. The Xilinxfounders thought that through an extremefocus on a few core competencies, Xilinxcould deliver highly differentiated productsand drive technology innovation forward.

Most notably at the outset was the needfor a manufacturing partner. The foundersfundamentally believed that there was noneed to fund such a capability in-house – aradical concept in the era of “real men ownfabs.” (The average price tag for a fab at thetime was $300 million, about one-tenth oftoday’s going rate, but still a hefty invest-ment for a startup company in 1984.)

Turning an industry cliché into a successful business model.

Celebrating 20 Years of Partnership


VP of Worldwide Marketing Sandeep Vij in the Xilinx Hall of Patents

Company founder Bernie Vonderschmittleveraged past relationships and his solid rep-utation for fair play to negotiate a manufac-turing deal with Japanese giant Seiko, whichagreed to allow Xilinx-designed chips to beproduced in its fabs. Sealed with only ahandshake, Xilinx had its first partner andthe industry had a new model – the fablesssemiconductor company.

In short order Xilinx signed up anothercritical partner as its first distributor,because the founders viewed the salesprocess as they did manufacturing: essen-tial, yes, but not necessarily something thecompany needed to “own.” As with Seiko,the distribution agreement was built onmutual trust and a benefit to both sides – abenefit that could be measured beyond justdollars and cents.

Since then, Xilinx has formed partner-ships with a wide range of other suppliersin the semiconductor supply chain, allguided by a consistent principle.

“When we look at forming a partner-ship, the first question we ask is ‘what’s init for you?’” Xilinx CEO Wim Roelandtssays, explaining a philosophy that mayseem counterintuitive to the traditionalapproach. “It really should be weighted51-49 in the partner’s favor. They need toget something out of it, as much – if notmore – than we do.”

Such an approach has helped Xilinxassemble critical components to fill the“solution gap” in its offerings, allowing it tofocus on developing the core technologyfor which it has gained the deserved repu-tation of a world-class innovator. It has alsomade Xilinx one of the most respectedcompanies in all of high technology and afavorite among complementary suppliersboth large and small.

“For us, a partnership is more than afinancial transaction or relationship. It real-ly is about shared goals and ways of think-ing,” says Sandeep Vij, vice president ofworldwide marketing at Xilinx. “Yes, we

“Programmable technology requires thesmallest geometries and advanced processes –and we must be a leader in those areas. Weare willing to invest to be able to achieve suchthings as producing the world’s largest dies,to be first to 90 nm. And our partners mustbe, too.”

Ooi also points out that because Xilinx isa mission-critical supplier to its customers,its partners must share that sense of urgencyand flexibility. “They have to be able to scalewith us,” he says of an increasingly valuableasset in the cyclical semiconductor industry.

Vincent Tong, vice president of prod-uct technology, agrees, adding that thenumber-one criterion for a Xilinx partneris to be a “technology leader.

“We can’t afford to partner with compa-nies that aren’t leaders in what they aredoing. Three or four years ago, when itcame to manufacturing, you could kind ofthrow a design over the wall. Today weneed to be engaged tightly with our part-ners to drive technology forward. We havemore than 80 process engineers and wedon’t even own a fab,” he says, underscor-ing the commitment level of Xilinx even inareas in which it chooses to partner.

Through its partnership strategy inmanufacturing, Xilinx is already pushinginto areas beyond the current state-of-the-art, including joint development work in75 and 65 nm process geometries.

The Link to the CustomerAs with manufacturing, Xilinx made thedecision early on that it would work withpartners to sell and distribute its products(notably, field support of those products wasalways viewed as a critical internal function).

“It was a decision borne out of necessityand practicality,” explains Vice President ofSales Steve Haynes, who’s been with thecompany for nearly 20 years. “We knewthat as a company we needed to focus onwhat we do best – design, technology, inno-vation. We needed a ready-made channel to

use partnerships to maintain our own focusand we know it doesn’t make sense econom-ically for us to invest in all areas. But itcomes down to results – our partnerships areaimed at making breakthroughs that allowour customers to scale new heights.”

Manufacturing PartnershipsManufacturing still represents the most sub-stantial of the Xilinx partnering strategies, ifonly because of the cost of today’s modern fab-rication facility. Xilinx has emerged as one ofonly a small handful of semiconductor com-panies that truly “pushes the envelope” whenit comes to implementing new technologyprocesses. Recently, it became the first compa-ny to ship a production device based on 90nm process geometries, considered the leadingedge of expertise. It also is among the leadersin the use of 300 mm wafers to produce itschips. Both manufacturing achievementsallow Xilinx to reach new price/performancemilestones with its products and further dis-tance itself from its competitors.

Although such advances are enabled bychoosing the right type of company to part-ner with (for manufacturing, Xilinx partnerswith UMC™ and IBM™), Xilinx itself is akey contributor to driving manufacturingadvancements. The company has more than100 engineers on-site at UMC, for example,working in tandem with their R&D teams.And because of the “regular” nature of itsstructure, programmable logic technology isan excellent means for manufacturers tocharacterize new processes, as UMC hasdone with its last several generations of newprocess nodes. But perhaps the secret ingre-dient is mindset.

“Our partners must share our view on risk-taking. They must be willing to engage injoint risk-taking and be willing to try newthings. It is the only way to stay on top of lead-ing-edge technology, to truly innovate,” saysB.C. Ooi, Xilinx vice president of operationsand the man responsible for seeing that Xilinxproducts stay on the leading edge.


...Programmable logic technology is an excellent means for manufacturers to characterize new processes...

get our technology in the hands of the cus-tomers. There were, and still are, firms thatbring an expertise and reach that we couldn’tor didn’t want to develop ourselves.”

Today Xilinx uses a network of close to30 partners to deliver its products to cus-tomers around the world. Some are broad-line distributors who sell complementarytechnology to round out the use of program-mable logic. Others are regional or verticalmarket specialists. In most cases, Xilinx is themost significant product line they represent,and in all cases the relationship is based onmutual trust and shared values.

“When a customer looks at a rep [resen-tative], they are looking at Xilinx. We haveto be on the same page in all facets of therelationship. We have to know them as wellas we know ourselves,” says Haynes.

Haynes and his team meet regularly withsales partners to align their goals and strate-gies, and make sure the company’s productsare being represented consistently with the“Xilinx Way.”

The formula is surely working, as Xilinxsales and customer satisfaction metricsshow. But it’s a constantly evolving process,as Haynes well knows. “Good partnershipsevolve. Our channel looks a lot differentthan it did 20 years ago. It’s like being in amarriage – you have to work at it.”

Comprehensive SolutionsThe design and use of programmable logichas become an increasingly complex process.In the early days of Xilinx, third-party designtools were just coming to market as the EDAindustry took shape, and commercial IP coreswere almost non-existent. Today, they, alongwith a set of other capabilities, are essential todeveloping multi-million gate, multi-func-tion systems on chip (SoCs). Thus, the Xilinxpartnership model has expanded significantlyto include technology partners who canround out the core offering.

“Today’s markets call for a completesolution, which includes the FPGA and afull set of components and tools,” saysSenior Manager of StrategicRelationships Jasbinder Bhoot, whooversees all of the partnership programsat Xilinx. “Xilinx has been successfullydelivering for years the best FPGA prod-ucts in the industry. Now, together withour partners, we have a focused emphasison providing comprehensive solutions toour customers. We seek out and collabo-rate with best-in-class companies tocomplement our product offerings withEDA tools, IP, design services, referencedesigns and manufacturing kits.”

Xilinx partners must share our senseof business integrity and win-win philos-ophy. “We are fairly selective inwho we work with. Yes,they must bring a best-of-breed offering,and yes, it mustmake econom-ic sense for

both sides. But these are the companieswith whom we will be on the front lineswith our customers, so we have to be insynch on many different levels,” explainsBhoot.

Bhoot and his team use well-definedmetrics to gauge how effective each andevery partnership is for Xilinx and itscustomers. And they are constantly onthe lookout for new areas to developpartnerships and make Xilinx technolo-gy more accessible and complete.

Today, Xilinx counts some 250 com-plementary technology and serviceproviders in its “ecosystem” of companiesthat help it deliver the most robust solu-tions in the industry. From industry lead-ers such as IBM™, Cadence™, MentorGraphics®, Synopsys™, Synplicity™

and Wind River™ to specializedexperts in key areas, Xilinx

partnerships provide maxi-mum breadth and

depth of technologyofferings.

Today, Xilinx counts some 250 complementary technology and service providers in its “ecosystem” of companies that

help it deliver the most robust solutions in the industry.


Jasbinder Bhoot, Senior Manager of Strategic Relationships


Among the areas in which Xilinx partners are:

• Intellectual property cores. Xilinxworks closely with independent third-party core developers to produce abroad selection of industry-standardsolutions, deemed AllianceCORE™,dedicated for use in and optimizedfor Xilinx programmable logic.

• Design tools. Xilinx’s AllianceEDApartners are among the tool leadersfor each step in the design process,including such critical areas as high-level design, synthesis, logic verifica-tion, and complete PCB design.Xilinx and its partners develop themethodologies and tool flows thathelp make programmable logic usersproductive and well positioned totake full advantage of Xilinx devices.

• Design services. Xperts are a globalnetwork of certified design expertstrained to take full advantage of thefeatures present in the Xilinx PlatformFPGAs, software, and IP cores. Whencustomers need design expertise, theycan access a sophisticated resourcedatabase and quickly identify designconsultants in their own regions.

• Embedded development tools.Xilinx AllianceEmbedded partners are experts in the field of embeddedsystems – inclusive of compiler,debugger, IDE, and trace/visibility

tools – as well as RTOS require-ments. They support the Xilinx commitment to deliver high-per-formance, cost-effective embedded processor-based solutions.

• Reference designs. Xilinx teams upwith industry-leading semiconduc-tor vendors to develop referencedesigns for accelerating its cus-tomers’ product and system time to market.

The Spirit of PartnershipXilinx has developed a successfulformula for delivering a steadystream of innovation and technol-ogy firsts to the market in its first20 years. Its partnership approachis an essential element of that for-mula, and although no oneintends to alter the basic strategy,the technology industry mandatesthat change is a constant.

“Xilinx is in a much differ-ent position as a company nowthan when we first started 20years ago,” Roelandts says.“Resource-wise we could con-sider doing more things our-selves. But we know that thekey to our success has been ourfocus. That has enabled ourinnovation, which is why we area leader. In that respect, part-

nerships make even more sense, especiallyas the world gets more complicated. Ourchallenge is to continue to develop theright set of relationships with companiesthat share our vision and make sure we all

derive a benefit. We will not waver on thebasic principles that guide our partner-ship strategy, but we will keep the processdynamic to address new market needsand conditions.”

So don’t expect to see Xilinx buildingits own fab in the next 20 years. Butthanks to is unique Spirit of Partnership,it’s a safe bet that Xilinx and its partnerswill continue to set the standard for inno-vation and best business practices in thesemiconductor industry.

Xilinx has developed a successful formula for delivering a steady stream of innovation and technology firsts to

the market in its first 20 years.

by Clive “Max” MaxfieldPresidentTechBites [email protected]

When reading a technical book, you maysometimes find yourself muttering, “Ha!The author is a complete and utter idiot! I could have done a better job than that!”

Or you may be working on an interest-ing project – or have just developed a novelsolution to some problem – when you sud-denly think, “I could write a really coolbook about this!”

That initial flush of enthusiasm sooncools, however, when you start to mull overthings in a little more detail, realizing thatyou don’t actually have a clue where tostart. Is there a market for such a book?What should it cover? Who will create thegraphics? How will you find a publisher foryour masterpiece?

Given these imponderables, it usuallydoesn’t take long before you’ve talked your-self out of becoming an author. This isunfortunate, because there may be a lot ofpotential readers out there who could real-ly benefit from your expertise. And ofcourse, being known as an author can onlyenhance your career prospects and makeyour family and friends very proud.

Turn your terrific idea into a technical tome through the Xcell Publishing Alliance.

Author! Author!


To assist authors-to-be (like yourself?),Xilinx® has created an innovative new pro-gram called the Xcell Publishing Alliance.The program is designed to help you takeyour magnum opus from initial concept,through planning and implementation, allthe way to publication, fame, and glory.

In fact, as I pen these words, I’m bask-ing in the glow of having just received theauthor copies of my latest book, “TheDesign Warrior’s Guide to FPGAs:Devices, Tools, and Flows.” This book wasmade possible in large part by Xilinx andMentor Graphics®, both of whom provid-ed me with access to a wide variety ofexperts and information sources. Thus, inthis article I thought I’d walk you throughthe process of creating a book – using “TheDesign Warrior’s Guide” as an example –and then discuss what Xilinx can do to helpyou create your very own tour de force.

Topical QuestionsThe very first thing you have to decide onis a topic. What exactly would you like towrite about? There’s little point in spendingvast amounts of precious time and effortcreating a book that no one actually wantsto read.

I’ve been fortunate in this regard,because I’ve tended to write books on top-ics that interest me and that I would liketo read myself. Happily, the folks whoread my books seem to enjoy them also.For example, my very first effort – “Bebopto the Boolean Boogie: AnUnconventional Guide to Electronics” –was recently re-released in its second edi-tion due to popular demand.

Looking back, I realized that most ofmy tomes were introductory in nature, sothe time seemed right to focus on a partic-ular topic in more depth. FPGAs havebecome phenomenally powerful andsophisticated in recent years. Today’s

I felt that this background informationwould be useful to less-technical readers,while techno-weenies could leap directlyinto the more challenging middle sectionof the book. Among many other topics,this section takes an in-depth look at:

• FPGA versus ASIC design styles

• Schematic-based design flows (yes, theyare still used to support legacy designs)

• HDL-based design flows

• Silicon virtual prototyping for FPGAs

• C/C++-based design flows

• DSP-based design flows

• Embedded processor-based design flows

• Modular and incremental design

• High-speed design

• Migrating ASIC designs to FPGAs,and vice versa

One thing I recall from my collegedays is that despite having scores of text-books, I was unable to find the fact I waslooking for in any of them. For this rea-son, “The Design Warrior’s Guide”includes a third section boasting a host ofperipheral topics, including:

• Choosing the right device

• Gigabit serial interfaces

• Reconfigurable computing

• Field programmable node arrays(FPNAs)

• Independent design tools

• Creating a design flow based on open-source tools

Just looking at the above lists makes myeyes water, because I well remember theresearch and effort that went into fleshing

FPGA devices can be used to implementextremely large and complex functionsthat previously could be realized onlyusing ASICs, and thus an increasing num-ber of design engineers are starting to usethe little rascals. When I began to lookaround, however, there seemed to be adearth of useful material in this arena.

Readership to ShoreOnce you’ve decided on your topic, youwill have to flesh it out into an outline, andeventually grow it into a full-blown pro-posed contents list. An integral part of thisprocess is to decide who your audience is,because the type of information you willcover will typically vary depending onwhether you are talking to engineeringgurus or novices.

I personally dislike reading books thattalk down to me as though I am the villageidiot. But equally, I’m less than enamoredby books that try to impress me with theauthor’s brilliance, or those that require meto return to college just to wend my wearyway through the first chapter.

In the case of “The Design Warrior’sGuide to FPGAs,” I wanted to address theneeds of an unusually wide audience,including students, sales and marketingprofessionals in the EDA arena, and full-blown engineers. For this reason, I devotedthe first section of the book to fundamen-tal concepts such as:

• What are FPGAs and why are they ofinterest?

• Underlying technologies, such as anti-fuses, flash memory, and SRAM cells

• Alternative architectures and concepts

• Different programming techniques

• Who are the various players in the FPGA space?


The Xcell Publishing Alliance is designed to help you take your magnum opus from initial concept, through planning and

implementation, all the way to publication, fame, and glory.

out these topics when I finally got aroundto writing the book.

In StyleYet another point to ponder before you leapinto the fray is the style you intend to use.To a large extent this will be determined byyour target audience, but it will also bestrongly influenced by your personality.

I soon become disgruntled when read-ing boring books. Unfortunately, thisseems to cover the vast majority of techni-cal books out there (although there are afew notable exceptions). It’s almost asthough someone sent out a memo saying,“Whatever you do, don’t make engineeringbooks interesting – otherwise all sorts offolks might decide to read them.”

Fortunately, I didn’t receive this memo,so I don’t feel bound to follow it. As a sim-ple rule of thumb, I tend to write the sortof book that I personally would like toread. Thus, I use a somewhat informal,chatty style – much like this article – and Ialso like to include nuggets of trivia andtidbits of information, such as “Where didthis come from?” or “Why do we do thingsthis way rather than that?”

Furthermore, in my later books I’vestarted to include little pronunciationnotes as sidebar items for technicalacronyms and terms. I do this because ifyou mispronounce a word when talking tosomeone in the industry, you immediatelybrand yourself as an outsider. Some engi-neers have been known to scoff at me forthis, but I’ve received many e-mails fromless-technical readers that say, “Only theother day you saved me from a potentiallyembarrassing situation.”

Yes, There’s MoreAt some stage, of course, you are going tohave to actually put pen to paper (or fingersto keyboard). Writing a book-length proj-ect isn’t easy. You may start off full of vimand enthusiasm, but as you approach themiddle of the project things seem to slowdown and become increasingly difficult –much like wading through molasses. Andthen, suddenly, you’ll find that you’ve crest-ed the brow of the hill and are racing downthe other side towards the finish line.

Another consideration is creatinggraphics. I personally go by the adage that“a picture is worth a thousand words,” so

I festoon my writings with graphics wherev-er I can. For technical books and whitepapers, I tend to use line art created inMicrosoft™ Visio™, an incredibly usefuland easy-to-use tool. As an example, consid-er a sample illustration from “The DesignWarrior’s Guide” (Figure 1), which reflects asimple multiplexer-based FPGA architec-ture. Logic gates are not usually shown withgray fills and shadows, but I think it looksmore interesting – and it’s my book.

Another consideration is finding some-one to help you proofread and copyedityour work and to offer suggestions as topresentation and style. Although many edi-tors can discourse for hours on the manyand varied uses of the apostrophe, theloathsome split infinitive, and parallel sen-tence structure, actually finding one whohas a clue what you are talking about tech-nology-wise can be somewhat taxing.

And last, but certainly not least, onceyou’ve finally finished, you will need tofind a publisher who can take your master-piece, lay it out, print it, distribute it, andpromote it far and wide.

The Xcell Publishing AllianceAll of the above may seem a little over-whelming at first, but things aren’t asdaunting as they appear. The idea behindthe Xcell Publishing Alliance is to helpfolks write books on FPGA-related topics,where said “folks” may range from individ-ual engineers to small engineering housesto large Xilinx partner companies.

One key point to note is that it is not thepurpose of the Xcell Publishing Allianceprogram to flood the market with Xilinx-centric books. The guys and gals at Xilinxaren’t stupid, and they know that the lastthing engineers need is for technical booksto mutate into marketing brochures halfwaythrough. The only criteria are for the booksto address FPGA-related issues and to begenerally useful to a wide audience.

How can Xilinx help you create thebook of your dreams? Well, in the case ofpartner companies, Xilinx can put you intouch with authors (like me) who can writethe book on your behalf; they can help youdecide on the contents; and they can facil-itate your relationship with a publisher.


Figure 1 – An example figure created in Visio.

For individual authors or small engi-neering houses who wish to write and pub-lish a book, the Xcell Publishing Alliancecan help in the following ways:

• Consulting with you on the topic, out-line, and eventual contents list

• Providing access to the appropriate tech-nical and marketing employees, both atXilinx and their partner companies

• Facilitating access to industry insiderssuch as technical experts, editors, andanalysts

• Helping to create any figures, dia-grams, and cover art

• Proofreading and copyediting your man-uscript (or finding someone who can)

• Providing access to a publishing house

• Helping you market, promote, andpublicize your book

Xilinx has recently committed to apartnership with Elsevier, whom I’minformed is the largest English languagepublisher in the world.

And as for to helping you market, pro-mote, and publicize your book, Xilinx canbe a powerhouse working on your behalf.For example, in addition to their insidecontacts at the various industry magazines,soon after your book rolls off the printingpresses, you could pen an article on it forthe Xcell Journal.

After all, since it is published quarterlyin five languages, distributed in 114 coun-tries, and directly targeted to more than50,000 programmable digital designusers, the Xcell Journal can carry a hugeamount of weight. And let’s not forget theadvantages of any publicity for yourselfand your company (see the info blurb onmy company, for example).

ConclusionWriting a book is much harder than mostpeople imagine, and there will be momentsthat you rue the day you ever had the ideafor such a project. It’s also true that thechances of ever getting rich from a techni-cal book are laughably slight.

On the bright side, however, the feelingyou get when holding the first copy of yourbaby when it comes back from the publish-er is absolutely fantastic. Be prepared torun around with a silly “aw shucks” grin onyour face. And don’t discount the fact thathaving a book in print is a wonderful wayto market yourself, open doors, reinforceyour career, and enhance your futureemployment prospects.

Embarking on a project like this is amajor task, but the chances of your suc-cess will be far greater if you have thesupport of the Xcell Publishing Alliance.For more information about this excitingnew program, please send an e-mail [email protected].

R

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Clive “Max” Maxfield is president of TechBites Interactive Inc.(www.techbites.com). A marketing consultancy, TechBites specializesin servicing high-technology companies, ranging from small “ Fred-in-a-shed” startups all the way to the “big boys” in EDA.

The services provided by TechBites include logo creation, corporate/product branding, marketing plans, web design anddevelopment, collateral design and production, technical and creative writing, technical translation, and digitizing.


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New Edition

by Jim CairnsDirector of Corporate Solutions MarketingXilinx, [email protected]

Making your products and subsystemscompetitive in performance, features, andcost requires constant awareness of newleading-edge programmable technologies.Making your designing as productive aspossible requires steady learning of leadingapplication solutions, tools, and techniques.

Beginning this October (see Table 1),Programmable World 2004 brings togetherthousands of engineers and system architectsfor an action-packed day of learning andnetworking around the most exciting newprogrammable technology in the world: theVirtex-4™ solution from Xilinx®.

Last year’s Programmable World 2003workshops packed new technical contentfrom the vast Xilinx partner ecosystem andits leading expert users into a highly pro-ductive day-long training event in 20 citiesaround the world. Xilinx and fellow indus-try leaders such as Agilent™, IBM™,Intel™, The MathWorks, MentorGraphics®, Texas Instruments™, andWind River™ led engineers throughworkshop tracks covering DSP, embeddedprocessing, high-speed connectivity, andsystem logic design.

Workshop attendees received a 556-pageworkbook filled with direction on key solu-tions to the most pressing design and verifi-cation issues facing hardware engineers,ASIC designers, system engineers andarchitects, and embedded software develop-ers in getting products to market quicklyand competitively.

At Programmable World 2004, Xilinx andits partners will showcase the new Virtex-4solution in each of four digital “domains” –DSP, processor, connectivity, and logic – witha full-day track dedicated to each.

Experience Programmable World 2004

Experience Programmable World 2004


Xilinx and fellow technology leaders offer one-day workshops to showcase the “state-of-the-art” in programmable digital design.

Xilinx and fellow technology leaders offer one-day workshops to showcase the “state-of-the-art” in programmable digital design.

DSP TrackLearn about the amazing price reductions,power improvements, and performanceacceleration that Virtex-4 solutions willbring to your video and digital communi-cations applications and algorithms. Seethe latest enhancements to the industry’seasiest end-to-end tool flow for designing,verifying, and debugging, from designentry in MathWorks tools to real-timeXilinx hardware in-the-loop.

This track will include reference designsand other real-life examples to help you getthe most out of your communications andvideo designs.

Connectivity TrackPreview the newest high-speed serial technol-ogy that enables data rates as high as 11 Gbpswith impeccable signal integrity chip-to-chip, across backplanes and even box-to-box.Share techniques for minimizing error rates,board cost, and system cost for your connec-tivity applications. Anticipate and under-stand potential signal integrity issues early inyour design cycle and apply the latest stream-lined methodologies to proactively preventsignal integrity issues.

This track will cover the use of XilinxRocketIO™ models in high-speed PCBsimulations as well as analyzing and sim-ulating GHz signal paths for via- and surface-mounted components in PCBdesign. You’ll see how signal integrityanalysis is used to reduce overshoot, ring-ing, cross talk, timing margins, inter-symbol interference, and radiatedemissions. Instructors will showHSPICE™ correlation, eye diagrams,signal pre-emphasis, and S-parameterconnector models using simulation tools.You’ll also work on predicting perform-ance using a combination of electromag-netic field simulation and circuit andsystem simulation, and on optimizationof interconnect and transitions used forhigh-performance PCB designs.

Processor TrackWalk through the comprehensive Virtex-4embedded processing solution, from thePicoBlaze™ 8-bit microcontroller refer-ence design, 32-bit MicroBlaze™ soft

“Ask the Experts” opportunities bring youtogether with leading technologists fromXilinx to discuss how their products, servic-es, and applications support can address yourspecific architecture and engineering chal-lenges. Interactive networking sessions willallow you to share best practices and trendswith other engineers and architects.

Conclusion Programmable World 2004 packs hundreds of new programmable digitalinnovations and techniques into a singleday of intense learning that you will notwant to miss. For more information, or toregister for the Programmable Worldworkshop in a location near you, visitwww.xilinx.com/pw2004/.

processor implementation, the enhanced on-chip PowerPC™ processor, and theUltraController solution that uses theembedded PowerPC. Delve into design toolsfrom Wind River, MontaVista Software™,and Mentor Graphics/ATI and learn aboutthe latest Virtex-4 RTOS support.

Mix and match the latest combinations of:

• Virtex-4 silicon architecture

• 32-bit RISC processor cores and periph-erals

• Third-party RTOS support

• Intelligent design tools

• Integrated hardware/software debug plat-forms

• Development boards

• Reference designs

• Board support packages

• Design services

• Technical support from Xilinx andindustry-leading partners

See how the newest Xilinx EmbeddedDevelopment Kit with the Platform StudioIDE automates and accelerates the develop-ment process, allowing hardware and soft-ware designers alike to design, debug, andboot a processor platform easily in time-frames never before possible.

Logic TrackSee how the latest design and debug toolsfrom Xilinx, Synplicity™, MentorGraphics, and Agilent help leverage theblazing fast Virtex-4 logic fabric and fea-tures. Learn the latest design techniques forthe fastest performance, shortest designtimes, and lowest project costs. Workthrough FPGA physical synthesis for high-est quality of results; high-speed memoryinterface design using real-time debug toslash verification times; and bench-top test-ing to verify signals in real time.

You’ll experience much beyond the inten-sive workshop sessions at ProgrammableWorld 2004. Technical demos will show howVirtex-4 solutions and partner offerings canhelp you solve real-world engineering prob-lems faster and easier.


Programmable World 2004 Dates and Locations

October 2004 Paris, France

Munich, Germany Milan, Italy

Stockholm, Sweden San Diego, California San Jose, California

November 2004 Raleigh, North Carolina

Dallas, Texas Boston, Massachusetts Baltimore, Maryland

Orlando, Florida Chicago, Illinois

Ottawa, Ontario, Canada Shanghai, China Shenzhen, China Hsinchu, Taiwan

Seoul, Korea Yokohama, Japan

Osaka, Japan

December 2004 Tel Aviv, Israel

Table 1 – Programmable World 2004 schedule

by Philippe ButelASIC/FPGA Design Section HeadMBDA [email protected]

Gerard HabayTechnical Manager [email protected]

Alain RachetSenior ASIC/FPGA DesignerMBDA [email protected]

This article reports the work currentlybeing done in the European Union (EU)R&D project “Design Methodology and Environment for DynamicRECONFigurable FPGA,” whose shortname is RECONF2 (see www.cordis.lu/en/home.htm for more details on EU-fundedresearch projects). Targeting designers, thisproject aims to ease the access to changingthe configuration of part of an FPGA designwhile the circuit is running. Xilinx® alreadyoffers this technology, but the lack of a sim-ple methodology and appropriate tools is amajor limitation to its implementation.

Therefore, the partners of this project(both academic and industrial) defined acomplete and validated methodology, alongwith the required front-end tools, address-ing the complete design flow: dynamic par-titioning, control of the dynamic behavior,and dynamic verifications. Tools coveringall of the specifics related to dynamic recon-figuration are fully compatible with thestandard design flow (a clear request fromour industrial partners). Also, neither themethodology nor the tools are dedicated toa particular application domain and arethus suitable for any embedded application,especially real-time ones.

Many advantages exist in using thistechnique, including the ability to changethe behavior of a system while it still run-ning to adapt it to an externally changingenvironment.

In this article, two of the project part-ners – MBDA France and Deltatec – willdemonstrate these benefits through a shortpresentation of the methodological flow, aswell as citing one example.

Adapted methodology and tools available from RECONF2 make partial dynamic reconfiguration in Xilinx devices a reality.Adapted methodology and tools available from RECONF2 make partial dynamic reconfiguration in Xilinx devices a reality.

Managing Partial Dynamic Reconfiguration in Virtex-II Pro FPGAs

Managing Partial Dynamic Reconfiguration in Virtex-II Pro FPGAs


Adapted Design FlowThe goal of the RECONF2 project is tobuild a set of partial bitstreams represent-ing different features, so as to partiallyreconfigure the FPGA with those bit-streams when needed under the control ofthe FPGA itself or through the use of anexternal controller. To reduce the difficul-ty in managing such a dynamically recon-figured application and to provide areliable implementation, the academicpartners developed a set of tools and associated methodologies addressing thefollowing issues:

• Automatic or manual partitioning of aconventional design

• Specification of the dynamic constraints

• Verification of the dynamic implemen-tation through dynamic simulations atmajor steps of the design flow

• Automatic generation of the configura-tion controller core for VHDL or Cimplementation

• Dynamic floorplanning managementand guidelines for modular back-endimplementation

The resulting adapted design flowshown in Figure 1 is based on both stan-dard and RECONF2-specific CAD tools.The input of the design flow is a conven-tional VHDL static description of theapplication. You can also provide multipledescriptions of a given VHDL entity toenable dynamic switching between twoarchitectures sharing the same interfacesand area on the FPGA.

We have enriched the “classical” designflow with three major steps: partitioning ofthe design code, verification of the dynam-ic behavior, and generation of the configu-ration controller.

Partitioning the ApplicationBased on the knowledge of the design archi-tecture and the use of each sub-module intime, you can indicate which part of thefeature to dynamically load, and underwhich conditions. You can also specify datamanagement constraints to retain someinternal states of the application after

(in terms of content) and the associat-ed constraints for loading and unload-ing them. You can also specify dynamicrelations between two dynamic mod-ules, making them share the same areaof the FPGA or by declaring themmutually exclusive in time.

• A VHDL entity and architecture setcorresponding to the static part of thefinal implementation. This partincludes all primary design instanceson which no dynamic constraints havebeen applied. These instances willremain permanently inside the FPGA.

unloading and reloading the correspondingdynamic module.

By identifying portions of the design inthe code at instance level, VHDL process,or VHDL assignment, you can make thedynamic specification flexible and inde-pendent of the application coding style.The outputs of this partitioning task are:

• A VHDL entity and architecture setcorresponding to an identified dynam-ic module and containing the relevantHDL code.

• A dynamic constraint file (.dcf ) thatcontains the definition of each module


HDL Input Parser

ConstraintsEditor/ManualPartitioning

HDLSimulator

ConfigurationControl

GeneratorHDLSynthesizer

HDL Files(Static Part +

Dynamic Modules)

VHDL PostProcessing Tool

DCF File

System Scheduler

AutomaticPartitioning

Constraints(DCF file)

Placement

Routing

Input Files RECONF Tools Standard Tools

Static DesignEntry

Partitioning Tool

Static Verification

Dynamic Behavorial Verification

Dynamic Structural Verification

Dynamic Behavorial Back-Annotated Verification(Exact Bitstream Length)

Dynamic Post Layout Back-Annotated Verification

Configuration Controller Generator

SynthesisPost-Processing

Tool

Synthesis

Back-End

Figure 1 – Adapted design flow

Figure 2 – Dynamic verification flow

Verifying the Dynamic ImplementationImplementing such dynamic reconfigura-tion mechanisms must be checked – andwith standard simulation tools. To be ableto do so, we had to adapt the classical veri-fication flow to verify the dynamic behav-ior of the design and the coherence ofdynamic constraints applied to and the useof the design during simulation (Figure 2).As a result, you can perform this dynamicverification with behavioral, post-synthesis,or post-layout VHDL netlists.

Simply enter a partitioned database tothe post-processing tool, which generatesan equivalent VHDL description of thedynamic design that you can simulateunder standard static VHDL simulators.The unloading of each dynamic module ismodeled by a wrapper that isolates theinputs and outputs of each dynamic mod-ule from the rest of the design according torelevant dynamic constraints (Figure 3).When a dynamic module is not presentinside the device, its outputs generate “X”or “Z” states to the rest of the design.

The post-processing tool also automati-cally generates two VHDL configurationcontroller cores:

• The functional configuration controller(FCC) is used during dynamic behav-ioral simulation. The FCC controlsisolation switches by detecting eventsinside the application, according to the.dcf constraints. To assist with the veri-fication process, the FCC can also issuedifferent warnings each time a dynamicmodule is requested in violation ofexclusivity rules defined in the .dcf.

• The physical configuration controller(PCC) is a synthesizable version of theFCC and is mapped as a static part ofthe FPGA. As with the FCC, it detectsthe loading and unloading conditionsaccording to the .dcf and manages thedynamic reconfiguration of the FPGAby reading bistreams in storage memo-ries and rewriting the FPGA’s configura-tion. The PCC also provides an interfaceto monitor the reconfiguration processfor hardware debugging purposes.

For dynamic behavioral verification,you can enter an estimation of the bit-stream lengths into the post-processingtool to take into account reconfigurationdelays. After layout, you can replace themwith accurate ones, while a back-annotat-ed VHDL netlist can replace the VHDL-partitioned code to obtain accurate vitalverifications.

Placement and RoutingYou would synthesize the static part of thedesign and the VHDL code of eachdynamic module separately to obtain sepa-rate electronic design interchange format(EDIF) netlists. You can then use theXilinx modular back-end flow to place androute each module and to generate theassociated bitstream, resulting in a typicalfloor plan (shown in Figure 4).

In the scope of the RECONF2 project,the industrial partners extensively testedthese tools and methodologies throughvarious applications, including video pro-cessing, complex state machines, automat-ically adaptive portable equipment, andfault-tolerant aerospace applications.

An Implementation ExampleFigure 5 shows a complete video effectsconsole architecture using two effects gen-erators (A and B); their outputs feed a tran-sition mixer. Channel A feeds the liveoutput while the operator sets up the sec-ond (Channel B) for a new effect, visiblethrough the preview output.

When ready, the operator selects a tran-sition scheme such as “wipe” or “fade” andswaps the live and preview outputs (typical-ly using a T-bar). Effects generators selecttheir inputs from several external videosources or feedback channels implementedin an SDRAM-based frame store.

The challenging part of this application isthe building of a RECONF2-based imple-mentation with uninterrupted outputs.


Switchxz

Switchxz

Switchxz

Switchxz

Switchxz

SwitchxzD_module1

D_module3

Signal Events

Clock

D_module2

Configuration Controller(FCC)

ReconfigurationInterface

Static

Unused Resources D_FPGA

D_MODULE 2

D_MODULE 1

ConfigurationController

Data StorageLogic

InterrfaceLogic

Figure 3 – Switch insertion for dynamic simulation

Figure 4 -Typical layout

We designed a dedicated hardwaredevelopment platform based on a Virtex-II™ XC2V3000 device with a 64-bit PCIadapter board (see Figure 6), taking intoaccount the specific constraints of theXilinx partial reconfiguration design flowand providing the required flexibility for anevaluation environment.

Dynamic Architecture of the DesignBased on Figure 5, we partitioned thedesign into three processing modules (shar-ing the same footprint), applied in

sequence to every field/frame. Each effectsgenerator also supports a collection ofeffects, possibly changing from frame toframe, implemented as separate exclusivemodules.

1. Compute effects A output

2. Compute effects B output

3. Compute mixer output

This implies saving intermediate andfinal results, while reconfiguring the mod-ule for the next operation. An SDRAM

memory pool provides this buffering capa-bility. Also, the processing must run atthree times the video speed so that totalprocessing time remains unchanged.

In a reconfigurable design, there isalways a trade-off between the processingtime and reconfiguration time of a dynam-ic module. This means that one dynamicmodule must process a “significantamount” of data before being replaced tomeet the real-time constraints.

In our real-time video application, acommon data unit is one field/frame to beprocessed in 20/40 ms – compared withthe ~25 ms needed to configure the fullXC2V3000 device via its Select Map inter-face.

Figure 8 shows the architecture used fordynamically reconfigurable processing,while Figure 7 shows the correspondinglayout. We instantiated field buffers on theinput and output side. Although the SDIinput/output pixel rate is 13.5 MHz, pixelprocessing can run much faster, at 50MHz, for instance.

Figure 9 shows typical phase alternatingline (PAL)-interlaced video timing.Without buffering, dynamic modulereconfiguration must occur within theblanking interval (1.57 ms), while process-ing (at 13.5 MHz) fills the entire activevideo interval (18.43 ms).

With the field buffers and 50 MHz pro-


Video EffectsGenerator A

OutputTransition Mixer

PreviewSelector

InputSelector

Constant

FX-A

Feedback Channel(s)

FrameStore

(SDRAM)

Video EffectsGenerator B

Host Controller

Video in 1

Video in 2

Video in 3

Video in 4

FX-A Live Output

Preview

Key

FX-B

FX-B

Figure 5 – Video effects console

Figure 6 – Hardware development platform

cessing, we obtain timing (as in Figure 9B)with 16 ms allocated to reconfigurationand 4 ms for video processing. Two pro-cessing steps can be interleaved (as inFigure 9C): 6 ms remain available fordynamic module reconfiguration.

Applying the same reasoning to framebuffering (2 fields –> 40 ms), we double theavailable time for reconfiguration (as inFigure 9D).

The RECONF2 tools and flow willhelp investigate these trade-offs.

Figure 10 shows the manual partition-ing tool GUI, with the input VHDLdesign in the left window. The partitioneddesign appears in the right window. A sim-ple drag-and-drop assigns chunks of logic

to one particular module. Scheduling con-straints (load/unload and frame) are thenentered for each module.

Our design lends itself by nature tomanual partitioning: one particular effect isalways applied to a full video field/frame.Each effect is implemented as an inde-pendent dynamic module.

The configuration controller generatoranalyzes the partitioned design and its con-straint file to produce:

• An FCC for simulation purposes

• A PCC for implementation in hardware(VDHL code) or software (C code)

To evaluate as many features of the tools

as possible, we chose to support both con-figuration controller schemes and testedthem on our hardware development plat-form. Nonetheless, our preferred solutionwas a software configuration under thecontrol of an on-board DSP because ofcritical real-time issues; we optimized theplatform accordingly.

The Xilinx Partial ReconfigurationDesign Flow, based on the modular designavailable within ISE 6.2 software, is used toproduce one global bitstream for startupand several partial bitstreams for the differ-ent dynamic modules. See Xilinx applica-tion note XAPP290 for a detaileddescription of this flow.

One benefit of the RECONF2approach for this video console applicationis obvious: we can add as many new videoeffects (such as video enhancement filters),fitting in the reserved dynamic modulespace without the need for additionalFPGA resources. This effectively increasesthe “functional density” of the FPGA.

A further increase comes from executingseveral processing steps (effects A, B, andtransition) within a single video field/frameduration, as previously explained. This isvery similar to the traditional “parallel vs.serial” arithmetic trade-off, and makes agreat deal of sense given the extraordinaryprogression of FPGA performance over thelast several years.

One less obvious advantage existsthanks to this partitioned approach: simul-taneously supporting all of the functionsresults in unneeded complexity that mayadversely impact the design’s performance.The operating model is also more complexfor the control application. Smaller, dedi-cated modules will run faster and need lessoperating parameters, making them moremanageable objects.

In the example presented, we see thereconfiguration time as a clear limitation.This time is directly linked to the dynamicmodule size and to other FPGA parameters.We are currently trying to implement adynamic module “caching”: two dynamicmodules slots are reserved, and one moduleis reloaded while the other is processing, andvice versa. Reconfiguration time is com-pletely “hidden,” at the cost of FPGA space.

VP5 (24)

XC2V3000 : 484 IOS

LEFT STATIC PORT RIGHT STATIC PORT

SD

RA

MB

ank

0 (5

0)

Spare

Spare

SD

RA

MB

ank

1 (5

0)

VP0 (24)

VP1 (24)

VP2 (24)

VP3 (24)

VP6 (24)

Local BusInterface (60)

EMIF BInterface (60*)

16 B

RA

M

16 B

RA

M

16 B

RA

M

16 B

RA

M

16 B

RA

M

16 B

RA

M

DY

NA

MIC

MO

DU

LE

(S) A

RE

A

SDIVIDEO IN 2

SDIVIDEO IN 1

VIDEO IN 1Odd Field

Buffer

VIDEO IN 2Odd Field

Buffer

VIDEO IN 1Even Field

Buffer

VIDEO IN 2Even Field

Buffer

13.5 Mps 13.5 Mps50 MpsSDRAM-Based Input

Field BuffersSDRAM-Based Output

Field Buffers

DynamicProcessing

Module

VIDEO OUT 1Odd Field

Buffer

VIDEO OUT 2Odd Field

Buffer

VIDEO OUT 1Even Field

Buffer

SDI VIDEOOUTPUT

VIDEO OUT 2Even Field

Buffer

Host PCPreview Pane

(DMA)

Figure 7 – XC2V3000 layout with VP 0.3 as generic video input ports, VP 5 and 6 as generic video output ports

Figure 8 – Field double buffering


ConclusionMost of the specific tasks required by par-tial dynamic reconfiguration are handledby a complete methodology and associat-ed tools. These have been designed to befully compatible with the ones used forclassic Xilinx FPGA implementation.Furthermore, our approach is usable withany technology compatible with dynamicre-configuration.

The academic partners developed themethod and tools according to specifica-tions that take into account industrial con-straints, such as:

• Compatibility with standard tools suchas simulators and synthesizers

• Usability with any technology compat-ible with dynamic re-configuration, inparticular with Xilinx technology andback-end tools

The academic partners have made thetools and methods available to the industri-al partners, who are currently testing themfor complex circuit design, thus ensuringease of use and efficiency.

MBDA France will then be able to takefull advantage of this technology in deeply

embedded on-board computers, characterizedby small volumes and low power dissipation.

Deltatec develops digital imaging prod-ucts for multimedia, industrial/medical,and professional broadcast markets.Upcoming video applications will requiremore and more versatility. High-definitiontelevision (HDTV) applications must tack-le multiple formats (resolution, frame rate,interlaced/progressive scan) as well as con-verge with the computer graphics world.Simultaneous support for all existing for-mats/functions may rapidly become anightmare and even hamper feasibilitybecause of cost or performance issues (forexample, an HDTV pixel rate of 75 MHz,almost a six-fold increase over standard dig-ital television [SDTV]).

The RECONF2 tools and methodolo-gy circumvent these problems, as only therequired function blocks are loaded at anyparticular instant:

• FPGA size (and cost) remains acceptable,while keeping the same integration level.

• Smaller, less generic, optimized func-tion modules more easily reach per-formance goals.

At this time, the methodology andtools are accessible to our project partnersand could be extended to other third par-ties, such as tool suppliers for distributionand support in order to enable a largeraccess to this technology. For more infor-mation on the RECONF2 project, visitwww.reconf.org.

Odd field20 ms

Even field20 ms

Blanking 1.57 ms

Active video18.43 ms

Blanking 1.57 ms

Active video18.43 ms

Odd field20 ms

Even field20 ms

Reconf 16 ms

Process 4 ms

Reconf 16 ms

Process 4 ms

A. PAL Video TimingB. One Processing Step

Per FieldC. Two Processing Steps

Per Field

Odd field20 ms

Even field20 ms

Reconf 6 ms

Process 2: 4 ms

Reconf 6 ms

Process 2: 4 ms

Reconf 6 ms

Process 1: 4 ms

Reconf 6 ms

Process 1: 4 ms

D. Two Processing StepsPer Frame

Odd field20 ms

Even field20 ms

Reconf 16 ms

Process 1: 8 ms

Reconf 16 ms

Process 2: 8 ms

Frame40 ms

Figure 9 – Video frame and operations timing

Figure 10 – Manual partitioning tool


by Chang Ning SunTechnical Marketing EngineerMentor Graphics [email protected]

Embedded system developmenttraditionally requires a hardwaredesign cycle to create a prototype;a software implementation cyclecan only begin once that proto-type is available. Co-design andco-verification tools such as theSeamless™ co-verification envi-ronment (CVE) from MentorGraphics® provide great flexibilityand early system integration, butthese tools have mostly been usedfor large-scale systems such asASIC designs. Ordinary embed-ded system designs have not yetbenefited from hardware/softwareco-design and co-verification.

The Nucleus real-time operating system is now available for Xilinx FPGAs with MicroBlaze and PowerPC 405 cores.The Nucleus real-time operating system is now available for Xilinx FPGAs with MicroBlaze and PowerPC 405 cores.

Nucleus for Xilinx FPGAs – A New Platform for Embedded System Design

Nucleus for Xilinx FPGAs – A New Platform for Embedded System Design


In recent years, innovations in FPGAtechnology have shifted the use of thesedevices from supporting logic to forminga central part of the embedded system.With their high logic density and highperformance, modern FPGAs allow youto implement almost an entire embeddedhardware system in a single FPGA device.

Xilinx® Spartan-II™, Spartan-3™,and Virtex-II™ Platform FPGAs (com-bined with the MicroBlaze™ soft proces-sor core) and Virtex-II Pro™ PlatformFPGAs (combined with the PowerPC™405 hard processor core) offer new hard-ware platforms and facilitate new method-ologies in embedded system design.

The Nucleus™ real-time operatingsystem (RTOS) from AcceleratedTechnology (Mentor Graphics’ EmbeddedSystems Division) fully supports XilinxPlatform FPGAs. Together with ourFPGA design flow and Seamless CVEtools, the Nucleus RTOS is a complete hard-ware/software co-design and co-verificationenvironment.

The Nucleus RTOSVery few embedded software developersstart their development on bare hardware;most choose a commercial embeddedRTOS like Nucleus as the base environ-ment and develop their applications on topof the operating system.

Generally, an RTOS provides a multi-tasking kernel and middleware compo-nents such as a TCP/IP stack, file system,or USB stack. Application developersbuild their application software by usingthe system services provided by the RTOSkernel and the middleware components. Anumber of commercial RTOSs are avail-able: some have hard real-time kernels,some have extensive middleware support,and some have good development tools.The Nucleus RTOS has all of these fea-tures from a single vendor.

Figure 1 shows the Nucleus systemarchitecture.

Nucleus PLUSNucleus PLUS, a fully preemptive and scala-ble kernel suitable for hard real-time applica-tions, is designed specifically for embedded

more difficult. These standards are oftenimplemented as middleware componentsand provided together with the RTOS.

The Nucleus RTOS has an extensivelibrary of middleware support (Table 1),which covers every vertical market of theembedded industry. Nucleus NET utilizesa zero-copy mechanism for transferringdata between user memory space and theTCP/IP stack, which significantlyimproves data transmission efficiency andreduces dynamic memory allocation.

Nucleus software fully supports thePOSIX standard for software portability.POSIX interface libraries are available forall Nucleus middleware components.

Nucleus Device DriversThe Nucleus RTOS has an extensive list ofoff-the-shelf device drivers. When you selecta new hardware IP or peripheral to use inyour design, the driver source code mayalready be available. If not, a driver templatelets you easily develop a functional driver.

systems. It has a very small footprint; the ker-nel itself can be as small as 15-20 kB.

All Nucleus kernel functions are provid-ed as libraries, so only the required kernelfunctionality is linked with the applicationcode in the final image. Nucleus PLUSprovides complete multi-tasking kernelfunctions, including task management,inter-task communication, inter-task syn-chronization, memory management(MMU), and timer management. Recently,we added a dynamic download library(DDL) into Nucleus PLUS to allowdynamic downloading and allocation ofsystem modules.

Nucleus MiddlewareThe middleware available for an RTOS hasbecome an important factor when selectinga commercial RTOS for a particular applica-tion. As embedded applications becomeincreasingly more complicated, applicationdevelopers find implementing industry stan-dards like TCP/IP, WiFi, USB, and MPEG


(written in C, C++, POSIX or Java™)

Figure 1 - Nucleus system architecture

Mentor Graphics will continue to adddevice drivers to the Nucleus library fornew hardware IP blocks for Xilinx FPGAsas well as for third parties, such as its ownIP Division.

Nucleus Development ToolsThe Nucleus RTOS has the most inte-grated development environment (IDE)in the industry. Combined with ourMicrotec compiler tools, the code|labembedded development environment(EDE) and XRAY debuggers provide acomplete software design flow, fromcompilation to debugging.

Our C/C++ source-level debuggerssupport both run-mode and freeze modedebugging with complete Nucleus kernelawareness. The XRAY debugger supportsboth homogeneous and heterogeneousmulti-core debugging, and a wide range ofprocessors and DSPs.

In addition to the Microtec compil-ers, the EDE, IDE, and debuggers arealso integrated with many third-party

compiler tools such as GNU. For system-on-chip (SoC) users, inte-

gration of the Nucleus RTOS and XRAYdebugger with other products in theMentor Graphics lineup (such as SeamlessCVE for hardware/software co-verifica-tion) offer a complete hardware/softwareco-design and co-verification platform.

Royalty-Free with Source CodeThe royalty-free with source code busi-ness model of the Nucleus RTOS, com-bined with the high scalability and smallfootprint architecture, provides greatvalue to customers developing large-vol-ume products such as cell phones, PDAs,and cameras. A single up-front license feecovers all production rights for a singleproduct using Nucleus software, with noadditional royalty fees and no need totrack shipment numbers.

Nucleus software has proven to be arobust RTOS and has been widely used inevery vertical market of the embeddedindustry, including consumer electronics,

telecom, defense/aerospace, automotive,and telematics.

Nucleus for Xilinx FPGAsThe scalable and configurable nature ofNucleus products, combined with the flexi-bility and versatility of FPGAs, providesgreat potential for hardware/software co-design, co-verification, and early integra-tion of your software and hardware projects.

Nucleus for MicroBlazeThe MicroBlaze soft processor core featuresa Harvard-style RISC architecture with 32-bit instruction and data buses. AMicroBlaze soft core can be programmedinto Spartan-II, Spartan-3, or Virtex-IIPlatform FPGAs.

Nucleus software fully supports theXilinx MicroBlaze soft processor core withGNU compiler tool and GDB debugger.

Nucleus for Virtex-II ProFPGAs/PowerPC 405

Many embedded system developers arealready familiar with the PowerPC 405processor. Xilinx Virtex-II Pro FPGAs pro-vide fully configurable hardware platformswith the PowerPC 405 hard processor core.

Nucleus software fully supportsVirtex-II Pro FPGAs with the PowerPC405 hard core, providing a MicrotecPowerPC compiler and XRAY kernel-aware debugger, as well as GNU compil-er tools and GDB debugger.

FPGA Reference Design for Nucleus SoftwareTo give embedded system developers aquick start with Nucleus software forXilinx FPGAs, we worked with Xilinx andMemec™ Insight to develop referencedesigns for running Nucleus software. Eachreference design is a sample FPGA hard-ware configuration based on a MemecInsight FPGA development board.

You can build and implement all of thereference designs into the FPGA device by


Nucleus Product Function

Nucleus NET Complete embedded TCP/IP stack

Nucleus Extended Protocols Telnet, FTP, TFTP, Embedded Shell

Nucleus SNMP version 1,2,3 Network management protocols

Nucleus RMON (1-9 groups) Network remote monitoring protocols

Nucleus Residential Gateway NET, PPP, PPPoE, DHCP server

Nucleus WebServ Embedded HTTPD web server

Nucleus EMAIL POP3 and SMTP

Nucleus FILE MS DOS compatible file system

Nucleus GRAFIX Graphics-rendering engine with windowing toolkit

Nucleus USB Complete USB stack for USB specifications 1.1, 2.0, and OTG

Nucleus 802.11 STA (WiFi) 802.11b and 802.11g protocol stack

Nucleus IPv6 IP version 6 protocol stack

CEE-J Java VM for Nucleus CLDC, MIDP, Embedded Java, and Personal Java

Nucleus software has proven to be a robust RTOS and has been widely used in every vertical market of the embedded industry...

Table 1 - Primary Nucleus middleware components

using Xilinx EDK and ISE software. Foreach reference design, we provide a LimitedVersion (LV) of our Nucleus software,including the Nucleus PLUS kernel andthe relevant middleware (such as NucleusNET) to help you evaluate Nucleus soft-ware with the FPGA.

The LV version of Nucleus softwarefunctions exactly the same as a full version,but is provided as binary only andruns for a limited time. Currently,we have FPGA reference designs forthe following Memec Insightboards:

• Spartan-IIE LC MicroBlaze development board

• Spartan-3 LC MicroBlaze development board

• Spartan-3 MB MicroBlaze development board

• Virtex-II MB MicroBlaze development board

• Virtex-II Pro PowerPC development board

We have also created a website(www.acceleratedtechnology.com/xilinx) tosupport Nucleus software for Xilinx FPGAs,where you can download FPGA referencedesigns and Nucleus software updates.

FPGA Design FlowThe FPGA reference designs for theNucleus RTOS can be used as your startingpoint to build a custom FPGA-based hard-ware platform. All of the reference designsare provided as Xilinx Platform Studio(XPS) projects, so you can directly openthese projects in XPS and edit, build, andimplement the design with Xilinx EDKand ISE software. Typically, building aNucleus system using an FPGA and con-figurable cores involves the following:

• Configuring a hardware platform withFPGA, processor core, hardware IP,and memory

• Building the design with EDK/ISE soft-ware to generate an FPGA bitstream

• Building software libraries with EDKto generate low-level device driver code

• Developing Nucleus device drivers andNucleus applications

• Programming the FPGA device

• Downloading Nucleus into the FPGAhardware board

Once you have reached this point, youcan start evaluating your Nucleus softwareand begin debugging your application.

Xilinx EDK and ISE software provide acomplete environment for configuring andimplementing an FPGA-based hardwareplatform. At the same time, EDK also gen-erates software libraries and C header filesfor the hardware design. These librariesprovide basic processor boot-up code andlow-level hardware IP device driver func-tion code. These low-level functions canbe treated as a “BIOS” layer for Nucleus.

Figure 2 shows the source code directo-ries generated by EDK in an XPS project.You will find one subdirectory for each pieceof hardware IP, such as “emac_v1_00_d” forEthernet and “uartlite_v1_00_b” for UART.Each subdirectory contains the driver codefor that hardware IP. These driver functionsare included with the hardware IP from thevendor and have been integrated into theEDK installation.

Nucleus software provides an OSadaptation layer that is an interface layerbetween the EDK-generated “BIOS”function layer and the Nucleus high-leveldevice drivers. This OS adaptation layer

serves as a hardware abstraction layer,which will significantly simplify theNucleus device driver porting overFPGA-based hardware platforms.

Nucleus Software DebuggingBoth MicroBlaze soft-core and PowerPC405 hard-core designs provide a standardJTAG debug interface. So after imple-

menting the hardware design inthe FPGA, you can take fulladvantage of our JTAG-basedcode|lab EDE or XRAY debuggerto facilitate application debug-ging. Both code|lab and XRAYhave complete Nucleus kernelawareness, which can help youanalyze complex real-time behav-iors in a multi-tasking system.

Co-Design and Co-VerificationAs we mentioned earlier, Nucleussoftware provides a viable platformfor hardware/software co-designand co-verification. As one of theonly EDA companies with anembedded software focus, MentorGraphics’ Nucleus RTOS and

XRAY debugger are fully integrated withour Seamless hardware/software co-verifi-cation software platform.

The combination of the Nucleus RTOSand Seamless co-verification tool providesyou with one of the most comprehensivehardware/software co-design and co-verifi-cation tools possible.

ConclusionEmbedded systems are becoming increasing-ly complicated. To meet the challenge, inte-grated solutions including hardware/softwareco-design and co-verification are required.FPGAs with configurable processor coresbring a new, innovative approach to mod-ern embedded system designs and open thedoor to hardware/software co-design andco-verification.

Nucleus software for FPGAs can sig-nificantly accelerate your hardware/soft-ware development cycle and improveyour hardware/software integration quali-ty. For more information, please visitwww.acceleratedtechnology.com.


Figure 2 - Xilinx EDK-generated source code directories

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X serial transceivers are implemented on the industry’s most

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library of serial IP cores and reference designs supports all major

standards. The reconfigurability of the Platform FPGA can

dynamically accommodate any spec changes. And together with

industry leading partners such as Mentor and Cadence, Xilinx

provides all the tools and training you need.

THE PROVEN SOLUTION. THE FAST TRACK TO SAVINGS.

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©2004, Xilinx, Inc. All rights reserved. The Xilinx name, the Xilinx logo are registered trademarks. RocketIO and SelectIO, Virtex-II Pro are trademarks, and The Programmable Logic Company is a service mark of Xilinx, Inc. All other

trademarks and registered trademarks are the property of their respective owners.


by Zulfiqar Ali ZamindarField Application EngineerNu Horizons Electronics [email protected]

Xilinx® FPGAs have been a great platformfor control logic and system interfaces foryears, but have been missing the processorcapabilities fulfilled by external processorsin every application. Today’s complex sys-tems require a large amount of memory, asuper fast microprocessor, a digital signalprocessor, and a variety of system interfacesto communicate with other chips, systems,and backplanes.

Every system has an external processorand memory component that delays systemperformance and increases system compo-nent cost. Once you’ve integrated both,you can then concentrate on making yoursystem faster and eliminate performancebottlenecks.

Many companies have focused theirefforts on developing the system-on-chipconcept by adding feature sets to bringadditional functionality to single silicon.These customized ASICs have become avery costly solution in today’s competitiveand time-to-market landscape.

FPGA technology has come a long wayin recent years by increasing a large numberof intellectual properties to reduce the costof silicon development in various markets.This was accomplished by optimizingarchitecture, leading process technology,and adding both soft and hard embeddedprocessor cores.

Implement an Embedded System with FPGAsImplement an Embedded System with FPGAs


Merging the processor capability onto the FPGA on board can boost system performance and lower overall system cost.Merging the processor capability onto the FPGA on board can boost system performance and lower overall system cost.

Some of the applicationsfor embedded processors areinfotainment systems inautomotives, security sys-tems in storage and network-ing markets, high-speed dataanalysis by data warehouse,and system monitoring invarious applications. Havinga processor inside an FPGAis the perfect design innova-tion for these types of appli-cations; a programmablesystem-on-chip in the FPGAwill not only support chang-ing IP standards but can alsoquickly adapt to newlydefined programmable sys-tems for new markets.

Embedded Development KitXilinx expanded the features within itsFPGAs by adding embedded IBM™PowerPC™ 405 processors in its Virtex-IIPro™ devices and MicroBlaze™ softprocessors in both the Virtex™ andSpartan™ architectures. This is just anotherstep towards innovation, similar to embed-ded block memory, block multipliers, clockmanagement, and multiple high-speed I/Ocircuitries.

Time to market still remains critical toall companies developing both hardwareand software for a system. With theEmbedded Development Kit (EDK) fromXilinx, you can simultaneously create bothhardware and software designs and gener-ate a system file with just a few tool clicks.The tool allows you to create block-basedprocessor systems with many widely usedperipherals like Ethernet MAC, GPIO,SDRAM Controller, UART, and IIC, all inone silicon.

With EDK v6.2 (Figure 1), the base sys-tem builder (BSB) wizard allows you toselect any board from Xilinx and its dis-tributors and connect the processor to anyboard component with just a few clicks. Italso creates a simple software application inC that you can expand and customize.

The EDK tool also comes with a GNU-based compiler/debugger, allowing you tocompile and debug within the same GUI

the same way that you can adduser or Xilinx IP. Once you havedownloaded the design into atarget board, you can open thelogic analyzer to trigger signalsand view the wave form todebug your systems.

With ChipScope Pro 6.2software, a powerful virtualI/O core has been added,which you can use as a DIPswitch or LED to simulate sig-nals and view outputs.

The Nu Horizons Spartan-3 BoardXilinx and its distributors haveseveral boards for prototyping oremulating a processor-based sys-tem. A low-cost and widely

adaptable prototyping platform from NuHorizons is the Spartan-3™ developmentboard (HW-AFX-SP3-400-DB).

NuHorizons recognizes the importanceof prototyping platforms for its customers,as well as entering into new markets whereSpartan-3 allows us to increase marketshare. The board (Figure 2) comprises thefollowing:

• Xilinx 3S400-4PQ208C Spartan-3device

• 4 x 24 character LCD

• LED

• Push button

• Oscillator with PLL

• RS232-C interface

• A/D and D/A converter

• Flash memory

• SDRAM memory

• JTAG configuration header for pro-gramming

• Test point headers for debuggingdevice

This fully loaded Spartan-3 develop-ment board includes all the features neces-sary to prototype a MicroBlaze-basedembedded system design. The board comeswith the Xilinx WebPACK™ version of

used to develop the hardware system. Thelibrary generator (LibGen) in EDK createsall of the libraries, drivers, executables, andlink files for the processor design.

Initial support for the board supportpackage (BSP) includes Wind RiverSystems’ vxWorks™ for PowerPC-basedembedded designs and the Xilinx micro-kernel for MicroBlaze-based designs.

EDK v6.2 has automated the memoryaddressing capabilities of all of the select-ed design peripherals. It also has thecapacity to bring developed cores into thetools environment, adding them to theprocessor or peripheral bus. For example,you can create a core in System Generatorfor DSP and bring a finite impulseresponse (FIR) filter or other IP into yourprocessor-based design.

EDK is fully capable of running ISEtools in the background with a built-in fea-ture called XFLOW, achieved by a com-mand-line script file. This flow cansynthesize, place, route, and generate hard-ware configuration files; compile and exe-cute multiple software codes; generatelibraries for code; and merge firmware tohardware files for downloading to a targetboard. All of this is achieved by just a fewclicks in the EDK software.

EDK v6.2 also allows you to addChipScope Pro™ cores during the designprocess to debug your design in hardware.You can add ICON, ILA, and IBA cores


Figure 1 – BSB flow

ISE tools, design files, user’s manual, anddocumentation. The option of getting theboard bundled with ChipScope Pro andEDK software is also available.

The Spartan-3 board comes with a simpledisplay controller design that uses theMicroBlaze core, a few GPIOs, RS232,and a JTAG interface designed in EDK.The BSB flow makes it very easy to targetthe Nu Horizons board in EDK and gen-erate an embedded design with theMicroBlaze processor in a few clicks. Withthe GNU debugger and ChipScope Prosoftware, you can debug a design withinthe same GUI environment.

Besides the MicroBlaze core, theSpartan-3 platform is a great tool in whichto implement the Xilinx PicoBlaze™ 8-bitsoft controller reference design. Nu Horizons field application engineershave written several designs coveringmemory controllers, embedded processors,hardware-in-the-loop with digital signalprocessing (DSP), and system monitordesign using analog-to-digital (ADC) anddigital-to-analog converters (DAC) on theboard. ADC and DAC are very powerfulattributes of our low-cost board, and twoof the many competitive board features.

The Nu Horizons Spartan-3 board also

supports Shift-Right Technologies’ freeopen-source eXtreme Minimal Kernel(XMK). XMK is a 100% free, preemptivemulti-threaded RTOS for microcon-trollers. XMK’s primary design goal is to beextremely small without sacrificing per-formance or functionality.

XMK’s minimal footprint makes itideal for running an 8-bit microcontroller,while its feature content makes it an excel-lent choice for 16-bit and 32-bit micro-controllers.

uIP is one of the several free TCP/IPstacks integrated into the XMK operatingsystem. The uIP TCP/IP stack makes itpossible to connect to a TCP/IP networkwithout sacrificing interoperability orRFC-standard compliance.

ConclusionThe era of creating embedded designs inFPGAs is here. With tools like EDK, any-one can implement a powerful system-on-chip design within days.

The Spartan-3 board from Nu Horizonsis a perfect solution for prototyping logicand embedded processing in Xilinx FPGAs.The board has all of the interfaces necessaryto create an embedded system design.

Nu Horizons is also in the process ofreleasing a Spartan-3 (3S1500) platformboard for those who need higher densitylogic, more memory, and a high-perform-ance interface for video and imagingapplications.

All of the designs and related documen-tation for the Spartan-3 board are availableon the Nu Horizons website atwww.nuhorizons.com/products/xilinx/spartan3/development-board.html.


ConfigurationPROMXCF02

20 UserI/O

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25 PinD-Sub

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2 Channel12-bit A/DLTC1865L

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ICL3232

32Mb FlashSTMicro

ST29W320

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LCD Display2x24 Character

4M X 16SDRAM-64Mb

ISSI

Xilinx Spartan-3XC3S400-4PQ208

Figure 2 – Spartan-3S400 board block diagram

by Shawn McCloudHigh-Level Synthesis Product ManagerMentor Graphics [email protected]

High-end electronic design flows have tradi-tionally included the creation ofVerilog™/VHDL representations by hand.These manual methods were effective in thepast, but the algorithms used in many oftoday’s new designs are so complex that tra-ditional design practices are now inadequate.

Meanwhile, FPGAs are increasinglyattractive because companies can avoidtime-consuming, exorbitant mask re-spinsand other risks associated with ASICs. Theemergence of multimillion-gate, 1,000+pin, “ASIC-like” devices incorporatingembedded processors and innovative mem-ory architectures calls for a system-levelapproach to programmable logic design.

FPGAs have already moved beyondtheir traditional applications into newdomains such as digital signal processing(DSP). Unfortunately, creating registertransfer level (RTL) implementations forhigh-end FPGAs can become as error-prone and time-consuming as when target-ing an ASIC, thereby negating much oftheir inherent value.

Using pure, untimed algorithmic C dramatically speeds implementation and increases design flexibility when compared to other C-based flows.Using pure, untimed algorithmic C dramatically speeds implementation and increases design flexibility when compared to other C-based flows.

Algorithmic C Synthesis Optimizes ESL Design Flows Algorithmic C Synthesis Optimizes ESL Design Flows


You can now prevent these problems byadopting a design flow based on the simu-lation and synthesis of C representations.By using pure untimed C++ to describefunctional intent, your design teams canmove up to a far more productive abstrac-tion level for designing hardware, thusreducing implementation efforts by asmuch as 20 times while creating a morerepeatable and reliable design flow.

An important outcome of this approachis that you can produce designs of betterquality than traditional RTL methods byidentifying fundamentally superior micro-architectural solutions.

In this article, we’ll examine the con-ventional design flow and its associatedproblems, and highlight some alternativeapproaches to hardware design based onthe use of C/C++, comparing the pros andcons of SystemC™ and the pure, untimedC++ used by Mentor Graphics®

Catapult™ C Synthesis tool.

Traditional Design Flow Many high-end designs in the communica-tions or video/image processing industriesare typically based on extremely complexalgorithms. The first step in a conventional

• RTL Area/Timing Optimization.Iterate through RTL synthesis to meetdesign goals.

In some cases, the hardware engineersmanually translate the floating-pointuntimed algorithm into bit-accurate RTL,either Verilog or VHDL. This RTL is sub-sequently synthesized into a gate-levelnetlist using traditional RTL synthesistechnology (Figure 1).

The main problems associated with thistraditional flow are:

• Functional Intent. A significant con-ceptual and representational divideexists between the system architectsworking with untimed algorithms andthe hardware designers working withthe timed RTL in VHDL/Verilog. As aresult, the original design intent speci-fied by the system architect is easilymisinterpreted, causing functionalerrors in the end product. In addition,it is relatively easy to implement andevaluate specification changes in theuntimed algorithm, but very painfuland time-consuming to subsequentlyfold these changes into the RTL. Thisis a serious consideration in wirelessapplications, because broadcast stan-dards and protocols constantly evolveand change.

• Meeting Requirements. Predictingdesign performance (area, delay,power) is difficult until RTL is done.Therefore, system-level partitioningand the resulting block-level designgoals are inaccurate at best. Many system-level timing closure problemsare directly related to poor macro-architectural choices and unrealisticgoals placed on the hardware engineerdesigning the hardware blocks.

• Design Complexity. Because theuntimed algorithmic domain and RTLdomain are dissimilar, the manualtranslation from untimed algorithms toRTL is prolonged and error-prone. Inaddition, RTL uses technology-dependent coding styles and “hard-codes” the micro-architecture.Evaluating alternative implementations

design flow involves model-ing and proving the designfunctionality at the algorith-mic level of abstraction, usingtools such as MATLAB™from The MathWorks orplain C/C++ modeling.

MATLAB is good for ini-tial algorithm proof-of-con-cept and validation, althoughmany design teams alsodevelop C/C++ models tofacilitate high-speed system-level verification beyondwhat MATLAB can provide.For subsequent discussion,we’ll use the term “untimed”to represent those algorithmswritten either in MATLABor pure ANSI C/C++.

Based on project require-ments, system architectsthen partition the designinto blocks to be implement-

ed either in hardware or software. For thehardware blocks, a floating-point algo-rithm represents the functionality. Next,either the system or hardware designerquantizes the floating-point algorithminto an integral or fixed-point algorithm.These fixed-point algorithms are repre-sented in MATLAB, Simulink™, oruntimed C++ using bit-accurate types(SystemC 2.0). After validating the fixed-point algorithm, the hardware designerstarts the long and tedious manual processof creating Verilog or VHDL for the RTLabstraction. This process can be dividedinto three distinct phases:

• Micro-Architecture Definition. Decideon the structure of the data path, con-trol, and interfaces. Typically done onpaper or perhaps a Microsoft™Excel™ spreadsheet. The resultingmicro-architecture has a significantimpact on the overall speed/area of thehardware. Designs can easily swing by10 times in area or performance basedon the decisions made.

• RTL Design. Manually write theRTL to represent the defined micro-architecture.


Algorithm FunctionalDescription

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Micro-architectureDefinition

RTLDesign +

RTL Area/TimingOptimization

Figure 1 – The manual, iterative methods used in conventionalRTL flows no longer work for today’s complex designs.

is impractical because modifying andre-verifying RTL to perform a series of“what-if ” analyses of alternate micro-architecture implementations is toolengthy to be practical. Such evalua-tions may include performing certainoperations in parallel versus sequential-ly; pipelining portions of the designversus non-pipelining; or sharing com-mon resources. Because of the amountof time involved, design teams are lim-ited to the number of evaluations theycan perform, which can result in anon-optimal implementation. Thecomplexity of high-end, compute-intensive applications exemplifies thedifficulties associated with traditionalhand-coded RTL.

• RTL Reuse. Using the same RTL foran ASIC and FPGA implies that theASIC implementation is sub-optimaldue to inherent FPGA performancelimitations. Conversely, users can real-ize performance goals in an FPGAthrough massive parallelism; however,this parallelism may not be necessaryfor an ASIC. This makes it extremelydifficult, if not impossible, to re-targeta complex RTL design to create atuned representation for the technolo-gy node. Finally, because RTL hard-codes the micro-architecture, using thesame RTL for a 10 MHz application(for example) versus a high-perform-ance 400 MHz application will resultin sub-optimal hardware.

• Functional Verification. Using tradi-tional logic simulation to verify a largedesign represented in RTL is computa-tionally expensive and extremely slow.

The most important challenge facing thedesigner is that all of the implementation“intelligence” associated with the design ishard-coded into the RTL, which thereforebecomes rigid and implementation-specific.

Next-Generation C-based FlowAn examination of the conventional flowreveals three stages:

• Untimed algorithm evaluation inMATLAB or C/C++, including quanti-zation and integral/fixed-point analysis

• Algorithm (untimed) to RTL (timed)translation, including verification and“what-if ” implementation analysis

• RTL to gate-level netlist using industry-standard RTL synthesis

The front-end untimed algorithm eval-uations and the back-end RTL-to-netlistsynthesis are both well known and effi-

cient. The bottleneck is the manual cre-ation of the RTL, including performing“what-if ” evaluations, implementing speci-fication changes, and verifying the RTL.

Any ideal flow should be based onindustry-standard ANSI C/C++, the lan-guage of choice for software and system-level modeling for many years. The pure,untimed C/C++ written by system design-ers is an excellent source for creating hard-

ware because it is void of implementationdetails. This maximizes flexibility to thesynthesis tool and provides a source that is“liquid” – capable of targeting ASICs,FPGAs, highly compact small solutions,and highly parallel fast solutions.Translation from MATLAB to C/C++ isstill manual, but because these domains areconceptually very close, the translation isrelatively quick and easy.

The untimed C/C++ adds significantvalue by providing much faster simulationthan the MATLAB Simulink environment,and is thus ideally suited for system-levelvalidation. Following verification, the Crepresentation is used to automatically gen-

erate RTL, which in turn is subsequentlyused to drive existing RTL synthesis tech-nology (Figure 2).

With this flow, you can synthesize theuntimed C/C++ directly into a gate-levelnetlist. However, generating the intermedi-ate RTL provides a timed “comfort zone”for existing flows by allowing you to vali-date the implementation decisions made bythe C synthesis tool.



MATLABSPW

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Floating PointModel

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RTLSynthesis

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Fixed PointC++ Model

Micro-ArchitectureDefinition

RTLDesign +

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+

Any ideal flow should be based on industry-standard ANSI C/C++, the language of choice for software and system-level modeling for many years.

Figure 2 – This ideal design flow basedon algorithmic synthesis of pure,untimed C/C++ addresses all of theproblems associated with traditionalflows in which the untimed algorithmis hand-translated into RTL.

Furthermore, RTL is a useful point to“stitch” the various functional blockstogether. Large portions of today’s designsexist as IP blocks represented at the RTLlevel of abstraction. This means that RTL isa useful point in the design flow for inte-grating and verifying the entire hardwaresystem. Your design teams can thus takefull advantage of existing, mature, androbust RTL design tools such as test inser-tion or power analysis.

The ideal flow based on algorithmicsynthesis of pure, untimed C/C++ address-es all of the traditional bottlenecks:

• Functional Intent. Almost no concep-tual gap exists because system archi-tects and hardware designers use thesame untimed C/C++ source. Theirworlds are connected for the first time.Moreover, it eliminates any chance ofmisinterpretation by the hardwaredesigner, thereby reducing errors andimproving overall reliability. The newflow also easily accommodates designspecification changes.

• Meeting Requirements. Algorithmic Csynthesis provides accurate metrics upfront, shortening lengthy RTL synthesisruntimes and manual RTL optimiza-tion. You can leverage these metrics tomake system-level macro-architecturepartitioning decisions, thus creating adesign that is better architected to meetsystem performance.

• Design Complexity. You can addressthe design complexity issue by using

algorithmic C synthesis to thoroughlyexplore any highly complex designspace. C is fast and efficient to createand verify, providing additional bene-fits around system-level validation andintegration. RTL uses technology-dependent coding styles and hard-codes the micro-architecture. Using theideal flow, evaluating alternative imple-mentations is fast and efficient. Youcan modify and re-verify C to effec-tively perform a series of “what-if ”evaluations of alternative algorithms.Thus, your design teams are not limit-ed by the number of evaluations theycan perform, which results in an opti-mal implementation.

• RTL Reuse. A key feature of this idealflow is that the C representation is com-pletely abstracted from the final imple-mentation. Therefore, as opposed toembedding implementation “intelli-gence” into the C representation, design-ers can instead use such intelligence todrive the C to the RTL implementationthrough a series of “soft” constraints. Inturn, this means that they can easily re-target the same C representation for dif-ferent micro-architectures andASIC/FPGA implementations.

• Functional Verification. Verifying C isfast and efficient. A pure untimed Crepresentation will simulate as much as10,000 times faster than an equivalentRTL representation (the larger thedesign, the faster C is compared to itsRTL counterpart).

Let’s examine alternatives to hardwaredesign based on the use of C/C++. Theseinclude SystemC and the synthesizable sub-set of pure untimed C++ used by theMentor Graphics Catapult C Synthesis tool.

SystemC-Based FlowTwo main SystemC-based design flowsexist: both require the untimed algorithmrepresentation to be manually translatedinto its SystemC counterpart. Followingverification via simulation, you can auto-matically translate the SystemC representa-tion into an RTL equivalent for use withexisting synthesis technology. Alternatively,you can directly synthesize the SystemCrepresentation into a gate-level netlist(Figure 3).

Because it was specifically created torepresent hardware, SystemC is equippedwith hardware-centric data types, includ-ing integral and fixed-point entities withrounding and overflow modes. SystemCalso includes system-level simulationcapabilities, including support forabstract data transactions. Although pow-erful, SystemC is an extremely complexlanguage. Moreover, the pseudo-timedconstructs required for SystemC synthesisand simulation are foreign to both sys-tem-level and hardware designers.

One advantage of SystemC is that itsimulates as much as 100 times faster thanan equivalent RTL representation specifiedat the same level of abstraction. However,to make a SystemC representation suitablefor RTL generation or direct C synthesis,designers would need to write it at nearlythe same level of abstraction as hand-translated RTL, which largely negates theadvantages of using it in the first place.

Even worse, all of the implementation“intelligence” associated with the designhas to be hard-coded into the SystemC rep-resentation, which therefore becomesimplementation-specific. This means that aSystemC representation intended for anFPGA is not suitable for a subsequent ASICrealization, and vice versa. Finally, it is notpossible to re-target the SystemC represen-tation to a compact or highly parallel solu-tion because the micro-architecture ishard-coded.


MATLAB SystemC

RTL

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Gate-LevelNetlist

Gate-LevelNetlist

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SystemArchitects

HardwareDesign Engineers

AutomaticTranslation

Non-implementationspecific, fast to simulate,

easy to modify

ManualTranslation

Time consuming to create, implementationspecific, relatively slow to simulate,

relatively difficult to modify

Figure 3 – To make a SystemC representation suitable for RTL generation or direct C synthesis, you would need to write it at nearly the same level of abstraction as hand-translated RTL.


Another SystemC approach“wraps” the untimed C++ algorithmin a timed interface. This approachmay have some advantages in system-level integration; however, the result-ing source is now pseudo-timed andhard-coded to the hardware interface.Therefore, the notion of interfaceexploration is not practical.

For example, targeting the C sourceto a streaming I/O model versus a sin-gle-port memory implies re-coding theinterface wrapper (difficult and timeconsuming). In addition, the source isno longer the pure, untimed C++description already validated andproven by the system designer. Thus,any interface changes will require re-verification and possibly introduce for-eign coding concepts to the pure C++representation.

Finally, the degree of interfacedetail is extremely critical. Too muchinformation stifles the behavioral synthesistool and results in sub-optimal designs. Toolittle means the tool doesn’t have the mini-mum information needed to synthesize thedesign, resulting in functional errors.

Catapult C-Based FlowAs noted previously, the most significantproblem with existing C-based design flowsis that the implementation “intelligence”associated with the design has to be hard-

coded into the C representation, whichthen becomes implementation-specific.This is the key differentiator of theCatapult C-based design flow from MentorGraphics. In this flow, the C code is veryclose to what a system designer would writeto model functional behavior without anypreconceived hardware implementation ortarget device architecture in mind.

As opposed to adding “intelligence” tothe source code (thereby locking it into a

target implementation), all of the intel-ligence is provided by controlling theCatapult C engine itself (Figure 4).

Catapult C uses industry-standardC++ source code augmented withSystemC data types that allow specificbit-widths to be associated with vari-ables and constants. An advantage isthat many companies already create anuntimed C/C++ representation of theirdesigns for algorithmic validation. Theydo this because a pure C representationis easy and compact to write and simu-lates 100 to 10,000 times faster than anequivalent RTL representation.

The only modification typicallyrequired to use this model withCatapult C is to add a single pragma tothe source code to indicate the top ofthe functional portion of the design –anything conceptually above this pointis considered part of the test bench.

Another Catapult C advantage is itsintuitive interface. Once the tool has readthe source code, you can immediately per-form micro-architecture tradeoffs and eval-uate their effects in terms of size and speed.Catapult C easily associates ports with reg-isters or RAM blocks. It identifies con-structs like loops and allows you to specify– on an individual basis – whether theyshould be unrolled, partially unrolled, orleft alone. You can also specify if you wishto perform resource sharing on specific enti-ties, pipeline loops, and other constructs.

All of these evaluations are done with-in a few seconds or minutes depending ondesign size. Catapult C then reports totalsize/area and latency in terms of clockcycles or input-to-output delays (orthroughput time/cycles in the case ofpipelined designs). You can name, save,and reuse any of these “what-if ” scenar-ios. It would be almost impossible to per-form these tradeoffs in a timely mannerusing a conventional hand-coded RTL-based flow.

More importantly, the fact that the Csource code used by Catapult C is notrequired to contain any implementation“intelligence” – and that all such intelligenceis supplied by controlling the Catapult Cengine itself – means that your design teams

C++Algorithm

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Non-Implementation Specific)"m" Language (Used by MATLAB)

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Specific

Less Abstract, MoreImplementation

SpecificVerilog and/or VHDLRTL Domain

(Implementation Specific)

Timed C Domain(Implementation Specific)

Untimed C Domain(Non-Implementation Specific)

Figure 4 – The Catapult C tool’s “what if ” analysis allows complete, interactive exploration of the micro-architectureand interface design space, yielding high-performance hardware

that rivals hand-coded design quality.

Figure 5 – The Catapult C-based design flow supports a higher level of synthesis abstraction, speedingimplementation time and increasing design flexibility when compared to other C-based flows.


can easily re-target the same source code toalternative micro-architectures and differentimplementation technologies.

ConclusionThe fundamental difference between the var-ious C-based design flows is the level of syn-thesis abstraction they support (Figure 5).SystemC offers significant system-level sim-ulation capabilities, but its synthesizablesubset is at a lower abstraction level, so mod-ification to the source drives the results.

This lack of synthesis abstraction caus-es the SystemC representations to beimplementation-specific. This makes themdifficult to create and modify, and signifi-cantly reduces their flexibility with regardto performing “what-if ” evaluations andre-targeting them toward alternativeimplementation technologies.

By comparison, Catapult C employsmodels represented in standard C++ andsupports a high level of synthesis abstrac-tion. Because they are not implementation-specific, Catapult C models are compactand can thus be easily created and modified.

By means of the Catapult C engineitself, you can quickly perform “what-if ”evaluations and re-target the design towardalternative implementation technologies.

The end result is that the Catapult C-based design flow dramatically speedsimplementation, improves design flow reli-ability, and increases design flexibility whencompared to other C-based flows or tradi-tional hand-coded RTL methods.

Catapult C Synthesis has already beeninstrumental in many successful tapeoutsfrom major hardware design companiesworldwide. The mature, second-genera-tion algorithmic synthesis environmentunites two distinct domains – system-leveldesign and hardware design – and whencombined with Mentor GraphicsModelSim™ simulation tools, lays thefoundation for next-generation electronicsystem level (ESL) design.

To learn more about how Catapult CSynthesis can address your hardware designneeds, call Mentor Graphics to schedule acomplete product demonstration, or visitour website for the latest product news andcase studies at www.mentor.com/c-design.

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The Xilinx® Integrated SoftwareEnvironment (ISE 6) is the current versionof our industry-leading logic design tools,focused on delivering the highest perform-ance available in PLD design. That leading-edge performance can help you get thehighest quality of results available, and itcan also significantly contribute to lower-ing design time and costs.

ISE 6 is packed with features designedto streamline the design flow, with technol-ogy such as:

• Timing-driven map – an ISE mapperoption that helps pack more designinto your highly utilized device

• ASIC-to-FPGA transition tools

• A spectrum of high-density designoptions built into ISE

ISE 6 can help eliminate engineeringbottlenecks while delivering the fastestpush-button performance available in pro-grammable logic design.

Lower Potential Device CostsIntroduced in September 2003, ISE 6 addsa new timing-driven map option that helpsget better design utilization for your FPGAdevice, particularly if the device is alreadymore than 90% utilized. Timing-drivenmap is a next-generation enhancement toISE physical synthesis, and combines

Design Tool Performance that Lowers Your CostsDesign Tool Performance that Lowers Your Costs


ISE software includes advanced capabilities that slash design and verification times, getting you to design closure faster.ISE software includes advanced capabilities that slash design and verification times, getting you to design closure faster.

placement with logic slice packing forVirtex-II™, Virtex-II Pro™, and Spartan-3™ devices to improve placement qualityfor “unrelated logic.”

In recent benchmarks, timing-drivenmap was tested on large, highly-utilizeddesigns that contained tight timing con-straints, versus the standard map and placeand route flow. Results varied based onmany factors in the design, yet timing-driv-en map showed an average 30% betteroverall logic placement.

This advantage gives Xilinx ISE 6 cus-tomers the potential to stay in their chosendevice, even if utilization is pushing 90%or higher, when competing tools wouldhave already forced the design into a largerand thus more expensive device. The tim-ing-driven map option is included freewith all configurations of ISE 6.

Streamlining ASIC-to-FPGA TransitionsThe last few years have seen a steep declinein the number of ASIC design starts, and agood number of those projects have movedto Xilinx FPGAs for their logic deliverymedium. Helping those project engineerstransition from ASIC design flows withadvanced support has been a priority forISE development: thus, a number of toolsare available to help.

Starting at the front of the design flow,you can use many of your existing ASICcode-checking tools to verify your HDLsource. Xilinx has created a set of XilinxFPGA-specific libraries for Synopsys™LEDA VHDL and Verilog™ “linting”tools. The libraries are free to registeredSynopsys users, and you can use them toconfigure your existing LEDA checker.They contain critical coding-style rules thathelp ensure HDL source quality and opti-mize implementation for the target FPGA.

ISE place and route tools also help youensure efficient implementation. The placeand route tools results offer interactive sug-gestions on how you can change your HDLcode to reduce design size and implemen-tation results. These suggestions help makemore efficient use of FPGA resources andsave overall design space.

The ISE design flow also supports tech-nology that some ASIC designers have

by source such as purchased IP, or to effi-ciently reuse HDL from an earlier proj-ect. Good floorplanning can help achievefaster timing closure and optimize designperformance.

Incremental DesignISE also contains Incremental Design, atechnology that can slash re-implementa-tion time by as much as 75%. IncrementalDesign uses a design floorplan as the start-ing point. The design is then implementedor passed through the synthesis and placeand route cycle. If subsequent modifica-tions are required, Incremental Designupdates only the area affected by thechange, leaving the other completed designareas intact and dramatically shortening there-implementation cycle. IncrementalDesign is useful during the verificationphase, where debug and design changes aremost commonly encountered.

Modular DesignModular Design isanother option includedin ISE supporting theteam design environ-ment. Modular Designlets team managersdivide a high-densitydesign up into “mod-ules.” Each design teamcan then use the entiresuite of ISE design toolsto complete their module independently.Modular Design deploys

a “divide and conquer” strategy to high-density designs, letting teams operate effi-ciently in parallel, finishing the overallproject faster.

ConclusionHigh-performance ISE technology isn’tonly about getting the fastest clock speed inyour design. The advanced technology builtinto ISE 6 also can cut your design and ver-ification times, slash project costs, and offerpotentially lower device savings in the longrun. Upgrade your designs to ISE 6, ordownload the evaluation version of ISE byvisiting www.xilinx.com/ise_eval.

already invested in for verification. Forexample, formal verification is a technolo-gy that saw initial adoption in the ASICdesign space. This structural equivalencycomparison technique can drastically speedup verification time, and is often seen as analternative to more traditional HDL simu-lation methods, particularly for higher den-sity designs. These same tools also workwith ISE FPGA-based designs, so if you’reusing Synopsys Formality™ or VerplexConformal LEC, you can use formal equiv-alency checking on your Xilinx FPGAdesign as well.

High-Density Design TechniquesYou can also slash design times and projectcosts by using the high-density designoptions built into ISE. Free to all Xilinxusers and included with ISE, these optionscan lead to faster timing closure and fasterimplementation times.

Area Mapping and FloorplanningISE includes two floorplanning options:PACE (Pin Assignment and ConstraintsEditor – shown in Figure 1), and ISEFloorplanner. Also, PlanAhead™, thehigh-level floorplanning tool, is now anoptional, separately purchased Xilinxdesign tool offering through the recentacquisition of Hier Design, integratingdirectly to the ISE design flow.

These tools let you group logic togeth-er and associate those groups to an areaon the target FPGA. Area mapping is afast way to keep critical sections of thedesign together, associate HDL together


Figure 1 – The pin assignment and constraints editor (PACE)

by Brent PrzybusChipScope Pro Product Marketing Manager Xilinx, [email protected]

Brad FrossChipScope Pro Engineering ManagerXilinx, [email protected]

Most of us have been there: our initial per-formance requirement has been increased toaccommodate a new external memory inter-face or incorporate pre-processing nowrequired because of an ASIC flaw. Theinnate flexibility of FPGAs makes them theperfect solution to address these last-minutechanges and additions. But adding newcapabilities is often much easier than debug-ging them when things no longer work.

Fortunately, Xilinx® provides a solu-tion. ChipScope Pro™ tools enable you toplace logic analysis, bus analysis, and evenvirtual input and output cores directly intoyour FPGA design and perform real-timedebug and verification.

Although ChipScope Pro cores are opti-mized for size and performance and canrun as fast as 200 MHz in Virtex-II Pro™FPGAs, this is often not enough. Plus,

adding these cores to a design may preventit from meeting specified timing. Fordesigns operating between 85 MHz and150 MHz and using less than 80% of theavailable FPGA resources, ChipScope Protools can provide the easy visibility andaccess needed to debug and verify yourdesigns.

For designs exceeding 150 MHz and/orusing more than 80% of FPGA resources,techniques exist that allow you to useChipScope Pro tools without impactingFPGA design performance.

In this article, we’ll describe three tech-niques to get the most performance out ofChipScope Pro cores, gain access and visi-bility to debug your design, and still meetFPGA design performance.

ChipScope Pro Debug Methodology The easiest way to ensure that ChipScopePro tools will not impact your design per-formance is to plan in advance. ChipScopePro cores are no different that any other IPin your design – they also use logic andblock RAM. By adopting a ChipScope Prodebug methodology in advance, determin-ing what signals you would like to accessfor debug, and how many samples you will

need to observe, you will have the bestchance of meeting design performance.

The following checklist will help youmeet your debug performance goals:

• Decide which signals you want toobserve. This is similar to decidingwhich signals you are going to routeout to a test header on your board.The difference is that you place virtualtest headers directly within yourdesign. And for those designs requiringmore than one core, ChipScope Protools allow you to include as many as15 ILA cores in a single design.

• Define how many trigger ports youneed based on how you might want totrigger on different groups of signals.Consider attaching similar signals (suchas individual address signals) into thesame trigger port while attaching unre-lated signals (such as control and datasignals) to separate trigger ports. Notonly will the separate trigger ports makeit easier for you to create trigger condi-tions, but by using multiple smallertrigger ports, you might find that it iseasier for the implementation tools topack, place, and route your design.

Exploit ChipScope Pro to debug your high-performance designs.Exploit ChipScope Pro to debug your high-performance designs.

The Need for SpeedThe Need for Speed


• Decide which signals are to be used astriggers and which signals are to be cap-tured as data. You can conserve deviceresources by being careful to captureonly the signals you need to debug yourdesign. Although ChipScope Pro toolsprovide many of the familiar triggercapabilities found in expensive bench-top logic analyzers (such as multipletrigger ports and complex triggersequencing), you should always beaware that many of these features con-sume additional device resources.

• Determine the number of samples youneed to observe. To do this, determinethe time over which you anticipateneeding to view data and divide this bythe system clock rate. As many as16,384 samples of data storage areavailable using on-chip block RAM. Ifyou need more storage, you can usemultiple debug cores or you can usethe ChipScope Pro-enabled Agilent™FPGA dynamic probing solution,which allows you to store internallyprobed signal data directly on an exter-nal Agilent logic analyzer.

• Decide how you are going to get dataoff-chip. Start with a JTAG port andAgilent trace port. You can use theJTAG port for configuration, hardwaredebug, and software debug. The Agilenttrace port provides the flexibility tointerface to the Agilent 16900 serieslogic analyzer with FPGA dynamicprobing technology. You will probablyalready have JTAG set up on yourboard for FPGA configuration. TheAgilent trace port uses between four and128 user I/O pins that tie directly to aMictor™ or Agilent soft-touch probepad connector. Instructions for layingout these connectors are included inthe Agilent data sheet, available atwww.xilinx.com/chipscopepro/.

• Use the core generator to define theILA cores to the specifications youhave defined in the previous steps. TheChipScope Pro core generator will pro-duce embeddable EDIF netlists andHDL component instance templatesthat you can incorporate into your

• Properly constrain your design. Run“trce -a” to report unconstrained netswithin your design. Apply timingconstraints where needed and use aconstrained system clock net to driveany ChipScope Pro cores.

• Disable RPMs. Sometimes allowingthe ChipScope Pro core logic to float– particularly the flops that make upthe cores – enables you to better fitChipScope Pro cores within anyavailable logic.

When All Else Fails ...If you’ve tried all of these techniques andyour design still doesn’t meet timing, or if the tools seem to choke ontiming, try this advanced technique.Guide filing uses your non-instrumenteddesign netlist as a guide for routing inChipScope Pro cores. Although thistechnique does not guarantee that timing will be met, it can work in some cases.

The steps to guide filing are:

1. Synthesize your design.vhd intodesign.ngc using your chosen syn-thesis tool (substitute design.edf fordesign.ngc, if you are not using thexst synthesis tool).

2. Translate your design.ngc intodesign.ngd using ngdbuild.

3. Map your design.ngd intodesign_map.ncd using the map tool.

4. Place and route yourdesign._map.ncd to design_par.ncdusing the par tool.

Now add ChipScope Pro cores to thisdesign by following these steps:

5. Copy the design.ngc todesign_debug.ngc.

6. Insert ChipScope Pro cores intodesign_debug.ngc using theChipScope Pro core inserter tool.

7. Translate design_debug.ngc intodesign_debug.ngd using ngdbuild.

HDL design. If your design has alreadybeen synthesized, you can use theChipScope Pro core inserter to addChipScope Pro cores to a design byselecting which nets and signals youwant to view.

By defining a debug and verificationmethodology in advance, you haveaccounted for the logic, block RAM, androuting resources needed – and minimizedthe chances of ChipScope Pro coresimpacting your design timing.

Techniques to Achieve PerformanceWhat if you have not planned for debug?Let’s say your design is running at close to200 MHz and something is not function-ing correctly. When you add a ChipScopePro ILA core to view signals in the faultylogic, the design fails to meet your timingrequirements. Here are some techniquesthat can help:

• Reduce the size and complexity of yourtrigger ports and corresponding matchunits. Start with a basic trigger type,with a width as narrow as possible. Forexample, an 8-bit basic match unit willconsume a fraction of the logic of a36-bit range-type match unit.

• Use “trigger same as data.” By selectingtrigger same as data, you reduce thenumber of loads on the instrumenteddesign nets from two to one.

• Avoid critical paths. Understand the crit-ical paths within your design and avoidinstrumenting them if at all possible.

• Watch what you instrument. Avoidinstrumenting combinatorial logic,which may cause the new logic imple-mentation to split into multiple slices.Whenever possible, try to instrumentthe outputs of flip-flops instead.

• Apply area constraints to ChipScopePro cores. Bound the inner logic of aChipScope Pro core and allow theouter flip-flops to float. A tighter fitmay result in higher performance ofthe ILA core while allowing the outerflip-flops to be placed close to theinstrumented design nets.


8. Map design_debug.ngd intodesign_debug_map.ncd using a -gm(guide mode) option, specifying youroriginal design_map.ncd as the guidefile. You will have the option of speci-fying exact, incremental, or leveragedguide modes. Start with exact; it maytake a little longer to compile, butwill probably deliver the best results.If that doesn’t work, or if you wouldlike a better result, try the leveragedoption. This option allows logic inyour design to be moved if it willbenefit placement of the newChipScope Pro cores.

9. Place and route design_debug_map.ncdinto design_debug_par.ncd using a -gf(guide file) option and specifying youroriginal design_par.ncd as the guide file.Use the same -gm guide mode option(exact, incremental, or leveraged) thatyou used in step 8.

10. Convert design_debug_par.ncd into abitstream called design_debug_par.bitand use the ChipScope Pro analyzerto configure and debug your FPGAdesign.

After steps 8 and 9, you will receivetool messages stating that a percentage ofthe net names in the design have changed.This represents the new ChipScope Prologic added to your design.

If after performing these steps yourinstrumented design is still not meetingtiming, you may want to go back to step 2in your original design and try to allocatean area region for ChipScope Pro cores.Then repeat the remaining steps.

Conclusion In this article, we’ve shown you tech-niques for debugging high-speed FPGAdesigns using ChipScope Pro tools. Nodesign is the same and sometimes moreadvanced techniques are required. If youhave techniques that have worked for youand you’d like to share them, or if youneed help in implementing any of thetechniques described, please send an e-mail to [email protected].



For the second straight year, the MySupport.xilinx.com web site has been voted one of the

“Ten Best” by the Association of Support Professionals. More than 130,000 engineers count

on this resource every month to deliver content-rich, personalized, 24/7 support for designing

with Xilinx programmable logic solutions.

©2004 Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124. Europe +44-870-7350-600; Japan +81-3-5321-7711; Asia Pacific +852-2-424-5200; Xilinx is a registered trademark,and The Programmable Logic Company is a service mark of Xilinx, Inc.

130,000 engineers a month… can’t be wrong!

by Suhel DhananiSr. Solutions Marketing Manager, Spartan SolutionsXilinx, [email protected]

Lowering total system costs is the key goalwhen developing high-volume/low-costsystems. Although many system designerscarefully select components with the lowestunit cost, they often ignore the actual costof manufacturing the PCB.

However, with careful design considera-tions, you can achieve the same functional-ity and performance within a smaller PCB,using fewer layers and sometimes with lesscomponents.

Some of the newer low-cost FPGAs,such as Xilinx® Spartan-3™ devices, nowinclude a host of features that can reducethe number of on-board components andinterconnect traces, enhance signal integri-ty, and reduce system electromagneticinterference (EMI) noise levels, essentiallyenabling you to significantly lower yoursystem costs.

Reducing PCB Size and ComplexityThe most obvious way to reduce the cost ofany PCB is to make it smaller and havefewer layers. By reducing the total boardarea and using fewer layers (four instead ofsix, for example), you can cut down on themanufacturing expense.

For a typical 4” x 6” board, going fromsix to four layers can reduce the cost byanywhere from $2 to $4 per board. Whenyou calculate the total savings based on thequantity of boards manufactured, thiscould be a substantial amount.

Another factor that influences themanufacturing cost of a PCB is EMInoise compliance. In cases where EMI isan issue, you need to design for the low-est possible EMI level, because trying toretrofit the PCB to meet EMI compliancecan result in expensive redesign, re-lay-out, or shielding.

Good design techniques such as main-taining optimum signal integrity, havingfewer traces running lower voltage levels,and distributing slower clocks on board canall help reduce the overall EMI level.

By using features found in Spartan-3

Lower Your PCB Manufacturing Costs


By choosing an FPGA with the right features, you can reduce your PCB manufacturing costs and even EMI levels.

FPGAs, you can reduce total PCB manu-facturing costs by optimizing the area andnumber of layers and minimize total EMInoise levels.

Spartan-3 FeaturesDigitally Controlled ImpedanceOne of the key features provided bySpartan-3 devices is digitally controlledimpedance (DCI). This allows you to notonly (potentially) eliminate most externalresistors, but also design for optimum sig-nal integrity.

DCI actively adjusts both parallel andseries terminations to accurately match thecharacteristic impedance of the transmis-sion line. This adjustment process compen-sates for differences in I/O impedance thatcan result from normal variations in theambient temperature, supply voltage, andmanufacturing process. This feature isavailable for most popular I/O standards,including LVCMOS, LVDS, SSTL,HSTL, and GTL.

Figure 1 illustrates how the DCI featurecan eliminate external resistors normally usedfor termination. Not only does this featureallow you to tune the output driver imped-ance – thereby optimizing signal integrity –but it also reduces the total number of com-ponents on board, with the resultant benefitsin reliability, manufacturability, procurementcosts, board area, and routability.

Drive Strength and Slew Rate ControlAnother Spartan-3 feature is the ability toadjust the output drive strength and slewrate of the output drivers. Two options,fast and slow, control the output slew rate.You can select as many as seven differentlevels of current drive strength: 2, 4, 6, 8,12, 16, and 24 mA. (These options areavailable when using one of the LVCMOSor LVTTL standards.)

Choosing the appropriate drive strengthlevel is yet another means to minimize bustransients and optimize board signalintegrity, as shown in Figure 2.

These adjustments can be made bymerely updating the device bitstream andrequire no board re-layout. Thus, you cancontinue optimizing the drive strengthslong after the board has been laid out.

Figure 1 – Spartan-3 DCI feature eliminates the need for external matching resistors.

Figure 2 – Drive strength can be adjusted by loading an updated bitstream.

Figure 3 – With as many as four DCMs per device, Spartan-3 devices provide complete control over clock frequency, phase shift, and skew using the DCMs.


On-Chip DCMsAll Spartan-3 devices have multiple high-per-formance digital clock managers (DCMs).Each DCM allows clock skew elimination,clock multiplication, clock division, andreconstruction, as well as phase shifting.

Although you can use the DCMs to elim-inate the need for external clock manage-ment devices, they also allow you to run aslower clock on board (using the internalclock multiplication feature) and run fewerclock traces on board (using the clock recon-struction feature), as shown in Figure 3.

Using these features simplifies the layoutof high-speed PCBs and can lower overallEMI levels by allowing you to run fewerand slower clocks traces across the board.

On-Chip Voltage and I/O Standard TranslationAll I/Os in Spartan-3 devices are allocatedbetween eight banks, as shown in Figure 4.Each I/O bank has an independent VREF line.

The I/Os support most of the popularsingle-ended I/O standards such as LVTTL,LVCMOS, SSTL, HSTL, GTL, as well asdifferential I/O standards such as LVDS andRSDS. Because each I/O bank can inde-pendently support a different I/O standardand a different VCCO, this feature lets youimplement voltage translators and I/O stan-dard translators within the FPGA, eliminat-ing the need for external components. Fewer

components translates to smaller PCB andlower system costs.

Comprehensive Support for Differential SignalingThe Spartan-3 family is the only low-costFPGA family whose I/Os support LVDStransmission without the need for exter-nal resistors. This popular standard iswidely used for high-speed chip-to-chipcommunication because of its highernoise immunity, lower EMI, and higherperformance.

Because LVDS is a low swing standard(~350 mV) with a slower slew rate (1V/ns),it exhibits lower EMI. And because it is adifferential I/O standard, it has better noiseimmunity. LVDS allows for very high data

transfer rates (622 Mbps in the Spartan-3architecture), enabling fewer pins to transferlarge amounts of data serially.

All of the device package combina-tions of Spartan-3 support LVDS. Thismeans that you can choose low-cost QFPpackages as well as higher pin-count BGApackages.

Figure 5 illustrates how competing low-cost FPGAs require three external resistorsfor each LVDS transmit channel. Spartan-3 LVDS transmitters do not require the useof an external resistor network because theI/O buffers were designed to support lowswing differential signaling.

ConclusionUsing the many features available withSpartan-3 FPGAs allows you to eliminateexternal components such as resistors,voltage translators, level shifters, and evenexternal clock management devices. Thisnot only increases board reliability andeases manufacturing costs, but alsoreduces the size of the board and may insome cases reduce the number of layersrequired for routing, potentially loweringtotal system costs.

If EMI compliance is a concern, thereare many features within Spartan-3 devicesthat improve signal integrity, allow forfewer traces, and enable low swing I/O sig-naling – all of which contribute to lowerthe EMI level of the system.

For more information on Spartan-3 features and how these features can help you reduce your system cost, visitwww.xilinx.com/spartan3/.


LVTTLLVCMOS 33LVCMOS 25LVCMOS 18LVCMOS 15LVCMOS 12

PCI 32/64 bit 33MHzSS TL2 Class ISS TL2 Class IISS TL18 Class I

HSTL Class IHSTL Class III

HSTL18 Class IHSTL18 Class IIHSTL18 Class III

GTLGTL+

LVDS2.5Bus LVDS2.5LVDS_ext2.5

RSDSLDT2.5LVPECL

3.3V3.3V2.5V1.8V1.5V1.2V3.0V2.5V2.5V1.8V1.5V1.5V1.8V1.8V1.8V----

2.5V2.5V2.5V2.5V2.5V2.5V

--------------

1.25V1.25V0.9V0.75V0.9V0.9V0.9V1.1V0.8V1.0V------------

Standard

Sin

gle

En

ded

Output VCCO Input VREF

Dif

fere

nti

al

Figure 4 – With eight independent I/O banks and support for multiple I/O standards,

Spartan-3 devices eliminate the need for external voltage or I/O translators.

Figure 5 – Spartan-3 I/Os are designed to transmit LVDS signals without the need for external resistors.

by Dan HarrisDirector of Product MarketingProduct Acceleration [email protected]

Manu PillaiCEOProduct Acceleration [email protected]

Philippe GarraultTechnical Marketing EngineerXilinx, [email protected]

Suresh SubramaniamSenior Design EngineerXilinx, [email protected]

Managing signal assignment of high-pin-count FPGAs, especially in multi-FPGA designs, is a growing problem. Asmost hardware managers will attest, thisproblem manifests itself in three ways.

First, the number of communicationchannels interfacing with a typical FPGAmakes I/O assignment a cognitive challengefor logic designers to balance. These cogni-tive challenges include the handling of:

• Key constraints imposed by each channel,including voltage, signal strength, termi-nation, and data versus clock skew.

• FPGA signal assignment constraints,such as I/O banking and simultaneousswitching output rule sets.

Plan FPGA Signal Assignments and Optimize PCB RoutabilityPlan FPGA Signal Assignments and Optimize PCB Routability


Eliminate or reduce design iterations with DesignF/X.Eliminate or reduce design iterations with DesignF/X.

Second, because of an excessive numberof wire crossings, layout engineers may findit physically impossible to route theirdesigns with the specified stackup and PCBdesign rule checks (DRCs). The onlyoption is to increase both the number ofsignal routing layers and via count.However, this will result in reduced signalquality and may drive up the manufactur-ing cost substantially.

Third, most of today’s EDA tools focuson solving the above issues for a singledevice, and have little or no knowledge ofother system devices or their connections.The end result is a sub-optimal pinout thathas been assigned without knowledge of thesystem. If you are a logic designer, youknow it is likely that the pinout will needseveral refinements because of requirednegotiations between you, the hardwareengineer, and SI engineer.

This time-consuming process is furtherexacerbated as system complexity increases,along with the need for precision changecontrol and the resulting process manage-ment overhead. Figure 1 shows one ofmany complex design configurations.

Design F/X directly addresses thesethree core system design issues by:

• Significantly reducing the need tomemorize I/O banking rules.DesignF/X provides an automatedsignal assignment optimization processand keeps you informed of DRC rulesand requirements associated with yourselected I/O standards.

• Providing system-level optimization ofthe signal assignment for one or moreFPGAs and their associated devices ina PCB environment, while honoringthe design rules. This optimization willresult in the highest PCB routability,enabling you to reduce your designiterations and focus on core design.

Design F/X and Existing Design FlowsDesignF/X is easy to learn and even easierto integrate into your existing design flow.Figure 2 highlights a typical DesignF/Xflow on the right, compared to today’stime-consuming and error-prone iterativeprocess on the left.

• There is no tool to validate data frompackage to component to netlist. Forexample, neither the schematic nor thenetlist have knowledge of the package,yet package knowledge is required forproper validation.

• The back annotation process is oftenbroken because required FPGAupdates and attributes are not auto-matically passed completely through tothe board tools for more efficient rout-ing and planning.

• Generally, several iterations arerequired to get the correct FPGApinout based on negotiations betweenlayout engineers and FPGA designers.

DesignF/X eliminates these issues byallowing end-to-end design with verified

We argue that the traditional design flowis a lengthy and error-prone process because:

• Several manual entry points exist,including HDL, signal assignmentspreadsheets, schematic symbols,schematics, package drawings, andconstraint information.


XilinxFPGA1

Connector

CPU/DSP

XilinxFPGAnMemory Memory

Tim

e-C

on

sum

ing

Iter

atio

ns

SchematicCapture

Tool

CadenceAllegro

Routable?(Allegro)

CompleteRouting, Release

Design

FPGA SignalAssignments

DesignF/XCreate/Import

Device PinAssignment and

Board Connectivity

Develop .UCFFile for FPGA

System Analysisand Optimize

SystemArchitecture

Updated, Back-Annotatable

Netlist

.PAD or .CSV Files

Start RTL forFPGA

DesignF/X enabled process(Xilinx and Cadence support)

Netlist file

Board File

.UCF File

Board File

Figure 1 – A typical multi-FPGA system design

Figure 2 – DesignF/X flow as it relates to overall PCB design flow

data inputs and correct-by-design FPGApinouts that are optimized at the systemlevel for best routability.

You need not interrupt your currentdesign flow, because DesignF/X providesseveral vector points at which you can ana-lyze your design. DesignF/X also providesthe I/O capabilities shown in Figure 3.

Only two successive steps are required toget an optimized design in a single iteration:

1. Create or import device pin assign-ment and board connectivity.

2. Analyze and optimize your config-urable devices for the best possibleroutability while honoring XilinxFPGA design rules.

Signal Assignment PlanningDesignF/X is built around Xilinx parts andtheir associated design rules. As of June2004, DesignF/X supports the followingcapabilities:

• I/O banking DRCs (voltage, I/O stan-dards, and on-chip termination arechecked for intra-bank compatibility)

• Automatic reservation of Vref, VRP,and VRN pins when necessary, basedon the selected I/O standard

• Automated recognition and handlingof differential pairs, including swap-ping signals as a pair where legal dur-ing optimization

Usage ModelThe first step is to select a Xilinx-specificdevice (see Figure 4). After you select your

package, you may import a Xilinx .pad or .csvfile, or you can start with no file inputs. Ineither case, you can use the signal assignmentspreadsheet shown in Figure 5 to:

• Assign signals to pins and create signalgroups and buses

• Apply I/O standards and mark specificpins as fixed if you do not want themconsidered for optimization

Each time you change a signal’s I/O stan-dard, location, or pin type (direction),DesignF/X will respond with a DRC forcompliance with Xilinx-specific rules.

The screen shot for Figure 6 was generat-ed after changing the I/O standard of twobuses within the same bank. The outputscreen is interactive and shows which pinsare causing the DRC error. A key ease-of-usefeature shown is the way a number of relatederrors are summarized into one line.

After you have finished assigning signals,DesignF/X will perform one last DRC. If theDRC passes, you will be allowed to use thepart for analysis and optimization on the “vir-tual PCB” screen. You can also rapidly gener-ate a .ucf file for use in your Xilinx ISEenvironment for a rapid place and route check.

Signal Assignment for Optimal PCB RoutingOnce you have all your programmable devicesdescribed and pin assignments defined, youcan choose to import your connectivity infor-mation using a netlist file, or, if you do nothave a netlist, use a table to define connectivi-ty. Once connectivity information is defined,you can place your components on the “virtu-al PCB” and optimize them.

As a PCB designer you probably want tooptimize your devices at the system levelfor the best possible routing early in thedesign phase – before completion of theFPGA place and route – while maintainingcompliance to fundamental Xilinx DRCson the I/O side. This will help you:

• Reduce PCB wire crossings, whichdirectly correlates to reduced via counts,potentially reduced layer counts, andfaster routes that enable early routestudies for more what-if analyses

• Reduce SI complications and generatehigher quality signals, also fromreduced wire crossings and via counts(vias can result in stubs at high speedthat are detrimental to edge rates)


Xilinx PAD, CSV

Excel Spreadsheet

Allegro Netlist

Allegro Netlist

CSV, UCF

Allegro Board File Allegro Board File

PAI SignalOptimization

Algorithm

Xilinx System DRC Rules

DesignF/X

Figure 3 – DesignF/X I/O capabilities

Figure 4 – Select Xilinx device or define new device screen

Figure 5 – Signal assignment screen

Figure 6 – DRC interactive screen

Summary of ResultsRecently, a major semicon-ductor/systems client was inthe process of developing anew system with two XilinxVirtex-II™ devices of 1,704pins each and a third at 1,152pins, combined with a cus-tom processor.

The client faced the fol-lowing challenges:

• A team co-located inthree different cross-country cities: theFPGA engineer, thehardware engineer, andthe layout engineerswere each located in different cities.

• The fast-paced designreached layout, but thePCB board was notroutable.

• Obviously, any changes made to get thePCB board to route needed to complywith the rules of the Xilinx devices.

Instead of investing several man-weeksto fly all of the engineers to one locationand attempt to fix the problem by hand,they called on DesignF/X to provide thefollowing solution:

• The FPGA engineer sent the neces-sary Xilinx .pad files to the hardwareengineer.

• The layout engineers sent the CadenceAllegro board file to the hardwareengineer.

• The hardware engineer imported allfiles into DesignF/X and the PCB wasoptimizing within hours.

• The hardware engineer then output theupdated Cadence Allegro board file andthe updated Xilinx .ucf files and sentthem back to the appropriate engineers.

• The FPGA engineer confirmed thatthe new pinouts for the Xilinx partsdid not violate any Xilinx rules andsigned off on the update.

• The layout engineers successfully rout-ed the PCB board and back-annotatedthe changes to the Cadence OrCADschematic.

The entire process took days instead ofweeks. Figure 7 shows the layout of thethree Xilinx FPGAs before and afterDesignF/X optimization. This design wasnot routable for a given PCB layer countuntil DesignF/X optimized the pinouts ofthe three FPGAs.

ConclusionWhether you are a logic designer, a hard-ware engineer, a PCB layout engineer, anengineering manager, or an FAE, you are

likely facing one or more of the issues men-tioned in this article with complex designs.

To learn about the latest DesignF/Xfeatures, visit the Product Accelerationwebsite at www.prodacc.com. To schedulea DesignF/X demonstration, please sendan e-mail to [email protected] or call(408) 551-0882.


Problem Viewed in Cadence Allegro Problem Viewed in DesignF/X

Before Optimization 19,002 Wire Crossings

Figure 7a Figure 7b

After Optimization (< 10 Minutes) 1501 Wire Crossings (92% Improvement)

Figure 7c Figure 7d

For the full account of this example application, visit www.prodacc.com.

Figure 7a Figure 7b

Figure 7c Figure 7d

Figure 7 – PCB before and after optimization, shown in Cadence Allegro and DesignF/X

Product Acceleration is a member of the Cadence Connections program and the

Xilinx EDA Alliance Program. We are committed to the best solutions possible for complex FPGA

design implementation integrated with the CadenceAllegro Platform and Xilinx ISE software.

by Tom FischaberSr. Design Engineer, IP Solutions DivisionXilinx, [email protected]

Krista MarksSr. Manager, IP Solutions DivisionXilinx, [email protected]

Hamish FallsideSr. Manager, Advanced Products DivisionXilinx, [email protected]

SONET networks are ubiquitous in thetelecommunications industry for trans-porting both voice and data over long dis-tances. Standard protocols have targetedthe underlying transport layer, includingATM for voice and data and HDLC orPPP for data transfer. However, each ofthese protocols introduces bandwidth inef-ficiencies, as none were developed specifi-cally to address data transport overSONET/SDH networks.

Additionally, telecom carriers are moti-vated to increase revenues by diversifyingthe types of client traffic transported acrosstheir networks and optimizing their band-width utilization. This includes capturingnew market sectors such as storage area net-works (SAN – utilizing Fibre Channel) andemerging video on demand (utilizingDVB-ASI). In this case, Fibre Channeland DVB represent two specific types ofclient traffic or client data as defined bythese data network protocols.

The Generic Framing Procedure (GFP)is the first encapsulation mechanism capa-ble of addressing this wide range of datatransport applications by supporting a suiteof client network protocols (summarized inTable 1). GFP was introduced by theInternational Telecommunication Union(ITU) as recommendation G.7041/Y.1303,and provides a flexible, efficient mapping ofvarious protocols onto a transport network.

In this article, we’ll describe a flexiblesuite of networking solutions that addressthe needs of systems vendors deployingmetro equipment to provide these services.Xilinx® supports applications ranging from

The Xilinx GFP core enables efficient transport of LAN/SAN protocols over SONET-based networks.The Xilinx GFP core enables efficient transport of LAN/SAN protocols over SONET-based networks.

Next-Generation Data Transport over Metro Area Networks

Next-Generation Data Transport over Metro Area Networks


a completely integrated client adaptationwith Virtex-II Pro™ devices to low-costprotocol encapsulation with Spartan-3™FPGAs. The multi-client protocol supportin Virtex-II Pro and Virtex-II Pro X high-speed RocketIO™ transceivers enablesseamless communication with protocolsoperating at up to 10.3125 Gbps.Coupling this technology with the

embedded PowerPC™ processor enablesnot only client adaptation, but also real-time control and processing capabilitieswithin a single FPGA.

Implemented on these platforms andcombined with a suite of additional Xilinxintellectual property, the new GFP core

Some aspects of the GFP protocol arecommon to all implementations. Thisincludes options such as frame delineationand synchronization; CRC insertion/detec-tion/correction; and scrambling.

In addition to the common aspects ofthe GFP protocol, client-specific functionsare required to handle unique differences inprotocol mapping. This includes optionsspecific to the two types of client data map-ping: frame-mapped (GFP-F) and trans-parent-mapped (GFP-T). Table 1 lists all ofthe GFP-F and GFP-T protocols support-ed in the G.7041 specification.

GFP-F supports variable-sized packetlengths of framed data, where one clientframe (such as an Ethernet frame) mapsdirectly into one GFP-F frame. Thisrequires a media access controller (MAC)in the system to terminate the Layer 2 pro-tocol. In Ethernet, for example, anEthernet MAC removes the preamble andstart of frame delimiter, checks the CRC,and passes the Ethernet frame to the GFPend-point for encapsulation.

GFP-T supports fixed-sized packetlengths and transports block-coded constantrate bitstreams (such as Fibre Channel,Ethernet, or ESCON/SBCON). This gen-erates a GFP frame that encapsulates block-coded data, which contains the clientprotocol 8B10B data and control (symbols)that are mapped to 64B65B block codes.

The transparent-mapped protocol doesnot require that application buffers com-plete frames before transmission. Instead,both data and control symbols are accumu-lated. Eight 8B/10B symbols (plus a flagbit) are combined to create a 64B/65Bblock code. This block code will includeboth data words and control characters.

Eight 64B/65B block codes are thencombined to create superblocks (65 bytes ofdata + CRC16). Multiple superblocks arecombined to create the GFP payload, wherethe number of superblocks per frame is pro-tocol-specific (95 for Gigabit Ethernet and13 for Fibre Channel). GFP-T does notrequire MAC functionality, as it is notional-ly transparent to the protocol transmitted.

The selection of GFP-F versus GFP-Tdepends on the application and systemrequirements. GFP-F provides bandwidth

provides a fully configurable way to imple-ment custom solutions that can dynamical-ly adapt in a rapidly changing environment.

The GFP SpecificationThe GFP uses an octet-based stream ofdata that maps directly into an octet-syn-chronous stream, such as synchronousoptical network/synchronous digital hierar-

chy (SONET/SDH). GFPframes are scrambled toensure DC balance and run-ning disparity, and they aredelineated by using a lengthfield within the core header,as shown in Figure 1.

Because the start and endof the frame is embeddedwithin the GFP stream, syn-chronization of the two GFPend-points must first occur toensure that data can be trans-mitted. Synchronization at anindividual end-point is

achieved by the detection of a correct CRCover the core header, then using the lengthfield to point to the start of the followingframe. Once this process is successfullyrepeated a programmable number of times,the GFP stream is synchronized, and datacan be transmitted.


Core Header

Payload Area Options:- Payload Scrambler/ De-scrambler

Core Header Options:- Header Scrambler/De-scrambler- CRC-16: cHEC Generate/Check/Correct- Frame Delineation (Synchronization)

Payload Header

Linear Extension Header(Optional)

Payload Information Field Payload Info Field Options:- Transparent-Mapped: Assembles/ Disassembles Superblock for Transmission- Frame-Mapped: Transmits/Receives User Data

Extension Header Options:- CRC-16: eHEC Generate/Check/Correct

Payload Header Options:- CRC-16: tHEC Generate/Check/Correct

Frame Check Sequence (FCS)CRC-32

(Optional)

FRAME MAP PROTOCOLS TRANSPARENT MAP PROTOCOLS

Ethernet Fibre Channel

PPP Gigabit Ethernet

RPR (IEEE 802.17) ESCON

FC-BBW DVB ASI

Multiple-Access Protocol Over SDH (MAPOS)

FICON

Asynchronous FC

Table 1 – Client network protocols supported by GFP

Figure 1 – GFP core options for frame processing

efficiency by ensuring that only actual datais transmitted, whereas GFP-T transmitsall information including data, framingcodes, preamble, and idles.

GFP-F incurs higher latency throughthe system, because complete frames mustbe buffered before transmission. This mayimply the use of external memory, depend-ing on the system.

GFP-T does not require complete frametransmission, and therefore can achievelower system latencies. In practice, trans-mission over long distances will incur alatency (due to the medium) that requiresadditional functionality in the client adap-tation layer to ensure that the protocols’latency requirements are met. This is called

“spoofing” and is critical for some clientprotocols, such as Fibre Channel, wherestrict latency requirements exist.

Xilinx GFP CoreXilinx offers a GFP IP core solution that sup-ports all of these protocols and fully imple-ments the G.7041/Y.1303 specificationdefined by the ITU-T. This includes system-level capability of end-to-end frame delin-eation, support for both client managementand data frames, and configuration of frameor transparent mapping on a per-channelbasis. In addition to supporting all of the fea-tures specified by G.7041, the Xilinx solu-tion also provides options to facilitatesystem-level integration and debugging.

With the Xilinx CORE Generator™tool, you can easily configure the GFP coreto support your system requirements,selecting one of three operating modes:frame-mapped, transparent-mapped, ormixed mode. Mixed mode enables you tospecify on a per-channel basis whether thechannel is frame- or transparent-mapped.You can also change the mode through theGFP host interface.

The core also provides optional supportfor linear extension headers, which can beconfigured for as many as 10 unique chan-nels. You can select an optional generichost interface that enables you to modifythe control and status registers in real time.Some of the key system features of the GFPcore are highlighted in Figure 2.

Using the CORE Generator system,you can fully customize the behavior of thecore. A specific configuration determineshow the core processes frames and alsodetermines the resources required forimplementation. The composition of aframe and the options provided are illus-trated in Figure 1.

The GFP core is split into a MAP coreand an UNMAP core, as illustrated inFigure 3. The MAP core receives client net-work protocol data (such as Ethernet) onthe system interface, encapsulates this data,and transmits the resulting frames on theline interface (such as SONET).

The UNMAP core does the sameprocess in reverse, receiving encapsulateddata on the line interface and de-mappingthe frames to extract client network proto-col data, which is in turn transmitted on thesystem interface. The GFP core utilizes theXilinx LocalLink interface standard on theline and client interfaces for direct connec-tion to other cores and reference designs.

In frame-mapped mode, the client sup-plies the MAP core’s system interface witha complete data frame, which is then trans-mitted without pause. In the transparentmapped mode, the MAP core automatical-ly handles underflow by inserting padwords into the frame so that the client doesnot have to provide uninterrupted framesof data.

Each core has a host interface (aPowerPC™ device control register [DCR]


GFPCore

SPI-4.2Core Framer

Xilinx GFP Core Supports: End-to-End Frame Delineation (Synchronizatiion)

Client Data Frames and Client Management Frames

Multiple Channels

Frame-Mapped, Transparent-Mapped, Mixed-Mode

OC-48 and OC-192 Line Rates

Forced Transmission of Corrupted Frames

Reference Designs for Packet Buffering/Arbitration

Microprocessor Interface (PPC DCR Bus)

SPI-4.2Core

GFPCoreFramer SONET

SystemInterface

Data(Local Link I/F)

MAP CORE

Sys

tem

Inte

rfac

e (t

o C

lien

t)

Lin

e In

terf

ace

(to

SO

NE

T)


Control and

Status (DCR)

Line Interface

HostInterface

SystemInterface


UNMAP CORE


Control and

Status (DCR)

Line Interface

HostInterface

Figure 2 – Features supported by the Xilinx GFP IP core, enabling system solutions

Figure 3 – Block diagram of GFP IP MAP and UNMAP core interfaces

bus) that provides access to a bank of con-trol and status registers. If you only requirethe default control signals, you can config-ure the core without status registers toreduce the number of resources.

Xilinx Complete SolutionsXilinx provides a complete and versatilesolution that allows you to configure theFPGA for your system needs. A myriad ofapplications exist for GFP, and the archi-tecture and requirements of the system willdrive any given set of requirements.

For example, if you are utilizing aframer that is GFP-aware, you can config-ure the GFP core to enhance the framer bysupporting options that the framer doesnot. Common examples of this includechannelization using the linear extensionheader, or transparent map mode.

If the application is using a framer thatis not GFP-aware, you can configure theGFP core to perform all GFP functional-ity, including frame delineation and syn-chronization, CRC, and scrambling.Using CORE Generator software enablesyou to specifically craft the implementa-tion that meets your requirements, andthus minimize the resource utilization ofthe FPGA.

In addition to the GFP core, otherXilinx solutions enable the implementationof a complete system to transfer Ethernetor Fibre Channel over SONET. Some ofthese additional solutions are illustrated inFigure 4 and described below:

• Configurable PCS (CPCS) Xilinxapplication note XAPP739 demon-strates how to utilize Virtex-II ProMGTs by providing a configurablePCS for a suite of protocols (FC [1G,2G], ESCON/SBCON, and GE). Itdynamically controls the PCS mode on each port, using the PowerPC and scales to support as many as eightchannels in both transparent and frame map modes.

• The System Packet Interface level 4phase 2 (SPI-4.2) IP solution providesa fully compliant core to address thedata path connectivity between POS(Packet Over SONET) physical layer

devices and link layer devices in net-working and communications systems.The SPI-4.2 core offers support for aresource-optimized OC-48 (2.5 Gbps)interface and a high-performance(greater than 14 Gbps) interface toconnect network processors with OC-192 framers and mappers, as well asgigabit and 10 Gigabit Ethernet data-link MACs.

• The 1GE MAC IP core solution pro-vides a half- and full-duplex 1 GbpsMAC controller designed to IEEE802.3-2002. The MAC core performsthe link function of the GigabitEthernet standard. The core can inter-face to an off-chip PHY using thecore’s gigabit media independent inter-face (GMII). Alternatively, it can bedelivered with an integrated1000BASE-X PCS with a ten-bit inter-face (TBI), or a 1000BASE-X PCS andPMA using the integrated RocketIOtransceiver in Virtex-II Pro devices.

• The buffer manager reference designdemonstrates how to interface to exter-nal DDR-RAM to buffer data on aper-channel basis.

• The Fibre Channel reference designdemonstrates some of the specificrequirements for transmitting FibreChannel over a SONET/SDH networkoutside of the GFP specification. Thisincludes an example flow control

mechanism that address the latency-sensitive Fibre Channel requirements.

• Xilinx reference design XAPP695demonstrates an example sub-systemintegration in Virtex-II Pro devicesfor a multi-channel Gigabit Ethernetto SPI-4.2, complete with PowerPCcontrol plane. This topic was coveredin the Summer 2004 issue of the Xcell Journal, in the article, “EthernetAggregation of GFP Framing inVirtex-II Pro.” The design does notinclude the core described here.

ConclusionThe Virtex-II Pro family of FPGAs pro-vides a powerful, flexible platform forimplementing networking solutions. Thehigh-speed serial MGTs and PowerPC,combined with proven IP cores and refer-ence designs, provide pre-verified solutionsfor managing and transporting a wide vari-ety of data protocols.

The ITU-T GFP specification providesa flexible and efficient mapping of thesedata protocols onto a transport network.Using Xilinx Virtex-II Pro FPGAs com-bined with the GFP core, you can quicklyand reliably apply this new technology toyour SONET/SDH systems and imple-ment a solution crafted to address your spe-cific system requirements. For moreinformation, visit www.xilinx.com/products/design_resources/conn_central/index.htm.


FCConfigurable

PCS (XAPP739)

MAC Core1000 Base-X

Reference Designs:

FibreChannel

RD

BufferManager

RD

(xN Links)

Ethernet

FC

Ethernet

ConfigurablePCS (XAPP739)

MAC Core1000 Base-X

GFPCORE

GFP-TGFP-F

Mixed Mode

SPICORE

SPI-4.2SPI-4.2 Lite

SPI-3

SONETFramer

RAM

Figure 4 – A GFP application example of Ethernet over SONET and FC over SONET

by Narinder LallSenior Manager, DSP Product and Solutions MarketingXilinx, [email protected]

The demands of next-generation wirelessinfrastructures require system designers toaddress not only processing bottlenecks butconnectivity bottlenecks. Xilinx® FPGAsprovide the ideal mix of high-performanceDSP to handle the most demanding chip-rate and radio algorithms and serial MGTs,addressing high-speed connectivity andinteroperability challenges.

Tomorrow’s wireless infrastructureequipment designers will face an increasein algorithmic complexity and data ratebrought on by the convergence of data,video, and voice. Solutions based on dis-crete devices such as microprocessors,DSPs, and transceivers provide tremen-dous headaches related to interoperabilityand latency, and can quickly drive up bothcost and power per channel.

An FPGA-centric approach that com-bines Xilinx high-performance DSP capa-bility and serial RapidIO™ (SRIO) willhelp alleviate some of these system per-formance bottlenecks and provide an inte-grated solution that better meetseconomic and energy constraints. In addi-tion, an FPGA-centric approach allowsyou the flexibility to recover from mis-takes and make hardware changes evenafter system deployment, thereby reduc-ing overall design risk.

The DSP Industry Embraces SRIOFigure 1 shows that in the late 1990s, GSMsystems that provided voice communica-tions only supported terminal data ratesbelow 10 kbps. In contrast, W-CDMA sys-tems, which started rolling out in 2002,needed to support voice, data, and video,and hence used 2 Mbps data rates. Futuresystems such as W-CDMA (HSDPA) andCDMA2000 (1xEV-DO and DV) will usedata rates greater than 2 Mbps.

Designers have implemented ASICs –and more increasingly FPGAs – in wirelesssystems to handle digital radio (modula-tion/demodulation, DDC/DUC) and high-chip-rate processing. FPGAs exploit parallelprocessing techniques through hard-wired

embedded multipliers and provide you withthe flexibility to make algorithmic changeseven after system deployment, saving mil-lions in maintenance or field upgrade costs.

Second, the need to transport such highinformation packets presents new connectiv-ity challenges. Traditional buses are fast run-ning out of bandwidth. Wide parallel busesare becoming too complicated to design andincreasingly difficult to scale. As serial I/Otechnology begins to mature, wireless infra-structure equipment designers are lookingtowards system interconnect architecturesbased on MGTs to handle their transportproblems. This gives rise to potential chip-to-chip and board-to-board interoperabilityheadaches for system designers.

Designing Next-Generation Wireless Systems Designing Next-Generation Wireless Systems


GSM GPRS EDGE

TDMA

IS95a/b

2G 2.5G 3G 3.5G 4G

1xRTT

1xEV-D0

TD-SCDMA

W-CDMA

HSDPA

Wireless LANs

3xRTT

4G

1xEV-DV

9.6 kbps 114 kbps 384 kbps

9.6 kbps

14.4-64 kbps 153 kbps

2.4 Mbps

2 Mbps

>2.4 Mbps

>2 Mbps

IEEE 802.11IEEE 802.16

Current Being Deployed Development Future

An FPGA-centric approach using XtremeDSP and serial RapidIO solutions.

Figure 1 – Mobile technology roadmap

What is encouraging is thatleading DSP IC suppliers thatsupply chip-rate and symbol-rate processing solutions (suchas Texas Instruments™,Motorola™, and Xilinx) are atthe forefront of the SRIO revo-lution and are keen to addressconnectivity and interoperabili-ty challenges in next-generationwireless infrastructure systems.

DSP processor vendors areprojected not to start samplingproducts for some time, but as asystem designer, you can startyour development today usingXilinx Virtex-II Pro™ FPGAs,which incorporate high-perform-ance DSP capability, SRIO connectivity, andeven control functions through embeddedPowerPC™ 405 processors.

As chip-rate processors, FPGAs providean ideal complement to DSP processors,which have traditionally been used forlower sample- and symbol-rate processing.

SRIO Benefits Using Virtex-II Pro FPGAsSerial RapidIO technology using Virtex-IIPro FPGAs provides a number of benefits towireless infrastructure equipment designers:

• High-performance throughput provides the necessary bandwidth to cope with next-generation data transport needs.

Combining Xilinx XtremeDSP and SRIO TechnologyThe availability of SRIO-basedASICs, FPGAs, and DSPs givesyou a number of options forimplementing your wirelessinfrastructure systems. One suchimplementation could use aVirtex-II Pro FPGA solely as acentral switch between chip andsymbol-rate devices.

A more integrated option(shown in Figure 2), based ondistributing the switching tomultiple Virtex-II Pro devicesthat can also handle high-per-formance DSP for multi-chan-nel radio and chip-rate

processing, provides a more integrated,cost-effective approach.

Xilinx high-performance DSP capabili-ty lies at the heart of much of today’s sec-ond- and third-generation wirelessinfrastructure equipment. In addition tohundreds of 18 x 18 embedded multipli-ers for implementing custom algorithms,you can also use Xilinx DSP IP cores fordemanding functions such as digitalup/down conversion and forward errorcorrection (such as 3GPP2 TCC, TPCdecoding, and Viterbi decoding). You canfind out more about the XilinxXtremeDSP™ solution by visitingwww.xilinx.com/dsp/.

ConclusionWith the addition of SRIO technology,Xilinx Virtex-II Pro FPGAs provide systemdesigners with another means to furtherenhance system throughput, lower cost-per-channel, and retain the flexibility of anFPGA-centric solution.

Figure 3 shows that the Xilinx SerialRapidIO IP core provides a complete end-point solution comprising transport, logi-cal, and physical layers, and also complieswith Revision 1.2 of the specification,including Errata 1. It supports all recoverymechanisms: packet retry, stomp, linkrequest, and CRC.

For more information on the Xilinx SerialRapidIO core, visit www.xilinx.com/rapidio/.

• Lower complexity software and an abilityto complete peer-to-peer transactionssimplifies systems. In addition, it alsoprovides a well-defined mechanism forcongestion control.

• A flexible, low-risk solution offers scala-ble bandwidth options for futuredemands and fast time to market.

• With many DSP and other system IC(microprocessor, ASIC) vendors commit-ting to SRIO, designers will have archi-tectural flexibility. Virtex-II Pro FPGAscan provide interoperability security.

• Lower system cost through the use of asmall silicon footprint and high band-width efficiency.


C6416C6416

ASIC

ASIC

ASIC

.

.

.

SRIO

SRIOSwitching

PCI

SRIO

SRIO

SRIO

SRIO

RFDemodulation, DDC

and Chip Rate Symbol Rate

Bac

kpla

ne

HOST

RocketIO

Fabric

• IP Core – Implemented in a Standard Virtex-II Pro FPGA

• Fully Compliant with RapidIO Interconnect Specification v1.2 Including Errata 1 – Implements All Three Layers

UserLogic

Register Manager

RapidIOFabric

I/OLogical &Transport

Layer

BufferModule

PhysicalLayer

Module Implementation in a 2VP50• 17% Utlization

• One RocketIO Transceiver

Figure 2 – Serial RapidIO usage example in wireless infrastructure

Figure 3 – Xilinx Serial RapidIO endpoint

by Sam SanyalSolutions Marketing ManagerXilinx, [email protected]

Conformance tests are one of the mostimportant items for embedded platforms likethe Xilinx® Virtex™ and Spartan™ familyof FPGAs. As these platforms are built onmultiple building blocks, using standards-based technology that is independently test-ed addresses key issues such as acceleratedtime to market and interoperability. GettingXilinx products tested also demonstrates ourcommitment to the technology.

Xilinx is the first FPGA vendor in theindustry to meet the University of NewHampshire (UNH) IEEE 802.3 standardfor Xilinx 10/100, 1 Gbps, and 10 GbpsMAC conformance tests. The UNHInterOperability Lab (IOL) tests are key inestablishing our product line, winningdesigns, and building customer confidence.

Adhering to standards and undergoingtesting by reputable organizations like theUNH IOL ensures interoperability betweensystems, networks, and applications.Because enterprises have the flexibility tochoose best-in-class solutions, conformancetesting fosters competition and innovationbetween solution providers.

Meeting Interoperability Standards Meeting Interoperability Standards


The University of New Hampshire InterOperability Lab completes conformance testing for the Xilinx Ethernet family.The University of New Hampshire InterOperability Lab completes conformance testing for the Xilinx Ethernet family.

Why UNH IOL Conformance? The UNH IOL has the longest history offostering interoperability and conformancein connectivity technologies. Throughtheir independent testing methodologyand relationships with major corporationsand industry engineers, numerous compa-nies have refined their technologies andextended their products’ compatibility.

Specification standards are establishedin the hope that products from differentvendors can interoperate with each other;for example, that two Ethernet cards pur-chased from two different vendors willcommunicate. This enables you to choosethe system that best meets your needs foreach application.

In the past, some vendors made claimsof interoperability that were not quiteachieved. However, this is not the case any-more; a number of vendors have successful-ly tested interoperability together at theUNH IOL. The limitations are betteraddressed through their tests.

A successful UNH conformance test isa confidence builder that ensures projectsuccess in the shortest possible develop-ment time.

The UNH IOL features: • A neutral environment. A win-win sit-

uation for everyone involved, neutrali-ty is achieved by using standard testbeds, methodologies, and tools.

• Industry involvement. The IOL’s par-ticipation in various trade associationsand standards organizations keeps thelab appraised of the latest develop-ments in technology. In turn, the IOLeffects positive change in standardsorganizations by providing technicalcontributions, editorial assistance, veri-fication, and feedback during standardsdevelopment.

• Enhanced image and visibility. The UNH IOL testing consortium’srelationship with industry leaders

• Frame Length Test

• Minimum Received Inter-Frame Gap

• Transmit Preamble Test

• Minimum Transmitted Inter-Frame Gap

• Defer to Carrier Sense While FrameWaiting

• Deference after Collision

• Do Not Defer Test (Full Duplex)

Flow control conformance testingincluded the following test suites:

• Receive PAUSE Frame with Zeropause_time

• Receive PAUSE Frame with Non-Zeropause_time

• Resume Transmission

• Discard Invalid PAUSE Frames

• Receive JUMBO MAC ControlPAUSE Frames

• Receive RUNT MAC Control PAUSEFrames

• Receive MAC Control PAUSE Frameswith Incorrect CRC

• PAUSE Frame Transmission

PCS conformance testing included thefollowing test suites:

• End of Stream Delimiter Test

• Invalid Data Symbol Test

• False Carrier Detect

Figure 1 shows a block diagram of thetest setup of an Insight Virtex-II™ (DS-BD-V2MB1000) board with a P160 com-munications module (DS-BD-MBEXF1).

Tests Configuration for 1 GbpsThe Figure 2 block diagram of the testdesign based on the ML320 platformmakes use of the PowerPC™ processor inVirtex-II Pro™ devices as well as an inter-

(Cisco Systems™, Broadcom™,Cadence™, Dell™, HP™,Conexant™, Brocade™, and3Com™) works as an indirect advertising tool for your products.

• Excellence in testing services. Throughindustry-recognized standardized andcustom test suites, expertise, advancedtesting facilities and equipment, openand widely reviewed testing proceduresfor both conformance and interoper-ability testing creates confidence inyour product with plug-and-play capa-bility in a heterogeneous network.

Test RoutinesMany more tests are available from theUNH IOL, but the tests listed here wereperformed on Xilinx devices.

Tests Configuration for 10/100 MAC conformance testing included thefollowing test suites:

• Collision Detect/Enforcement Test(Half Duplex)

• Collision Detection Timing SensitivityTest (Half Duplex)

• Late Collision Detection Test (HalfDuplex Only)

• Retransmission Attempt Limit Test(Half Duplex Only)

• Collision Backoff Algorithm (HalfDuplex Only)

• No Collision Test (Full Duplex Only)

• FCS Error Test

• Alignment Error Test

• Fragment/Runt Test

• Large Frame Test

• Jabber Frame Test

• Received Preamble Test

• Start of Frame Delimiter Test


A successful UNH conformance test is a confidence builder that ensures project success in the shortest possible development time.

nally developed asynchronous FIFO andwith firmware developed in C.

MAC conformance testing included thefollowing nine test suites:

• Frame with FCS Errors

• Fragments and Runts

• Transmit Proper SFD and Preamble

• Receive Variable Preamble

• Does Not Defer

• No Collisions

• No Extension

• No Bursting

• Transmission of Minimum Inter-Frame Gap

Flow control conformance testingincluded the following five test suites:

• Receive PAUSE Frame with Zeropause_time

• Receive PAUSE Frame with Non-Zeropause_time

• Resume Transmission

• Receive PAUSE Frames of Incorrect Size

• PAUSE Frame Transmission

The UNH IOL also performed PCS,Auto-Negotiation, and Point-to-PointInteroperability tests.

Tests Configuration for 10 GbpsThe UNH IOL performs MAC tests onthe frame reception and frame transmis-sion. The frame reception tests cover MACoperations specific to reception of frames,designed to verify that the device undertest (DUT) properly receives valid frames,discards frames with errors, and reportsthese errors if possible. The test setup wasdone according to the block diagramshown in Figure 3.

The UNH IOL performed these specif-ic tests on the Xilinx DUT:

• Frames Greater than Max Frame Size

• Frames with Length Errors

• Receive All Frame Sizes 64-1518 (or1,522) Bytes

The frame transmission tests coverMAC operations specific to the transmis-sion of MAC frames, designed to verifythat the DUT transmits properly formedMAC frames.

They also performed these specific testson the DUT:

• Transmit Proper Length within theLength/Type Field

• Compute and Transmit Proper CRC

• Transmission of Minimum Inter-FrameGap

Figure 3 shows the setup used through-out the testing process. An arbitrary wave-form generator (AWG) is used to generate

the required clock signals. A PC communi-cated with the testing station usingNational Instruments’™ LabView soft-ware, to download firmware for the DUTand access Xilinx ChipScope™ embeddedlogic analyzers.

The XGMII interface of the DUT wasused to provide access below the MAClayer in all test cases. Using multipleChipScope embedded logic analyzers forbus monitoring and a transmit frame gen-erator module obtained access above theMAC layer.

Reconciliation sublayer tests aredesigned to verify that the DUT reactsproperly to the receipt of data, both validand invalid, at the reconciliation sublayer.


PatternGenerator FIFO

ILA

MAC

ILA

PowerPC UART RS=232

PCS/PMA

LMB BRAMIF_CNTRL

LMB BRAMIF_CNTRLBRAM Block

LMB_V10

MicroBlaze

OPB_V20

OPB JTAGUART

OPB INTC OPB EMC

OPB UARTLITE

OPB Ethernet

P160SRAM

P160Ethernet PHY

External to FPGA

Main Serial Port

Debug

SYS CLK/RST

Figure 1 – Tests Configuration for 10/100

Figure 2 – Tests Configuration for 1 Gbps

The UNH IOL performed these specifictests on the DUT:

• Start Control Character Creation andAlignment

• Reception of Start Control Character

• Reception of Preamble and SFD

• Reception of Terminate ControlCharacter

• Assertion of DATA_VALID_STATUS

• Reception of /E/ duringDATA_VALID_STATUS

• Continuous Reception of FaultSequences

• Reception of Identical Fault Sequences

• Reception of Non-Identical FaultSequences

• Setting of col_cnt

The Value PropositionXilinx is the industry’s only FPGA vendorthat has its complete Ethernet IP productfamily neutrally tested to IEEE 802.3 stan-dards conformance and interoperability.These tests on the Ethernet IP product fam-ily of 10/100, 1 Gbps, and 10 Gbps speedsensure the following value proposition:

• Proven interoperability with industry-standard equipment

• Reduced hardware testing burden for cus-tomers

• First-time design success and seamlessoperation (such as plug-and-play)

This invaluable approval builds customerconfidence with low risk and accelerated timeto market, while conformance testing alsoshows the company’s commitment to quality.

ConclusionUnderstanding interoperability is the key tomarket acceptance and opportunity.Interoperability means plug-and-play opera-tion that works within your environment andapplication, independent of who provided theproduct.

The UNH IOL Consortium acts as anextension of research and development labs,helping members test their products for con-formance to industry standards and interoper-ability between devices from differentmanufacturers.

Xilinx is the only FPGA vendor to success-fully bring the complete Ethernet solution tothe market with the certification of the UNHIOL. With proven interoperability, you canconfidently built a system for first-time designsuccess, meet your design goals, and acceleratetime to market instead of worrying about theunderlying infrastructure.

For more information, visit www.xilinx.com/systemio/interop.index.htm.


Lab View Interface

PC

Parallel Port Serial Port

JTAG Interface

Oscilloscope

XGMII Tx

Logic Analyzer

AWG

XGMII Rx XGMII Tx

Xilinx FPGA Main Board(Testing Station)

MicroBlaze uController

ILA Core (ChipScope)

RX Good Frame RX Bad Frame

External Clk

(156.25 MHz)

Xilinx 10 GbE Test Board (DUT)

Figure 3 – Tests Configuration for 10 Gbps

Xilinx Events and Tradeshows

Xilinx participates in numerous trade shows and events throughout

the year. This is a perfect opportunity to meet our silicon and software experts, ask questions, see demonstrations of new

products and technologies, and hear other customers’ success stories with

Xilinx products.For more information and the most up-to-date schedule, visit

www.xilinx.com/events/.

Worldwide Events Schedule

North AmericaJuly 20-21 Nuclear and Space Radiation Effects

Conference (NSREC) Atlanta, GA

September 14 Mentor Graphics EDA Tech Forum Ottawa, ON

September 14-15 Embedded Systems ConferenceBoston, MA

September 27-30 Global Signal Processing Expo (GSPx) Santa Clara, CA

October 18 Mentor Graphics EDA Tech ForumSan Jose, CA

October 18-20 Convergence Detroit, MI

Europe17 July Mentor Graphics EDA Tech Forum

Munich, Germany

6 October Mentor Graphics EDA Tech ForumReading, UK

20 October Boundary-scan Design For Test (DFT)European Seminar SeriesFrankfurt, Germany

Asia Pacific13 August Mentor Graphics EDA Tech Forum

Shanghai, China

16 August Mentor Graphics EDA Tech Forum Beijing, China

18 August Mentor Graphics EDA Tech ForumSingapore

20 August Mentor Graphics EDA Tech ForumBangalore, India

24 August Mentor Graphics EDA Tech ForumHsin Chu, Taiwan

2 September Mentor Graphics EDA Tech ForumSeoul, South Korea

Japan26-27 August Mentor Graphics EDA Tech Forum

Tokyo

31 August Mentor Graphics EDA Tech ForumKyoto

North AmericaJuly 20-21 Nuclear and Space Radiation Effects

Conference (NSREC) Atlanta, GA

September 14 Mentor Graphics EDA Tech Forum Ottawa, ON

September 14-15 Embedded Systems ConferenceBoston, MA

September 27-30 Global Signal Processing Expo (GSPx) Santa Clara, CA

October 18 Mentor Graphics EDA Tech ForumSan Jose, CA

October 18-20 Convergence Detroit, MI

Europe17 July Mentor Graphics EDA Tech Forum

Munich, Germany

6 October Mentor Graphics EDA Tech ForumReading, UK

20 October Boundary-scan Design For Test (DFT)European Seminar SeriesFrankfurt, Germany

Asia Pacific13 August Mentor Graphics EDA Tech Forum

Shanghai, China

16 August Mentor Graphics EDA Tech Forum Beijing, China

18 August Mentor Graphics EDA Tech ForumSingapore

20 August Mentor Graphics EDA Tech ForumBangalore, India

24 August Mentor Graphics EDA Tech ForumHsin Chu, Taiwan

2 September Mentor Graphics EDA Tech ForumSeoul, South Korea

Japan26-27 August Mentor Graphics EDA Tech Forum

Tokyo

31 August Mentor Graphics EDA Tech ForumKyoto

Xilinx Alliance EDA Members and Products

AccelChipwww.accelchip.comHigh-level synthesis tools that read MATLAB and output RTL

Alatekwww.alatek.comHardware acceleration (HES)

Altiumwww.altium.com/nexar/Low cost, system level tool for targetingSpartan™ series FPGAs

Ansoftwww.ansoft.comHigh-frequency products for system analy-sis, circuit design, and electromagnetic sim-ulation (Ansoft Designer™, HFSS™)

Apache Designwww.apache-da.comHSPICE®-compatible simulator using actu-al S-parameter data (NSPICE) for Virtex-IIPro™ MGT-based PCB design

Aptixwww.aptix.comASIC emulation (Prototype Studio™)

Atrentawww.atrenta.com/partners/index.htm#xilinxRTL Linter technology for Virtex™-II andVirtex-II Pro FPGAs (SpyGlass®)

Auspywww.auspy.comFPGA partition (APS II) and ASIC emula-tion (ACE Compiler)

Cadence Design Systemswww.cadence.comVirtex-II Pro MGT support for high-speedPCB design (Allegro® PCB SI); NCSimfamily for FPGA design simulation; NC-Protect support for Xilinx EDK IPs

Celoxicawww.celoxica.comC-level design creation, compilation, andverification for Virtex-II™ and Virtex-IIPro FPGAs

Endeavorwww.endeav.comCo-verification for Virtex-II Pro(CoSimple™)

EVEwww.eve-team.comRTL-level simulator accelerator (ZEBU)

Forte Designwww.forteds.comHLL compiler to RTL (Cynthesizer); tim-ing specification and analysis tool(TimingDesigner)

MAGMAwww.magma-da.comArchitecture-specific synthesis and layoutoptimization for Virtex-II series FPGAs(PALACE™ and Blast FPGA™)

The MathWorkswww.mathworks.comSystem-level design tools for FPGA andprocessor-based signal processing systems

Mentor Graphicswww.mentor.comVirtex-II Pro MGT support for high-speedPCB design (HyperLynx™, ICX™,Tau™); complete FPGA design flow usingthe ModelSim® family of simulators andPrecision® RTL and Precision Physical syn-thesis; Seamless® co-verification support forVirtex-II Pro; FPGA symbol generation forfast PCB design iterations for Virtex-II andVirtex-II Pro FPGAs (IO Designer)

Novilitwww.novilit.comDesign partitioning using ISE EDK(AnyWare) for Virtex-II and Virtex-II ProFPGAs

Product Acceleration Inc.www.prodacc.comFPGA symbol generation(LiveComponent™); automated pin assignment optimization for PCB layer and via count control (DesignF/X)

Simucadwww.simucad.comVerilog simulator for FPGAs (Silos)

Synopsyswww.synopsys.comVirtex-II Pro multi-gigabit transceiversupport for high-speed PCB design(HSPICE); DC FPGA RTL synthesis forVirtex series and Spartan-3™ familyFPGAs; VCS™(MX)/Scirocco™(MX)simulators; Formality® formal verifica-tion, LEDA® RTL linter, andPrimeTime™ static timing analysis

Synplicitywww.synplicity.comRTL synthesis (Synplify®), RTL leveldebugger (Identify™), physical synthesis(Amplify®), and ASIC prototyping(Certify®) for Xilinx FPGAs

Impulse Cwww.impulsec.comC language hardware/software co-develop-ment tool for Xilinx FPGAs(CoDeveloper™)

Summit Designwww.summit-design.comCapture and verify designs in C/C++ orSystemC (Visual Elite™)

ProDesignwww.uchipit.com/ce/index.htmFPGA prototyping system (CHIPit™)



Xilinx AllianceCORE Third-PartyIP Providers and Products

4i2i Communications Ltd.www.4i2i.comVideo coding, modems (OFDM), errorcorrection

Amirix Systems, Inc.www.amirix.comEmbedded systems

Amphion Semiconductor, Ltd.www.amphion.comDSP, wireless communications, and multi-media cores

Avnet Design Serviceswww.ads.avnet.comStrong-ARM to PCI bridge, SDRAM controller

Barco-Silexwww.barco-silex.comDSP cores, with a specialization in image-audio applications

Calyptech Design Serviceswww.calyptech.comPacket over SONET, ATM, xDSL

CAST, Inc.www.cast-inc.comGeneral-purpose IP for processors, peripher-als, multimedia, networking, encryption,serial communications, and bus interfaces

Crossbow Technologies, Inc.www.crossbowip.comSystem Interconnect IP for on-chip andchip-to-chip multiprocessing

Deltatec S.A.www.deltatec.be/IP and services for digital imaging, DSP,multimedia, PCI, and datacom

Derivation Systems, Inc.www.derivation.comIP cores for high-assurance hardware/soft-ware applications and embedded systemsproducts; 32-bit Java processor core

Digital Communications Technologies, Ltd.www.dctl.comEmbedded Java solutions

Digital Core Designwww.dcd.plMicroprocessor, microcontroller, floatingpoint, and serial communication con-troller cores

Dolphin Integrationwww.dolphin-integration.comBus interface, processor, peripheral, andDSP cores; EDA software

Duma Video, Inc.www.dumavideo.comDigital video, AES/EBU audio, MPEGand DCT cores; real-time MPEG-2 HD and SD compression

eInfochips Pvt. Ltd.www.einfochips.comPCI, USB, 80186, multimedia, and wireless cores

Eureka Technologywww.eurekatech.comSilicon-proven IP for CPU interface, PCI,PCMCIA, memory control, and otherperipheral functions for SoC designs

GDA Technologies, Inc.www.gdatech.comHypertransport, PCI, Ethernet, designservices

HCL Technologies, Ltd.www.hcltechnologies.comIT services and product engineering companies with a focus on technology and R&D outsourcing

Helion Technology Limitedwww.heliontech.comEncryption and DSP algorithms; design services

iCoding Technology, Inc.www.icoding.comTurbo Code-related error correction products including system design

Intelliga Integrated Design, Ltd.www.intelliga.co.ukDigital automotive networks, embeddedserial communications, microcontrollerdesign

Loarant Corporationwww.loarant.comProprietary 16-bit RISC CPU; embedded system design

MEET Ltd.www.meet-electronics.comIP cores dedicated to industrial servo motor control

Memec Designwww.memeccore.comPeripheral, bus interfaces, encryption andcommunications cores

ModelWare, Inc.www.modelware.comDatacom/telecom cores including ATM,HDLC, POS, IMA, UTOPIA, and bridges

NewLogic Technologies AGwww.newlogic.comCores for wireless applications includingBluetooth and 802.11

Northwest Logicwww.nwlogic.comNetworking, digital video, embedded computing

Paxonet Communications, Inc.www.paxonet.comSolutions for interworking metro networking technologies to SONET

Pentek, Inc.www.pentek.comFPGA IP cores including FFTs, digitalreceivers, and pulse compressions algo-rithms; DSP, data acquisition, softwareradio boards, and system solutions

Phystream Ltd.www.phystream.comIntegrated hardware/software data processing systems, transmission (PDH,SDH, SONET), ATM, frame relay, LAN(Ethernet, FDDI), multiservice, wirelessprotocols

Pinpoint Solutions, Inc.www.asic-design.comStandards-based telecom and datacom IP;video

QinetiQ Limitedwww.quixilica.comFloating point cores, FPU forMicroBlaze™

RealFast Intellectual Property ABwww.realfast.seReal-time systems and RTOS; operatingsystem cores

Robert Bosch GmbHwww.can.bosch.comAutomotive; CAN

Roman-Jones, Inc.www.roman-jones.comDesign services: data acquisition, micro-processors (embedded and off-chip), auto-motive, PCI, analog design, DSP, video

SoC Solutions, LLCwww.socsolutions.comEmbedded µP and software; networking,wireless, audio, GPS and handheld; peripheral cores

X I L I N X P A R T N E R Y E L L O W P A G E S

SysOnChip, Inc.www.sysonchip.co.kr/IP and products for CDMAcellular/PCS/WLL modem, FEC and Bluetooth

Tensilica, Inc.www.tensilica.comConfigurable processors cores and development tools

TurboConceptwww.turboconcept.comTurbo code forward error correction solutions

Xylon d.o.o.www.logicbricks.comHuman-machine interfaces and industrialcommunication controllers; video

Zuken, Inc.www.zuken.co.jp/soc/PCI2.2,10/100 Ethernet and GigabitEthernet cores

Reference Design PartnersThe Xilinx Reference Design AllianceProgram builds partnerships with industry-leading semiconductor manufacturers todevelop reference designs for acceleratingour customer’s product and system time tomarket. The goal is to build a library ofhigh-quality, multicomponent system-levelreference designs in the areas of networking,communications, image and video processing, DSP, and emerging technolo-gies and markets.

Agere Systemswww.agere.com

AMCCwww.amcc.com

Analog Deviceswww.analog.com

Bay MicroSystemswww.baymicrosystems.com

BitBlitz Communicationswww.bitblitz.com

Broadcom Corp.www.broadcom.com

Centilliumwww.centillium.com

Cypress Semiconductorwww.cypress.com

IBM Microelectronicswww.ibm.com/us/

IDTwww.idt.com

Ignis Opticswww.ignis-optics.com

Infineon Technologies AGwww.infineontechnologies.com

Intel Corporationdeveloper.intel.com/design/network/

Intrinsitywww.intrinsity.com/home.htm

Micron Technologywww.micron.com

Motorolawww.motorola.com

National Semiconductor Corporationwww.national.com

NetLogic Microsystems, Inc.www.netlogicmicro.com

Octasic Semiconductorwww.octasic.com

PMC-Sierra Inc.www.pmc-sierra.com/index.html

Samsung Semiconductor, Inc.www.usa.samsungsemi.com

SiberCore Technologieswww.sibercore.com

Texas Instrumentswww.ti.com

TransSwitch Coporationwww.transwitch.com/index_flash.jsp

Vitessewww.vitesse.com

ZettaComwww.zettacom.com




XPERTS Partners

3T BVwww.3T.nl/Design services; measurement instruments;fail-safe controlling; medical equipment,communication, and computer peripherals

Accent S.r.l.www.Accent.it/Complex FPGAs; SoCs; PowerPCs™; IP platforms; software, PCB, and ICfoundry services, from concept to silicon

ADI Engineeringwww.adiengineering.comReference designs; custom designs; designservices focused on Intel IXA and XScale™

Advanced Electronic Designs, Inc.www.aedbozeman.comDesign services and manufacturing support;hardware and software design for embeddedsystems

Advanced Principles Group, Inc.www.advancedprinciples.comDesign services and consulting; softwarealgorithm acceleration and application-specific computing systems

Alpha Datawww.alpha-data.comPCI/PMC/CPCI FPGA boards; embeddedapplications using HDL or SystemGenerator methodologies

AMIRIX Systems Inc.www.amirix.comDesign services for electronic product realization; high-performance digital boards;programmable logic; embedded software

Andraka Consulting Group, Inc.www.andraka.comExclusively FPGAs for DSP since 1994;applications include radar, sonar, digitalcommunications, imaging, and video

Array Electronicswww.array-electronics.de/SoC/FPGA/PCB designs in telecom, industrial, and DSPs; concepts; verification;prototypes; cores

Avnet Design Serviceswww.ads.avnet.comEmbedded processing FPGA design services; Virtex-II Pro; high-speedSERDES; IP core integration; timing closure; RLDRAM; RapidIO™

Baranti Group Inc.www.baranti.comAward-winning design/manufacturing firm;expertise in digital video, FPGAs

Barco Silexwww.barco-silex.comTotal solutions consisting of IP, FPGA, and board design

Benchmark Electronics Inc.www.bench.comEMS/JDM team; product design, support,introduction, and launch into volume production

Birger Engineering, Inc.www.birger.comDevelopment of algorithms, electronics,and systems for digital imaging

BitSim ABwww.bitsim.comDesign services; DSP, video, 3G, andWLAN designs; high-speed prototypingboards

Bottom Line Technologies Inc.www.bltinc.comFPGA, product, and system design services;networking; data communications;telecommunications; video; PCI; signalprocessing; defense; aerospace

CES Design Services @ Siemens Program and System Engineeringwww.ces-designservices.comPlatform-oriented SoC/FPGA/PCB andfirmware design in telecom, industrial, andvideo processing; customized solutions;concept; verification; prototypes

CG-CoreEl Programmable Solutions P. Ltd.www.cg-coreel.comDesign services; telecom, networking, andprocessor IP and designs; turnkey FPGA;RTL design/validation

Chess iT/Embeddedwww.chess.nl/Embedded hardware and software design ofproducts and services at the chip, board,and system level

Colorado Electronic Product Design, Inc.www.cepdinc.comDesigning embedded systems with FPGAs for DSP; interfaces for medical,consumer, aerospace, and military

Comit Systems, Inc.www.comit.comHigh-end FPGA/SoC design services,including the integration of customer-developed and third-party IP

ControlNet India Pvt Ltd.www.controlnetindia.comASIC/SoC Analog/RF FPGA design services; IP development; domains:Ethernet, IEEE1394, USB, security, PCI,WLAN, Infiniband

Convergent Design LLCwww.convergent-design.comAudio/video design for professional/consumer products

DATA Respons ASAwww.datarespons.comProfessional design and development services for embedded hardware/softwaresolutions; FPGA/digital hardware applica-tion specialists

Deltatec International Inc.www.deltatec.be/Design services; digital imaging applica-tions; broadcast video, image processing, and image synthesis

Digicom Answers Pty. Ltd. www.fpga.com.au/Design services; experienced FPGAresources; design-on-demand; pre-designadvice; reviews and problem solving

Digital Design Corporation (DDC)www.digidescorp.comDesign services and products; image pro-cessing; video; communications; DSP;audio; automotive; controls; interfaces

Dillon Engineering, Inc.www.dilloneng.comDesign services; FPGA-based DSP algorithms; high-bandwidth, real-time digital signal and image processingapplications



DRS Tactical Systems West Inc.(formally Catalina Research)www.catalinaresearch.comDesign services; FPGAs for DSP, includingthe manufacturer of Virtex reconfigurablecomputing boards

Eden Networks, Inc.www.edennetworks.comTurnkey design services; telecom and net-working designs (Ethernet, SONET, ATM,VoIP)

Edgewood Technologies, LLCwww.edgewoodtechnologies.comDesign services; FPGAs for telecom, DSP,embedded processors

Enea Data ABwww.enea.se/Telecommunication, data communication,DSP, RTOS, automotive, defense, high-reliability, and consumer electronics design

Enterpoint Ltd.www.enterpoint.co.uk/Design services; development boards; video,telecommunications, military, and high-speed design

ESD Inc.www.esdnet.comDesign services; FPGAs for embedded systems, software/hardware design, PCBlayout

Evatronix S.A.www.evatronix.pl/Design services; FPGA design (Virtex,Virtex-E, Spartan-II); embedded systems;SoC and SoPC designs

Evermore Systems Inc.www.evermoresystems.comDesign services; FPGA designs for commu-nications, audio/video, wireless, and homenetworking

ExaLinx www.exalinx.comDesign services; ASIC emulation for high-speed communications and wireless applica-tions; reference designs

Fidus Systems Inc.www.fidus.ca/Design services; FPGAs; communications;video; DSP; interface conversions; ASICverification; hardware; PCB layout; soft-ware; SI/EMC

First Principles Technology, Inc.www.fptek.comDesign/assembly/test services; FPGA +PCB + DSP/processor + system; imaging;video; test; satellite telecom; control

Flexibilis Oywww.flexibilis.comIP development; FPGA design services;Linux™ device drivers

Flextronics Designwww.flextronics.com/design/Complete product design and developmentservices for high-speed communications;reconfigurable computing; imaging;audio/video; military

GDA Technologies, Inc.www.gdatech.comA leading services company focused ondesigning systems, SoC, ASIC, FPGA, and IP

HCL Technologieswww.hcltech.comHigh-speed board, ASIC, and FPGAdesign and verification services in avionics,medical, networking/telecom, and consumer electronics

Helion Technology Limitedwww.heliontech.comDesign services and IP for FPGA with afocus on data security, wireless, and DSP

IDERS Inc.www.iders.ca/Contract electronic engineering and EMSresource, providing complete product cyclesranging from specifications to production

Image Technology Laboratory Corporationwww.gazogiken.co.jp/Design services; FPGAs for image process-ing; design tools: EDK, System Generator,and Forge

Innovative Computer Technologyictconn.comDigital, analog, Xilinx FPGA, and softwaredesign solutions for customers in a widevariety of industries throughout the UnitedStates

iWave Systems Technologies Private Ltd.www.iwavesystems.comEmbedded hardware and software design;board design; FPGA and ASIC develop-ment services

Liewenthal Electronics Ltd.www.liewenthal.ee/Embedded systems design services; develop-ment of software and hardware includingVirtex and Spartan FPGAs

Logic Product Developmentwww.logicpd.comFull-service product development, includingindustrial design, mechanical, electrical, andsoftware engineering

M&M [email protected] services; imaging; video and audiodesigns; high-density ASIC emulation

Memec Design www.memecdesign.com/xilinx Focused on FPGA design for Xilinx technology, we have completed more than 1,300 designs worldwide

Memondo Graphicswww.memondo.comImplementation of digital signal processing,communications, and image processingsolutions and algorithms over Xilinx FPGAs

Mikrokrets ASwww.mikrokrets.no/FPGA development comprising telecom-munication, network communications, andembedded systems; PCB development

Millogic Ltd.www.millogic.comDesign services and synthesizable cores; expertise in PCI, video, imaging,DSP, compression, ASIC verification, and communications

Milstar Inc.www.milstar.co.il/Design services and manufacturers (industrial and military specs); DSP; communication; video; audio; high-speed boards

Misarc srl - Agratewww.misarc.comDesign services and manufacturers;telecommunications; SoC development; test equipment boards using FPGA solu-tions



Multi Video Designswww.mvd-fpga.comDesign services; DSP for video, telecom-muications; SoC with Virtex-II/Pro andSpartan (PowerPC/MicroBlaze); Xilinxtraining

Multiple Access Communications Ltd.www.macltd.comDesign services; products and consultancy;DSP for wireless communications

Nallatechwww.nallatech.comEmbedded reconfigurable computers forhigh-performance applications in DSP,imaging, and defense; Xilinx DiamondXPERTS

NetModule AGwww.netmodule.ch/Design services for system design; FPGAapplications in telecommunication systemsand medical electronics

NetQuest Corporationwww.netquestcorp.comTurnkey engineering design and produc-tion services in advanced high-speedembedded communications

North Pole Engineering Inc.www.northpoleengineering.comHardware and software design services forFPGA, ASIC, and embedded systems

Northwest Logicwww.nwlogic.comPCI, PCI-X, and SDRAM controller IP;high-end FPGA design services

NovTech Engineeringwww.novtech.comBoard-level and IP cores; turnkey designservices; imaging; communication; PCIcores; encryption

NUVATIONwww.nuvation.comDesign services; imaging and communica-tions for defense/security, medical, con-sumer, and datacom/telecom markets

Plextek Ltd.www.plextek.comDesign services; FPGA, DSP, radio,microwave, and microprocessor technolo-gies for defense and communications

POLAR-Designwww.polar-design.de/High-end FPGA design for telecom, networking, and DSP applications

Polybus Systems Corporationwww.polybus.comTest patterns; customizable in-systemFPGA test patterns; design services; net-working and communications

Presco, Inc.www.prescoinc.comTwenty-five years of experience in customelectronics design/manufacturing for high-performance image processing, data com-munications, inkjet

Productivity Engineering GmbH www.pe-gmbh.comDesign services; PCI design; microproces-sor cores; obsolete component replace-ments; ASIC prototyping

Programall Technologies Inc.www.ProgramallTechnologies.comDesign services; embedded systems target-ing Virtex, Spartan, Virtex-II, and Virtex-IIPro FPGAs

R&D Consulting972-9-7673074 FPGA development; video; imaging;graphics; DSP; communications

Rapid Prototypes, Inc.www.fpga.comDesign services; high-performance reconfig-urable FPGA applications requiring maxi-mum speed or density using physicaldesign principles

RDLABSwww.rdlabs.comFPGA/ASIC design; wireless communica-tions; 802.11b/a IP cores; MATLAB,Sysgen, ModelSim; instruments HP1661A,HP8594E, HP54520A

RightHand Technologies, Inc.www.righthandtech.comDesign services; Virtex-II Pro FPGAs,boards, and software for video gaming, storage, medical, and wireless

Rising Edge Technology Inc.www.risingedgetech.comComplete design solutions from theground up; FPGA interface designs

Riverside Machines Ltd.www.riverside-machines.comDesign services and project management;DSP, wireless, network, and processor development; Verilog™, VHDL,SystemC™, Specman

Roke Manor Researchwww.roke.co.uk/Design services; IP, ATM, DSP, imaging,radar, and control solutions for FPGAs

Roman-Jones, Inc.www.roman-jones.comDesign services; FPGAs for embeddedmicroprocessors; PCI; DSP; low-cost 8051softcore

Sapphire Computers, [email protected] design consulting; high-speeddigital and FPGA design

Siemens AG, Electronic Design Housewww.eda-services.comDesign services; system-on-chip; ASICs;FPGAs; IPs; DSPs; boards; EMC; embedded software; prototypes

Silicon & Software Systems Ltd. (S3)www.s3group.comWorld-class electronics design companyuniquely combining IC, FPGA, software,and hardware design expertise

Silicon Interfaces America Inc.www.siliconinterfaces.comDesign services; develops IP in areas of networking, wireless, optical, datacom,interconnect, and microcontrollers

Silicon System Solutions P/Lwww.silicon-systems.comDesign services; FPGAs for very high-speedapplications including communications andDSP applications

Siscad S.p.A.www.siscad.it/Xilinx FPGA design services; IP development and integration

Smart Logic, Inc.www.smart-logic.comDesign services; FPGAs for rapid prototyping including imaging, compres-sion, and real-time control


Micriµm Technologies Corp.www.ucos-ii.comµC/OS-II RTOS support for XilinxMicroBlaze 32-bit soft processor core

Mind NVwww.mind.be/v2p/ecosMind NV eCos RTOS support for Virtex-II Pro embedded PowerPC

MontaVista Softwarewww.mvista.comMontaVista® Linux® Professional Edition subscription support for Virtex-II Pro embedded PowerPC

Nohau Corporationwww.nohau.comEMUL-MicroBlaze-PC debugger support for Xilinx MicroBlaze 32-bit soft processor

QNX Softwarewww.qnx.comQNX® Neutrino® RTOS support for Virtex-II Pro embedded PowerPC

Wind River Systemswww.windriver.comVxWorks® RTOS support for Virtex-II Proembedded PowerPC; Diab™ XilinxEdition (XE) C/C++ Compiler;SingleStep™ Xilinx Edition debugger;visionPROBE II Xilinx Edition; visionICE II Emulator; visionTRACEEmulator


SoleNet, Inc.www.solenet.netFPGA, board, and system designs for wire-less, telecommunications, consumer, andreference design applications

so-logic electronic consultingwww.so-logic.netEmbedded systems (PowerPC,MicroBlaze); system-level design (Forge, System Generator, Handel-C);Xilinx training centers (Austria, Eastern Europe)

Styrex ABwww.styrex.se/Design services for embedded systems; programmable logic; hardware develop-ment; microprocessor programming

Synopsys Professional Serviceswww.synopsys.comDesign services to solve your design challenges in system-level design, RTLdesign, and physical design

Syntera ABwww.syntera.se/Design services; FPGAs for radar, digitalcommunications, telecom automotive, aerospace, and DSP

Tao of Digital, Inc.www.taoofdigital.comHigh-speed, large-gate-count SoC designsusing IP cores for maximum modularityand efficiency

Technolution B.V.www.technolution.nl/Innovative hardware and software solutions

Tezzaron Semiconductorwww.tezzaron.comDesign services for portable computing,networking, and embedded systems

Thales Airborne Systemswww.thalesgroup.com/airbornesystems/Provider and integrator with high expertisein FPGA design for radars, DSP, and communications

TietoEnator R&D Services ABwww.tietoenator.comEuropean design services for telecom,industrial IT, and automotive; Xilinx exclu-sive training provider in Scandinavia

V-Integrationwww.V-Integration.comProviding first-pass success in complexFPGA designs; applications include imag-ing, communications, and interface design

Williams Consulting, [email protected] systems hardware and software;video; MPEG; control

AllianceEmbedded Memberswww.xilinx.com/allianceembedded

See these AllianceEmbedded members forinformation about the following products(contact Xilinx for Wind River XilinxEdition products):

Accelerated Technology® Division of Mentor Graphicswww.acceleratedtechnology.comNucleus® RTOS support for XilinxMicroBlaze 32-bit soft processor cores

Avnet Design Services single board computerswww.em.avnet.com/home/ADS Xilinx Virtex-II Pro Evaluation Kit

Corelis Inc.www.corelis.comCodeRunner JTAG debugger support for Virtex-II Pro embedded PowerPC

Express Logicwww.expresslogic.comThreadX® RTOS support for XilinxMicroBlaze 32-bit soft processor

Green Hills Softwarewww.ghs.comMULTI® debugger support for Virtex-II Pro embedded PowerPC; Green Hills™ Optimizing C Compiler support for Virtex-II Pro embedded PowerPC

MEMEC Design single board computerswww.insight-electronics.com/virtex2pro/Virtex series system boards


The hard work is done! Now ASIC and FPGA designers can prototypelogic designs for a fraction of the cost of existing solutions. Here are 6+ million gates(measured the ASIC way) on an easy to use, stand-alone, USB2.0-hosted board (a PCI/PCI-X interface is coming soon). The DN6000k10 supports up to 9, 2vp100 VirtexII-Pro FPGA’s,with an incredible amount of FPGA to FPGA interconnect for easy logic partitioning. FPGA’sare interconnected with rocket I/O’s, enabling the movement of data between them at100’s of GB/s. In addition to 6M+ gates, the DN6000k10 also packs on-board:

• 2 PowerPC cores per FPGA (400MHz)

• Up to 8MB embedded RAM, 444, 18x18 multipliers — per FPGA

• 12 external 133MHz 32M x 16 DDR SDRAM’s, 5 4Mx16 FLASH

• 480+ connections for daughter card and logic analyzer interfaces

Configuration is fast, easy, and robust using a SmartMedia-based FLASH card or, via theUSB interface. Every tool, utility, driver, and support application that The Dini Group couldimagine you might need is included. Please contact us for complete specifications, we areeager to show you how our hard work can make you job easier.

1010 Pearl Street, Suite 6 • La Jolla, CA 92037 • (858) 454-3419 • Email: [email protected]

So Many GatesSo Many Gates

So Few Dollars

Xil

inx V

irte

x™-I

I Seri

es

FPG

As

htt

p:/

/ww

w.x

ilin

x.c

om

/de

vic

es/


System Gates (see note 1)

Virtex-II Series EasyPath Solutions (see note 4)

CLB Array (Row x Col)XC

2VP2

*16

x 2

2

Number of Slices

1,40

8

Logic Cells (see note 2)

3,16

8

CLB Flip-Flops

2816

Max. Distributed RAM Bits (kbits)

44

# 18 kbits Block RAM

12

Total Block RAM (kbits)

216

# 18x18 Dedicated Multipliers

12

CLB

Reso

urce

sM

emor

y Re

sour

ces

DSP

I/O F

eatu

res

Spee

d

DCM Frequency (min/max)

24/4

20

# DCM Blocks (see note 3)

4

Digitally Controlled Impedance

YES

Maximum Differential I/O Pairs

100

Maximum I/O

204

I/O Standards

LDT-

25, L

VDS-

25, L

VDSE

XT-2

5,

BLVD

S-25

, ULV

DS-2

5, L

VPEC

L-25

, LV

CMO

S25,

LVC

MO

S18,

LV

CMO

S15,

PCI

33, L

VTTL

, LV

CMO

S33,

PCI

-X, P

CI66

, GTL

, G

TL+

, HST

L I (

1.5V

,1.8

V),

HSTL

II (1

.5V,

1.8V

), HS

TL II

I (1.

5V,1

.8V)

, HS

TL IV

(1.5

V,1.

8V),

SSTL

2I,

SSTL

2II,

SSTL

18 I,

SST

L18

II

LDT-

25, L

VPEC

L-33

, LV

DS-3

3, L

VDS-

25,

LVDS

EXT-

33, L

VDSE

XT-2

5,

BLVD

S-25

, ULV

DS-2

5,

LVTT

L, L

VCM

OS3

3,

LVCM

OS2

5, L

VCM

OS1

8,

LVCM

OS1

5, P

CI33

, PCI

66,

PCI-X

, GTL

, GTL

+, H

STL

I, HS

TL II

, HST

L III

, HST

L IV

, SS

TL2I

, SST

L2II,

SST

L3 I,

SS

TL3

II, A

GP,

AGP-

2X

Commercial Speed Grades(slowest to fastest)

-5 -6

-7

Industrial Speed Grades(slowest to fastest)

-5 -6

*XC

2VP4

40

x 2

2 3,

008

6,76

86,

016

9428

504

28

24/4

204

YES

172

348

-5 -6

-7-5

-6

Cloc

k Re

sour

ces

XC2V

P7

*40

x 3

4 4,

928

11,0

889,

856

154

4479

244

24/4

204

YES

196

396

-5 -6

-7-5

-6

XC2V

P20

*56

x 4

69,

280

20,8

8018

,560

290

881,

584

8824

/420

8YE

S27

656

4-5

-6 -7

-5 -6

XC2V

P30

*80

x 4

613

,696

30,8

1627

,392

428

136

2448

136

24/4

208

YES

372

644

-5 -6

-7-5

-6

XC2V

P40

*88

x 5

819

,392

43,6

3238

,784

606

192

3,45

619

224

/420

8YE

S39

680

4-5

-6 -7

-5 -6

XC2V

P50

*88

x 7

023

,616

53,1

3647

,232

738

232

4,17

623

224

/420

8YE

S42

085

2-5

-6 -7

-5 -6

XC2V

P70

*10

4 x

8233

,088

74,4

4866

,176

1,03

432

85,

904

328

24/4

208

YES

492

996

-5 -6

-7-5

-6

XC2V

P100

*12

0 x

9444

,096

99,2

1688

,192

1,37

844

47,

992

444

24/4

2012

YES

572

1,16

4-5

-6 -7

-5 -6

XC2V

4040

K8

x 8

256

576

512

84

724

24/4

204

YES

4488

-4 -5

-6-4

-5

XC2V

8080

K16

x 8

512

1,15

21,

024

168

144

824

/420

4YE

S60

120

-4 -5

-6-4

-5

XC2V

250

250K

24 x

16

1,53

63,

456

3,07

248

2443

224

24/4

208

YES

100

200

-4 -5

-6-4

-5

XC2V

500

500K

32 x

24

3,07

26,

912

6,14

496

3257

632

24/4

208

YES

132

264

-4 -5

-6-4

-5

XC2V

1000

1M40

x 3

25,

120

11,5

2010

,240

160

4072

040

24/4

208

YES

216

432

-4 -5

-6-4

-5

XC2V

1500

1.5M

48 x

40

7,68

017

,280

15,3

6024

048

864

4824

/420

8YE

S26

452

8-4

-5 -6

-4 -5

XC2V

2000

2M56

x 4

810

,752

24,1

9221

,504

336

561,

008

5624

/420

8YE

S31

262

4-4

-5 -6

-4 -5

XC2V

3000

3M64

x 5

614

,336

32,2

5628

,672

448

961,

728

9624

/420

12YE

S36

072

0-4

-5 -6

-4 -5

XC2V

4000

4M80

x 7

223

,040

51,8

4046

,080

720

120

2,16

012

024

/420

12YE

S45

691

2-4

-5 -6

-4 -5

XC2V

6000

6M96

x 8

833

,792

76,0

3267

,584

1,05

614

42,

592

144

24/4

2012

YES

552

1,10

4-4

-5 -6

-4 -5

XC2V

8000

XCE2

VP30

XCE2

VP40

XCE2

VP50

XCE2

VP70

XCE2

VP10

0

XCE2

V300

0

XCE2

V400

0

XCE2

V600

0

XCE2

V800

08M

112

x 10

446

,592

104,

882

93,1

841,

456

168

3,02

416

824

/420

12YE

S55

41,

108

-4 -5

-4 -5

Configuration Memory (Bits)

1.3M

RocketIO™

Transceiver Blocks(3.125 Gbps)

4

RocketIO™

X Transceiver Blocks (10.3125 Gbps)

3.0M

4

4.4M

8

8.2M

8

11.3

M8

15.5

M0

or 1

2

19.0

M0

or 1

6

25.6

M16

or 2

0

33.5

M0

or 2

0

XC2V

PX20

*56

x 4

69,

792

22,0

3219

,584

306

8815

8488

24/4

208

YES

276

552

Sam

e as

abo

ve

-5 -6

-7TB

D8.

05M

08

0.4M

––

0.6M

––

1.7M

––

2.8M

––

4.1M

––

5.7M

––

7.5M

––

10.5

M–

–

15.7

M–

–

21.9

M–

–

29.1

M–

–

PowerPC™ Processor Blocks

0 1 1 2 2 2 2 2 2 1 – – – – – – – – – – –

EasyPath

✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔

Platform FPGAs

* Lo

gic

cell

coun

ts a

re a

mor

e m

eani

ngfu

l mea

sure

men

t of d

ensi

ty fo

r the

Virt

ex-II

Pro

fam

ily s

ince

sys

tem

gat

e co

unt d

oes

not t

ake

into

con

side

ratio

n th

e be

nefit

s of

the

imm

erse

d sp

ecia

l blo

cks

such

as

Pow

erPC

pro

cess

ors

and

mul

ti-gi

gabi

t tra

nsce

iver

s. 1.

Sy

stem

Gat

es in

clud

e 20

-30%

of C

LBs

used

as

RAM

2.

Log

ic c

ell =

One

4-In

put L

ook

Up

Tabl

e (L

UT)

+ F

lip F

lop

+ C

arry

Log

ic.

3.

DCM

= D

igita

l Clo

ck M

anag

emen

t 4

. Vi

rtex

-II S

erie

s Ea

syPa

th s

olut

ion

avai

labl

e to

pro

vide

a n

o ris

k, n

o ef

fort

cos

t red

uctio

n pa

th fo

r vol

ume

prod

uctio

nN

otes

:

Virt

ex-II

Pro

Fam

ily –

1.5

Vol

t

Virt

ex-II

Fam

ily –

1.5

Vol

t

XC2V

PX70

*10

4 x

8233

,088

74,4

4866

,176

1034

308

5544

308

24/4

208

YES

492

992

Sam

e as

abo

ve

-5 -6

-7TB

DXC

E2VP

X70

25.6

0M0

202

✔

Virt

ex-II

Pro

X F

amily

– 1

.5 V

olt

Pro

du

ct S

ele

ctio

n M

atr

ix

Impo

rtan

t:Ve

rify

all

data

in t

his

docu

men

t w

ith

the

devi

ce d

ata

shee

ts f

ound

at

http

://w

ww

.xili

nx.c

om/p

arti

nfo/

data

book

.htm

Xil

inx V

irte

x™-I

I Seri

es

FPG

As

htt

p:/

/ww

w.x

ilin

x.c

om

/de

vic

es/


XC2VP2

204

XC2VP4

348

XC2VP7

396

XC2VP20

564

XC2VP30

692

XC2VP40

804

XC2VP50

852

XC2VP7099

6

XC2VP100

1164

Virt

ex-II

Pro

(1.5

V)

XC2V40

88

XC2V80

120

XC2V250

200

XC2V500

264

XC2V1000

432

XC2V1500

528

XC2V2000

624

XC2V3000

720

XC2V4000

912

XC2V6000

1104

XC2V8000

1108

Virt

ex-II

(1.5

V)Vi

rtex

-II P

ro X

(1.5

V)

Pins

3A

rea

8892

9214

412

x 1

2 m

m

328

392

408

575

31 x

31

mm

516

728

35 x

35

mm

140

140

8812

017

217

217

225

617

x 1

7 m

m

156

248

248

200

264

324

4564

23 x

23

mm

404

416

416

392

456

484

6764

27 x

27

mm

204

348

396

672

27 x

27

mm

396

556

556

432

528

624

8965

31 x

31

mm

564

644

692

692

720

824

824

824

1152

535

x 3

5 m

m

804

812

1148

635

x 3

5 m

m

852

964

912

1104

1108

1517

40 x

40

mm

996

1040

1704

42.5

x 4

2.5

mm

1164

1696

642

.5 x

42.

5 m

m

XC2VPX20

552

552

624

684

684

684

957

Not

es:

1. N

umbe

rs in

tabl

e in

dica

te m

axim

um n

umbe

r of u

ser I

/Os.

2. T

he n

umbe

r of I

/Os

for R

ocke

tIO M

GTs

are

not

incl

uded

in th

is ta

ble.

3. W

ithin

the

sam

e fa

mily

, all

devi

ces

in a

par

ticul

ar p

acka

ge a

re p

in-o

ut (f

ootp

rint)

com

patib

le.

4. V

irtex

-II p

acka

ges

FG45

6 an

d FG

676

are

also

foot

prin

t com

patib

le.

5. V

irtex

-II p

acka

ges

FF89

6 an

d FF

1152

are

als

o fo

otpr

int c

ompa

tible

.6.

Roc

ketIO

una

vaila

ble

in th

is p

acka

ge.

40 x

40

mm

XC2VPX70

992

992

Chip

Sca

le P

acka

ges

(CS)

– w

ire-

bond

chi

p-sc

ale

BGA

(0.8

mm

bal

l spa

cing

)

BGA

Pac

kage

s (B

G) –

wir

e-bo

nd s

tand

ard

BGA

(1.2

7 m

m b

all s

paci

ng)

FGA

Pac

kage

s (F

G) –

wir

e-bo

nd fi

ne-p

itch

BG

A (1

.0 m

m b

all s

paci

ng)

FFA

Pac

kage

s (F

F) –

flip

-chi

p fin

e-pi

tch

BGA

(1.0

mm

bal

l spa

cing

)

BFA

Pac

kage

s (B

F) –

flip

-chi

p fin

e-pi

tch

BGA

(1.2

7 m

m b

all s

paci

ng)

Pb-fr

ee s

olut

ions

are

ava

ilabl

e. F

or m

ore

info

rmat

ion

abou

t Pb-

free

solu

tions

vis

it w

ww

.xili

nx.c

om/p

bfre

e.

Impo

rtan

t:Ve

rify

all

data

in t

his

docu

men

t w

ith

the

devi

ce d

ata

shee

ts f

ound

at

http

://w

ww

.xili

nx.c

om/p

arti

nfo/

data

book

.htm

XC2VP2

XC2VP4

XC2VP7

XC2VP20

XC2VP30

XC2VP40

XC2VP50

XC2VP70

XC2VP100

Pack

age

Rock

etIO

(3.1

25G

bps)

Rock

etIO

X

(10G

bps)

Tran

scei

ver

Bloc

ks

4FG

256

4

4FG

456

48

FG67

68

88

4FG

672

48

FF89

68

88

FF11

528

812

16

FF11

486

00

FF15

1716

16

FF17

0420

20

FF16

966

0

XC2VPX20

8

XC2VPX70

20

XGC1

120

- Ult

ra M

SA

Dev

ice

Rock

etPH

Y Fa

mily

of 1

0Gbp

s Ph

ysic

al L

ayer

Tra

nsce

iver

s

For m

ore

info

rmat

ion

abou

t the

Roc

ketP

HY fa

mily

, vis

it w

ww

.xili

nx.c

om/ro

cket

phy

√

SONET OC-192SDH STM - 64

√

G . 709

√

10G ETHERNET

√

XGC1

121

- 10G

SO

NET

/SD

H√

XFP

Tran

scei

vers

,SO

NET

/SDH

– b

ased

tr

ansm

issi

on s

yste

ms,

fiber

opt

ic te

st

equi

pmen

t

10G FIBRE CHANNEL

MSA

Mod

ules

XFP

Tran

scei

vers

,SO

NET

/SDH

tr

ansm

issi

on s

yste

ms,

OTN

sys

tem

w/F

EC,

fiber

opt

ic te

st

equi

pmen

t

Applications

XSBI

SFI-4

SFI-4

XGC1

320

- 10G

E/10

GFC

√√

XSBIParallel Interface

FT25

6

FT25

6

FT25

6

Package

XFP

Tran

scei

vers

,da

ta tr

ansm

issi

on

equi

pmen

t, N

ICs,

test

equ

ipm

ent,

edge

rout

ers,

stor

age

area

net

wor

ks

Xil

inx V

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x-I

I Seri

es

FPG

As

an

d R

ock

etP

HY

Ph

ysi

cal

Layer

Tran

sceiv

ers

Xil

inx S

part

an

™Seri

es

FPG

As

htt

p:/

/ww

w.x

ilin

x.c

om

/de

vic

es/


Pro

du

ct S

ele

ctio

n M

atr

ix CLB

Reso

urce

sM

emor

y Re

sour

ces

CLK

Reso

urce

sD

SPI/O

Fea

ture

sSp

eed

PRO

M


CLB Array (Row x Col)

XC3S

5050

K16

x 1

2

Number of Slices

768

Logic Cells (see note 2 )

1,72

8CLB Flip-Flops

1,53

6

Max. Distributed RAM Bits

12K

# Block RAM

4

Block RAM (bits)

72K

Dedicated Multipliers

4

DCM Frequency (min/max)

24/3

30

# DCMs

2

Frequency Synthesis

YES

Phase Shift

YES

Digitally Controlled Impedance

Number of Differential I/O Pairs

Maximum I/O

I/O Standards


YES

5612

4Si

ngle

-end

edLV

TTL,

LVC

MO

S3.3

/2.5

/1.8

/1.

5/1.

2, P

CI 3

.3V

– 32

/64-

bit

33M

Hz, S

STL2

Cla

ss I

& II

, SS

TL18

Cla

ss I,

HST

L Cl

ass

I, III

, HST

L1.8

Cla

ss I,

II &

III,

GTL

, GTL

+

Diffe

rent

ial

LVDS

2.5,

Bus

LVD

S2.5

,U

ltra

LVDS

2.5,

LVD

S_ex

t2.5

,RS

DS, L

DT2.

5, L

VPEC

L

-4 -5

Industrial Speed Grades(slowest to fastest)

-4


.4M

XC3S

200

200K

24

x 2

01,

920

4,32

03,

840

30K

1221

6K12

24/3

304

YES

YES

YES

7617

3-4

-5-4

1.0M

XC3S

400

400K

32

x 2

83,

584

8,06

47,

168

56K

1628

8K16

24/3

304

YES

YES

YES

116

264

-4 -5

-41.

7M

XC3S

1000

10

00K

48 x

40

7,68

017

,280

15,3

6012

0K24

432K

2424

/330

4YE

SYE

SYE

S17

539

1-4

-5-4

3.2M

XC3S

1500

15

00K

64 x

52

13,3

1229

,952

26,6

2420

8K32

576K

3224

/330

4YE

SYE

SYE

S22

148

7-4

-5-4

5.2M

XC3S

2000

20

00K

80 x

64

20,4

8046

,080

40,9

6032

0K40

720K

4024

/330

4YE

SYE

SYE

S27

056

5-4

-5-4

7.7M

XC3S

4000

40

00K

96 x

72

27,6

4862

,208

55,2

9643

2K96

1,72

8K96

24/3

304

YES

YES

YES

312

712

-4 -5

-411

.3M

XC3S

5000

50

00K

104

x 80

33,2

8074

,880

66,5

6052

0K10

41,

872K

104

24/3

304

YES

YES

YES

344

784

-4 -5

-413

.3M

Not

e:

1. S

yste

m G

ates

incl

ude

20-3

0% o

f CLB

s us

ed a

s RA

Ms

2.

For

Spa

rtan

-3, a

Log

ic C

ell i

s de

fined

as

a 4-

inpu

t LU

T +

flip

-flop

3. A

utom

otiv

e Q

-Gra

de S

olut

ions

for S

part

an-3

will

be

avai

labl

e 2H

2004

.

Spar

tan-

3 Fa

mily

– 1

.2 V

olt

(see

not

e 3)

Impo

rtan

t:Ve

rify

all

data

in t

his

docu

men

t w

ith

the

devi

ce d

ata

shee

ts f

ound

at

http

://w

ww

.xili

nx.c

om/p

arti

nfo/

data

book

.htm

Xil

inx S

part

an

™Seri

es

FPG

As

htt

p:/

/ww

w.x

ilin

x.c

om

/de

vic

es/


CLB

Reso

urce

sM

emor

y Re

sour

ces

CLK

Reso

urce

sI/O

Fea

ture

sSp

eed


CLB Array (Row x Col)

XC2S

50E

50K

16 x

24

Number of Slices

768

Logic Cells (see notes 2 and 3)

1,72

8

CLB Flip-Flops

1,53

6

Max. Distributed RAM Bits

24K

# Block RAM

8

Block RAM (bits)

32K

DLL Frequency (min/max)

25/3

20

# DLL’s

4

Frequency Synthesis

YES

Phase Shift

YES

Number of Differential I/O Pairs

Maximum I/O

I/O Standards


8318

2LV

TTL,

LVCM

OS2

, LV

CMO

S18,

PCI

33, P

CI66

, G

TL, G

TL+

, HST

L I,

HSTL

III,

HSTL

IV, S

STL3

I, S

STL3

II,

SSTL

2 I,

SSTL

2 II,

AG

P-2X

, CT

T, LV

DS, B

LVDS

, LVP

ECL

LVTT

L, L

VCM

OS2

,PC

I33

(3.3

V &

5V)

,PC

I66

(3.3

V), G

TL, G

TL+

,

HS

TL I,

HST

L III

, HST

L IV

,

SS

TL3

I, SS

TL3

II, S

STL2

I,

SSTL

2 II,

AG

P-2X

, CTT

-6 -7

Industrial Speed Grade(slowest to fastest)

-6


0.6M

XC2S

100E

100K

20 x

30

1,20

02,

700

2,40

037

K10

40K

25/3

204

YES

YES

8620

2-6

-7-6

0.9M

XC2S

150E

150K

24 x

36

1,72

83,

888

3,45

654

K12

48K

25/3

204

YES

YES

114

265

-6 -7

-61.

1M

XC2S

200E

200K

28 x

42

2,35

25,

292

4,70

473

K14

56K

25/3

204

YES

YES

120

289

-6 -7

-61.

4M

XC2S

300E

300K

32 x

48

3,07

26,

912

6,14

496

K16

64K

25/3

204

YES

YES

120

329

-6 -7

-61.

9M

XC2S

400E

400K

40 x

60

4,80

010

,800

9,60

015

0K40

160K

25/3

204

YES

YES

172

410

-6 -7

-62.

7M

XC2S

600E

600K

48 x

72

6,91

215

,552

13,8

2421

6K72

288K

25/3

204

YES

YES

205

514

-6 -7

-64.

0M

XC2S

1515

K8

x 12

192

432

384

6K4

16K

25/2

004

YES

YES

NA

86-5

-6-5

0.2M

XC2S

3030

K12

x 1

843

297

286

413

.5K

624

K25

/200

4YE

SYE

SN

A92

-5 -6

-50.

4M

XC2S

5050

K16

x 2

476

81,

728

1,53

624

K8

32K

25/2

004

YES

YES

NA

176

-5 -6

-50.

6M

XC2S

100

100K

20 x

30

1,20

02,

700

2,40

037

.5K

1040

K25

/200

4YE

SYE

SN

A17

6-5

-6-5

0.8M

XC2S

150

150K

24 x

36

1,72

83,

888

3,45

654

K12

48K

25/2

004

YES

YES

NA

260

-5 -6

-51.

1M

XC2S

200

200K

28 x

42

2,35

25,

292

4,70

473

.5K

1456

K25

/200

4YE

SYE

SN

A28

4-5

-6-5

1.4M

XCS0

5XL

5K10

x 1

010

023

820

03.

1KN

AN

AN

AN

AN

AN

AN

A77

-4 -5

-40.

05M

XCS1

0XL

10K

14 x

14

196

466

392

6.1K

NA

NA

NA

NA

NA

NA

NA

112

-4 -5

-40.

09M

XCS2

0XL

20K

20 x

20

400

950

800

12.5

KN

AN

AN

AN

AN

AN

AN

A16

0-4

-5-4

0.18

M

XCS3

0XL

30K

24 x

24

576

1,36

81,

152

18.0

KN

AN

AN

AN

AN

AN

AN

A19

2-4

-5-4

0.25

M

XCS4

0XL

40K

28 x

28

784

1,86

21,

568

24.5

KN

AN

AN

AN

AN

AN

AN

A20

5-4

-5-4

Automotive Q-Grade Speed Grade

-6 -6 -6 -6 -6 -6 -6 -5 -5 -5 -5 -5 -5 -4 -4 -4 -4 -40.

33M

Automotive Q-Grade Solutions(see note 4)

✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔

Not

e:

1. S

yste

m G

ates

incl

ude

20-3

0% o

f CLB

s us

ed a

s RA

M

2. L

ogic

cel

l = (1

) 4 In

put (

LUT)

and

a re

gist

er

3. F

or S

part

an-II

E/II/

XL, a

Log

ic C

ell i

s de

fined

as

a 4-

inpu

t LU

T +

a re

gist

er4.

Aut

omot

ive

Q-G

rade

Sol

utio

ns a

re q

ualif

ied

to -4

0ºC

to +

125º

C ju

nctio

n te

mpe

ratu

re fo

r FPG

As. Q

-Gra

de p

rodu

cts

for S

part

an-3

will

be

avai

labl

e 2H

2004

Spar

tan-

II Fa

mily

– 2

.5 V

olt

Spar

tan-

XL F

amily

– 3

.3 V

olt

Spar

tan-

IIE F

amily

– 1

.8 V

olt

Pro

du

ct S

ele

ctio

n

Matr

ix

Impo

rtan

t:Ve

rify

all

data

in t

his

docu

men

t w

ith

the

devi

ce d

ata

shee

ts f

ound

at

http

://w

ww

.xili

nx.c

om/p

arti

nfo/

data

book

.htm

Xil

inx S

part

an

™Seri

es

FPG

As

htt

p:/

/ww

w.x

ilin

x.c

om

/de

vic

es/


Not

e 1:

Num

bers

in ta

ble

indi

cate

max

imum

num

ber o

f use

r I/O

sN

ote

2: A

rea

dim

ensi

ons

for l

ead-

fram

e pr

oduc

ts a

re in

clus

ive

of th

e le

ads.

Pb-fr

ee s

olut

ions

are

ava

ilabl

e. F

or m

ore

info

rmat

ion

abou

t Pb-

free

solu

tions

vis

it w

ww

.xili

nx.c

om/p

bfre

e.

Auto

mot

ive

prod

ucts

are

hig

hlig

hted

: -40

C to

+12

5C ju

nctio

n te

mpe

ratu

re fo

r FPG

As.

Auto

mot

ive

Q-G

rade

pro

duct

s w

ill b

e av

aila

ble

in S

part

an-3

fam

ily 2

H200

4.Fo

r mor

e in

form

atio

n on

IQ S

olut

ions

ple

ase

visi

t htt

p://w

ww

.xili

nx.c

om/a

utom

otiv

e

XC2S50E

XC2S100E

XC2S150E

XC2S200E

XC2S300E

XC2S400E

XC2S600E

I/O’s

182

202

265

289

329

410

514

XC2S15

XC2S30

XC2S50

XC2S100

XC2S150

XC2S200

8692

176

176

260

284

XCS05XL

XCS10XL

XCS20XL

XCS30XL

XCS40XL

7711

216

019

219

2

XC3S50

XC3S200

XC3S400

XC3S1000

XC3S1500

XC3S2000

XC3S4000

Are

a2Pi

nsI/O

’s12

417

326

439

148

756

571

278

4XC3S5000

192

192

6077

77

112

92

146

146

146

146

146

140

140

140

140

160

169

169

6077

77

102

102

8692

9292

113

113

30.6

x 3

0.6

mm

208

34.6

x 3

4.6

mm

240

16.0

x 1

6.0

mm

100

6363

22.0

x 2

2.0

mm

144

97

12 x

12

mm

144

124

141

141

9797

PQFP

Pac

kage

s (P

Q) –

wir

e-bo

nd p

last

ic Q

FP (0

.5m

m le

ad s

paci

ng)

VQFP

Pac

kage

s (V

Q) –

ver

y th

in T

QFP

(0.5

mm

lead

spa

cing

)

TQFP

Pac

kage

s (T

Q) –

thi

n Q

FP (0

.5m

m le

ad s

paci

ng)

Chip

Sca

le P

acka

ges

(CS)

– w

ire-

bond

chi

p-sc

ale

BGA

(0.8

mm

bal

l spa

cing

)

31 x

31

mm

900

565

633

633

35 x

35

mm

1156

712

784

176

202

265

289

260

410

514

192

182

182

182

182

182

182

176

176

176

329

329

329

284

205

17 x

17

mm

256

17 x

17

mm

256

23 x

23

mm

456

264

333

27 x

27

mm

676

391

487

489

27 x

27

mm

256

173

173

173

333

19 x

19

mm

320

221

221

221

FGA

Pac

kage

s (F

T) –

wir

e-bo

nd fi

ne-p

itch

thi

n BG

A (1

.0 m

m b

all s

paci

ng)

FGA

Pac

kage

s (F

G) –

wir

e-bo

nd fi

ne-p

itch

BG

A (1

.0 m

m b

all s

paci

ng)

BGA

Pac

kage

s (B

G) –

wir

e-bo

nd s

tand

ard

BGA

(1.2

7 m

m b

all s

paci

ng)

Spar

tan-

IIE (1

.8V)

Spar

tan-

II (2

.5V)

Spar

tan-

XL (3

.3V)

Spar

tan-

3 (1

.2V)

Pack

ag

e O

pti

on

s an

d U

ser

I/O

1

Impo

rtan

t:Ve

rify

all

data

in t

his

docu

men

t w

ith

the

devi

ce d

ata

shee

ts f

ound

at

http

://w

ww

.xili

nx.c

om/p

arti

nfo/

data

book

.htm

Xil

inx C

PLD

htt

p:/

/ww

w.x

ilin

x.c

om

/de

vic

es


XCR3

032X

L75

032

XCR3

064X

L15

0064

XCR3

128X

L30

0012

8

XCR3

256X

L60

0025

6

XCR3

384X

L90

0038

4

XCR3

512X

L12

000

512

48 48 48 48 48

365

-5 -7

-10

-7 -1

04

16

686

-6 -7

-10

-7 -1

04

16

108

6-6

-7 -1

0 -7

-10

416

164

7.5

-7 -1

0 -1

2-1

0 -1

24

16

220

7.5

-7 -1

0 -1

2-1

0 -1

24

16

3.3/

5

3.3/

5

3.3/

5

3.3/

5

3.3/

5

3.3/

5

3.3

3.3

3.3

3.3

3.3

3.3

260

7.5

-7 -1

0 -1

2-1

0 -1

24

16

XC2C

3275

032

XC2C

6415

0064

XC2C

128

3000

128

XC2C

256

6000

256

XC2C

384

9000

384

XC2C

512

1200

051

2

40 40 40 40 40 40

System Gates

Macrocells

Product Terms per Macrocell

1.5/

1.8/

2.5/

3.3

Input Voltage Compatible

1.5/

1.8/

2.5/

3.3

33Output Voltage Compatible

Maximum I/O

13

I/O Banking

Min. Pin-to-pin Logic Delay (ns)

-3 -4

-6-6

Commercial Speed Grades(fastest to slowest)

Industrial Speed Grades(fastest to slowest)

3Global Clocks

17

1.5/

1.8/

2.5/

3.3

1.5/

1.8/

2.5/

3.3

641

4-4

-5 -7

-73

17

1.5/

1.8/

2.5/

3.3

1.5/

1.8/

2.5/

3.3

100

24.

5-4

-6 -7

-73

17

1.5/

1.8/

2.5/

3.3

1.5/

1.8/

2.5/

3.3

184

25

-5 -6

-7-7

317

1.5/

1.8/

2.5/

3.3

1.5/

1.8/

2.5/

3.3

240

46

-6 -7

-10

-10

317

1.5/

1.8/

2.5/

3.3

1.5/

1.8/

2.5/

3.3

270

46

-6 -7

-10

-10

317Product Term Clocks per

Function Block

Cool

Runn

er-II

Fam

ily –

1.8

Vol

t

Cool

Runn

er X

PLA

3 Fa

mily

– 3

.3 V

olt

-10

-10

-10

-12

-12

-12-6

IQ Speed Grade

-7 -7 -7 -10

-10

I/OFe

atur

esSp

eed

Cloc

king

48

Pro

du

ct S

ele

ctio

n M

atr

ix –

Co

olR

un

ner™

Seri

es

Pack

ag

e O

pti

on

s an

d U

ser

I/O

* JT

AG p

ins

and

port

ena

ble

are

not p

in c

ompa

tible

in th

is p

acka

ge fo

r thi

s m

embe

r of t

he fa

mily

Not

e 1:

Are

a di

men

sion

s fo

r lea

d-fra

me

prod

ucts

are

incl

usiv

e of

the

lead

s.

Auto

mot

ive

prod

ucts

are

hig

hlig

hted

: -40

C to

+12

5C a

mbi

ent t

empe

ratu

re fo

r CPL

Ds

XC2C512

XCR3032XL

XCR3064XL

XCR3128XL

XCR3256XL

XCR3384XL

3636

XCR3512XL

Are

a1Pi

ns

17.5

x 1

7.5

mm

44

XC2C32

XC2C64

XC2C128

XC2C256

XC2C384

XC2C512

30.6

x 3

0.6

mm

208

12.0

x 1

2.0

mm

44

3333

16.0

x 1

6.0

mm

100

118*

22.0

x 2

2.0

mm

144

486

x 6

mm

5633

45

8 x

8 m

m13

210

010

6

4036

7 x

7 m

m48

108

12 x

12

mm

144

164

16 x

16

mm

280

212

164

212

17 x

17

mm

256

184

212

212

260

220

23 x

23

mm

324

240

270

173

173

173

180

164

172

3333

3636

6884

6480

80

108

120

100

118

118

PQFP

Pac

kage

s (P

Q) –

wir

e-bo

nd p

last

ic Q

FP (0

.5m

m le

ad s

paci

ng)

VQFP

Pac

kage

s (V

Q) –

ver

y th

in T

QFP

(0.5

mm

lead

spa

cing

)

TQFP

Pac

kage

s (T

Q) –

thi

n Q

FP (0

.5m

m le

ad s

paci

ng)

FGA

Pac

kage

s (F

T) –

wir

e-bo

nd fi

ne-p

itch

thi

n BG

A (1

.0 m

m b

all s

paci

ng)

FBG

A P

acka

ges

(FG

) – w

ire-

bond

Fin

e-lin

e BG

A (1

.0 m

m b

all s

paci

ng)

Chip

Sca

le P

acka

ges

(CS)

– w

ire-

bond

chi

p-sc

ale

BGA

(0.8

mm

bal

l spa

cing

)

Chip

Sca

le P

acka

ges

(CP)

– w

ire-

bond

chi

p-sc

ale

BGA

(0.5

mm

bal

l spa

cing

)

Cool

Runn

er X

PLA

3Co

olRu

nner

-II

PLCC

Pac

kage

s (P

C) –

wir

e-bo

nd p

last

ic c

hip

carr

ier

(1.2

7mm

lead

spa

cing

)

Xil

inx C

PLD

htt

p:/

/ww

w.x

ilin

x.c

om

/de

vic

es


Pro

du

ct S

ele

ctio

n M

atr

ix –

9500 S

eri

es

Pack

ag

e O

pti

on

s an

d U

ser

I/O

XC9536XV

XC9572XV

XC95144XV

XC95288XV

3434

XC9536XL

XC9572XL

XC95144XL

XC95288XL

3434

3434

8181

117

117

117

117

3836

3836

117

117

192

192

192

192

192

72

34

5236

72

Auto

mot

ive

prod

ucts

are

hig

hlig

hted

: -40

C to

+12

5C a

mbi

ent t

empe

ratu

re fo

r CPL

Ds

Not

e 1:

Are

a di

men

sion

s fo

r lea

d-fra

me

prod

ucts

are

incl

usiv

e of

the

lead

s.

Are

a1Pi

ns

17.5

x 1

7.5

mm

44

23.3

x 1

7.2

mm

100

12.0

x 1

2.0

mm

44

12.0

x 1

2.0

mm

64

16.0

x 1

6.0

mm

100

22.0

x 2

2.0

mm

144

6 x

6 m

m56

8 x

8 m

m13

2

7 x

7 m

m48

12 x

12

mm

144

16 x

16

mm

280

27 x

27

mm

256

17 x

17

mm

256

17 x

17

mm

256

23 x

23

mm

324

XC9536

XC9572

XC95108

XC95144

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8181

34

XC95216

XC95288

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69

31.2

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160

108

133

133

168

168

168

30.6

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mm

208

166

168

192

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352

166

192

FGA

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System Gates

Macrocells

Product Terms per Macrocell

Input Voltage Compatible

Output Voltage Compatible

Maximum I/O

I/O Banking

Min. Pin-to-pin Logic Delay (ns)

Commercial Speed Grades(fastest to slowest)

Industrial Speed Grades(fastest to slowest)

Global Clocks

Product Term Clocks perFunction Block

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I/OFe

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318

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216

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610

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117

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NA

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318

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3.3

2.5/

3.3

2.5/

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1.8/

2.5/

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MULTs

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t:Ve

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all

data

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his

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t w

ith

the

devi

ce d

ata

shee

ts f

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at

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ww

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om/p

arti

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data

book

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nd

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ag

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Com

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Software Storage

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Xilin

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Yes

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Syst

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s

Yes

Ye

s

Yes

STAM

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odel

s

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Yes

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HSPI

CE M

odel

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s

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Yes

Ye

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Yes

Chip

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Chip

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Sold

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mpl

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list o

f Xili

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pro

duct

s, vi

sit t

he X

ilinx

IP C

ente

r at h

ttp:

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w.x

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Mod

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dded

mic

ropr

oces

sor

DS-K

IT-S

2E3L

C*

Spar

tan-

IIE L

C 2S

300E

Dev

elop

men

t Kit

Insi

ght (

Mem

ec)

XC2S

300E

-6FG

456C

G

ener

al p

urpo

se S

part

an-3

dev

elop

men

t pla

tform

DS-K

IT-S

2E3L

C-IS

E-BA

S Sp

arta

n-IIE

LC

Deve

lopm

ent K

it w

/ISE

Base

X In

sigh

t (M

emec

) XC

2S30

0E-6

FG45

6C

DS-K

IT-S

2E6L

C*

Spar

tan-

IIE L

C 2S

600E

Dev

elop

men

t Kit

Insi

ght (

Mem

ec)

XC2S

600E

-6FG

456C

DS-K

IT-S

2E6L

C-IS

E-BA

S Sp

arta

n-IIE

LC

2S60

0E D

evel

opm

ent K

it w

/ISE

Base

X In

sigh

t (M

emec

) XC

2S60

0E-6

FG45

6C

iDEV

2 CA

N, L

IN a

nd T

TCAN

Dev

elop

men

t Pla

tform

and

Sta

rter

Kit

Inte

lliga

Inte

grat

ed D

esig

n, L

td.

XC2S

300E

Au

tom

otiv

e, In

dust

rial

HW-A

FX-D

IGI-2

S200

E

* In

sigh

t Pro

duct

s: A

ppen

d -E

URO

to p

art n

umbe

r for

inte

rnat

iona

l kits

(ex.

DS-

KIT-

2SLC

100-

EURO

); P

ower

Sup

ply

not i

nclu

ded

in -E

URO

kits

Spar

tan-

IIE D

evel

opm

ent B

oard

N

uHor

izon

s XC

2S20

0E

Prot

otyp

ing,

DSP

, Mul

timed

ia, R

econ

figur

able

Com

putin

g

Xil

inx O

n B

oard

– D

evelo

pm

en

t R

efe

ren

ce B

oard

sh

ttp

://w

ww

.xil

inx

.co

m/b

oa

rd_s

ea

rch


Boar

d Pa

rt N

umbe

r

ADS-

SP2-

MB-

EVL

Boar

d D

escr

ipti

on

Spar

tan-

II Ev

alua

tion

Kit w

/Mic

roBl

aze

& C

omm

unic

atio

ns/

Mem

ory

Mod

ule

Supp

lier

Avne

t Des

ign

Serv

ices

Xilin

x D

evic

e Su

ppor

t

XC2S

150-

5PQ

208

App

licat

ion

Net

wor

king

, tel

ecom

mun

icat

ion,

dat

a co

mm

unic

atio

n, e

mbe

dded

and

con

sum

er m

arke

ts

Spar

tan-

II

ADS-

XLX-

SP2-

EVL

Spar

tan-

II Ev

alua

tion

Kit

Avne

t Des

ign

Serv

ices

XC

2S15

0-5P

Q20

8 Ve

ry c

ost e

ffect

ive

eval

uatio

n an

d pr

otot

ypin

g pl

atfo

rm to

dev

elop

and

test

des

igns

that

are

ta

rget

ed to

the

Xilin

x Sp

arta

n-II

FPG

A fa

mily

- he

lps

shor

ten

and

sim

plify

the

desi

gn c

ycle

2D F

abric

Boa

rd

2D F

abric

Eva

luat

ion

and

Dem

o Bo

ard

Cros

sbow

Tech

nolo

gies

, Inc

. XC

2S15

0 M

ulti-

proc

essi

ng s

yste

m d

evel

opm

ent;

Net

wor

king

, wire

less

bas

esta

tions

, VoP

gat

eway

s

DS-K

IT-2

S100

* Sp

arta

n-II

100

Deve

lopm

ent K

it In

sigh

t (M

emec

) XC

2S10

0 DS

P, Di

gita

l Vid

eo, I

P-Ba

sed

Syst

ems,

Imag

e Pr

oces

sing

DS-K

IT-2

S200

* Sp

arta

n-II

PCI 2

S200

Dev

elop

men

t Kit

Insi

ght (

Mem

ec)

XC2S

200-

6FG

456C

DS

P, Di

gita

l Vid

eo, I

P-Ba

sed

Syst

ems,

Imag

e Pr

oces

sing

, PCI

, Rec

onfig

urab

le C

ompu

ting

DS-K

IT-2

S200

-ISE-

BAS

Spar

tan-

II PC

I 2S2

00 D

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opm

ent K

it w

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Base

X an

d JT

AG C

able

In

sigh

t (M

emec

) XC

2S20

0-6F

G45

6C

DSP,

Digi

tal V

ideo

, IP-

Base

d Sy

stem

s, Im

age

Proc

essi

ng, P

CI, R

econ

figur

able

Com

putin

g

DS-K

IT-2

S200

-PAK

* Sp

arta

n-II

PCI 2

S200

Dev

elop

men

t Kit

w/W

ebPA

CK C

D an

d JT

AG C

able

In

sigh

t (M

emec

) XC

2S20

0-6F

G45

6C

DSP,

Digi

tal V

ideo

, IP-

Base

d Sy

stem

s, Im

age

Proc

essi

ng, P

CI, R

econ

figur

able

Com

putin

g

DS-K

IT-2

SLC1

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Spar

tan-

II LC

2S1

00 D

evel

opm

ent K

it In

sigh

t (M

emec

) XC

2S10

0-5P

Q20

8C

Gen

eral

pur

pose

Spa

rtan

-II d

evel

opm

ent p

latfo

rm

DS-K

IT-2

SLC1

00-IS

E-BA

S Sp

arta

n-II

LC 2

S100

Dev

elop

men

t Kit

w/IS

E Ba

seX

and

JTAG

Cab

le

Insi

ght (

Mem

ec)

XC2S

100-

5PQ

208C

G

ener

al p

urpo

se S

part

an-II

dev

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men

t pla

tform

DS-K

IT-2

SLC1

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AK*

Spar

tan-

II LC

2S1

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opm

ent K

it w

/Web

PACK

CD

and

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Insi

ght (

Mem

ec)

XC2S

100-

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208C

G

ener

al p

urpo

se S

part

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dev

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men

t pla

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DS-K

IT-M

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E-S2

Sp

arta

n-II

Mic

roBl

aze

Kit

Insi

ght (

Mem

ec)

Spar

tan-

II Em

bedd

ed m

icro

proc

esso

r

DS-K

IT-P

CI32

S-20

0 Sp

arta

n-II

200

PCI D

evel

opm

ent K

it w

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nx S

ingl

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ojec

t PC

I325

Lic

ense

In

sigh

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emec

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2S20

0 DS

P, Di

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l Vid

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mag

e Pr

oces

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, PCI

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ting

RT-D

AC4/

PCI-D

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NI

Digi

tal O

MN

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rd

INTE

CO

XC2S

100,

XC2

S150

, XC2

S50

ASIC

Pro

toty

ping

, DSP

, Dat

a St

orag

e, D

ata

Tran

smis

sion

& M

anip

ulat

ion,

Dig

ital V

ideo

, Em

bedd

ed M

icro

proc

esso

r, Em

bedd

ed S

yste

m, I

P-Ba

sed

Syst

ems,

Imag

e Pr

oces

sing

, Lo

w p

ower

des

igns

, Mul

timed

ia, N

avig

atio

n, P

CI, R

econ

figur

able

Com

putin

g, S

eria

l/De

seria

lizat

ion,

Tele

com

/ Da

taco

m, T

elem

atic

s, Vo

IP

RT-D

AC4/

PCI-O

MN

I O

MN

I Boa

rd

INTE

CO

XC2S

100,

XC2

S150

, XC2

S50

ASIC

Pro

toty

ping

, DSP

, Dat

a St

orag

e, D

ata

Tran

smis

sion

& M

anip

ulat

ion,

Dig

ital V

ideo

, Em

bedd

ed M

icro

proc

esso

r, Em

bedd

ed S

yste

m, I

P-Ba

sed

Syst

ems,

Imag

e Pr

oces

sing

, Lo

w p

ower

des

igns

, Mul

timed

ia, N

avig

atio

n, P

CI, R

econ

figur

able

Com

putin

g, S

eria

l/De

seria

lizat

ion,

Tele

com

/ Da

taco

m, T

elem

atic

s, Vo

IP

Mic

roEn

gine

V

CPU

+ F

PGA

(Virt

ex/S

part

an-II

) Mic

roEn

gine

Car

ds

Intr

insy

c, In

c.

Spar

tan-

II Em

bedd

ed S

yste

ms

NPE

565-

M

Spar

tan-

II Po

wer

-PC

Engi

ne

Nor

th P

ole

Engi

neer

ing

XC2S

200

Prot

otyp

ing,

DSP

, Em

bedd

ed S

yste

m, I

ndus

tria

l Aut

omot

ive,

Rec

onfig

urab

le C

ompu

ting

NV-

FPSD

-001

FP

GA

SDRA

M C

ontr

olle

r Eva

luat

ion

Boar

d N

ovte

ch

XC2S

50

Prot

otyp

ing,

DSP

, Dat

a St

orag

e, D

ata

Tran

smis

sion

& M

anip

ulat

ion,

Dig

ital V

ideo

, Em

bedd

ed

Mic

ropr

oces

sor,

Embe

dded

Sys

tem

, IP-

Base

d Sy

stem

s, Im

age

Proc

essi

ng, L

ow p

ower

des

igns

, M

ultim

edia

, Nav

igat

ion,

PCI

, Rec

onfig

urab

le C

ompu

ting,

Ser

ial/D

eser

ializ

atio

n, Te

leco

m /

Data

com

, Tel

emat

ics,

VoIP

SPCM

USB

-EVL

U

SB 2

.0 M

ass

Stor

age

Clas

s Re

fere

nce

Desi

gn

Spec

soft

Cons

ultin

g, In

c.

XC2S

200

Prot

otyp

ing,

Dat

a St

orag

e, E

mbe

dded

Sys

tem

, IP-

Base

d Sy

stem

s

SPCV

USB

-EVL

U

SB 2

.0 V

ideo

Cla

ss R

efer

ence

Des

ign

Spec

soft

Cons

ultin

g, In

c.

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200

Prot

otyp

ing,

Dat

a Tr

ansm

issi

on &

Man

ipul

atio

n, E

mbe

dded

Sys

tem

, IP-

Base

d Sy

stem

s

* In

sigh

t Pro

duct

s: A

ppen

d -E

URO

to p

art n

umbe

r for

inte

rnat

iona

l kits

(ex.

DS-

KIT-

2SLC

100-

EURO

); P

ower

Sup

ply

not i

nclu

ded

in -E

URO

kits

Xil

inx O

n B

oard

– D

evelo

pm

en

t R

efe

ren

ce B

oard

sh

ttp

://w

ww

.xil

inx

.co

m/b

oa

rd_s

ea

rch


Boar

d Pa

rt N

umbe

r

ADM

-XPL

Boar

d D

escr

ipti

on

Reco

nfig

urab

le C

ompu

ter B

ased

on

Virt

ex-II

Pro

Supp

lier

Alph

a Da

ta

Xilin

x D

evic

e Su

ppor

t

XC2V

P7, X

C2VP

20

App

licat

ion

DSP,

Reco

nfig

urab

le C

ompu

ting

, Im

age

Proc

essi

ng ,

ASIC

Pro

toty

ping

Virt

ex-II

Pro

PCI P

latfo

rm

Virt

ex-II

Pro

PCI

Pla

tform

FPG

A De

velo

pmen

t Boa

rd

Amiri

x Sy

stem

s, In

c.

XC2V

P7,X

C2VP

20, X

C2VP

30

Net

wor

king

(SAN

, VoI

P, Br

idge

s), C

omm

unic

atio

ns, D

SP, I

mag

e Pr

oces

sing

, Ind

ustr

ial C

ontr

ols,

Inst

rum

enta

tion,

test

and

mea

sure

men

t

ADS-

XLX-

V2PR

O-D

EVP2

0-6

Virt

ex-II

Pro

Dev

elop

men

t Kit

w/X

C2VP

20, -

6 sp

eed

grad

e Av

net D

esig

n Se

rvic

es

XC2V

P20

Prot

otyp

ing,

DSP

, Dat

a St

orag

e, D

ata

Tran

smis

sion

& M

anip

ulat

ion,

Em

bedd

ed M

icro

proc

esso

r, Em

bedd

ed S

yste

m, I

P-Ba

sed

Syst

ems,

Nav

igat

ion,

PCI

, Rec

onfig

urab

le C

ompu

ting,

Ser

ial /

De

seria

lizat

ion

ADS-

XLX-

V2PR

O-D

EVP3

0-6

Virt

ex-II

Pro

Dev

elop

men

t Kit

w/X

C2VP

30, -

6 sp

eed

grad

e Av

net D

esig

n Se

rvic

es

XC2V

P30

Prot

otyp

ing,

DSP

, Dat

a St

orag

e, D

ata

Tran

smis

sion

& M

anip

ulat

ion,

Em

bedd

ed M

icro

proc

esso

r, Em

bedd

ed S

yste

m, I

P-Ba

sed

Syst

ems,

Nav

igat

ion,

PCI

, Rec

onfig

urab

le C

ompu

ting,

Ser

ial /

De

seria

lizat

ion

ADS-

XLX-

V2PR

O-D

EVP7

-5

Virt

ex-II

Pro

Dev

elop

men

t Kit

w/X

c2VP

7, -5

spe

ed g

rade

Av

net D

esig

n Se

rvic

es

XC2V

P7

Prot

otyp

ing,

DSP

, Dat

a St

orag

e, D

ata

Tran

smis

sion

& M

anip

ulat

ion,

Em

bedd

ed M

icro

proc

esso

r, Em

bedd

ed S

yste

m, I

P-Ba

sed

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ems,

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ion,

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, Rec

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le C

ompu

ting,

Ser

ial /

De

seria

lizat

ion

ADS-

XLX-

V2PR

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EVP7

-6

Virt

ex-II

Pro

Dev

elop

men

t Kit

w/X

c2VP

7, -6

spe

ed g

rade

Av

net D

esig

n Se

rvic

es

XC2V

P7

Prot

otyp

ing,

DSP

, Dat

a St

orag

e, D

ata

Tran

smis

sion

& M

anip

ulat

ion,

Em

bedd

ed M

icro

proc

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r, Em

bedd

ed S

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m, I

P-Ba

sed

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ems,

Nav

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ion,

PCI

, Rec

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le C

ompu

ting,

Ser

ial /

De

seria

lizat

ion

ADS-

XLX-

V2PR

O-E

VLP7

-5

Virt

ex-II

Pro

Eva

luat

ion

Kit w

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VP7,

-5 s

peed

gra

de

Avne

t Des

ign

Serv

ices

XC

2VP7

Ve

ry c

ost e

ffect

ive

eval

uatio

n an

d pr

otot

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g pl

atfo

rm to

dev

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and

test

des

igns

targ

eted

to

the

Virt

ex-II

Pro

dev

ice

ADS-

XLX-

V2PR

O-E

VLP7

-6

Virt

ex-II

Pro

Eva

luat

ion

Kit w

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VP7,

-6 s

peed

gra

de

Avne

t Des

ign

Serv

ices

XC

2VP7

Ve

ry c

ost e

ffect

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eval

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n an

d pr

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g pl

atfo

rm to

dev

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and

test

des

igns

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to

the

Virt

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Pro

dev

ice

V2PR

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it Vi

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ro™

Dev

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men

t Kit

Avne

t Des

ign

Serv

ices

XC

2VP7

, XC2

VP20

, SC2

VP30

Pa

cket

sw

itchi

ng; n

etw

ork

secu

rity;

SAN

, ser

vers

and

sup

er c

ompu

ters

; vid

eo c

ompu

ting/

tran

smis

sion

; Hig

h-sp

eed

seria

l int

erfa

ces

D6PC

Da

nube

6-P

aC

Bitt

War

e, In

c.

XC2V

P20

DSP,

Data

Tran

smis

sion

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anip

ulat

ion,

Em

bedd

ed S

yste

m, I

mag

e Pr

oces

sing

, Mul

timed

ia,

Reco

nfig

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le C

ompu

ting,

Tele

com

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acom

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DN60

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0S A

SIC

Prot

otyp

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Engi

ne

DIN

I Gro

up

XC2V

P125

, XC2

VP70

Pr

otot

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g, D

SP, D

ata

Stor

age,

Dat

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on &

Man

ipul

atio

n, D

igita

l Vid

eo, E

mbe

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M

icro

proc

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r, Em

bedd

ed S

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m, I

P-Ba

sed

Syst

ems,

Imag

e Pr

oces

sing

, Low

pow

er d

esig

ns,

Mul

timed

ia, N

avig

atio

n, P

CI, R

econ

figur

able

Com

putin

g, S

eria

l/Des

eria

lizat

ion,

Dat

acom

/ Te

leco

m, T

elem

atic

s, Vo

IP

DS-K

IT-2

VP20

FF11

52*

Virt

ex-II

Pro

FF1

152

P20

Deve

lopm

ent K

it In

sigh

t (M

emec

) XC

2VP2

0 in

FF1

152

DS-K

IT-2

VP30

FF11

52*

Virt

ex-II

Pro

FF1

152

P30

Deve

lopm

ent K

it In

sigh

t (M

emec

) XC

2VP3

0 in

FF1

152

DS-K

IT-2

VP4F

F672

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ro F

F672

P4

Deve

lopm

ent K

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sigh

t (M

emec

) XC

2VP4

in F

F672

DS-K

IT-2

VP4F

G45

6*

Virt

ex-II

Pro

P4

FG45

6 De

velo

pmen

t Kit

Insi

ght (

Mem

ec)

XC2V

P4 in

FG

456

DSP,

Digi

tal V

ideo

, Em

bedd

ed S

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m, I

P-Ba

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Syst

ems,

Imag

e Pr

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VP7F

F672

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ro F

F672

P7

Deve

lopm

ent K

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URO

Insi

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Mem

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XC2V

P7 in

FF6

72

DS-K

IT-2

VP7F

G45

6*

Virt

ex-II

Pro

P7

FG45

6 De

velo

pmen

t Kit

Insi

ght (

Mem

ec)

XC2V

P7 in

FG

456

DSP,

Digi

tal V

ideo

, Em

bedd

ed S

yste

m, I

P-Ba

sed

Syst

ems,

Imag

e Pr

oces

sing

BenP

RO-2

VP7-

6 Be

nPRO

N

alla

tech

XC

2VP7

-XC2

VP20

Da

ta N

etw

orks

& D

igita

l Sig

nal p

roce

ssin

g, E

mbe

dded

Sys

tem

, Tel

ecom

SMT3

87

Disk

Sto

rage

Mod

ule

Sund

ance

Mul

tipro

cess

or C

o.

XC2V

P20

DSP,

Data

Sto

rage

, Dat

a Tr

ansm

issi

on &

Man

ipul

atio

n, D

igita

l Vid

eo, E

ncry

ptio

n De

vice

s, Im

age

Proc

essi

ng, R

econ

figur

able

Com

putin

g

TB-V

2P-2

0-M

GT

Virt

ex-II

Pro

Roc

ket I

/O E

valu

atio

n Bo

ard

Toky

o El

ectr

on D

evic

e Li

mite

d XC

2VP2

0-6F

F896

Pr

otot

ypin

g, D

SP, D

ata

Tran

smis

sion

& M

anip

ulat

ion,

Em

bedd

ed M

icro

proc

esso

r, Em

bedd

ed

Syst

em, I

P-Ba

sed

Syst

ems,

Reco

nfig

urab

le C

ompu

ting,

Ser

ial /

Des

eria

lizat

ion

TB-V

2P-3

0-M

GT

Virt

ex-II

Pro

Roc

ket I

/O E

valu

atio

n Bo

ard

Toky

o El

ectr

on D

evic

e Li

mite

d XC

2VP3

0-6F

F896

Pr

otot

ypin

g, D

SP, D

ata

Tran

smis

sion

& M

anip

ulat

ion,

Em

bedd

ed M

icro

proc

esso

r, Em

bedd

ed

Syst

em, I

P-Ba

sed

Syst

ems,

Reco

nfig

urab

le C

ompu

ting,

Ser

ial /

Des

eria

lizat

ion

* In

sigh

t Pro

duct

s: A

ppen

d -E

URO

to p

art n

umbe

r for

inte

rnat

iona

l kits

(ex.

DS-

KIT-

2SLC

100-

EURO

); P

ower

Sup

ply

not i

nclu

ded

in -E

URO

kits

. For

Virt

ex-II

Pro

, 2VP

40 a

nd 2

VP50

boa

rds

are

avai

labl

e up

on c

usto

mer

requ

est.

Xil

inx O

n B

oard

– D

evelo

pm

en

t R

efe

ren

ce B

oard

sh

ttp

://w

ww

.xil

inx

.co

m/b

oa

rd_s

ea

rch


Boar

d Pa

rt N

umbe

r

TB-V

2P-7

-MG

T

Boar

d D

escr

ipti

on

Virt

ex-II

Pro

Roc

ket I

/O E

valu

atio

n Bo

ard

Supp

lier

Toky

o El

ectr

on D

evic

e Li

mite

d

Xilin

x D

evic

e Su

ppor

t

XC2V

P7-6

FF89

6

App

licat

ion

Prot

otyp

ing,

DSP

, Dat

a Tr

ansm

issi

on &

Man

ipul

atio

n, E

mbe

dded

Mic

ropr

oces

sor,

Embe

dded

Sy

stem

, IP-

Base

d Sy

stem

s, Re

conf

igur

able

Com

putin

g, S

eria

l / D

eser

ializ

atio

n

Virt

ex-II

Pro

XSP-

016

Virt

ex-II

Pro

Pow

erPC

&M

icro

Blaz

e Ev

alua

tion

Boar

d To

kyo

Elec

tron

Dev

ice

Lim

ited

XC2V

P7-5

FG45

6 Pr

otot

ypin

g, D

SP, D

ata

Tran

smis

sion

& M

anip

ulat

ion,

Em

bedd

ed M

icro

proc

esso

r, Em

bedd

ed

Syst

em, I

P-Ba

sed

Syst

ems,

Reco

nfig

urab

le C

ompu

ting

DO-V

2P-M

L300

-EC

Virt

ex-II

Pro

ML3

00 E

valu

atio

n Pl

atfo

rm- E

C ve

rsio

n Xi

linx

Onl

ine

Stor

e XC

2VP7

Pr

otot

ypin

g, D

SP, D

ata

Stor

age,

Dat

a Tr

ansm

issi

on &

Man

ipul

atio

n, D

igita

l Vid

eo, E

mbe

dded

M

icro

proc

esso

r, Em

bedd

ed S

yste

m, I

P-Ba

sed

Syst

ems,

Imag

e Pr

oces

sing

, Mul

timed

ia,

Nav

igat

ion,

PCI

, Rec

onfig

urab

le C

ompu

ting,

Ser

ializ

atio

n / D

eser

ializ

atio

n, Te

leco

m

DO-V

2P-M

L300

-UK

Virt

ex-II

Pro

ML3

00 E

valu

atio

n Pl

atfo

rm- U

K ve

rsio

n Xi

linx

Onl

ine

Stor

e XC

2VP7

Pr

otot

ypin

g, D

SP, D

ata

Stor

age,

Dat

a Tr

ansm

issi

on &

Man

ipul

atio

n, D

igita

l Vid

eo, E

mbe

dded

M

icro

proc

esso

r, Em

bedd

ed S

yste

m, I

P-Ba

sed

Syst

ems,

Imag

e Pr

oces

sing

, Mul

timed

ia,

Nav

igat

ion,

PCI

, Rec

onfig

urab

le C

ompu

ting,

Ser

ializ

atio

n / D

eser

ializ

atio

n, Te

leco

m

DO-V

2P-M

L300

-USA

Vi

rtex

-II P

ro M

L300

Eva

luat

ion

Plat

form

- US

vers

ion

Xilin

x O

nlin

e St

ore

XC2V

P7

Prot

otyp

ing,

DSP

, Dat

a St

orag

e, D

ata

Tran

smis

sion

& M

anip

ulat

ion,

Dig

ital V

ideo

, Em

bedd

ed

Mic

ropr

oces

sor,

Embe

dded

Sys

tem

, IP-

Base

d Sy

stem

s, Im

age

Proc

essi

ng, M

ultim

edia

, N

avig

atio

n, P

CI, R

econ

figur

able

Com

putin

g, S

eria

lizat

ion

/ Des

eria

lizat

ion,

Tele

com

/ Da

taco

m, T

elem

atic

s, Vo

IP

DO-V

2P-M

L300

-WRS

-EC

Virt

ex-II

Pro

ML3

00 E

valu

atio

n Pl

atfo

rm w

ith

Win

dRiv

er to

ols

- EC

vers

ion

Xilin

x O

nlin

e St

ore

XC2V

P7

Prot

otyp

ing,

DSP

, Dat

a St

orag

e, D

ata

Tran

smis

sion

& M

anip

ulat

ion,

Dig

ital V

ideo

, Em

bedd

ed

Mic

ropr

oces

sor,

Embe

dded

Sys

tem

, IP-

Base

d Sy

stem

s, Im

age

Proc

essi

ng, M

ultim

edia

, N

avig

atio

n, P

CI, R

econ

figur

able

Com

putin

g, S

eria

lizat

ion

/ Des

eria

lizat

ion,

Tele

com

DO-V

2P-M

L300

-WRS

-UK

Virt

ex-II

Pro

ML3

00 E

valu

atio

n Pl

atfo

rm w

ith

Win

dRiv

er to

ols

- UK

vers

ion

Xilin

x O

nlin

e St

ore

XC2V

P7

Prot

otyp

ing,

DSP

, Dat

a St

orag

e, D

ata

Tran

smis

sion

& M

anip

ulat

ion,

Dig

ital V

ideo

, Em

bedd

ed

Mic

ropr

oces

sor,

Embe

dded

Sys

tem

, IP-

Base

d Sy

stem

s, Im

age

Proc

essi

ng, M

ultim

edia

, N

avig

atio

n, P

CI, R

econ

figur

able

Com

putin

g, S

eria

lizat

ion

/ Des

eria

lizat

ion,

Tele

com

DO-V

2P-M

L300

-WRS

-USA

Vi

rtex

-II P

ro M

L300

Eva

luat

ion

Plat

form

with

W

indR

iver

tool

s - U

S ve

rsio

n Xi

linx

Onl

ine

Stor

e XC

2VP7

Pr

otot

ypin

g, D

SP, D

ata

Stor

age,

Dat

a Tr

ansm

issi

on &

Man

ipul

atio

n, D

igita

l Vid

eo, E

mbe

dded

M

icro

proc

esso

r, Em

bedd

ed S

yste

m, I

P-Ba

sed

Syst

ems,

Imag

e Pr

oces

sing

, Mul

timed

ia,

Nav

igat

ion,

PCI

, Rec

onfig

urab

le C

ompu

ting,

Ser

ializ

atio

n / D

eser

ializ

atio

n, Te

leco

m /

Data

com

, Tel

emat

ics,

VoIP

HW-A

FX-F

F115

2-30

0 Vi

rtex

-II P

ro P

roto

Boa

rdXi

linx

Onl

ine

Stor

e XC

2VP2

0, X

C2VP

30, X

C2VP

40, X

C2VP

50

Prot

otyp

ing,

DSP

, Dat

a St

orag

e, D

ata

Tran

smis

sion

& M

anip

ulat

ion,

Em

bedd

ed M

icro

proc

esso

r, Em

bedd

ed S

yste

m, I

P-Ba

sed

Syst

ems,

Imag

e Pr

oces

sing

, Nav

igat

ion,

Rec

onfig

urab

le

Com

putin

g, S

eria

l / D

eser

ializ

atio

n, Te

leco

m /

Data

com

, Tel

emat

ics,

VoIP

HW-A

FX-F

F672

-300

Vi

rtex

-II P

ro P

roto

Boa

rd

Xilin

x O

nlin

e St

ore

XC2V

P2, X

C2VP

4, X

C2VP

7 Pr

otot

ypin

g, D

SP, D

ata

Stor

age,

Dat

a Tr

ansm

issi

on &

Man

ipul

atio

n, E

mbe

dded

Mic

ropr

oces

sor,

Embe

dded

Sys

tem

, IP-

Base

d Sy

stem

s, Im

age

Proc

essi

ng, N

avig

atio

n, R

econ

figur

able

Co

mpu

ting,

Ser

ial /

Des

eria

lizat

ion,

Tele

com

/ Da

taco

m, T

elem

atic

s, Vo

IP

HW-A

FX-F

G45

6-30

0 Vi

rtex

-II P

ro P

roto

Boa

rd

Xilin

x O

nlin

e St

ore

XC2V

P2, X

C2VP

4, X

C2VP

7 Pr

otot

ypin

g, D

SP, D

ata

Stor

age,

Dat

a Tr

ansm

issi

on &

Man

ipul

atio

n, E

mbe

dded

Mic

ropr

oces

sor,

Embe

dded

Sys

tem

, IP-

Base

d Sy

stem

s, Im

age

Proc

essi

ng, N

avig

atio

n, R

econ

figur

able

Co

mpu

ting,

Ser

ial /

Des

eria

lizat

ion,

Tele

com

/ Da

taco

m, T

elem

atic

s, Vo

IP

HW-A

FX-S

MA-

HSSD

C2

SMA

To H

SSDC

2 Co

nver

sion

Mod

ule

Xilin

x O

nlin

e St

ore

Supp

orts

boa

rds

with

SM

A co

nnec

tors

HW-A

FX-S

MA-

RJ45

SM

A To

RJ4

5 Co

nver

sion

Mod

ule

Xilin

x O

nlin

e St

ore

Supp

orts

boa

rds

with

SM

A co

nnec

tors

HW-A

FX-S

MA-

SATA

SM

A To

SAT

A Co

nver

sion

Mod

ule

Xilin

x O

nlin

e St

ore

Supp

orts

boa

rds

with

SM

A co

nnec

tors

HW-A

FX-S

MA-

SFP

SM

A To

SFP

Con

vers

ion

Mod

ule

Xilin

x O

nlin

e St

ore

Supp

orts

boa

rds

with

SM

A co

nnec

tors

DO-V

2P-M

L300

-USA

Vi

rtex

-II P

ro M

L300

Eva

luat

ion

Plat

form

- US

vers

ion

Xilin

x Sa

les

Offi

ces

XC2V

P7

Prot

otyp

ing,

DSP

, Dat

a St

orag

e, D

ata

Tran

smis

sion

& M

anip

ulat

ion,

Dig

ital V

ideo

, Em

bedd

ed

Mic

ropr

oces

sor,

Embe

dded

Sys

tem

, IP-

Base

d Sy

stem

s, Im

age

Proc

esin

g, M

ultim

edia

, N

avig

atio

n, P

CI, R

econ

figur

able

Com

putin

g, S

eria

l / D

eser

ializ

atio

n, Te

leco

m /

Data

com

, Te

lem

atic

s, Vo

IP

HW-V

2PRO

-XLV

DS

Virt

ex-II

Pro

XLV

DS

Xilin

x Sa

les

Offi

ces

XC2V

P20

Data

Tran

smis

sion

& M

anip

ulat

ion,

Em

bedd

ed S

yste

m, E

ncry

ptio

n De

vice

s, IP

-Bas

ed S

yste

ms,

Reco

nfig

urab

le C

ompu

ting,

Ser

ial /

Des

eria

lizat

ion,

Tele

com

/ Da

taco

m, T

est E

quip

men

t

* In

sigh

t Pro

duct

s: A

ppen

d -E

URO

to p

art n

umbe

r for

inte

rnat

iona

l kits

(ex.

DS-

KIT-

2SLC

100-

EURO

); P

ower

Sup

ply

not i

nclu

ded

in -E

URO

kits

Xil

inx O

n B

oard

– D

evelo

pm

en

t R

efe

ren

ce B

oard

sh

ttp

://w

ww

.xil

inx

.co

m/b

oa

rd_s

ea

rch


Boar

d Pa

rt N

umbe

r

ADM

-XPL

/2VP

7-5

Boar

d D

escr

ipti

on

ADM

-XPL

Supp

lier

Alph

a Da

ta

Xilin

x D

evic

e Su

ppor

t

XC2V

1000

, XC2

VP20

, XC2

VP7

App

licat

ion

Prot

otyp

ing,

DSP

, Im

age

Proc

essi

ng, R

econ

figur

able

Com

putin

g

Virt

ex-II

ADM

-XRC

-II

ADM

-XRC

-II

Alph

a Da

ta

XC2V

3000

, XC2

V400

0, X

C2V6

000,

XC2

V800

0 Pr

otot

ypin

g, C

ompr

essi

on, D

SP, E

ncry

ptio

n, R

econ

figur

able

CO

mpu

ting,

Sof

twar

e Ra

dio,

Vi

deo

/ Im

age

Proc

essi

ng, X

ML

proc

essi

ng

ADS-

V2-M

B-DE

V400

0XP

Virt

ex-II

XC2

V400

0XP

Deve

lopm

ent K

it w

ith M

icro

Blaz

e Av

net D

esig

n Se

rvic

es

XC2V

4000

Pr

otot

ypin

g. D

ata

Tran

smis

sion

& M

anip

ulat

ion,

Hig

hend

DSP

, IP-

Base

d Sy

stem

s, PC

I

ADS-

V2-M

B-DE

V600

0XP

Virt

ex-II

XC2

V600

0 De

velo

pmen

t Kit

with

Mic

roBl

aze

Avne

t Des

ign

Serv

ices

XC

2V60

00

Prot

otyp

ing.

Dat

a Tr

ansm

issi

on &

Man

ipul

atio

n, H

ighe

nd D

SP, I

P-Ba

sed

Syst

ems,

PCI

ADS-

XLX-

MB-

DEV1

500

Virt

ex-II

XC2

V150

0 De

velo

pmen

t Kit

with

Mic

roBl

aze

Avne

t Des

ign

Serv

ices

XC

2V15

00

Prot

otyp

ing,

Dat

a Tr

ansm

issi

on &

Man

ipul

atio

n, H

igh

End

DSP,

IP-b

ased

Sys

tem

s, PC

I

ADS-

XLX-

MB-

DEV4

000

Virt

ex-II

XC2

V400

0 De

velo

pmen

t Kit

with

Mic

roBl

aze

Avne

t Des

ign

Serv

ices

XC

2V40

00

Prot

otyp

ing,

Dat

a Tr

ansm

issi

on &

Man

ipul

atio

n, H

igh

End

DSP,

IP-b

ased

Sys

tem

s, PC

I

ADS-

XLX-

PMC-

IRL

PMC

IRL

Refe

renc

e De

sign

Kit

Avne

t Des

ign

Serv

ices

XC

2V10

00-4

FG45

6C/F

F896

C Co

nsum

er, I

ndus

tria

l, IR

L, P

AVE,

Tele

com

/Dat

acom

, Tel

ecom

mun

icat

ions

ADS-

XLX-

V2-D

EV15

00

Virt

ex-II

Dev

elop

men

t Kit

w/X

C2V1

500

devi

ce

Avne

t Des

ign

Serv

ices

XC

2V15

00

Com

plet

e ha

rdw

are

envi

ronm

ent t

o de

velo

p, p

roto

type

, and

test

des

igns

targ

eted

to th

e Vi

rtex

-II F

PGA

fam

ily

ADS-

XLX-

V2-D

EV40

00

Virt

ex-II

XC2

V400

0 De

velo

pmen

t Kit

w/X

C2V4

000

devi

ce

Avne

t Des

ign

Serv

ices

XC

2V40

00

Prot

otyp

ing,

Dat

a Tr

ansm

issi

on &

Man

ipul

atio

n, H

igh

End

DSP,

IP-b

ased

Sys

tem

s, PC

I

ADS-

XLX-

V2-D

EV40

00XP

Vi

rtex

-II X

C2V4

000X

P De

velo

pmen

t Kit

w/h

igh-

curr

ent p

ower

sup

ply

Av

net D

esig

n Se

rvic

es

XC2V

4000

Pr

otot

ypin

g. D

ata

Tran

smis

sion

& M

anip

ulat

ion,

Hig

hend

DSP

, IP-

Base

d Sy

stem

s, PC

I

ADS-

XLX-

V2-D

EV60

00XP

Vi

rtex

-II X

C2V6

000

Deve

lopm

ent K

it w

/hig

h-cu

rren

t pow

er s

uppl

y Av

net D

esig

n Se

rvic

es

XC2V

6000

Pr

otot

ypin

g. D

ata

Tran

smis

sion

& M

anip

ulat

ion,

Hig

hend

DSP

, IP-

Base

d Sy

stem

s, PC

I

ADS-

XLX-

V2-E

VL10

00

Virt

ex-II

XC2

V100

0 Ev

alua

tion

Kit

Avne

t Des

ign

Serv

ices

XC

2V10

00-4

FG25

6 Pr

otot

ypin

g, D

ata

Tran

smis

sion

& M

anip

ulat

ion,

Hig

h En

d DS

P, IP

-bas

ed S

yste

ms

ADS-

XLX-

XV2-

EVL

Virt

ex-II

Hig

h-Sp

eed

Eval

uatio

n Ki

t Av

net D

esig

n Se

rvic

es

XC2V

40

Data

Tran

smis

sion

& M

anip

ulat

ion,

DSP

BCPM

Ba

rrac

uda-

PMC+

Bi

ttW

are,

Inc.

XC

2V10

00

DSP,

Data

Tran

smis

sion

& M

anip

ulat

ion,

Em

bedd

ed S

yste

m, I

mag

e Pr

oces

sing

, Mul

timed

ia,

Reco

nfig

urab

le C

ompu

ting,

Tele

com

/Dat

acom

RFPM

Re

ef-P

MC+

Bi

ttW

are,

Inc.

XC

2V10

00

Prot

otyp

ing,

DSP

, Dat

a St

orag

e, D

ata

Tran

smis

sion

& M

anip

ulat

ion,

Dig

ital V

ideo

, Em

bedd

ed

Mic

ropr

oces

sor,

Embe

dded

Sys

tem

, IP-

Base

d Sy

stem

s, Im

age

Proc

essi

ng, L

ow p

ower

des

igns

, M

ultim

edia

, Nav

igat

ion,

PCI

, Rec

onfig

urab

le C

ompu

ting,

Ser

ial/D

eser

ializ

atio

n, D

atac

om /

Tele

com

, Tel

emat

ics,

VoIP

RMPM

Re

mor

a-PM

C+

Bitt

War

e, In

c.

XC2V

1000

Pr

otot

ypin

g, D

SP, D

ata

Stor

age,

Dat

a Tr

ansm

issi

on &

Man

ipul

atio

n, D

igita

l Vid

eo, E

mbe

dded

M

icro

proc

esso

r, Em

bedd

ed S

yste

m, I

P-Ba

sed

Syst

ems,

Imag

e Pr

oces

sing

, Low

pow

er d

esig

ns,

Mul

timed

ia, N

avig

atio

n, P

CI, R

econ

figur

able

Com

putin

g, S

eria

l/Des

eria

lizat

ion,

Dat

acom

/ Te

leco

m, T

elem

atic

s, Vo

IP

CYL2

T020

1-DV

K M

etro

Link

2T-2

Lin

k La

yer E

valu

atio

n Bo

ard

Cypr

ess

Sem

icon

duct

or C

orpo

ratio

n XC

2V20

00

Data

Tran

smis

sion

& M

anip

ulat

ion,

IP-B

ased

Sys

tem

s, Te

leco

m /

Data

com

PF31

00

PC/1

04-P

lus

Reco

nfig

urab

le M

odul

e Bo

ard

(PF3

100)

De

rivat

ion

Syst

ems,

Inc.

XC

2V10

00, F

G25

6 In

tern

et a

pplia

nce,

indu

stria

l con

trol

DN30

00K1

0 DN

3000

K10

ASIC

Pro

toty

ping

Eng

ine

DIN

I Gro

up

XC2V

4000

, XC2

V600

0, X

C2V8

000

Prot

otyp

ing,

DSP

, Dat

a St

orag

e, D

ata

Tran

smis

sion

& M

anip

ulat

ion,

Dig

ital V

ideo

, Em

bedd

ed

Mic

ropr

oces

sor,

Embe

dded

Sys

tem

, IP-

Base

d Sy

stem

s, Im

age

Proc

essi

ng, L

ow p

ower

des

igns

, M

ultim

edia

, Nav

igat

ion,

PCI

, Rec

onfig

urab

le C

ompu

ting,

Ser

ial/D

eser

ializ

atio

n, Te

leco

m/

Data

com

, Tel

emat

ics,

VoIP

DN30

00k1

0 DN

3000

k10

DIN

I Gro

up

XC2V

4000

, XC2

V600

0, X

C2V8

000

Prot

otyp

ing,

Alg

orith

mic

Acc

eler

atio

n, L

ogic

Em

ulat

ion,

PCI

/ PC

I-X, R

econ

figur

able

Com

putin

g

CHM

2-VM

E-60

4-SZ

Ch

amel

eon

II VM

E Re

conf

igur

able

Com

putin

g Bo

ard

DRS

Tact

ical

Sys

tem

s Wes

t, In

c.

XC2V

6000

Pr

otot

ypin

g, D

SP, I

P-Ba

sed

Syst

ems,

Imag

e Pr

oces

sing

, Rec

onfig

urab

le C

ompu

ting,

Tele

com

/ Da

taco

m, T

elem

atic

s

APB-

2V10

00

Virt

ex-II

Pro

toty

ping

Boa

rd fo

r 2V1

000

ErSt

Ele

ctro

nics

XC

2V10

00

Prot

otyp

ing,

Dat

a Tr

ansm

issi

on &

Man

ipul

atio

n, E

mbe

dded

Mic

ropr

oces

sor,

Embe

dded

Sys

tem

, IP

-Bas

ed S

yste

ms,

Imag

e Pr

oces

sing

, Mul

timed

ia, R

econ

figur

able

Com

putin

g, S

eria

l /

Dese

rializ

atio

n, Te

leco

m /

Data

com

, VoI

P

* In

sigh

t Pro

duct

s: A

ppen

d -E

URO

to p

art n

umbe

r for

inte

rnat

iona

l kits

(ex.

DS-

KIT-

2SLC

100-

EURO

); P

ower

Sup

ply

not i

nclu

ded

in -E

URO

kits

Xil

inx O

n B

oard

– D

evelo

pm

en

t R

efe

ren

ce B

oard

sh

ttp

://w

ww

.xil

inx

.co

m/b

oa

rd_s

ea

rch


Boar

d Pa

rt N

umbe

r

APB-

2V15

00

Boar

d D

escr

ipti

on

Virt

ex-II

Pro

toty

ping

Boa

rd fo

r 2V1

500

Supp

lier

ErSt

Ele

ctro

nics

Xilin

x D

evic

e Su

ppor

t

XC2V

1500

App

licat

ion

Prot

otyp

ing,

Dat

a Tr

ansm

issi

on &

Man

ipul

atio

n, E

mbe

dded

Mic

ropr

oces

sor,

Embe

dded

Sys

tem

, IP

-Bas

ed S

yste

ms,

Imag

e Pr

oces

sing

, Mul

timed

ia, R

econ

figur

able

Com

putin

g, S

eria

l /

Dese

rializ

atio

n, Te

leco

m /

Data

com

, VoI

P

Virt

ex-II

APB-

2V20

00

Virt

ex-II

Pro

toty

ping

Boa

rd fo

r 2V2

000

ErSt

Ele

ctro

nics

XC

2V20

00

Prot

otyp

ing,

Dat

a Tr

ansm

issi

on &

Man

ipul

atio

n, E

mbe

dded

Mic

ropr

oces

sor,

Embe

dded

Sys

tem

, IP

-Bas

ed S

yste

ms,

Imag

e Pr

oces

sing

, Mul

timed

ia, R

econ

figur

able

Com

putin

g, S

eria

l /

Dese

rializ

atio

n, Te

leco

m /

Data

com

, VoI

P

APB-

2V30

00

Virt

ex-II

Pro

toty

ping

Boa

rd fo

r 2V3

000

ErSt

Ele

ctro

nics

XC

2V30

00

Prot

otyp

ing,

Dat

a Tr

ansm

issi

on &

Man

ipul

atio

n, E

mbe

dded

Mic

ropr

oces

sor,

Embe

dded

Sys

tem

, IP

-Bas

ed S

yste

ms,

Imag

e Pr

oces

sing

, Mul

timed

ia, R

econ

figur

able

Com

putin

g, S

eria

l /

Dese

rializ

atio

n, Te

leco

m /

Data

com

, VoI

P

APB-

2V40

00

Virt

ex-II

Pro

toty

ping

Boa

rd fo

r 2V4

000

ErSt

Ele

ctro

nics

XC

2V40

00

Prot

otyp

ing,

Dat

a Tr

ansm

issi

on &

Man

ipul

atio

n, E

mbe

dded

Mic

ropr

oces

sor,

Embe

dded

Sys

tem

, IP

-Bas

ed S

yste

ms,

Imag

e Pr

oces

sing

, Mul

timed

ia, R

econ

figur

able

Com

putin

g, S

eria

l /

Dese

rializ

atio

n, Te

leco

m /

Data

com

, VoI

P

APB-

2V60

00

Virt

ex-II

Pro

toty

ping

Boa

rd fo

r 2V6

000

ErSt

Ele

ctro

nics

XC

2V60

00

Prot

otyp

ing,

Dat

a Tr

ansm

issi

on &

Man

ipul

atio

n, E

mbe

dded

Mic

ropr

oces

sor,

Embe

dded

Sys

tem

, IP

-Bas

ed S

yste

ms,

Imag

e Pr

oces

sing

, Mul

timed

ia, R

econ

figur

able

Com

putin

g, S

eria

l /

Dese

rializ

atio

n, Te

leco

m /

Data

com

, VoI

P

APB-

2V80

00

Virt

ex-II

Pro

toty

ping

Boa

rd fo

r 2V8

000

ErSt

Ele

ctro

nics

XC

2V80

00

Prot

otyp

ing,

Dat

a Tr

ansm

issi

on &

Man

ipul

atio

n, E

mbe

dded

Mic

ropr

oces

sor,

Embe

dded

Sys

tem

, IP

-Bas

ed S

yste

ms,

Imag

e Pr

oces

sing

, Mul

timed

ia, R

econ

figur

able

Com

putin

g, S

eria

l /

Dese

rializ

atio

n, Te

leco

m /

Data

com

, VoI

P

GVA

-300

DS

P Ha

rdw

are

Acce

lera

tor,

Virt

ex-II

(GVA

-300

) G

V &

Ass

ocia

tes,

Inc.

XC

2V15

00-4

, 200

0-4

or 3

000-

4 DS

P

GVA

-325

DS

P Ha

rdw

are

Acce

lera

tor,

Virt

ex-II

(GVA

-325

) G

V &

Ass

ocia

tes,

Inc.

XC

2V15

00-4

, 200

0-4

or 3

000-

4 DS

P

GVA

-350

DS

P Ha

rdw

are

Acce

lera

tor,

Virt

ex-II

(GVA

-350

) G

V &

Ass

ocia

tes,

Inc.

XC

2V40

00-4

, 600

0-4

or 8

000-

4 DS

P

DS-K

IT-M

BLAZ

E-V2

Vi

rtex

-II M

icro

Blaz

e Ki

t In

sigh

t (M

emec

) Vi

rtex

-II

Embe

dded

mic

ropr

oces

sor

DS-K

IT-V

2LC1

000*

Vi

rtex

-II L

C100

0 In

sigh

t (M

emec

) XC

2V10

00

Digi

tal V

ideo

, Im

age

Proc

essi

ng, T

elec

om /

Data

com

DS-K

IT-V

2LC1

000-

ISE

Virt

ex-II

LC1

000

w/IS

E Fo

unda

tion

and

JTAG

Cab

le

Insi

ght (

Mem

ec)

XC2V

1000

Di

gita

l Vid

eo, I

mag

e Pr

oces

sing

, Tel

ecom

/ Da

taco

m

DS-K

IT-V

2MB1

000*

Vi

rtex

-II M

B 2V

1000

Dev

elop

men

t Kit

Insi

ght (

Mem

ec)

XC2V

1000

-4FG

456C

DS

P, Di

gita

l Vid

eo, E

mbe

dded

Sys

tem

, Im

age

Proc

essi

ng, R

econ

figur

able

Com

putin

g,

Tele

com

/ Da

taco

m,

DS-K

IT-V

2MB1

000-

ISE

Virt

ex-II

MB

2V10

00 D

evel

opm

ent K

it w

/ISE

Foun

datio

n an

d JT

AG C

able

Insi

ght (

Mem

ec)

XC2V

1000

-4FG

456C

DS

P, Di

gita

l Vid

eo, E

mbe

dded

Sys

tem

, Im

age

Proc

essi

ng, R

econ

figur

able

Com

putin

g,

Tele

com

/ Da

taco

m,

Mic

roEn

gine

V-II

CP

U +

FPG

A (V

irtex

-II) M

icro

Engi

ne C

ards

In

trin

syc,

Inc.

Vi

rtex

-II

Embe

dded

Sys

tem

s

ASPE

-100

0 Ad

vanc

ed S

igna

l Pro

cess

ing

Engi

ne (A

SPE)

M

ultip

le A

cces

s Co

mm

unic

atio

ns

XC2V

1000

DS

P, Re

conf

igur

able

Com

putin

g, Te

leco

m /

Data

com

BenA

DDA-

2V25

0-4-

xx

BenA

DDA

Nal

late

ch

XC2V

250

- XC2

V600

0 In

frare

d Pr

oces

sing

, Mob

ile C

omm

unic

atio

ns S

yste

ms,

Mul

ti-ch

anne

l, M

ulti-

mod

e re

ceiv

ers,

Wid

eban

d Ca

ble

Syst

ems

BenB

LUE-

II-2V

4000

-4-0

1 Be

nBLU

E-II

Nal

late

ch

XC2V

4000

- XC

2V80

00

ASIC

Pro

toty

ping

, Im

age

Proc

essi

ng, R

econ

figur

able

Com

putin

g, S

oftw

are

Defin

ed R

adio

Da

ta P

roce

ssin

g

BenD

ATA-

DD-2

V300

0 Be

nDAT

A-DD

N

alla

tech

XC

2V30

00-X

C2V8

000

Data

Tran

smis

sion

& M

anip

ulat

ion,

Imag

e Pr

oces

sing

BenD

ATA-

WS-

2V40

00-4

-01

BenD

ATA-

WS

Nal

late

ch

XC2V

4000

- XC

2V80

00

Imag

e Pr

oces

sing

42-0

55-0

1 SO

NET

/ SD

H A

TM-P

OS

Boar

d N

etQ

uest

Cor

pora

tion

XC2V

4000

Da

ta Tr

ansm

issi

on &

Man

ipul

atio

n, E

mbe

dded

Sys

tem

, IP-

Base

d Sy

stem

s, M

ultim

edia

, Te

leco

m /

Data

com

* In

sigh

t Pro

duct

s: A

ppen

d -E

URO

to p

art n

umbe

r for

inte

rnat

iona

l kits

(ex.

DS-

KIT-

2SLC

100-

EURO

); P

ower

Sup

ply

not i

nclu

ded

in -E

URO

kits

Xil

inx O

n B

oard

– D

evelo

pm

en

t R

efe

ren

ce B

oard

sh

ttp

://w

ww

.xil

inx

.co

m/b

oa

rd_s

ea

rch


Boar

d Pa

rt N

umbe

r

42-0

59-0

1

Boar

d D

escr

ipti

on

Gig

abit

IP C

onte

nt P

roce

ssor

Boa

rd

Supp

lier

Net

Que

st C

orpo

ratio

n

Xilin

x D

evic

e Su

ppor

t

XC2V

4000

App

licat

ion

Data

Tran

smis

sion

& M

anip

ulat

ion,

Em

bedd

ed S

yste

m, I

P-Ba

sed

Syst

ems,

Mul

timed

ia,

Tele

com

/ Da

taco

m

Virt

ex-II

42-0

60-0

1 SO

NET

/ SD

H / P

DH G

room

er B

oard

N

etQ

uest

Cor

pora

tion

XC2V

3000

Da

ta Tr

ansm

issi

on &

Man

ipul

atio

n, E

mbe

dded

Sys

tem

, IP-

Base

d Sy

stem

s, M

ultim

edia

, Te

leco

m /

Data

com

XL90

00

XL 9

000

Mul

ti-Po

rt C

amer

a Li

nk P

CI F

ram

e G

rabb

er

Nov

tech

XC

2V20

00 (c

an b

e su

bstit

uted

by

XC2V

2000

-XC2

V800

0)

Data

Sto

rage

, Dat

a Tr

ansm

issi

on &

Man

ipul

atio

n, D

igita

l Vid

eo, I

mag

e Pr

oces

sing

GR-

PCI-X

C2V

LEO

N P

CI V

irtex

II D

evel

opm

ent B

oard

Pe

nder

Ele

ctro

nic

Desi

gn

XC2V

3000

Pr

otot

ypin

g, D

SP, D

ata

Stor

age,

Dat

a Tr

ansm

issi

on &

Man

ipul

atio

n, D

igita

l Vid

eo, E

mbe

dded

M

icro

proc

esso

r, Em

bedd

ed S

yste

m, I

P-Ba

sed

Syst

ems,

Imag

e Pr

oces

sing

, Low

pow

er d

esig

ns,

Mul

timed

ia, N

avig

atio

n, P

CI, R

econ

figur

able

Com

putin

g, S

eria

l/Des

eria

lizat

ion,

Tele

com

/ Da

taco

m, T

elem

atic

s, Vo

IP

Jock

oBoa

rd

Jock

oBoa

rd S

OC

Virt

ex-II

Pro

toty

ping

Pla

tform

Re

alFa

st O

pera

ting

Syst

ems A

B XC

2V10

00

Embe

dded

Sys

tem

s

600-

0042

2 PR

O-3

100

Virt

ex-II

FPG

A Pr

oces

sing

Eng

ine

Spec

trum

Sig

nal P

roce

ssin

g XC

2V30

00, X

C2V6

000

DSP,

Data

Tran

smis

sion

& M

anip

ulat

ion,

Rec

onfig

urab

le C

ompu

ting

650-

0007

5 eP

MC-

8120

Sp

ectr

um S

igna

l Pro

cess

ing

XC2V

6000

DS

P, Da

ta tr

ansm

issi

on &

Man

ipul

atio

n, R

econ

figur

able

Com

putin

g

SMT3

51-G

Mem

ory

Mod

ule

351-

GSu

ndan

ce M

ultip

roce

ssor

Co.

XC

2V10

00

Base

Ban

d Ra

dar S

ampl

ing,

Cel

lula

r / P

CS B

ase

Stat

ions

, Com

mun

icat

ions

, Dig

ital R

adio

Re

ceiv

ers,

Gen

eral

Dat

a Lo

ggin

g, IF

Rad

ar S

ampl

ing,

Mul

ti-Ch

anne

l Rec

eive

rs,

Spec

trum

Ana

lyse

rs

SMT3

51-M

M

emor

y M

odul

e 35

1-M

Su

ndan

ce M

ultip

roce

ssor

Co.

XC

2V10

00

Base

Ban

d Ra

dar S

ampl

ing,

Cel

lula

r / P

CS B

ase

Stat

ions

, Com

mun

icat

ions

, Dig

ital R

adio

Re

ceiv

ers,

Gen

eral

Dat

a Lo

ggin

g, IF

Rad

ar S

ampl

ing,

Mul

ti-Ch

anne

l Rec

eive

rs,

Spec

trum

Ana

lyse

rs

SMT3

65E

DSP

Mod

ule

Sund

ance

Mul

tipro

cess

or C

o.

XC2V

6000

Im

age

Proc

essi

ng, I

ndus

tria

l, M

edic

al, T

elec

omun

icat

ions

SMT3

98-1

000-

4-Z1

FP

GA

Mod

ule

1000

-4-Z

1 Su

ndan

ce M

ultip

roce

ssor

Co.

XC

2V10

00

Base

Ban

d Ra

dar S

ampl

ing,

Cel

lula

r / P

CS B

ase

Stat

ions

, Com

mun

icat

ions

, Dig

ital R

adio

Re

ceiv

ers,

Gen

eral

Dat

a Lo

ggin

g, IF

Rad

ar S

ampl

ing,

Imag

ing,

Mul

ti-Ch

anne

l Rec

eive

rs,

Spec

trum

Ana

lyse

rs

SMT3

98-2

000-

4-Z1

FP

GA

Mod

ule

2000

-4-Z

1 Su

ndan

ce M

ultip

roce

ssor

Co.

XC

2V20

00

Base

Ban

d Ra

dar S

ampl

ing,

Cel

lula

r / P

CS B

ase

Stat

ions

, Com

mun

icat

ions

, Dig

ital R

adio

Re

ceiv

ers,

Gen

eral

Dat

a Lo

ggin

g, IF

Rad

ar S

ampl

ing,

Imag

ing,

Mul

ti-Ch

anne

l Rec

eive

rs,

Spec

trum

Ana

lyse

rs

SMT3

98-3

000-

4-Z4

-Q2

FPG

A M

odul

e 30

00-4

-Z4-

Q2

Sund

ance

Mul

tipro

cess

or C

o.

XC2V

3000

Ba

se B

and

Rada

r Sam

plin

g, C

ellu

lar /

PCS

Bas

e St

atio

ns, C

omm

unic

atio

ns, D

igita

l Rad

io

Rece

iver

s, G

ener

al D

ata

Logg

ing,

IF R

adar

Sam

plin

g, Im

agin

g, M

ulti-

Chan

nel R

ecei

vers

, Sp

ectr

um A

naly

sers

SMT3

98-8

000-

4-Z4

-Q2

FPG

A M

odul

e 80

00-4

-Z4-

Q2

Sund

ance

Mul

tipro

cess

or C

o.

XC2V

8000

Ba

se B

and

Rada

r Sam

plin

g, C

ellu

lar /

PCS

Bas

e St

atio

ns, C

omm

unic

atio

ns, D

igita

l Rad

io

Rece

iver

s, G

ener

al D

ata

Logg

ing,

IF R

adar

Sam

plin

g, Im

agin

g, M

ulti-

Chan

nel R

ecei

vers

, Sp

ectr

um A

naly

sers

SMT3

70

Dual

Cha

nnel

A/D

and

D/A

Mod

ule

Sund

ance

Mul

tipro

cess

or Te

chno

logy

Ltd

. XC

2V10

00

Base

Ban

d Ra

dar S

ampl

ing,

Cel

lula

r / P

CS B

ase

Stat

ions

, Dig

ital R

adio

Rec

eive

rs, G

ener

al D

ata

Logg

ing

and

I/O C

ontr

ol, I

F Ra

dar S

ampl

ing,

Inst

rum

enta

tion,

Mul

ti-Ch

anne

l Rec

eive

rs, S

onar

, Sp

ectr

um A

naly

sers

XT20

00-X

XT

ENSA

Mic

ropr

oces

sor E

mul

atio

n Ki

t (XT

2000

-X)

Tens

ilica

, Inc

. XC

2V60

00-4

Pr

otot

ypin

g, E

mbe

dded

Sys

tem

s

DO-V

2000

-MLT

A Vi

rtex

-II M

ultim

edia

Boa

rd

Xilin

x O

nlin

e St

ore

XC2V

2000

Pr

otot

ypin

g, D

SP, D

ata

Stor

age,

Dat

a Tr

ansm

issi

on &

Man

ipul

atio

n, D

igita

l Vid

eo, E

mbe

dded

M

icro

proc

esso

r, Em

bedd

ed S

yste

m, I

P-Ba

sed

Syst

ems,

Imag

e Pr

oces

sing

, Mul

timed

ia,

Reco

nfig

urab

le C

ompu

ting,

Tele

com

/ Da

taco

m, V

oIP

* In

sigh

t Pro

duct

s: A

ppen

d -E

URO

to p

art n

umbe

r for

inte

rnat

iona

l kits

(ex.

DS-

KIT-

2SLC

100-

EURO

); P

ower

Sup

ply

not i

nclu

ded

in -E

URO

kits

Xil

inx O

n B

oard

– D

evelo

pm

en

t R

efe

ren

ce B

oard

sh

ttp

://w

ww

.xil

inx

.co

m/b

oa

rd_s

ea

rch


Boar

d Pa

rt N

umbe

r

HW-A

FX-F

F115

2-20

0

Boar

d D

escr

ipti

on

FF11

52-2

00 P

roto

Boa

rd

Supp

lier

Xilin

x O

nlin

e St

ore

Xilin

x D

evic

e Su

ppor

t

XC2V

3000

, XC2

V400

0, X

C2V6

000,

XC2

V800

0

App

licat

ion

Prot

otyp

ing,

DSP

, Dat

a St

orag

e, D

ata

Tran

smis

sion

& M

anip

ulat

ion,

Em

bedd

ed S

yste

m,

Mul

timed

ia, P

CI, R

econ

figur

able

Com

putin

g, Te

leco

m /

Data

com

, Tel

emat

ics,

VoIP

Virt

ex-II

Virt

ex a

nd V

irte

x-E

HW-A

FX-F

G25

6-20

0 FG

256-

200

Prot

o Bo

ard

Xilin

x O

nlin

e St

ore

XC2V

1000

, XC2

V250

, XC2

V40,

XC2

V500

, XC

2V80

Pr

otot

ypin

g, D

SP, D

ata

Stor

age,

Dat

a Tr

ansm

issi

on &

Man

ipul

atio

n, E

mbe

dded

Sys

tem

, M

ultim

edia

, PCI

, Rec

onfig

urab

le C

ompu

ting,

Tele

com

/ Da

taco

m, T

elem

atic

s, Vo

IP

HW-A

FX-F

G45

6-20

0 FG

456

Virt

ex-II

Pro

to B

oard

Xi

linx

Onl

ine

Stor

e XC

2V10

00, X

C2V2

50, X

C2V5

00

Prot

otyp

ing,

DSP

, Dat

a St

orag

e, D

ata

Tran

smis

sion

& M

anip

ulat

ion,

Em

bedd

ed S

yste

m,

IP-B

ased

Sys

tem

s, M

ultim

edia

, PCI

, Rec

onfig

urab

le C

ompu

ting,

Tele

com

/ Da

taco

m,

Tele

mat

ics,

VoIP

HW-A

FX-F

G67

6-20

0 FG

676

Virt

ex-II

Pro

to B

oard

Xi

linx

Onl

ine

Stor

e XC

2V15

00, X

C2V2

000,

XC2

V300

0 Pr

otot

ypin

g, D

SP, D

ata

Stor

age,

Dat

a Tr

ansm

issi

on &

Man

ipul

atio

n, E

mbe

dded

Sys

tem

, IP

-Bas

ed S

yste

ms,

Mul

timed

ia, P

CI, R

econ

figur

able

Com

putin

g, Te

leco

m /

Data

com

, Te

lem

atic

s, Vo

IP

ADS-

VE-M

B-DE

V Vi

rtex

-E D

evel

opm

ent K

it w

/Mic

roBl

aze

Avne

t Des

ign

Serv

ices

XC

V100

0E

Net

wor

king

, tel

ecom

mun

icat

ion,

dat

a co

mm

unic

atio

n, e

mbe

dded

and

con

sum

er m

arke

ts

ADS-

VE-M

B-EV

L Vi

rtex

-E E

valu

atio

n Ki

t w/M

icro

Blaz

e Av

net D

esig

n Se

rvic

es

XCV1

00E

Net

wor

king

, tel

ecom

mun

icat

ion,

dat

a co

mm

unic

atio

n, e

mbe

dded

and

con

sum

er m

arke

ts

ADS-

XLX-

VE-D

EV

Virt

ex-E

Dev

elop

men

t Kit

Avne

t Des

ign

Serv

ices

XC

V100

0E

Com

mun

icat

ions

, Em

bedd

d Co

ntro

l, LA

N R

oute

rs, L

AN S

witc

h, N

etw

orki

ng, W

AN A

cces

s, xD

SL E

quip

men

t

ADS-

XLX-

VE-E

VL

Virt

ex-E

Eva

luat

ion

Kit

Avne

t Des

ign

Serv

ices

XC

V100

E

Very

cos

t effe

ctiv

e ev

alua

tion

and

prot

otyp

ing

plat

form

to d

evel

op a

nd te

st d

esig

ns ta

rget

ed

to th

e Vi

rtex

-E d

evic

e

DN20

00k1

0 DN

2000

k10

DIN

I Gro

up

XCV1

000,

XCV

1000

E, X

CV16

00E,

XCV

2000

E Pr

otot

ypin

g, A

lgor

ithm

ic A

ccel

erat

ion,

Log

ic E

mul

atio

n, P

CI /

PCI-X

GVA

-290

DS

P Ha

rdw

are

Acce

lera

tor,

Virt

ex-E

(GVA

-290

) G

V &

Ass

ocia

tes,

Inc.

2-

XCV1

000E

, 160

0E o

r 200

0E's

DS

P

BenA

DIC-

2000

E Be

nADI

C N

alla

tech

XC

V200

0E, X

CV60

0E

Mul

ticha

nnel

Dat

a Ac

quis

ition

& S

oftw

are

Radi

o, P

hase

d Ar

ray

Rada

r, Sm

art A

nten

na A

rray

s

BenE

RA-1

000E

-6-A

Be

nERA

N

alla

tech

XC

V100

0E-X

CV20

00E

Com

mun

icat

ions

& R

eal-T

ime

syst

ems,

DSP,

Imag

e Pr

oces

sing

, Rec

onfig

urab

le C

ompu

ting

BenF

AD-2

000E

Be

nFAD

N

alla

tech

XC

V200

0E

Broa

dban

d w

irele

ss/s

atel

lite

com

mun

icat

ions

, Dat

a Ac

quis

ition

/sig

nal a

naly

sis

syst

ems

42-0

47-0

1 SO

NET

/ SD

H P

OS

PCI N

IC C

ard

Net

Que

st C

orpo

ratio

n XC

V600

Da

ta Tr

ansm

issi

on &

Man

ipul

atio

n, IP

-Bas

ed S

yste

ms,

Mul

timed

ia, T

elec

om /

Data

com

42-0

53-0

1 SO

NET

/ SD

H A

TM P

CI N

IC C

ard

Net

Que

st C

orpo

ratio

n XC

V600

Da

ta Tr

ansm

issi

on &

Man

ipul

atio

n, IP

-Bas

ed S

yste

ms,

Mul

timed

ia, T

elec

om /

Data

com

DO-D

I-DSP

-DK2

Xt

rem

eDSP

Dev

elop

men

t Kit

Xilin

x O

nlin

e St

ore

2V30

00

High

Per

form

ance

DSP

DO-D

I-DSP

-DK2

-SG

Xt

rem

eDSP

Dev

elop

men

t Kit

+ S

yste

m G

ener

ator

for D

SP

Xilin

x O

nlin

e St

ore

2V30

00

Hard

war

e in

the

loop

from

Sim

ulin

k us

ing

Syst

em G

ener

ator

sof

twar

e an

d hi

gh p

erfo

rman

ce

DSP

boar

d

HW-A

FX-B

G35

2-10

0 BG

352-

100

Prot

o Bo

ard

Xilin

x O

nlin

e St

ore

XCV1

50, X

CV20

0, X

CV30

0

Prot

otyp

ing,

DSP

, Dat

a St

orag

e, D

ata

Tran

smis

sion

& M

anip

ulat

ion,

Dig

ital V

ideo

, Em

bedd

ed

Syst

em, I

P-Ba

sed

Syst

ems,

Imag

e Pr

oces

sing

, Mul

timed

ia, N

avig

atio

n, P

CI, R

econ

figur

able

Co

mpu

ting,

Tele

com

/ Da

taco

m, T

elem

atic

s, Vo

IP

HW-A

FX-B

G43

2-10

0 BG

432-

100

Prot

o Bo

ard

Xilin

x O

nlin

e St

ore

XCV3

00/E

, XCV

400/

E, X

CV60

0/E,

XCV

800

Prot

otyp

ing,

DSP

, Dat

a St

orag

e, D

ata

Tran

smis

sion

& M

anip

ulat

ion,

Dig

ital V

ideo

, Em

bedd

ed

Syst

em, I

P-Ba

sed

Syst

ems,

Imag

e Pr

oces

sing

, Mul

timed

ia, N

avig

atio

n, P

CI, R

econ

figur

able

Co

mpu

ting,

Tele

com

/ Da

taco

m, T

elem

atic

s, Vo

IP

* In

sigh

t Pro

duct

s: A

ppen

d -E

URO

to p

art n

umbe

r for

inte

rnat

iona

l kits

(ex.

DS-

KIT-

2SLC

100-

EURO

); P

ower

Sup

ply

not i

nclu

ded

in -E

URO

kits

Xil

inx O

n B

oard

– D

evelo

pm

en

t R

efe

ren

ce B

oard

sh

ttp

://w

ww

.xil

inx

.co

m/b

oa

rd_s

ea

rch


Boar

d Pa

rt N

umbe

r

HW-A

FX-B

G56

0-10

0

Boar

d D

escr

ipti

on

BG56

0-10

0 Pr

oto

Boar

d

Supp

lier

Xilin

x O

nlin

e St

ore

Xilin

x D

evic

e Su

ppor

t

XCV1

000/

E, X

CV16

00E,

XCV

2000

E, X

CV40

0/E,

XC

405E

, XCV

600/

E, X

CV80

0, X

CV81

2E

App

licat

ion

Prot

otyp

ing,

DSP

, Dat

a St

orag

e, D

ata

Tran

smis

sion

& M

anip

ulat

ion,

Dig

ital V

ideo

, Em

bedd

ed

Syst

em, I

P-Ba

sed

Syst

ems,

Imag

e Pr

oces

sing

, Mul

timed

ia, N

avig

atio

n, P

CI, R

econ

figur

able

Co

mpu

ting,

Tele

com

/ Da

taco

m, T

elem

atic

s, Vo

IP

Virt

ex-II

Rock

etPH

Y

Cool

Runn

er-II

HW-A

FX-P

Q24

0-10

0 PQ

240-

100

Prot

o Bo

ard

Xilin

x O

nlin

e St

ore

XCV1

00, X

CV15

0, X

CV20

0, X

CV30

0, X

CV50

Pr

otot

ypin

g, D

SP, D

ata

Stor

age,

Dat

a Tr

ansm

issi

on &

Man

ipul

atio

n, D

igita

l Vid

eo, E

mbe

dded

Sy

stem

, IP-

Base

d Sy

stem

s, Im

age

Proc

essi

ng, M

ultim

edia

, Nav

igat

ion,

PCI

, Rec

onfig

urab

le

Com

putin

g, Te

leco

m /

Data

com

, Tel

emat

ics,

VoIP

HW-A

FX-P

Q24

0-11

0 PQ

240-

110

Prot

o Bo

ard

Xilin

x O

nlin

e St

ore

XCV1

00, X

CV15

0, X

CV20

0, X

CV30

0, X

CV50

Pr

otot

ypin

g, D

SP, D

ata

Stor

age,

Dat

a Tr

ansm

issi

on &

Man

ipul

atio

n, D

igita

l Vid

eo, E

mbe

dded

Sy

stem

, IP-

Base

d Sy

stem

s, Im

age

Proc

essi

ng, M

ultim

edia

, Nav

igat

ion,

PCI

, Rec

onfig

urab

le

Com

putin

g, Te

leco

m /

Data

com

, Tel

emat

ics,

VoIP

HWK-

RPHY

2XFP

-1

Rock

etPH

Y XF

P Ki

t Xi

linx

Sale

s O

ffice

s XG

C112

0 10

G U

ltra

MSA

Da

ta S

tora

ge, D

ata

Stor

age

(10

Gig

abit

Fibr

e Ch

anne

l), D

ata

Tran

smis

sion

& M

anip

ulat

ion,

Da

taco

m (1

0 G

igab

it Et

hern

et),

Seria

l / D

eser

ializ

atio

n, Te

leco

m (S

onet

OC-

192

/ FEC

), Te

leco

m /

Data

com

HWK-

RPHY

2XFP

-M

Rock

etPH

Y XF

P Ki

t with

XFP

Mod

ule

Xilin

x Sa

les

Offi

ces

XGC1

120

10G

Ultr

a M

SA

Data

Sto

rage

, Dat

a St

orag

e (1

0 G

igab

it Fi

bre

Chan

nel),

Dat

a Tr

ansm

issi

on &

Man

ipul

atio

n,

Data

com

(10

Gig

abit

Ethe

rnet

), Se

rial /

Des

eria

lizat

ion,

Tele

com

(Son

et O

C-19

2 / F

EC),

Tele

com

/ Da

taco

m

HWK-

RPHY

-DVL

P Ro

cket

PHY

Deve

lopm

ent K

it Xi

linx

Sale

s O

ffice

s XC

2VP2

0, X

GC1

120

10G

Ultr

a M

SA

Data

Sto

rage

, Dat

a St

orag

e (1

0 G

igab

it Fi

bre

Chan

nel),

Dat

a Tr

ansm

issi

on &

Man

ipul

atio

n,

Data

com

(10

Gig

abit

Ethe

rnet

), En

cryp

tion

Devi

ces,

Rout

ers,

Seria

l / D

eser

ializ

atio

n, Te

leco

m

(Son

et O

C-19

2 / F

EC),

Tele

com

/ Da

taco

m, T

est E

quip

men

t

HW-A

FX-C

OO

L2-2

56M

C Co

olRu

nner

-II E

valu

atio

n Bo

ard

NuH

oriz

ons

XC2C

256

Low

pow

er d

esig

ns

* In

sigh

t Pro

duct

s: A

ppen

d -E

URO

to p

art n

umbe

r for

inte

rnat

iona

l kits

(ex.

DS-

KIT-

2SLC

100-

EURO

); P

ower

Sup

ply

not i

nclu

ded

in -E

URO

kits

ADS-

XLX-

CR2-

EVL

Cool

Runn

er-II

Eva

luat

ion

Kit

Avne

t Des

ign

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Function

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Pro

Virt

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Vendor Name

Audio, Video & Image Processing

Burst Locked PLL (BURST_PLL) Pinpoint Solutions, Inc. V-II V-E S3 S-IIE

Color Space Converter, RGB2YCrCb (CSC) CAST, Inc. V-II V-E S-IIE S-II

Huffman Decoder (HUFFD) CAST, Inc. V-II V-E S-IIE S-II

JPEG Fast Codec (JPEG_FAST_C) CAST, Inc. V-IIP V-II V-E S3

JPEG, 2000 Decoder (BA111JPEG2000D) Barco-Silex V-IIP V-II S3

JPEG, 2000 Encoder (BA112JPEG2000E) Barco-Silex V-IIP V-II S3

JPEG, 2000 Encoder (JPEG2K_E) CAST, Inc. V-IIP V-II V-E

JPEG, Fast color image decoder (FASTJPEG_C DECODER) Barco-Silex V-II V-E

JPEG, Fast Decoder (JPEG_FAST_D) CAST, Inc. V-IIP V-II V-E S-IIE

JPEG, Fast Encoder (JPEG_FAST_E) CAST, Inc. V-IIP V-II V-E

JPEG, Fast gray scale image decoder (FASTJPEG_BW DECODER) Barco-Silex V-II V-E

JPEG, Motion Codec V1.0 (CS6190) Amphion Semiconductor, Ltd. V-II V-E

JPEG, Motion Decoder (CS6150) Amphion Semiconductor, Ltd. V-II V-E

JPEG, Motion Encoder (CS6100) Amphion Semiconductor, Ltd. V-II V-E

Longitudinal Time Code Generator Deltatec S.A. V-IIP V-II S3 S-IIE

Motion JPEG Decoder (JPEG Decoder) 4i2i Communications Ltd. V-IIP V-II V-E S3 S-IIE

Motion JPEG Encoder (JPEG Encoder) 4i2i Communications Ltd. V-IIP V-II V-E S3 S-IIE

MPEG-2 Decoder (CS6651) Amphion Semiconductor, Ltd. V-IIP V-II

MPEG-2 HDTV I & P Encoder (DV1 HDTV) Duma Video, Inc. V-II

MPEG-2 SDTV I & P Encoder (DV1 SDTV) Duma Video, Inc. V-II

MPEG-4 Video Compression Decoder 4i2i Communications Ltd. V-IIP V-II S3

MPEG-4 Video Compression Encoder 4i2i Communications Ltd. V-IIP V-II S3

NTSC Color Separator (NTSC-COSEP) Pinpoint Solutions, Inc. V-II V-E S3 S-IIE

Communication & Networking

3G FEC Package Xilinx V-II V-E

8b/10b Decoder Xilinx V-IIP V-II V-E S-3 S-IIE S-II

8b/10b Encoder Xilinx V-IIP V-II V-E S-3 S-IIE S-II

ADPCM, 1024 Channel Simplex (CS4190) Amphion Semiconductor, Ltd. V-II

ADPCM, 256 Channel Simplex (CS4130) Amphion Semiconductor, Ltd. V-II V-E

ADPCM, 512 Channel Duplex (CS4180) Amphion Semiconductor, Ltd. V-II

ADPCM, 768 Channel Amphion Semiconductor, Ltd. V-II

AES Decryption Family (CS5200) Amphion Semiconductor, Ltd. V-II V-E S-II

AES Encryption CAST, Inc. V-IIP V-II V-E S3 S-IIE

AES Encryption Family (CS5200) Amphion Semiconductor, Ltd. V-II V-E S-II

AES Standard Encryptor/Decryptor Helion Technology Limited V-IIP V-II V-E S3 S-IIE

AES Tiny Encryptor/Decryptor Helion Technology Limited V-IIP V-II V-E S3 S-IIE

ATM Adaptation Layer 5 (AAL5) ModelWare, Inc. V-II S3

ATM Adaption Layer 1 (AAL1) ModelWare, Inc. V-II V-E

ATM Cell Processor (CC200) Paxonet Communications, Inc. V-IIP V-II

ATM Utopia Level 2 Master and Slave w/OPB Interface Xilinx V-IIP V-II V-E S-IIE S-II

AWGN - Additive White Gaussian Noise Xilinx V-IIP V-II

Bluetooth Baseband Processor (BOOST Lite) NewLogic Technologies AG V-II

Convolutional Encoder Xilinx V-IIP V-II V-E S-3 S-IIE S-II

CRC-32 for 10 Gbps OC192 systems (CORE-CRC-128) Calyptech Design Services S3

CRC-32 for 40 Gbps OC-768 systems (CORE-CRC-256) Calyptech Design Services V-IIP V-II

Visit the Xilinx IP Center for more details at www.xilinx.com/ipcenter

Function

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Spar

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Vendor Name


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Dataflow Processor (phyCore) Phystream Ltd. V-IIP 0 0

DES and DES3 Encryption Engine (MC-XIL-DES) Memec Design V-II V-E S-IIE S-II

DES Encryption CAST, Inc. V-II V-E S-II

DES3 AMBA Platform SoC Solutions, LLC V-IIP V-II S3 S-IIE

DES3 Encryption CAST, Inc. V-IIP V-II V-E S3 S-IIE

DVB Satellite Modulator (MC-XIL-DVBMOD) Memec Design V-II V-E S-II

Email Trigger Amirix Systems, Inc. V-IIP

Ethernet 1000BASE-X PCS/PMA Xilinx V-IIP

Ethernet MAC, 1 Gigabit (CC281) Paxonet Communications, Inc. V-IIP V-II

Ethernet MAC, 1 Gigabit Half/Full duplex with GMII or 1000BASE-X PCS/PMA Xilinx V-IIP V-II V-E S-IIE

Ethernet MAC, 10 Gigabit Full Duplex with XGMII or XAUI Xilinx V-IIP V-II

Ethernet MAC, 10/100 Hitachi ULSI Systems Co., Ltd.

Ethernet MAC, 10/100 Zuken, Inc. V-II V-E

Ethernet MAC, 10/100 (CC271) Paxonet Communications, Inc. V-IIP V-II

Ethernet MAC, 10/100 (MAC) CAST, Inc. V-IIP V-II S3 S-IIE

Ethernet MAC, 10G (CC410) Paxonet Communications, Inc. V-II

Ethernet MAC, 10G (XGEMAC) GDA Technologies, Inc. V-IIP V-II

Ethernet MAC, 1Gigabit (MAC-1G) CAST, Inc. V-IIP V-II

Ethernet PCS, 10G (CC411) Paxonet Communications, Inc. V-IIP V-II

Ethernet PCS, 10G (MC-XIL-10GEPCS) Memec Design V-II

Framer, 1.25 Gb/s GFP (CC224) Paxonet Communications, Inc. V-IIP V-II S3 S-IIE

Framer, 2.5 Gb/s GFP (CC226) Paxonet Communications, Inc. V-IIP V-II

Framer, 8-Bit Multilchannel GFP (CC225) Paxonet Communications, Inc. V-IIP V-II

Framer, 8-Bit Transparent GFP (CC124) Paxonet Communications, Inc. V-IIP V-II

Framer, E1 (CC303) Paxonet Communications, Inc. V-IIP V-II S-IIE

Framer, OC12 (CC351) Paxonet Communications, Inc. V-IIP V-II

Framer, OC192/10 GB/s GFP (CC327) Paxonet Communications, Inc. V-IIP V-II

Framer, OTU2 (CC481) Paxonet Communications, Inc. V-IIP V-II

Framer, STS192/STM64 (CC314) Paxonet Communications, Inc. V-IIP V-II

Framer, STS48 (CC352) Paxonet Communications, Inc. V-IIP V-II

Framer, T1 (CC302) Paxonet Communications, Inc. V-IIP V-II S-IIE

Framer/Digital Wrapper, STS48 OTN (CC381) Paxonet Communications, Inc. V-IIP V-II

G.709 Compliant FEC Core (CC345) Paxonet Communications, Inc. V-IIP V-II

HDLC, Single-Channel (MC-XIL-HDLC) Memec Design V-IIP V-II S3

HyperTransport Cave 16-Bit GDA Technologies, Inc. V-IIP V-II

Interleaver/De-interleaver Xilinx V-IIP V-II V-E S-3 S-IIE S-II

Inverse Multiplexer for ATM (IMA) ModelWare, Inc. V-II V-E

Mapper, E1 (CC333) Paxonet Communications, Inc. V-IIP V-II S-IIE

MD5 Message Digest Algorithm CAST, Inc. V-IIP V-II S3 S-IIE

Modular Exponentiation Accelerator (MODEXP1) CAST, Inc. V-IIP V-II V-E S3 S-IIE

Multi Rate Performance Monitor Calyptech Design Services V-IIP V-II S3

Network Processor Forum Streaming Interface (NPSI) ModelWare, Inc.

Packet Processor (CC318) Paxonet Communications, Inc. V-IIP V-II S3 S-IIE

Path Processor, OC12c (CC321) Paxonet Communications, Inc. V-IIP V-II

Path Processor, STS192/STM64 (CC324) Paxonet Communications, Inc. V-IIP V-II

Path Processor, STS-48/STM-16 (CC322) Paxonet Communications, Inc. V-IIP V-II

Function

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Vendor Name


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Reed Solomon Decoder Xilinx V-IIP V-II V-E S-3 S-IIE S-II

Reed Solomon Decoder (MC-XIL-RSDEC) Memec Design V-II S-IIE S-II

Reed Solomon Encoder Xilinx V-IIP V-II V-E S-3 S-IIE S-II

Reed Solomon Encoder (MC-XIL-RSENC) Memec Design V-II S-IIE S-II

SDLC Controller (SDLC) CAST, Inc. V-IIP V-II V-E S3 S-IIE

SHA-1 Encryption Processor CAST, Inc. V-II V-E S-IIE S-II

SONET Performance Monitor (HCLT_SONETPM) HCL Technologies, Ltd. V-II

SPI 4.2 Interface (CC401) Paxonet Communications, Inc. V-IIP V-II

SPI-3 (POS-PHY L3) Link Layer Interface, 1-Ch Xilinx V-IIP V-II V-E S-IIE S-II



SPI-3 (POS-PHY L3) Link Layer Interface, Multi-Channel Xilinx V-IIP V-II V-E S-3 S-IIE S-II

SPI-3 (POS-PHY L3) Physical Layer Interface Xilinx V-E

SPI-4.1 (Flexbus 4) Interface Core, 1-Channel Xilinx V-II

SPI-4.1 (Flexbus 4) Interface Core, 4-Channel Xilinx V-II

SPI-4.2 (POS-PHY L4) Multi-Channel Interface Xilinx V-IIP V-II

SPI-4.2 (POS-PHY L4) to SPI-4.1 (Flexbus 4) Bridge Xilinx V-II

SPI-4.2 (POS-PHY L4) to XGMII (10GE MAC) Bridge Xilinx V-II

SPI-4.2 Lite (POS_PHY L4) Xilinx V-II S-3

System Packet Interface Level 4 Phase 2 (HCLT_SPI4-2) HCL Technologies, Ltd. V-IIP V-II

TDM Timeswitch Calyptech Design Services V-IIP V-II S3 S-IIE

Turbo Decoder, 3GPP SysOnChip, Inc. V-II V-E

Turbo Decoder, 3GPP (S3000) iCoding Technology, Inc. V-II V-E S-IIE

Turbo Decoder, Convolutional, 3GPP Compliant Xilinx V-II V-E

Turbo Decoder, Convolutional, 3GPP2/CDMA2000 Xilinx V-IIP V-II S-3

Turbo Decoder, DVB-RCS (S2000) iCoding Technology, Inc. V-II V-E

Turbo Decoder, DVB-RCS (TC1000) TurboConcept V-II V-E

Turbo Decoder, Product Code Xilinx V-IIP V-II S-3

Turbo Encoder, Convolutional, 3GPP Compliant Xilinx V-II V-E

Turbo Encoder, Convolutional, 3GPP2/CDMA2000 Xilinx V-IIP V-II S-3

Turbo Encoder, DVB-RCS (S2001) iCoding Technology, Inc. V-II V-E

Turbo Encoder, Product Code Xilinx V-IIP V-II S-3

Turbo Product Code Decoder, 160 Mbps (TC3404) TurboConcept V-II V-E

Turbo Product Code Decoder, 25 Mbps (TC3000) TurboConcept V-II V-E

Turbo Product Code Decoder, 30 Mbps (TC3401) TurboConcept V-E S-IIE

Viterbi Decoder, General Purpose Xilinx V-IIP V-II V-E S-3 S-IIE S-II

Viterbi Decoder, IEEE 802-compatible Xilinx V-IIP V-II V-E S-3 S-IIE S-II

XAPP 289: Common Switch Interface CSIX-L1

Reference Design Xilinx V-IIP V-II

XAUI Xilinx V-IIP

Digital Signal Processing

Bit Correlator Xilinx V-IIP V-II V-E S-IIE S-II

Cascaded Integrator Comb (CIC) Filter Xilinx V-IIP V-II V-E S-IIE S-II

CORDIC Xilinx V-IIP V-II V-E S-3 S-IIE S-II

Digital Down Converter (DDC) Xilinx V-IIP V-II V-E S-IIE S-II

Digital Down Converter, High-Speed Wideband (4954-422) Pentek, Inc. V-IIP V-II

Function

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Spar

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Vendor Name


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Digital Down Converter, Wideband (4954-421) Pentek, Inc. V-IIP V-II

Digital Up Converter (DUC) Xilinx V-IIP V-II S-3

Direct Digital Synthesizer (DDS) Xilinx V-IIP V-II V-E S-3 S-IIE S-II

Discrete Cosine Transform (eDCT) eInfochips Pvt. Ltd. V-II V-E S-IIE S-II

Discrete Cosine Transform, 2D Inverse (IDCT) CAST, Inc. V-II V-E S-II

Discrete Cosine Transform, Combined 2D Forward/Inverse (DCT_FI) CAST, Inc. V-II V-E S-II

Discrete Cosine Transform, Forward 2D (DCT) CAST, Inc. V-II V-E S-II

Discrete Cosine Transform, forward/inverse 2D (DCT/IDCT 2D) Barco-Silex V-II V-E S-II

Discrete Wavelet Transform (BA113FDWT) Barco-Silex V-IIP V-II S3 S-IIE

Discrete Wavelet Transform, Combined 2D Forward/Inverse (RC_2DDWT) CAST, Inc. V-II V-E S-II

Discrete Wavelet Transform, Inverse (BA114IDWT) Barco-Silex V-IIP V-II S3 S-IIE

Discrete Wavelet Transform, Line-based programmable forward (LB_2DFDWT) CAST, Inc. V-II V-E S-II

DOCSIS ITU-T J.83 Modulator Xilinx V-IIP V-II S-3

Fast Fourier Transform Xilinx V-IIP V-II S-3

FFT/IFFT for Virtex-II, 1024-Point Complex Xilinx V-II




FFT/IFFT, 1024-Point Complex Xilinx V-E

FFT/IFFT, 16-Point Complex Xilinx V-II V-E

FFT/IFFT, 256-Point Complex Xilinx V-II V-E

FFT/IFFT, 32-Point Complex Xilinx V-IIP V-II V-E S-IIE S-II

FFT/IFFT, 64-, 256-, 1024-Point Complex Xilinx V-IIP V-II S-3

FFT/IFFT, 64-Point Complex Xilinx V-E

FIR Filter using DPRAM eInfochips Pvt. Ltd. V-II V-E S-IIE S-II

FIR Filter, Distributed Arithmetic (DA) Xilinx V-IIP V-II V-E S-3 S-IIE S-II

FIR Filter, MAC Xilinx V-IIP V-II V-E S-3 S-IIE S-II

FIR Filter, Parallel Distributed Arithmetic eInfochips Pvt. Ltd. V-II V-E S-IIE S-II

LFSR, Linear Feedback Shift Register Xilinx V-IIP V-II V-E S-3 S-IIE S-II

Radar Pulse Compression (4954-440) Pentek, Inc. V-IIP V-II

TMS32025 DSP Processor (C32025) CAST, Inc. V-IIP V-II S3 S-IIE

TMS32025TX Digital Signal Processor (C32025TX) CAST, Inc. V-IIP V-II V-E S3 S-IIE

Math Function

Accumulator Xilinx V-IIP V-II V-E S-3 S-IIE S-II

Adder Subtracter Xilinx V-IIP V-II V-E S-3 S-IIE S-II

Divider, Pipelined Xilinx V-II V-E S-IIE S-II

Floating Point Adder (DFPADD) Digital Core Design V-II S-II

Floating Point Comparator (DFPCOMP) Digital Core Design V-II S-II

Floating Point Divider (DFPDIV) Digital Core Design V-II S-II

Floating Point Multiplier (DFPMUL) Digital Core Design V-II V-E S-II

Floating Point Square Root Operator (DFPSQRT) Digital Core Design V-II V-E S-II

Floating Point to Integer Converter (DFP2INT) Digital Core Design V-II S-II

Integer to Floating Point Converter (DINT2FP) Digital Core Design V-II S-II

Multiply Accumulator (MAC) Xilinx V-IIP V-II S-3 S-IIE S-II

Multiply Generator Xilinx V-IIP V-II V-E S-3 S-IIE S-II

Sine Cosine Look Up Table Xilinx V-IIP V-II V-E S-3 S-IIE S-II

Function

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Twos Complementer Xilinx V-IIP V-II V-E S-3 S-IIE S-II

Memories & Storage Element

Block Memory, Dual-Port Xilinx V-IIP V-II V-E S-3 S-IIE S-II

Block Memory, Single-Port Xilinx V-IIP V-II V-E S-3 S-IIE S-II

Content Addressable Memory (CAM) Xilinx V-IIP V-II V-E S-3 S-IIE S-II

Distributed Memory Xilinx V-IIP V-II V-E S-3 S-IIE S-II

FIFO, Asynchronous Xilinx V-IIP V-II V-E S-3 S-IIE S-II

FIFO, Synchronous Xilinx V-IIP V-II V-E S-3 S-IIE S-II

RLDRAM Memory Controller Avnet Design Services V-II

SDRAM Controller, DDR (EP525) Eureka Technology V-IIP V-II S3 S-IIE

SDRAM Controller, DDR (MC-XIL-SDRAMDDR) Memec Design V-II V-E S-II

SDRAM Controller, DDR (NW) Northwest Logic V-IIP V-II S3 S-IIE

SDRAM Controller, SDR (NW) Northwest Logic V-IIP V-II S3 S-IIE

Microprocessor, Controller & Peripheral

1 Gigabit Ethernet MAC w/PLB interface Xilinx V-IIP

10/100 Ethernet MAC Lite w/OPB interface Xilinx V-IIP V-II V-E S-IIE S-II

10/100 Ethernet MAC w/OPB interface Xilinx V-IIP V-II V-E S-IIE S-II

10/100 Ethernet MAC w/PLB interface Xilinx V-IIP

16450 UART (H16450) CAST, Inc. V-II V-E S-IIE S-II

16450 UART w/OPB interface Xilinx V-IIP V-II V-E S-3 S-IIE S-II

16450 UART w/PLB interface Xilinx V-IIP

16450 UART w/Synchronous Interface (H16450S) CAST, Inc. V-II V-E S-IIE S-II

16550 UART w/FIFOs & synch interface (H16550S) CAST, Inc. V-II V-E S-IIE S-II

16550 UART w/FIFOs (H16550) CAST, Inc. V-II V-E S-IIE S-II

16550 UART w/OPB interface Xilinx V-IIP V-II V-E S-3 S-IIE S-II

16550 UART w/PLB interface Xilinx V-IIP

2910A Microprogram Controller (C2910A) CAST, Inc. V-IIP V-II S3

2D Multiprocessing Interface Fabric (2D-fabric402C) Crossbow Technologies, Inc. V-IIP V-II S-IIE S-II

68000 Compatible Microprocessor (C68000) CAST, Inc. V-IIP V-II V-E S3 S-IIE

80186 Compatible Microprocessor (e80186) eInfochips Pvt. Ltd. V-II

8051 Base Compatible Microcontroller (DR8051BASE) Digital Core Design V-II S-II

8051 Compatible Microcontroller (C8051) CAST, Inc. V-IIP V-II V-E S3 S-IIE S-II

8051 Compatible Microcontroller (FLIP8051 Thunder) Dolphin Integration V-IIP V-II S-IIE

8051 High-speed 8-bit RISC Microcontroller (R80515) CAST, Inc. V-IIP V-II S3 S-IIE

8051 Microcontroller, PicoBlaze Emulated (PB8051-MX/TF) Roman-Jones, Inc. V-IIP V-II S3 S-IIE

8051 RISC Microcontroller (DR8051) Digital Core Design V-II S-II

8052 Compatible Microcontroller (DR8052EX) Digital Core Design V-II S-II

80530 8-bit Microcontroller (D80530) CAST, Inc. V-IIP V-II V-E S3 S-IIE

80C51 Compatible RISC Microcontroller (R8051) CAST, Inc. V-IIP V-II S3 S-IIE

8237 Programmable DMA Controller (C8237) CAST, Inc. V-II V-E S-II

8250 UART (H8250) CAST, Inc. V-II V-E S-IIE S-II

8254 Programmable Interval Timer/Counter (C8254) CAST, Inc. V-II V-E S-II

8254 Programmable Interval Timer/Counter (e8254) eInfochips Pvt. Ltd. V-II S-II

8255 Programmable I/O Controller (e8255) eInfochips Pvt. Ltd. V-II S-II

8259A Programmable Interrupt Controller (C8259A) CAST, Inc. V-II V-E S-II

Arbiter and Bus Structure w/OPB interface Xilinx V-IIP V-II V-E S-3 S-IIE S-II

Function

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Arbiter and Bus Structure w/PLB interface Xilinx V-IIP

ATM Utopia Level 2 Master and Slave w/OPB Interface Xilinx V-IIP V-II V-E S-IIE S-II

ATM Utopia Level 2 Master and Slave w/PLB Interface Xilinx V-IIP

BRAM Controller w/LMB interface Xilinx V-IIP V-II V-E S-IIE S-II

BRAM Controller w/OPB interface Xilinx V-IIP V-II V-E S-3 S-IIE S-II

BRAM Controller w/PLB interface Xilinx V-IIP

BSP Generator (SW only) Xilinx V-IIP

Compact Video Controller (logiCVC) Xylon d.o.o. V-II S-II

CRT Controller (C6845) CAST, Inc. V-II V-E S-IIE S-II

DCR Bus Structure Xilinx V-IIP

Direct Memory Access Controller (CZ80DMA) CAST, Inc. V-IIP V-II S3 S-IIE

External Memory Controller (EMC) w/OPB interface (Includes support

for Flash, SRAM, ZBT, System ACE) Xilinx V-IIP V-II V-E S-3 S-IIE S-II

External Memory Controller (EMC) w/PLB interface (Includes support

for Flash, SRAM, ZBT, System ACE) Xilinx V-IIP

FPU for Microblaze (Quixilica) QinetiQ Limited V-IIP V-II

GPIO w/OPB interface Xilinx V-IIP V-II V-E S-3 S-IIE S-II

HDLC Controller (Multi (256) Channel) w/OPB interface Xilinx V-IIP V-II V-E S-3 S-IIE S-II

HDLC Controller (Single Channel) w/OPB interface Xilinx V-IIP V-II V-E S-3 S-IIE S-II

IIC w/OPB interface Xilinx V-IIP V-II V-E S-3 S-IIE S-II

Internet Appliance (socPiP-1A_Platform) SoC Solutions, LLC V-II V-E

Interrupt Controller (IntC) w/DCR interface Xilinx V-IIP V-II V-E S-IIE S-II

Interrupt Controller (IntC) w/OPB interface Xilinx V-IIP V-II V-E S-3 S-IIE S-II

IPIF Address Decode w/OPB interface Xilinx V-IIP V-II V-E S-IIE S-II

IPIF DMA w/OPB interface Xilinx V-IIP V-II V-E S-IIE S-II

IPIF Interrupt Controller w/OPB interface Xilinx V-IIP V-II V-E S-IIE S-II

IPIF Master/Slave Attachment w/OPB interface Xilinx V-IIP V-II V-E S-IIE S-II

IPIF Read/Write Packet FIFO w/OPB interface Xilinx V-IIP V-II V-E S-IIE S-II

IPIF Scatter/Gather w/OPB interface Xilinx V-IIP V-II V-E S-IIE S-II

IPIF Slave Attachment w/PLB interface Xilinx V-IIP

Java Processor, 32-bit (Lightfoot) Digital Communications Technologies, Ltd. V-II S-II

Java Processor, Configurable (LavaCORE) Derivation Systems, Inc. V-II

JTAG UART w/OPB interface Xilinx V-IIP V-II V-E S-3 S-IIE S-II

Memory Test Utility (SW only) Xilinx V-IIP

MicroBlaze Soft RISC Processor Xilinx V-IIP V-II V-E S-3 S-IIE S-II

MicroBlaze Source Code Xilinx V-IIP V-II V-E S-3 S-IIE S-II

MIPS system controller (ES500) Eureka Technology V-II V-E

ML300 VxWorks BSP (SW only) Xilinx V-IIP

Motor Controller - 3 phase (MLCA_4) MEET Ltd. S-IIE S-II

OPB2DCR Bridge Xilinx V-IIP

OPB2OPB Bridge (Lite) Xilinx V-IIP V-II V-E S-3 S-IIE S-II

OPB2PCI Full Bridge (32/33) Xilinx V-IIP V-II V-E S-3 S-IIE S-II

OPB2PLB Bridge Xilinx V-IIP

Operating System Accelerator (Sierra S16) RealFast Intellectual Property AB V-II S-IIE S-II

PIC125x Fast RISC Microcontroller (DFPIC125X) Digital Core Design V-II S-II

PIC1655x Fast RISC Microcontroller (DFPIC1655X) Digital Core Design V-II S-II

Function

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PIC165X Compatible Microcontroller (C165X) CAST, Inc. V-IIP V-II V-E S3 S-IIE

PIC165x Fast RISC Microcontroller (DFPIC165X) Digital Core Design V-II V-E S-II

PIC16C55X Compatible RISC Microcontroller (C1655x) CAST, Inc. V-IIP V-II V-E S3 S-IIE

PicoBlaze UG129: PicoBlaze 8-bit Microcontroller for Spartan-3,

Virtex-II, and Virtex-II Pro Devices) - REFERENCE DESIGN Xilinx V-IIP V-II S-3

PicoBlaze (XAPP 213: PicoBlaze 8-bit Microcontroller

for Virtex-E and Spartan-II/E Devices) - REFERENCE DESIGN Xilinx V-E S-IIE S-II

PicoBlaze (XAPP 627: PicoBlaze 8-bit Microcontroller

for Virtex-II and Virtex-II Pro Devices) - REFERENCE DESIGN Xilinx V-IIP V-II

PLB2OPB Bridge Xilinx V-IIP

PowerPC Bus Master (EP201) Eureka Technology V-IIP V-II S3 S-IIE

PowerPC Bus Slave (EP100) Eureka Technology V-IIP V-II S3 S-IIE

RISC Processor, 16-bit Proprietary (AX1610) Loarant Corporation V-IIP V-II S3 S-IIE

SDRAM Controller w/OPB interface Xilinx V-IIP V-II V-E S-3 S-IIE S-II

SDRAM Controller w/PLB interface Xilinx V-IIP

SPI Master and Slave w/OPB interface Xilinx V-IIP V-II V-E S-3 S-IIE S-II

SwifTraxTM Rapid Development System SoC Solutions, LLC V-IIP V-II S3 S-IIE

Systems Reset Module Xilinx V-IIP

Timebase/Watch Dog Timer (WDT) w/OPB interface Xilinx V-IIP V-II V-E S-3 S-IIE S-II

Timer/Counter w/OPB interface Xilinx V-IIP V-II V-E S-3 S-IIE S-II

UART Lite w/OPB interface Xilinx V-IIP V-II V-E S-3 S-IIE S-II

UART, Generic Compact (MC-XIL-UART) Memec Design V-IIP V-II S3

UltraController Solution: A lightweight PowerPC

Microcontroller (XAPP672) - REFERENCE DESIGN Xilinx V-IIP

VxWorks Board Support Package (BSP) Xilinx V-IIP

XTENSA-V Configurable 32-bit Microprocessor Tensilica, Inc. V-II

Z80 Compatible Microprocessor (CZ80CPU) CAST, Inc. V-IIP V-II S3 S-IIE

Z80 Compatible Programmable Counter/Timer (CZ80CTC) CAST, Inc. V-IIP V-II V-E S3 S-IIE

Z80 Intelligent Peripheral Controller (CZ80PSC) CAST, Inc.

Z80 Peripheral I/O Controller (CZ80PIO) CAST, Inc. V-IIP V-II S3 S-IIE

Z80 Serial I/O Controller (CZ80SIO) CAST, Inc. V-IIP V-II V-E S-IIE

Standard Bus Interface

Advanced Switching Endpoint Core Xilinx V-IIP

CAN 2.0 B Compatible Network Controller (LogiCAN) Xylon d.o.o. V-IIP V-II S3 S-IIE

CAN 2.0B Bus Controller (iCAN) Intelliga Integrated Design, Ltd. V-IIP V-II V-E S3 S-IIE

CAN Bus Controller (MC-XIL-OPB-XCAN) Memec Design V-IIP V-II V-E S3 S-IIE S-II

CAN Bus Controller 2.0B CAST, Inc. V-IIP V-II S3 S-IIE

CAN Bus Controller with 32 Mail Boxes Robert Bosch GmbH V-IIP V-II S3 S-IIE

HyperTransport Cave, 8-bit GDA Technologies, Inc. V-IIP V-II

HyperTransport Single-Ended Slave Core Xilinx V-IIP V-II

I2C Bus Controller (I2C) CAST, Inc. V-IIP V-II V-E S3 S-IIE

I2C Bus Controller Master (DI2CM) Digital Core Design V-II V-E S-II

I2C Bus Controller Slave (DI2CS) Digital Core Design V-II V-E S-II

I2C Bus Controller Slave Base (DI2CSB) Digital Core Design V-II V-E S-II

I2C Two-Wire Serial Interface Master-Only (MC-XIL-TWSIMO) Memec Design V-II V-E S-IIE S-II

I2C Two-Wire Serial Interface Master-Slave (MC-XIL-TWSIMS) Memec Design V-II V-E S-IIE S-II

LIN - Local Interconnect Network Bus Controller (iLIN) Intelliga Integrated Design, Ltd. V-IIP V-II V-E S3 S-IIE

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LIN Controller CAST, Inc. V-IIP V-II S3 S-IIE

PCI 32-bit Master Interface (PCI-M32) CAST, Inc. V-IIP V-II S3 S-IIE

PCI 32-Bit Multifunction Target Interface (PCI-TMF) CAST, Inc. V-IIP V-II S3 S-IIE

PCI 32-bit Target Interface (PCI-T32) CAST, Inc. V-IIP V-II S3 S-IIE

PCI 64-bit/66-MHz master/target interface (EC240) Eureka Technology V-II V-E

PCI Express Endpoint Core Xilinx V-IIP

PCI Host Bridge (EP430) Eureka Technology V-II V-E

PCI Host Bridge (PCI-HB) CAST, Inc. V-IIP V-II S3 S-IIE

PCI, 64-bit Master Interface (PCI-M64) CAST, Inc. V-IIP V-II S-IIE

PCI, 64-bit Target Interface (PCI-T64) CAST, Inc. V-IIP V-II S-IIE

PCI32 Interface Design Kit (DO-DI-PCI32-DKT) Xilinx V-IIP V-II V-E S-IIE S-II

PCI32 Interface, IP Only (DO-DI-PCI32-IP) Xilinx V-IIP V-II V-E S-3 S-IIE S-II

PCI32 Single-Use License for Spartan (DO-DI-PCI32-SP) Xilinx S-3 S-IIE S-II

PCI64 & PCI32, IP Only (DO-DI-PCI-AL) Xilinx V-IIP V-II V-E S-3 S-IIE S-II

PCI64 Interface Design Kit (DO-DI-PCI64-DKT) Xilinx V-IIP V-II V-E S-IIE S-II

PCI64 Interface, IP Only (DO-DI-PCI64-IP) Xilinx V-IIP V-II V-E S-IIE S-II

PCI-PCI Bridge (EP440) Eureka Technology V-IIP V-II S3 S-IIE

PCI-X 64/133 Interface for Virtex-II (DO-DI-PCIX64-VE).

Includes PCI 64 bit interface at 33 MHz Xilinx V-IIP V-II

PCI-X 64/66 Interface for Virtex-E (DO-DI-PCIX64-VE).

Includes PCI 64 bit interface at 33 MHz Xilinx VE

PCI-X Arbiter SoC Solutions, LLC V-IIP V-II V-E S-IIE

PCI-X Interface (NWL PCI-X) Northwest Logic V-IIP V-II 0 0 0 0

RapidIO 8-bit port LP-LVDS Phy Layer (DO-DI-RIO8-PHY) Xilinx V-IIP V-II

RapidIO Logical (I/O) and Transport Layer (DO-DI-RIO8-LOG) Xilinx V-IIP V-II

RapidIO Phy Layer to PLB Bridge reference design - REFERENCE DESIGN Xilinx V-IIP

Serial Protocol Interface Slave (SPI Slave) CAST, Inc. V-II V-E S-IIE

Two-Wire Serial Interface - I2C (MC-XIL-TWSI) Memec Design V-IIP V-II V-E S3 S-IIE S-II

USB 1.1 Function Controller (CUSB) CAST, Inc. V-IIP V-II S3 S-IIE

USB 2.0 Function Controller (CUSB2) CAST, Inc. V-IIP V-II V-E S3 S-IIE

USB Function Controller with On-Chip Peripheral Bus (CUSB_OPB) CAST, Inc. V-IIP V-II S3 S-IIE

XAPP653: Virtex-II Pro/Spartan-3 3.3V PCI Reference Design - REFERENCE DESIGN Xilinx V-IIP S-3

Backplanes and Gigabit Serial I/O

Aurora 201, 401and 804 Designs - REFERENCE DESIGN Xilinx V-IIP

WP160: Emulating External SERDES Devices with

Embedded RocketIO Transceivers - WHITE PAPER Xilinx V-IIP

XAPP 649: SONET Rate Conversion in Virtex-II Pro Devices - REFERENCE DESIGN Xilinx V-IIP

XAPP 651: SONET and OTN Scramblers/Descramblers - REFERENCE DESIGN Xilinx V-IIP

XAPP 652: Word Alignment and SONET/SDH Framing - REFERENCE DESIGN Xilinx V-IIP

XAPP660: Partial Reconfiguration of RocketIO Attributes

using PPC405 core (DCR Bus) - REFERENCE DESIGN Xilinx V-IIP

XAPP661: RocketIO Transceiver Bit-Error Rate Tester (BERT) - REFERENCE DESIGN Xilinx V-IIP

XAPP662: Partial Reconfig. of RocketIO Attributes using PPC405 core (PLB or OPB bus) +

RocketIO Transceiver Bit-Error Rate Tester (BERT) - REFERENCE DESIGN Xilinx V-IIP

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FPGA

Design

©2003 Mentor Graphics Corporation. All Rights Reserved. Mentor Graphics is a registered trademark of Mentor Graphics Corporation.

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www.xilinx.com/virtex2pro

©2004, Xilinx, Inc. All rights reserved. The Xilinx name, the Xilinx logo are registered trademarks. Rocket IO and Virtex-II Pro are trademarks, and The Programmable Logic Company is a service mark of Xilinx, Inc.

PowerPC is a trademark of International Business Machines Corporation in the United States, or other countries, or both: All other trademarks and registered trademarks are the property of their respective owners.


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Documents

Xcell Journal Issue 50 - Xilinx...THE AUTHORITATIVE JOURNAL FOR PROGRAMMABLE LOGIC USERS R ISSUE 50, FALL 2004 XCELL JOURNAL XILINX, INC. Xcell journal COVER STORY COVER STORY FPGAs